Addressmap Information for 'ns_noc_io_spio_soc

ns_noc_io_spio_soc_ip.csr /project/jenkins/workspace/Esperanto_DV/soc_hal/esperanto-soc/dv/common/scripts/semifore_css/etsoc_esr.css spio_noc addressmap spio_noc spio_noc ns_noc_io_spio_soc_ip.csr 207197 NoC registers R/W Spio_noc Registers in NoC accessible through regbus register spio_noc.bridge_rbm_m_17_1_p_0 register spio_noc.bridge_rbm_m_17_1_p_1 register spio_noc.bridge_rbm_m_17_1_p_2 register spio_noc.bridge_rbm_m_17_1_p_3 register spio_noc.bridge_rbm_m_17_1_txe register spio_noc.bridge_rbm_m_17_1_txem register spio_noc.bridge_rbm_m_17_1_btus_0 register spio_noc.bridge_rbm_m_17_1_btus_1 register spio_noc.bridge_rbm_m_17_1_btrl_0 register spio_noc.bridge_rbm_m_17_1_btrl_1 register spio_noc.bridge_rbm_m_17_1_btrl_2 register spio_noc.bridge_rbm_m_17_1_btrl_3 register spio_noc.bridge_rbm_m_17_1_btperr register spio_noc.bridge_rbm_m_17_1_btperrm register spio_noc.bridge_rbm_m_17_1_rxe register spio_noc.bridge_rbm_m_17_1_rxem register spio_noc.bridge_rbm_m_17_1_brs_0 register spio_noc.bridge_rbm_m_17_1_brs_1 register spio_noc.bridge_rbm_m_17_1_brus register spio_noc.bridge_rbm_m_17_1_brperr0 register spio_noc.bridge_rbm_m_17_1_brperr1 register spio_noc.bridge_rbm_m_17_1_brperrm0 register spio_noc.bridge_rbm_m_17_1_brperrm1 register spio_noc.bridge_rbm_m_17_1_am_tocfg register spio_noc.bridge_rbm_m_17_1_am_osslv register spio_noc.bridge_rbm_m_17_1_am_cgc register spio_noc.bridge_rbm_m_17_1_am_cgo register spio_noc.bridge_rbm_m_17_1_am_cfg register spio_noc.bridge_rbm_m_17_1_am_sts register spio_noc.bridge_rbm_m_17_1_am_bridge_id register spio_noc.bridge_rbm_m_17_1_am_nocver_id register spio_noc.bridge_rbm_m_17_1_am_err register spio_noc.bridge_rbm_m_17_1_am_toslvid register spio_noc.bridge_rbm_m_17_1_am_era register spio_noc.bridge_rbm_m_17_1_am_ewa register spio_noc.bridge_rbm_m_17_1_am_intm register spio_noc.bridge_rbm_m_17_1_am_caddr register spio_noc.bridge_rbm_m_17_1_am_caddrmsk register spio_noc.bridge_rbm_m_17_1_am_ccmd0 register spio_noc.bridge_rbm_m_17_1_am_ccmdmsk0 register spio_noc.bridge_rbm_m_17_1_am_cntr0 register spio_noc.bridge_rbm_m_17_1_am_latnum0 register spio_noc.bridge_rbm_m_17_1_am_ccmd1 register spio_noc.bridge_rbm_m_17_1_am_ccmdmsk1 register spio_noc.bridge_rbm_m_17_1_am_cntr1 register spio_noc.bridge_rbm_m_17_1_am_latnum1 register spio_noc.bridge_rbm_m_17_1_am_arovrd register spio_noc.bridge_rbm_m_17_1_am_awovrd register spio_noc.bridge_rbm_s_4_1_as_cgc register spio_noc.bridge_rbm_s_4_1_as_cgo register spio_noc.bridge_rbm_s_4_1_as_sts register spio_noc.bridge_rbm_s_4_1_as_bridge_id register spio_noc.bridge_rbm_s_4_1_as_err register spio_noc.bridge_rbm_s_4_1_as_intm register spio_noc.bridge_rbm_s_4_1_as_ccmd register spio_noc.bridge_rbm_s_4_1_as_ccmdmsk register spio_noc.bridge_rbm_s_4_1_as_cntr register spio_noc.bridge_rbm_s_4_1_as_arovrd register spio_noc.bridge_rbm_s_4_1_as_awovrd register spio_noc.bridge_rbm_s_4_1_p_0 register spio_noc.bridge_rbm_s_4_1_p_1 register spio_noc.bridge_rbm_s_4_1_p_2 register spio_noc.bridge_rbm_s_4_1_p_3 register spio_noc.bridge_rbm_s_4_1_txe register spio_noc.bridge_rbm_s_4_1_txem register spio_noc.bridge_rbm_s_4_1_btus_0 register spio_noc.bridge_rbm_s_4_1_btus_1 register spio_noc.bridge_rbm_s_4_1_btrl_0 register spio_noc.bridge_rbm_s_4_1_btrl_1 register spio_noc.bridge_rbm_s_4_1_btrl_2 register spio_noc.bridge_rbm_s_4_1_btrl_3 register spio_noc.bridge_rbm_s_4_1_btperr register spio_noc.bridge_rbm_s_4_1_btperrm register spio_noc.bridge_rbm_s_4_1_rxe register spio_noc.bridge_rbm_s_4_1_rxem register spio_noc.bridge_rbm_s_4_1_brs_0 register spio_noc.bridge_rbm_s_4_1_brs_1 register spio_noc.bridge_rbm_s_4_1_brus register spio_noc.bridge_rbm_s_4_1_brperr0 register spio_noc.bridge_rbm_s_4_1_brperr1 register spio_noc.bridge_rbm_s_4_1_brperrm0 register spio_noc.bridge_rbm_s_4_1_brperrm1 register spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_cgc register spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_cgo register spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_sts register spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_bridge_id register spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_err register spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_intm register spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_ccmd register spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_ccmdmsk register spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_cntr register spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_arovrd register spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_awovrd register spio_noc.bridge_spio_p00_axi_comm_s_5_7_p_0 register spio_noc.bridge_spio_p00_axi_comm_s_5_7_p_1 register spio_noc.bridge_spio_p00_axi_comm_s_5_7_p_2 register spio_noc.bridge_spio_p00_axi_comm_s_5_7_p_3 register spio_noc.bridge_spio_p00_axi_comm_s_5_7_txe register spio_noc.bridge_spio_p00_axi_comm_s_5_7_txem register spio_noc.bridge_spio_p00_axi_comm_s_5_7_btus_0 register spio_noc.bridge_spio_p00_axi_comm_s_5_7_btus_1 register spio_noc.bridge_spio_p00_axi_comm_s_5_7_btrl_0 register spio_noc.bridge_spio_p00_axi_comm_s_5_7_btrl_1 register spio_noc.bridge_spio_p00_axi_comm_s_5_7_btrl_2 register spio_noc.bridge_spio_p00_axi_comm_s_5_7_btrl_3 register spio_noc.bridge_spio_p00_axi_comm_s_5_7_btperr register spio_noc.bridge_spio_p00_axi_comm_s_5_7_btperrm register spio_noc.bridge_spio_p00_axi_comm_s_5_7_rxe register spio_noc.bridge_spio_p00_axi_comm_s_5_7_rxem register spio_noc.bridge_spio_p00_axi_comm_s_5_7_brs_0 register spio_noc.bridge_spio_p00_axi_comm_s_5_7_brs_1 register spio_noc.bridge_spio_p00_axi_comm_s_5_7_brus register spio_noc.bridge_spio_p00_axi_comm_s_5_7_brperr0 register spio_noc.bridge_spio_p00_axi_comm_s_5_7_brperr1 register spio_noc.bridge_spio_p00_axi_comm_s_5_7_brperrm0 register spio_noc.bridge_spio_p00_axi_comm_s_5_7_brperrm1 register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_ahbs_ctl register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_ahbs_sts register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_ahbs_im register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_cgc register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_cgo register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_sts register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_bridge_id register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_err register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_intm register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_ccmd register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_ccmdmsk register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_cntr register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_arovrd register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_awovrd register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_p_0 register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_p_1 register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_p_2 register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_p_3 register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_txe register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_txem register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btus_0 register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btus_1 register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btrl_0 register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btrl_1 register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btrl_2 register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btrl_3 register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btperr register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btperrm register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_rxe register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_rxem register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_brs_0 register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_brs_1 register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_brus register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_brperr0 register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_brperr1 register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_brperrm0 register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_brperrm1 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_p_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_p_1 register spio_noc.bridge_spio_p00_dma_am_m_0_7_p_2 register spio_noc.bridge_spio_p00_dma_am_m_0_7_p_3 register spio_noc.bridge_spio_p00_dma_am_m_0_7_txe register spio_noc.bridge_spio_p00_dma_am_m_0_7_txem register spio_noc.bridge_spio_p00_dma_am_m_0_7_btus_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_btus_1 register spio_noc.bridge_spio_p00_dma_am_m_0_7_btrl_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_btrl_1 register spio_noc.bridge_spio_p00_dma_am_m_0_7_btrl_2 register spio_noc.bridge_spio_p00_dma_am_m_0_7_btrl_3 register spio_noc.bridge_spio_p00_dma_am_m_0_7_btperr register spio_noc.bridge_spio_p00_dma_am_m_0_7_btperrm register spio_noc.bridge_spio_p00_dma_am_m_0_7_rxe register spio_noc.bridge_spio_p00_dma_am_m_0_7_rxem register spio_noc.bridge_spio_p00_dma_am_m_0_7_brs_0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_brs_1 register spio_noc.bridge_spio_p00_dma_am_m_0_7_brus register spio_noc.bridge_spio_p00_dma_am_m_0_7_brperr0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_brperr1 register spio_noc.bridge_spio_p00_dma_am_m_0_7_brperrm0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_brperrm1 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_tocfg register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_osslv register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_cgc register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_cgo register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_cfg register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_sts register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_bridge_id register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_err register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_toslvid register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_era register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_ewa register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_intm register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_caddr register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_caddrmsk register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_ccmd0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_ccmdmsk0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_cntr0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_latnum0 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_ccmd1 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_ccmdmsk1 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_cntr1 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_latnum1 register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_arovrd register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_awovrd register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 register spio_noc.bridge_spio_p00_dma_m_1_7_p_0 register spio_noc.bridge_spio_p00_dma_m_1_7_p_1 register spio_noc.bridge_spio_p00_dma_m_1_7_p_2 register spio_noc.bridge_spio_p00_dma_m_1_7_p_3 register spio_noc.bridge_spio_p00_dma_m_1_7_txe register spio_noc.bridge_spio_p00_dma_m_1_7_txem register spio_noc.bridge_spio_p00_dma_m_1_7_btus_0 register spio_noc.bridge_spio_p00_dma_m_1_7_btus_1 register spio_noc.bridge_spio_p00_dma_m_1_7_btrl_0 register spio_noc.bridge_spio_p00_dma_m_1_7_btrl_1 register spio_noc.bridge_spio_p00_dma_m_1_7_btrl_2 register spio_noc.bridge_spio_p00_dma_m_1_7_btrl_3 register spio_noc.bridge_spio_p00_dma_m_1_7_btperr register spio_noc.bridge_spio_p00_dma_m_1_7_btperrm register spio_noc.bridge_spio_p00_dma_m_1_7_rxe register spio_noc.bridge_spio_p00_dma_m_1_7_rxem register spio_noc.bridge_spio_p00_dma_m_1_7_brs_0 register spio_noc.bridge_spio_p00_dma_m_1_7_brs_1 register spio_noc.bridge_spio_p00_dma_m_1_7_brus register spio_noc.bridge_spio_p00_dma_m_1_7_brperr0 register spio_noc.bridge_spio_p00_dma_m_1_7_brperr1 register spio_noc.bridge_spio_p00_dma_m_1_7_brperrm0 register spio_noc.bridge_spio_p00_dma_m_1_7_brperrm1 register spio_noc.bridge_spio_p00_dma_m_1_7_am_tocfg register spio_noc.bridge_spio_p00_dma_m_1_7_am_osslv register spio_noc.bridge_spio_p00_dma_m_1_7_am_cgc register spio_noc.bridge_spio_p00_dma_m_1_7_am_cgo register spio_noc.bridge_spio_p00_dma_m_1_7_am_cfg register spio_noc.bridge_spio_p00_dma_m_1_7_am_sts register spio_noc.bridge_spio_p00_dma_m_1_7_am_bridge_id register spio_noc.bridge_spio_p00_dma_m_1_7_am_err register spio_noc.bridge_spio_p00_dma_m_1_7_am_toslvid register spio_noc.bridge_spio_p00_dma_m_1_7_am_era register spio_noc.bridge_spio_p00_dma_m_1_7_am_ewa register spio_noc.bridge_spio_p00_dma_m_1_7_am_intm register spio_noc.bridge_spio_p00_dma_m_1_7_am_caddr register spio_noc.bridge_spio_p00_dma_m_1_7_am_caddrmsk register spio_noc.bridge_spio_p00_dma_m_1_7_am_ccmd0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_ccmdmsk0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_cntr0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_latnum0 register spio_noc.bridge_spio_p00_dma_m_1_7_am_ccmd1 register spio_noc.bridge_spio_p00_dma_m_1_7_am_ccmdmsk1 register spio_noc.bridge_spio_p00_dma_m_1_7_am_cntr1 register spio_noc.bridge_spio_p00_dma_m_1_7_am_latnum1 register spio_noc.bridge_spio_p00_dma_m_1_7_am_arovrd register spio_noc.bridge_spio_p00_dma_m_1_7_am_awovrd register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 register spio_noc.bridge_spio_p00_rot_m_2_7_p_0 register spio_noc.bridge_spio_p00_rot_m_2_7_p_1 register spio_noc.bridge_spio_p00_rot_m_2_7_p_2 register spio_noc.bridge_spio_p00_rot_m_2_7_p_3 register spio_noc.bridge_spio_p00_rot_m_2_7_txe register spio_noc.bridge_spio_p00_rot_m_2_7_txem register spio_noc.bridge_spio_p00_rot_m_2_7_btus_0 register spio_noc.bridge_spio_p00_rot_m_2_7_btus_1 register spio_noc.bridge_spio_p00_rot_m_2_7_btrl_0 register spio_noc.bridge_spio_p00_rot_m_2_7_btrl_1 register spio_noc.bridge_spio_p00_rot_m_2_7_btrl_2 register spio_noc.bridge_spio_p00_rot_m_2_7_btrl_3 register spio_noc.bridge_spio_p00_rot_m_2_7_btperr register spio_noc.bridge_spio_p00_rot_m_2_7_btperrm register spio_noc.bridge_spio_p00_rot_m_2_7_rxe register spio_noc.bridge_spio_p00_rot_m_2_7_rxem register spio_noc.bridge_spio_p00_rot_m_2_7_brs_0 register spio_noc.bridge_spio_p00_rot_m_2_7_brs_1 register spio_noc.bridge_spio_p00_rot_m_2_7_brus register spio_noc.bridge_spio_p00_rot_m_2_7_brperr0 register spio_noc.bridge_spio_p00_rot_m_2_7_brperr1 register spio_noc.bridge_spio_p00_rot_m_2_7_brperrm0 register spio_noc.bridge_spio_p00_rot_m_2_7_brperrm1 register spio_noc.bridge_spio_p00_rot_m_2_7_am_tocfg register spio_noc.bridge_spio_p00_rot_m_2_7_am_osslv register spio_noc.bridge_spio_p00_rot_m_2_7_am_cgc register spio_noc.bridge_spio_p00_rot_m_2_7_am_cgo register spio_noc.bridge_spio_p00_rot_m_2_7_am_cfg register spio_noc.bridge_spio_p00_rot_m_2_7_am_sts register spio_noc.bridge_spio_p00_rot_m_2_7_am_bridge_id register spio_noc.bridge_spio_p00_rot_m_2_7_am_err register spio_noc.bridge_spio_p00_rot_m_2_7_am_toslvid register spio_noc.bridge_spio_p00_rot_m_2_7_am_era register spio_noc.bridge_spio_p00_rot_m_2_7_am_ewa register spio_noc.bridge_spio_p00_rot_m_2_7_am_intm register spio_noc.bridge_spio_p00_rot_m_2_7_am_caddr register spio_noc.bridge_spio_p00_rot_m_2_7_am_caddrmsk register spio_noc.bridge_spio_p00_rot_m_2_7_am_ccmd0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_ccmdmsk0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_cntr0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_latnum0 register spio_noc.bridge_spio_p00_rot_m_2_7_am_ccmd1 register spio_noc.bridge_spio_p00_rot_m_2_7_am_ccmdmsk1 register spio_noc.bridge_spio_p00_rot_m_2_7_am_cntr1 register spio_noc.bridge_spio_p00_rot_m_2_7_am_latnum1 register spio_noc.bridge_spio_p00_rot_m_2_7_am_arovrd register spio_noc.bridge_spio_p00_rot_m_2_7_am_awovrd register spio_noc.bridge_spio_p10_apb0_s_7_8_apbslv_bridge_version register spio_noc.bridge_spio_p10_apb0_s_7_8_apbslv_bridge_id register spio_noc.bridge_spio_p10_apb0_s_7_8_apbslv_slvs_sleep_status register spio_noc.bridge_spio_p10_apb0_s_7_8_as_cgc register spio_noc.bridge_spio_p10_apb0_s_7_8_as_cgo register spio_noc.bridge_spio_p10_apb0_s_7_8_as_sts register spio_noc.bridge_spio_p10_apb0_s_7_8_as_bridge_id register spio_noc.bridge_spio_p10_apb0_s_7_8_as_err register spio_noc.bridge_spio_p10_apb0_s_7_8_as_intm register spio_noc.bridge_spio_p10_apb0_s_7_8_as_ccmd register spio_noc.bridge_spio_p10_apb0_s_7_8_as_ccmdmsk register spio_noc.bridge_spio_p10_apb0_s_7_8_as_cntr register spio_noc.bridge_spio_p10_apb0_s_7_8_as_arovrd register spio_noc.bridge_spio_p10_apb0_s_7_8_as_awovrd register spio_noc.bridge_spio_p10_apb0_s_7_8_p_0 register spio_noc.bridge_spio_p10_apb0_s_7_8_p_1 register spio_noc.bridge_spio_p10_apb0_s_7_8_p_2 register spio_noc.bridge_spio_p10_apb0_s_7_8_p_3 register spio_noc.bridge_spio_p10_apb0_s_7_8_txe register spio_noc.bridge_spio_p10_apb0_s_7_8_txem register spio_noc.bridge_spio_p10_apb0_s_7_8_btus_0 register spio_noc.bridge_spio_p10_apb0_s_7_8_btus_1 register spio_noc.bridge_spio_p10_apb0_s_7_8_btrl_0 register spio_noc.bridge_spio_p10_apb0_s_7_8_btrl_1 register spio_noc.bridge_spio_p10_apb0_s_7_8_btrl_2 register spio_noc.bridge_spio_p10_apb0_s_7_8_btrl_3 register spio_noc.bridge_spio_p10_apb0_s_7_8_btperr register spio_noc.bridge_spio_p10_apb0_s_7_8_btperrm register spio_noc.bridge_spio_p10_apb0_s_7_8_rxe register spio_noc.bridge_spio_p10_apb0_s_7_8_rxem register spio_noc.bridge_spio_p10_apb0_s_7_8_brs_0 register spio_noc.bridge_spio_p10_apb0_s_7_8_brs_1 register spio_noc.bridge_spio_p10_apb0_s_7_8_brus register spio_noc.bridge_spio_p10_apb0_s_7_8_brperr0 register spio_noc.bridge_spio_p10_apb0_s_7_8_brperr1 register spio_noc.bridge_spio_p10_apb0_s_7_8_brperrm0 register spio_noc.bridge_spio_p10_apb0_s_7_8_brperrm1 register spio_noc.bridge_spio_p10_apb1_s_8_8_apbslv_bridge_version register spio_noc.bridge_spio_p10_apb1_s_8_8_apbslv_bridge_id register spio_noc.bridge_spio_p10_apb1_s_8_8_apbslv_slvs_sleep_status register spio_noc.bridge_spio_p10_apb1_s_8_8_as_cgc register spio_noc.bridge_spio_p10_apb1_s_8_8_as_cgo register spio_noc.bridge_spio_p10_apb1_s_8_8_as_sts register spio_noc.bridge_spio_p10_apb1_s_8_8_as_bridge_id register spio_noc.bridge_spio_p10_apb1_s_8_8_as_err register spio_noc.bridge_spio_p10_apb1_s_8_8_as_intm register spio_noc.bridge_spio_p10_apb1_s_8_8_as_ccmd register spio_noc.bridge_spio_p10_apb1_s_8_8_as_ccmdmsk register spio_noc.bridge_spio_p10_apb1_s_8_8_as_cntr register spio_noc.bridge_spio_p10_apb1_s_8_8_as_arovrd register spio_noc.bridge_spio_p10_apb1_s_8_8_as_awovrd register spio_noc.bridge_spio_p10_apb1_s_8_8_p_0 register spio_noc.bridge_spio_p10_apb1_s_8_8_p_1 register spio_noc.bridge_spio_p10_apb1_s_8_8_p_2 register spio_noc.bridge_spio_p10_apb1_s_8_8_p_3 register spio_noc.bridge_spio_p10_apb1_s_8_8_txe register spio_noc.bridge_spio_p10_apb1_s_8_8_txem register spio_noc.bridge_spio_p10_apb1_s_8_8_btus_0 register spio_noc.bridge_spio_p10_apb1_s_8_8_btus_1 register spio_noc.bridge_spio_p10_apb1_s_8_8_btrl_0 register spio_noc.bridge_spio_p10_apb1_s_8_8_btrl_1 register spio_noc.bridge_spio_p10_apb1_s_8_8_btrl_2 register spio_noc.bridge_spio_p10_apb1_s_8_8_btrl_3 register spio_noc.bridge_spio_p10_apb1_s_8_8_btperr register spio_noc.bridge_spio_p10_apb1_s_8_8_btperrm register spio_noc.bridge_spio_p10_apb1_s_8_8_rxe register spio_noc.bridge_spio_p10_apb1_s_8_8_rxem register spio_noc.bridge_spio_p10_apb1_s_8_8_brs_0 register spio_noc.bridge_spio_p10_apb1_s_8_8_brs_1 register spio_noc.bridge_spio_p10_apb1_s_8_8_brus register spio_noc.bridge_spio_p10_apb1_s_8_8_brperr0 register spio_noc.bridge_spio_p10_apb1_s_8_8_brperr1 register spio_noc.bridge_spio_p10_apb1_s_8_8_brperrm0 register spio_noc.bridge_spio_p10_apb1_s_8_8_brperrm1 register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_cgc register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_cgo register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_sts register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_bridge_id register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_err register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_intm register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_ccmd register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_ccmdmsk register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_cntr register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_arovrd register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_awovrd register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_p_0 register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_p_1 register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_p_2 register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_p_3 register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_txe register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_txem register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btus_0 register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btus_1 register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btrl_0 register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btrl_1 register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btrl_2 register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btrl_3 register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btperr register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btperrm register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_rxe register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_rxem register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_brs_0 register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_brs_1 register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_brus register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_brperr0 register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_brperr1 register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_brperrm0 register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_brperrm1 register spio_noc.bridge_spio_p10_pcie_s_10_9_as_cgc register spio_noc.bridge_spio_p10_pcie_s_10_9_as_cgo register spio_noc.bridge_spio_p10_pcie_s_10_9_as_sts register spio_noc.bridge_spio_p10_pcie_s_10_9_as_bridge_id register spio_noc.bridge_spio_p10_pcie_s_10_9_as_err register spio_noc.bridge_spio_p10_pcie_s_10_9_as_intm register spio_noc.bridge_spio_p10_pcie_s_10_9_as_ccmd register spio_noc.bridge_spio_p10_pcie_s_10_9_as_ccmdmsk register spio_noc.bridge_spio_p10_pcie_s_10_9_as_cntr register spio_noc.bridge_spio_p10_pcie_s_10_9_as_arovrd register spio_noc.bridge_spio_p10_pcie_s_10_9_as_awovrd register spio_noc.bridge_spio_p10_pcie_s_10_9_p_0 register spio_noc.bridge_spio_p10_pcie_s_10_9_p_1 register spio_noc.bridge_spio_p10_pcie_s_10_9_p_2 register spio_noc.bridge_spio_p10_pcie_s_10_9_p_3 register spio_noc.bridge_spio_p10_pcie_s_10_9_txe register spio_noc.bridge_spio_p10_pcie_s_10_9_txem register spio_noc.bridge_spio_p10_pcie_s_10_9_btus_0 register spio_noc.bridge_spio_p10_pcie_s_10_9_btus_1 register spio_noc.bridge_spio_p10_pcie_s_10_9_btrl_0 register spio_noc.bridge_spio_p10_pcie_s_10_9_btrl_1 register spio_noc.bridge_spio_p10_pcie_s_10_9_btrl_2 register spio_noc.bridge_spio_p10_pcie_s_10_9_btrl_3 register spio_noc.bridge_spio_p10_pcie_s_10_9_btperr register spio_noc.bridge_spio_p10_pcie_s_10_9_btperrm register spio_noc.bridge_spio_p10_pcie_s_10_9_rxe register spio_noc.bridge_spio_p10_pcie_s_10_9_rxem register spio_noc.bridge_spio_p10_pcie_s_10_9_brs_0 register spio_noc.bridge_spio_p10_pcie_s_10_9_brs_1 register spio_noc.bridge_spio_p10_pcie_s_10_9_brus register spio_noc.bridge_spio_p10_pcie_s_10_9_brperr0 register spio_noc.bridge_spio_p10_pcie_s_10_9_brperr1 register spio_noc.bridge_spio_p10_pcie_s_10_9_brperrm0 register spio_noc.bridge_spio_p10_pcie_s_10_9_brperrm1 register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_ahbs_ctl register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_ahbs_sts register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_ahbs_im register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_cgc register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_cgo register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_sts register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_bridge_id register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_err register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_intm register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_ccmd register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_ccmdmsk register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_cntr register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_arovrd register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_awovrd register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_p_0 register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_p_1 register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_p_2 register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_p_3 register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_txe register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_txem register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btus_0 register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btus_1 register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btrl_0 register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btrl_1 register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btrl_2 register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btrl_3 register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btperr register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btperrm register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_rxe register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_rxem register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_brs_0 register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_brs_1 register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_brus register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_brperr0 register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_brperr1 register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_brperrm0 register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_brperrm1 register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_cgc register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_cgo register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_sts register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_bridge_id register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_err register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_intm register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_ccmd register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_ccmdmsk register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_cntr register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_arovrd register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_awovrd register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_p_0 register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_p_1 register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_p_2 register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_p_3 register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_txe register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_txem register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btus_0 register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btus_1 register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btrl_0 register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btrl_1 register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btrl_2 register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btrl_3 register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btperr register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btperrm register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_rxe register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_rxem register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_brs_0 register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_brs_1 register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_brus register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_brperr0 register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_brperr1 register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_brperrm0 register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_brperrm1 register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_cgc register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_cgo register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_sts register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_bridge_id register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_err register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_intm register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_ccmd register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_ccmdmsk register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_cntr register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_arovrd register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_awovrd register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_p_0 register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_p_1 register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_p_2 register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_p_3 register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_txe register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_txem register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btus_0 register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btus_1 register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btrl_0 register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btrl_1 register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btrl_2 register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btrl_3 register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btperr register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btperrm register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_rxe register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_rxem register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_brs_0 register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_brs_1 register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_brus register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_brperr0 register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_brperr1 register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_brperrm0 register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_brperrm1 register spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_cgc register spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_cgo register spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_sts register spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_bridge_id register spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_err register spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_intm register spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_ccmd register spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_ccmdmsk register spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_cntr register spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_arovrd register spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_awovrd register spio_noc.bridge_spio_sp_main0_ram_s_14_11_p_0 register spio_noc.bridge_spio_sp_main0_ram_s_14_11_p_1 register spio_noc.bridge_spio_sp_main0_ram_s_14_11_p_2 register spio_noc.bridge_spio_sp_main0_ram_s_14_11_p_3 register spio_noc.bridge_spio_sp_main0_ram_s_14_11_txe register spio_noc.bridge_spio_sp_main0_ram_s_14_11_txem register spio_noc.bridge_spio_sp_main0_ram_s_14_11_btus_0 register spio_noc.bridge_spio_sp_main0_ram_s_14_11_btus_1 register spio_noc.bridge_spio_sp_main0_ram_s_14_11_btrl_0 register spio_noc.bridge_spio_sp_main0_ram_s_14_11_btrl_1 register spio_noc.bridge_spio_sp_main0_ram_s_14_11_btrl_2 register spio_noc.bridge_spio_sp_main0_ram_s_14_11_btrl_3 register spio_noc.bridge_spio_sp_main0_ram_s_14_11_btperr register spio_noc.bridge_spio_sp_main0_ram_s_14_11_btperrm register spio_noc.bridge_spio_sp_main0_ram_s_14_11_rxe register spio_noc.bridge_spio_sp_main0_ram_s_14_11_rxem register spio_noc.bridge_spio_sp_main0_ram_s_14_11_brs_0 register spio_noc.bridge_spio_sp_main0_ram_s_14_11_brs_1 register spio_noc.bridge_spio_sp_main0_ram_s_14_11_brus register spio_noc.bridge_spio_sp_main0_ram_s_14_11_brperr0 register spio_noc.bridge_spio_sp_main0_ram_s_14_11_brperr1 register spio_noc.bridge_spio_sp_main0_ram_s_14_11_brperrm0 register spio_noc.bridge_spio_sp_main0_ram_s_14_11_brperrm1 register spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_cgc register spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_cgo register spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_sts register spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_bridge_id register spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_err register spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_intm register spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_ccmd register spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_ccmdmsk register spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_cntr register spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_arovrd register spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_awovrd register spio_noc.bridge_spio_sp_main0_rom_s_15_6_p_0 register spio_noc.bridge_spio_sp_main0_rom_s_15_6_p_1 register spio_noc.bridge_spio_sp_main0_rom_s_15_6_p_2 register spio_noc.bridge_spio_sp_main0_rom_s_15_6_p_3 register spio_noc.bridge_spio_sp_main0_rom_s_15_6_txe register spio_noc.bridge_spio_sp_main0_rom_s_15_6_txem register spio_noc.bridge_spio_sp_main0_rom_s_15_6_btus_0 register spio_noc.bridge_spio_sp_main0_rom_s_15_6_btus_1 register spio_noc.bridge_spio_sp_main0_rom_s_15_6_btrl_0 register spio_noc.bridge_spio_sp_main0_rom_s_15_6_btrl_1 register spio_noc.bridge_spio_sp_main0_rom_s_15_6_btrl_2 register spio_noc.bridge_spio_sp_main0_rom_s_15_6_btrl_3 register spio_noc.bridge_spio_sp_main0_rom_s_15_6_btperr register spio_noc.bridge_spio_sp_main0_rom_s_15_6_btperrm register spio_noc.bridge_spio_sp_main0_rom_s_15_6_rxe register spio_noc.bridge_spio_sp_main0_rom_s_15_6_rxem register spio_noc.bridge_spio_sp_main0_rom_s_15_6_brs_0 register spio_noc.bridge_spio_sp_main0_rom_s_15_6_brs_1 register spio_noc.bridge_spio_sp_main0_rom_s_15_6_brus register spio_noc.bridge_spio_sp_main0_rom_s_15_6_brperr0 register spio_noc.bridge_spio_sp_main0_rom_s_15_6_brperr1 register spio_noc.bridge_spio_sp_main0_rom_s_15_6_brperrm0 register spio_noc.bridge_spio_sp_main0_rom_s_15_6_brperrm1 register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_cgc register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_cgo register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_sts register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_bridge_id register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_err register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_intm register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_ccmd register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_ccmdmsk register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_cntr register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_arovrd register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_awovrd register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_p_0 register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_p_1 register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_p_2 register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_p_3 register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_txe register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_txem register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btus_0 register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btus_1 register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btrl_0 register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btrl_1 register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btrl_2 register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btrl_3 register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btperr register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btperrm register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_rxe register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_rxem register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_brs_0 register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_brs_1 register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_brus register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_brperr0 register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_brperr1 register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_brperrm0 register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_brperrm1 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_p_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_p_1 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_p_2 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_p_3 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_txe register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_txem register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btus_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btus_1 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btrl_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btrl_1 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btrl_2 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btrl_3 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btperr register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btperrm register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_rxe register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_rxem register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_brs_0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_brs_1 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_brus register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_brperr0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_brperr1 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_brperrm0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_brperrm1 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_tocfg register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_osslv register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_cgc register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_cgo register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_cfg register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_sts register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_bridge_id register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_err register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_toslvid register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_era register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_ewa register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_intm register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_caddr register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_caddrmsk register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_ccmd0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_ccmdmsk0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_cntr0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_latnum0 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_ccmd1 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_ccmdmsk1 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_cntr1 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_latnum1 register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_arovrd register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_awovrd register spio_noc.router_0_6_6_rivcs_h register spio_noc.router_0_6_6_rivcs_e register spio_noc.router_0_6_6_rivcs_s register spio_noc.router_0_6_6_rivcs_w register spio_noc.router_0_6_6_rivcs_n register spio_noc.router_0_6_6_rivcs_i register spio_noc.router_0_6_6_rivcs_j register spio_noc.router_0_6_6_rivcs_k register spio_noc.router_0_6_6_rovcs_h register spio_noc.router_0_6_6_rovcs_e register spio_noc.router_0_6_6_rovcs_s register spio_noc.router_0_6_6_rovcs_w register spio_noc.router_0_6_6_rovcs_n register spio_noc.router_0_6_6_rovcs_i register spio_noc.router_0_6_6_rovcs_j register spio_noc.router_0_6_6_rovcs_k register spio_noc.router_0_6_6_re register spio_noc.router_0_6_6_rem register spio_noc.router_0_6_6_recc register spio_noc.router_0_6_6_rec register spio_noc.router_0_6_6_id register spio_noc.router_0_6_6_rcgc register spio_noc.router_0_6_6_rcgo register spio_noc.router_0_6_6_p0_rperr register spio_noc.router_0_6_6_p1_rperr register spio_noc.router_0_6_6_p2_rperr register spio_noc.router_0_6_6_p3_rperr register spio_noc.router_0_6_6_p4_rperr register spio_noc.router_0_6_6_p5_rperr register spio_noc.router_0_6_6_p6_rperr register spio_noc.router_0_6_6_p7_rperr register spio_noc.router_0_6_6_p0_rperrm register spio_noc.router_0_6_6_p1_rperrm register spio_noc.router_0_6_6_p2_rperrm register spio_noc.router_0_6_6_p3_rperrm register spio_noc.router_0_6_6_p4_rperrm register spio_noc.router_0_6_6_p5_rperrm register spio_noc.router_0_6_6_p6_rperrm register spio_noc.router_0_6_6_p7_rperrm register spio_noc.router_0_6_6_roecc register spio_noc.router_0_6_6_roec register spio_noc.router_0_7_7_rivcs_h register spio_noc.router_0_7_7_rivcs_e register spio_noc.router_0_7_7_rivcs_w register spio_noc.router_0_7_7_rivcs_n register spio_noc.router_0_7_7_rivcs_i register spio_noc.router_0_7_7_rivcs_j register spio_noc.router_0_7_7_rivcs_k register spio_noc.router_0_7_7_rovcs_h register spio_noc.router_0_7_7_rovcs_e register spio_noc.router_0_7_7_rovcs_w register spio_noc.router_0_7_7_rovcs_n register spio_noc.router_0_7_7_rovcs_i register spio_noc.router_0_7_7_rovcs_j register spio_noc.router_0_7_7_rovcs_k register spio_noc.router_0_7_7_re register spio_noc.router_0_7_7_rem register spio_noc.router_0_7_7_recc register spio_noc.router_0_7_7_rec register spio_noc.router_0_7_7_id register spio_noc.router_0_7_7_rcgc register spio_noc.router_0_7_7_rcgo register spio_noc.router_0_7_7_p0_rperr register spio_noc.router_0_7_7_p1_rperr register spio_noc.router_0_7_7_p2_rperr register spio_noc.router_0_7_7_p4_rperr register spio_noc.router_0_7_7_p5_rperr register spio_noc.router_0_7_7_p6_rperr register spio_noc.router_0_7_7_p7_rperr register spio_noc.router_0_7_7_p0_rperrm register spio_noc.router_0_7_7_p1_rperrm register spio_noc.router_0_7_7_p2_rperrm register spio_noc.router_0_7_7_p4_rperrm register spio_noc.router_0_7_7_p5_rperrm register spio_noc.router_0_7_7_p6_rperrm register spio_noc.router_0_7_7_p7_rperrm register spio_noc.router_0_7_7_roecc register spio_noc.router_0_7_7_roec register spio_noc.router_0_8_8_rivcs_h register spio_noc.router_0_8_8_rivcs_w register spio_noc.router_0_8_8_rivcs_n register spio_noc.router_0_8_8_rivcs_i register spio_noc.router_0_8_8_rivcs_j register spio_noc.router_0_8_8_rivcs_k register spio_noc.router_0_8_8_rovcs_h register spio_noc.router_0_8_8_rovcs_w register spio_noc.router_0_8_8_rovcs_n register spio_noc.router_0_8_8_rovcs_i register spio_noc.router_0_8_8_rovcs_j register spio_noc.router_0_8_8_rovcs_k register spio_noc.router_0_8_8_re register spio_noc.router_0_8_8_rem register spio_noc.router_0_8_8_recc register spio_noc.router_0_8_8_rec register spio_noc.router_0_8_8_id register spio_noc.router_0_8_8_rcgc register spio_noc.router_0_8_8_rcgo register spio_noc.router_0_8_8_p0_rperr register spio_noc.router_0_8_8_p2_rperr register spio_noc.router_0_8_8_p4_rperr register spio_noc.router_0_8_8_p5_rperr register spio_noc.router_0_8_8_p6_rperr register spio_noc.router_0_8_8_p7_rperr register spio_noc.router_0_8_8_p0_rperrm register spio_noc.router_0_8_8_p2_rperrm register spio_noc.router_0_8_8_p4_rperrm register spio_noc.router_0_8_8_p5_rperrm register spio_noc.router_0_8_8_p6_rperrm register spio_noc.router_0_8_8_p7_rperrm register spio_noc.router_0_8_8_roecc register spio_noc.router_0_8_8_roec register spio_noc.router_1_6_6_rivcs_h register spio_noc.router_1_6_6_rivcs_e register spio_noc.router_1_6_6_rivcs_s register spio_noc.router_1_6_6_rivcs_w register spio_noc.router_1_6_6_rivcs_n register spio_noc.router_1_6_6_rivcs_i register spio_noc.router_1_6_6_rivcs_j register spio_noc.router_1_6_6_rivcs_k register spio_noc.router_1_6_6_rovcs_h register spio_noc.router_1_6_6_rovcs_e register spio_noc.router_1_6_6_rovcs_s register spio_noc.router_1_6_6_rovcs_w register spio_noc.router_1_6_6_rovcs_n register spio_noc.router_1_6_6_rovcs_i register spio_noc.router_1_6_6_rovcs_j register spio_noc.router_1_6_6_rovcs_k register spio_noc.router_1_6_6_re register spio_noc.router_1_6_6_rem register spio_noc.router_1_6_6_recc register spio_noc.router_1_6_6_rec register spio_noc.router_1_6_6_id register spio_noc.router_1_6_6_rcgc register spio_noc.router_1_6_6_rcgo register spio_noc.router_1_6_6_p0_rperr register spio_noc.router_1_6_6_p1_rperr register spio_noc.router_1_6_6_p2_rperr register spio_noc.router_1_6_6_p3_rperr register spio_noc.router_1_6_6_p4_rperr register spio_noc.router_1_6_6_p5_rperr register spio_noc.router_1_6_6_p6_rperr register spio_noc.router_1_6_6_p7_rperr register spio_noc.router_1_6_6_p0_rperrm register spio_noc.router_1_6_6_p1_rperrm register spio_noc.router_1_6_6_p2_rperrm register spio_noc.router_1_6_6_p3_rperrm register spio_noc.router_1_6_6_p4_rperrm register spio_noc.router_1_6_6_p5_rperrm register spio_noc.router_1_6_6_p6_rperrm register spio_noc.router_1_6_6_p7_rperrm register spio_noc.router_1_6_6_roecc register spio_noc.router_1_6_6_roec register spio_noc.router_1_7_7_rivcs_h register spio_noc.router_1_7_7_rivcs_e register spio_noc.router_1_7_7_rivcs_w register spio_noc.router_1_7_7_rivcs_n register spio_noc.router_1_7_7_rivcs_i register spio_noc.router_1_7_7_rivcs_j register spio_noc.router_1_7_7_rivcs_k register spio_noc.router_1_7_7_rovcs_h register spio_noc.router_1_7_7_rovcs_e register spio_noc.router_1_7_7_rovcs_w register spio_noc.router_1_7_7_rovcs_n register spio_noc.router_1_7_7_rovcs_i register spio_noc.router_1_7_7_rovcs_j register spio_noc.router_1_7_7_rovcs_k register spio_noc.router_1_7_7_re register spio_noc.router_1_7_7_rem register spio_noc.router_1_7_7_recc register spio_noc.router_1_7_7_rec register spio_noc.router_1_7_7_id register spio_noc.router_1_7_7_rcgc register spio_noc.router_1_7_7_rcgo register spio_noc.router_1_7_7_p0_rperr register spio_noc.router_1_7_7_p1_rperr register spio_noc.router_1_7_7_p2_rperr register spio_noc.router_1_7_7_p4_rperr register spio_noc.router_1_7_7_p5_rperr register spio_noc.router_1_7_7_p6_rperr register spio_noc.router_1_7_7_p7_rperr register spio_noc.router_1_7_7_p0_rperrm register spio_noc.router_1_7_7_p1_rperrm register spio_noc.router_1_7_7_p2_rperrm register spio_noc.router_1_7_7_p4_rperrm register spio_noc.router_1_7_7_p5_rperrm register spio_noc.router_1_7_7_p6_rperrm register spio_noc.router_1_7_7_p7_rperrm register spio_noc.router_1_7_7_roecc register spio_noc.router_1_7_7_roec register spio_noc.router_1_8_8_rivcs_h register spio_noc.router_1_8_8_rivcs_w register spio_noc.router_1_8_8_rivcs_n register spio_noc.router_1_8_8_rivcs_i register spio_noc.router_1_8_8_rivcs_j register spio_noc.router_1_8_8_rivcs_k register spio_noc.router_1_8_8_rovcs_h register spio_noc.router_1_8_8_rovcs_w register spio_noc.router_1_8_8_rovcs_n register spio_noc.router_1_8_8_rovcs_i register spio_noc.router_1_8_8_rovcs_j register spio_noc.router_1_8_8_rovcs_k register spio_noc.router_1_8_8_re register spio_noc.router_1_8_8_rem register spio_noc.router_1_8_8_recc register spio_noc.router_1_8_8_rec register spio_noc.router_1_8_8_id register spio_noc.router_1_8_8_rcgc register spio_noc.router_1_8_8_rcgo register spio_noc.router_1_8_8_p0_rperr register spio_noc.router_1_8_8_p2_rperr register spio_noc.router_1_8_8_p4_rperr register spio_noc.router_1_8_8_p5_rperr register spio_noc.router_1_8_8_p6_rperr register spio_noc.router_1_8_8_p7_rperr register spio_noc.router_1_8_8_p0_rperrm register spio_noc.router_1_8_8_p2_rperrm register spio_noc.router_1_8_8_p4_rperrm register spio_noc.router_1_8_8_p5_rperrm register spio_noc.router_1_8_8_p6_rperrm register spio_noc.router_1_8_8_p7_rperrm register spio_noc.router_1_8_8_roecc register spio_noc.router_1_8_8_roec register spio_noc.router_2_1_1_re register spio_noc.router_2_1_1_rem register spio_noc.router_2_1_1_id register spio_noc.router_2_1_1_rcgo register spio_noc.router_2_1_1_p1_rperr register spio_noc.router_2_1_1_p2_rperr register spio_noc.router_2_1_1_p3_rperr register spio_noc.router_2_1_1_p4_rperr register spio_noc.router_2_1_1_p1_rperrm register spio_noc.router_2_1_1_p2_rperrm register spio_noc.router_2_1_1_p3_rperrm register spio_noc.router_2_1_1_p4_rperrm register spio_noc.router_2_6_6_re register spio_noc.router_2_6_6_rem register spio_noc.router_2_6_6_id register spio_noc.router_2_6_6_rcgo register spio_noc.router_2_6_6_p0_rperr register spio_noc.router_2_6_6_p1_rperr register spio_noc.router_2_6_6_p4_rperr register spio_noc.router_2_6_6_p0_rperrm register spio_noc.router_2_6_6_p1_rperrm register spio_noc.router_2_6_6_p4_rperrm register spio_noc.router_2_7_7_re register spio_noc.router_2_7_7_rem register spio_noc.router_2_7_7_id register spio_noc.router_2_7_7_rcgo register spio_noc.router_2_7_7_p1_rperr register spio_noc.router_2_7_7_p2_rperr register spio_noc.router_2_7_7_p4_rperr register spio_noc.router_2_7_7_p1_rperrm register spio_noc.router_2_7_7_p2_rperrm register spio_noc.router_2_7_7_p4_rperrm 0x0 0x68137 spio_noc spio_noc 0x0 0x2FFF 0x3000 0x3000 spio_noc.bridge_rbm_m_17_1_p_0 spio_noc.bridge_rbm_m_17_1_p_0 0x3004 0x3007 0x3008 0x3008 spio_noc.bridge_rbm_m_17_1_p_1 spio_noc.bridge_rbm_m_17_1_p_1 0x300C 0x300F 0x3010 0x3010 spio_noc.bridge_rbm_m_17_1_p_2 spio_noc.bridge_rbm_m_17_1_p_2 0x3014 0x3017 0x3018 0x3018 spio_noc.bridge_rbm_m_17_1_p_3 spio_noc.bridge_rbm_m_17_1_p_3 0x301C 0x303F 0x3040 0x3040 spio_noc.bridge_rbm_m_17_1_txe spio_noc.bridge_rbm_m_17_1_txe 0x3044 0x3047 0x3048 0x3048 spio_noc.bridge_rbm_m_17_1_txem spio_noc.bridge_rbm_m_17_1_txem 0x304C 0x3057 0x3058 0x3058 spio_noc.bridge_rbm_m_17_1_btus_0 spio_noc.bridge_rbm_m_17_1_btus_0 0x305C 0x305F 0x3060 0x3060 spio_noc.bridge_rbm_m_17_1_btus_1 spio_noc.bridge_rbm_m_17_1_btus_1 0x3064 0x307F 0x3080 0x3080 spio_noc.bridge_rbm_m_17_1_btrl_0 spio_noc.bridge_rbm_m_17_1_btrl_0 0x3084 0x3087 0x3088 0x3088 spio_noc.bridge_rbm_m_17_1_btrl_1 spio_noc.bridge_rbm_m_17_1_btrl_1 0x308C 0x308F 0x3090 0x3090 spio_noc.bridge_rbm_m_17_1_btrl_2 spio_noc.bridge_rbm_m_17_1_btrl_2 0x3094 0x3097 0x3098 0x3098 spio_noc.bridge_rbm_m_17_1_btrl_3 spio_noc.bridge_rbm_m_17_1_btrl_3 0x309C 0x30A7 0x30A8 0x30A8 spio_noc.bridge_rbm_m_17_1_btperr spio_noc.bridge_rbm_m_17_1_btperr 0x30AC 0x30AF 0x30B0 0x30B0 spio_noc.bridge_rbm_m_17_1_btperrm spio_noc.bridge_rbm_m_17_1_btperrm 0x30B4 0x311F 0x3120 0x3120 spio_noc.bridge_rbm_m_17_1_rxe spio_noc.bridge_rbm_m_17_1_rxe 0x3124 0x3127 0x3128 0x3128 spio_noc.bridge_rbm_m_17_1_rxem spio_noc.bridge_rbm_m_17_1_rxem 0x312C 0x312F 0x3130 0x3130 spio_noc.bridge_rbm_m_17_1_brs_0 spio_noc.bridge_rbm_m_17_1_brs_0 0x3134 0x3137 0x3138 0x3138 spio_noc.bridge_rbm_m_17_1_brs_1 spio_noc.bridge_rbm_m_17_1_brs_1 0x313C 0x31AF 0x31B0 0x31B0 spio_noc.bridge_rbm_m_17_1_brus spio_noc.bridge_rbm_m_17_1_brus 0x31B4 0x31CF 0x31D0 0x31D0 spio_noc.bridge_rbm_m_17_1_brperr0 spio_noc.bridge_rbm_m_17_1_brperr0 0x31D8 0x31D8 spio_noc.bridge_rbm_m_17_1_brperr1 spio_noc.bridge_rbm_m_17_1_brperr1 0x31E0 0x31E0 spio_noc.bridge_rbm_m_17_1_brperrm0 spio_noc.bridge_rbm_m_17_1_brperrm0 0x31E8 0x31E8 spio_noc.bridge_rbm_m_17_1_brperrm1 spio_noc.bridge_rbm_m_17_1_brperrm1 0x31F0 0x3BFF 0x3C00 0x3C00 spio_noc.bridge_rbm_m_17_1_am_tocfg spio_noc.bridge_rbm_m_17_1_am_tocfg 0x3C08 0x3C08 spio_noc.bridge_rbm_m_17_1_am_osslv spio_noc.bridge_rbm_m_17_1_am_osslv 0x3C10 0x3C10 spio_noc.bridge_rbm_m_17_1_am_cgc spio_noc.bridge_rbm_m_17_1_am_cgc 0x3C18 0x3C18 spio_noc.bridge_rbm_m_17_1_am_cgo spio_noc.bridge_rbm_m_17_1_am_cgo 0x3C20 0x3C20 spio_noc.bridge_rbm_m_17_1_am_cfg spio_noc.bridge_rbm_m_17_1_am_cfg 0x3C28 0x3CFF 0x3D00 0x3D00 spio_noc.bridge_rbm_m_17_1_am_sts spio_noc.bridge_rbm_m_17_1_am_sts 0x3D08 0x3D08 spio_noc.bridge_rbm_m_17_1_am_bridge_id spio_noc.bridge_rbm_m_17_1_am_bridge_id 0x3D10 0x3D10 spio_noc.bridge_rbm_m_17_1_am_nocver_id spio_noc.bridge_rbm_m_17_1_am_nocver_id 0x3D18 0x3DFF 0x3E00 0x3E00 spio_noc.bridge_rbm_m_17_1_am_err spio_noc.bridge_rbm_m_17_1_am_err 0x3E08 0x3E08 spio_noc.bridge_rbm_m_17_1_am_toslvid spio_noc.bridge_rbm_m_17_1_am_toslvid 0x3E10 0x3E10 spio_noc.bridge_rbm_m_17_1_am_era spio_noc.bridge_rbm_m_17_1_am_era 0x3E18 0x3E18 spio_noc.bridge_rbm_m_17_1_am_ewa spio_noc.bridge_rbm_m_17_1_am_ewa 0x3E20 0x3E3F 0x3E40 0x3E40 spio_noc.bridge_rbm_m_17_1_am_intm spio_noc.bridge_rbm_m_17_1_am_intm 0x3E48 0x3EFF 0x3F00 0x3F00 spio_noc.bridge_rbm_m_17_1_am_caddr spio_noc.bridge_rbm_m_17_1_am_caddr 0x3F08 0x3F08 spio_noc.bridge_rbm_m_17_1_am_caddrmsk spio_noc.bridge_rbm_m_17_1_am_caddrmsk 0x3F10 0x3F10 spio_noc.bridge_rbm_m_17_1_am_ccmd0 spio_noc.bridge_rbm_m_17_1_am_ccmd0 0x3F18 0x3F18 spio_noc.bridge_rbm_m_17_1_am_ccmdmsk0 spio_noc.bridge_rbm_m_17_1_am_ccmdmsk0 0x3F20 0x3F20 spio_noc.bridge_rbm_m_17_1_am_cntr0 spio_noc.bridge_rbm_m_17_1_am_cntr0 0x3F28 0x3F28 spio_noc.bridge_rbm_m_17_1_am_latnum0 spio_noc.bridge_rbm_m_17_1_am_latnum0 0x3F30 0x3F30 spio_noc.bridge_rbm_m_17_1_am_ccmd1 spio_noc.bridge_rbm_m_17_1_am_ccmd1 0x3F38 0x3F38 spio_noc.bridge_rbm_m_17_1_am_ccmdmsk1 spio_noc.bridge_rbm_m_17_1_am_ccmdmsk1 0x3F40 0x3F40 spio_noc.bridge_rbm_m_17_1_am_cntr1 spio_noc.bridge_rbm_m_17_1_am_cntr1 0x3F48 0x3F48 spio_noc.bridge_rbm_m_17_1_am_latnum1 spio_noc.bridge_rbm_m_17_1_am_latnum1 0x3F50 0x3F5F 0x3F60 0x3F60 spio_noc.bridge_rbm_m_17_1_am_arovrd spio_noc.bridge_rbm_m_17_1_am_arovrd 0x3F68 0x3F68 spio_noc.bridge_rbm_m_17_1_am_awovrd spio_noc.bridge_rbm_m_17_1_am_awovrd 0x3F70 0x5C0F 0x5C10 0x5C10 spio_noc.bridge_rbm_s_4_1_as_cgc spio_noc.bridge_rbm_s_4_1_as_cgc 0x5C18 0x5C18 spio_noc.bridge_rbm_s_4_1_as_cgo spio_noc.bridge_rbm_s_4_1_as_cgo 0x5C20 0x5CFF 0x5D00 0x5D00 spio_noc.bridge_rbm_s_4_1_as_sts spio_noc.bridge_rbm_s_4_1_as_sts 0x5D08 0x5D08 spio_noc.bridge_rbm_s_4_1_as_bridge_id spio_noc.bridge_rbm_s_4_1_as_bridge_id 0x5D10 0x5DFF 0x5E00 0x5E00 spio_noc.bridge_rbm_s_4_1_as_err spio_noc.bridge_rbm_s_4_1_as_err 0x5E08 0x5E3F 0x5E40 0x5E40 spio_noc.bridge_rbm_s_4_1_as_intm spio_noc.bridge_rbm_s_4_1_as_intm 0x5E48 0x5EFF 0x5F00 0x5F00 spio_noc.bridge_rbm_s_4_1_as_ccmd spio_noc.bridge_rbm_s_4_1_as_ccmd 0x5F08 0x5F08 spio_noc.bridge_rbm_s_4_1_as_ccmdmsk spio_noc.bridge_rbm_s_4_1_as_ccmdmsk 0x5F10 0x5F10 spio_noc.bridge_rbm_s_4_1_as_cntr spio_noc.bridge_rbm_s_4_1_as_cntr 0x5F18 0x5F18 spio_noc.bridge_rbm_s_4_1_as_arovrd spio_noc.bridge_rbm_s_4_1_as_arovrd 0x5F20 0x5F20 spio_noc.bridge_rbm_s_4_1_as_awovrd spio_noc.bridge_rbm_s_4_1_as_awovrd 0x5F28 0x6FFF 0x7000 0x7000 spio_noc.bridge_rbm_s_4_1_p_0 spio_noc.bridge_rbm_s_4_1_p_0 0x7004 0x7007 0x7008 0x7008 spio_noc.bridge_rbm_s_4_1_p_1 spio_noc.bridge_rbm_s_4_1_p_1 0x700C 0x700F 0x7010 0x7010 spio_noc.bridge_rbm_s_4_1_p_2 spio_noc.bridge_rbm_s_4_1_p_2 0x7014 0x7017 0x7018 0x7018 spio_noc.bridge_rbm_s_4_1_p_3 spio_noc.bridge_rbm_s_4_1_p_3 0x701C 0x703F 0x7040 0x7040 spio_noc.bridge_rbm_s_4_1_txe spio_noc.bridge_rbm_s_4_1_txe 0x7044 0x7047 0x7048 0x7048 spio_noc.bridge_rbm_s_4_1_txem spio_noc.bridge_rbm_s_4_1_txem 0x704C 0x7057 0x7058 0x7058 spio_noc.bridge_rbm_s_4_1_btus_0 spio_noc.bridge_rbm_s_4_1_btus_0 0x705C 0x705F 0x7060 0x7060 spio_noc.bridge_rbm_s_4_1_btus_1 spio_noc.bridge_rbm_s_4_1_btus_1 0x7064 0x707F 0x7080 0x7080 spio_noc.bridge_rbm_s_4_1_btrl_0 spio_noc.bridge_rbm_s_4_1_btrl_0 0x7084 0x7087 0x7088 0x7088 spio_noc.bridge_rbm_s_4_1_btrl_1 spio_noc.bridge_rbm_s_4_1_btrl_1 0x708C 0x708F 0x7090 0x7090 spio_noc.bridge_rbm_s_4_1_btrl_2 spio_noc.bridge_rbm_s_4_1_btrl_2 0x7094 0x7097 0x7098 0x7098 spio_noc.bridge_rbm_s_4_1_btrl_3 spio_noc.bridge_rbm_s_4_1_btrl_3 0x709C 0x70A7 0x70A8 0x70A8 spio_noc.bridge_rbm_s_4_1_btperr spio_noc.bridge_rbm_s_4_1_btperr 0x70AC 0x70AF 0x70B0 0x70B0 spio_noc.bridge_rbm_s_4_1_btperrm spio_noc.bridge_rbm_s_4_1_btperrm 0x70B4 0x711F 0x7120 0x7120 spio_noc.bridge_rbm_s_4_1_rxe spio_noc.bridge_rbm_s_4_1_rxe 0x7124 0x7127 0x7128 0x7128 spio_noc.bridge_rbm_s_4_1_rxem spio_noc.bridge_rbm_s_4_1_rxem 0x712C 0x712F 0x7130 0x7130 spio_noc.bridge_rbm_s_4_1_brs_0 spio_noc.bridge_rbm_s_4_1_brs_0 0x7134 0x7137 0x7138 0x7138 spio_noc.bridge_rbm_s_4_1_brs_1 spio_noc.bridge_rbm_s_4_1_brs_1 0x713C 0x71AF 0x71B0 0x71B0 spio_noc.bridge_rbm_s_4_1_brus spio_noc.bridge_rbm_s_4_1_brus 0x71B4 0x71CF 0x71D0 0x71D0 spio_noc.bridge_rbm_s_4_1_brperr0 spio_noc.bridge_rbm_s_4_1_brperr0 0x71D8 0x71D8 spio_noc.bridge_rbm_s_4_1_brperr1 spio_noc.bridge_rbm_s_4_1_brperr1 0x71E0 0x71E0 spio_noc.bridge_rbm_s_4_1_brperrm0 spio_noc.bridge_rbm_s_4_1_brperrm0 0x71E8 0x71E8 spio_noc.bridge_rbm_s_4_1_brperrm1 spio_noc.bridge_rbm_s_4_1_brperrm1 0x71F0 0x9C0F 0x9C10 0x9C10 spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_cgc spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_cgc 0x9C18 0x9C18 spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_cgo spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_cgo 0x9C20 0x9CFF 0x9D00 0x9D00 spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_sts spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_sts 0x9D08 0x9D08 spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_bridge_id spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_bridge_id 0x9D10 0x9DFF 0x9E00 0x9E00 spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_err spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_err 0x9E08 0x9E3F 0x9E40 0x9E40 spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_intm spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_intm 0x9E48 0x9EFF 0x9F00 0x9F00 spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_ccmd spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_ccmd 0x9F08 0x9F08 spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_ccmdmsk spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_ccmdmsk 0x9F10 0x9F10 spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_cntr spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_cntr 0x9F18 0x9F18 spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_arovrd spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_arovrd 0x9F20 0x9F20 spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_awovrd spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_awovrd 0x9F28 0xAFFF 0xB000 0xB000 spio_noc.bridge_spio_p00_axi_comm_s_5_7_p_0 spio_noc.bridge_spio_p00_axi_comm_s_5_7_p_0 0xB004 0xB007 0xB008 0xB008 spio_noc.bridge_spio_p00_axi_comm_s_5_7_p_1 spio_noc.bridge_spio_p00_axi_comm_s_5_7_p_1 0xB00C 0xB00F 0xB010 0xB010 spio_noc.bridge_spio_p00_axi_comm_s_5_7_p_2 spio_noc.bridge_spio_p00_axi_comm_s_5_7_p_2 0xB014 0xB017 0xB018 0xB018 spio_noc.bridge_spio_p00_axi_comm_s_5_7_p_3 spio_noc.bridge_spio_p00_axi_comm_s_5_7_p_3 0xB01C 0xB03F 0xB040 0xB040 spio_noc.bridge_spio_p00_axi_comm_s_5_7_txe spio_noc.bridge_spio_p00_axi_comm_s_5_7_txe 0xB044 0xB047 0xB048 0xB048 spio_noc.bridge_spio_p00_axi_comm_s_5_7_txem spio_noc.bridge_spio_p00_axi_comm_s_5_7_txem 0xB04C 0xB057 0xB058 0xB058 spio_noc.bridge_spio_p00_axi_comm_s_5_7_btus_0 spio_noc.bridge_spio_p00_axi_comm_s_5_7_btus_0 0xB05C 0xB05F 0xB060 0xB060 spio_noc.bridge_spio_p00_axi_comm_s_5_7_btus_1 spio_noc.bridge_spio_p00_axi_comm_s_5_7_btus_1 0xB064 0xB07F 0xB080 0xB080 spio_noc.bridge_spio_p00_axi_comm_s_5_7_btrl_0 spio_noc.bridge_spio_p00_axi_comm_s_5_7_btrl_0 0xB084 0xB087 0xB088 0xB088 spio_noc.bridge_spio_p00_axi_comm_s_5_7_btrl_1 spio_noc.bridge_spio_p00_axi_comm_s_5_7_btrl_1 0xB08C 0xB08F 0xB090 0xB090 spio_noc.bridge_spio_p00_axi_comm_s_5_7_btrl_2 spio_noc.bridge_spio_p00_axi_comm_s_5_7_btrl_2 0xB094 0xB097 0xB098 0xB098 spio_noc.bridge_spio_p00_axi_comm_s_5_7_btrl_3 spio_noc.bridge_spio_p00_axi_comm_s_5_7_btrl_3 0xB09C 0xB0A7 0xB0A8 0xB0A8 spio_noc.bridge_spio_p00_axi_comm_s_5_7_btperr spio_noc.bridge_spio_p00_axi_comm_s_5_7_btperr 0xB0AC 0xB0AF 0xB0B0 0xB0B0 spio_noc.bridge_spio_p00_axi_comm_s_5_7_btperrm spio_noc.bridge_spio_p00_axi_comm_s_5_7_btperrm 0xB0B4 0xB11F 0xB120 0xB120 spio_noc.bridge_spio_p00_axi_comm_s_5_7_rxe spio_noc.bridge_spio_p00_axi_comm_s_5_7_rxe 0xB124 0xB127 0xB128 0xB128 spio_noc.bridge_spio_p00_axi_comm_s_5_7_rxem spio_noc.bridge_spio_p00_axi_comm_s_5_7_rxem 0xB12C 0xB12F 0xB130 0xB130 spio_noc.bridge_spio_p00_axi_comm_s_5_7_brs_0 spio_noc.bridge_spio_p00_axi_comm_s_5_7_brs_0 0xB134 0xB137 0xB138 0xB138 spio_noc.bridge_spio_p00_axi_comm_s_5_7_brs_1 spio_noc.bridge_spio_p00_axi_comm_s_5_7_brs_1 0xB13C 0xB1AF 0xB1B0 0xB1B0 spio_noc.bridge_spio_p00_axi_comm_s_5_7_brus spio_noc.bridge_spio_p00_axi_comm_s_5_7_brus 0xB1B4 0xB1CF 0xB1D0 0xB1D0 spio_noc.bridge_spio_p00_axi_comm_s_5_7_brperr0 spio_noc.bridge_spio_p00_axi_comm_s_5_7_brperr0 0xB1D8 0xB1D8 spio_noc.bridge_spio_p00_axi_comm_s_5_7_brperr1 spio_noc.bridge_spio_p00_axi_comm_s_5_7_brperr1 0xB1E0 0xB1E0 spio_noc.bridge_spio_p00_axi_comm_s_5_7_brperrm0 spio_noc.bridge_spio_p00_axi_comm_s_5_7_brperrm0 0xB1E8 0xB1E8 spio_noc.bridge_spio_p00_axi_comm_s_5_7_brperrm1 spio_noc.bridge_spio_p00_axi_comm_s_5_7_brperrm1 0xB1F0 0xC1FF 0xC200 0xC200 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_ahbs_ctl spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_ahbs_ctl 0xC208 0xC208 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_ahbs_sts spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_ahbs_sts 0xC210 0xC210 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_ahbs_im spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_ahbs_im 0xC218 0xDC0F 0xDC10 0xDC10 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_cgc spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_cgc 0xDC18 0xDC18 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_cgo spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_cgo 0xDC20 0xDCFF 0xDD00 0xDD00 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_sts spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_sts 0xDD08 0xDD08 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_bridge_id spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_bridge_id 0xDD10 0xDDFF 0xDE00 0xDE00 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_err spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_err 0xDE08 0xDE3F 0xDE40 0xDE40 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_intm spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_intm 0xDE48 0xDEFF 0xDF00 0xDF00 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_ccmd spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_ccmd 0xDF08 0xDF08 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_ccmdmsk spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_ccmdmsk 0xDF10 0xDF10 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_cntr spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_cntr 0xDF18 0xDF18 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_arovrd spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_arovrd 0xDF20 0xDF20 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_awovrd spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_awovrd 0xDF28 0xEFFF 0xF000 0xF000 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_p_0 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_p_0 0xF004 0xF007 0xF008 0xF008 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_p_1 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_p_1 0xF00C 0xF00F 0xF010 0xF010 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_p_2 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_p_2 0xF014 0xF017 0xF018 0xF018 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_p_3 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_p_3 0xF01C 0xF03F 0xF040 0xF040 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_txe spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_txe 0xF044 0xF047 0xF048 0xF048 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_txem spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_txem 0xF04C 0xF057 0xF058 0xF058 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btus_0 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btus_0 0xF05C 0xF05F 0xF060 0xF060 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btus_1 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btus_1 0xF064 0xF07F 0xF080 0xF080 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btrl_0 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btrl_0 0xF084 0xF087 0xF088 0xF088 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btrl_1 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btrl_1 0xF08C 0xF08F 0xF090 0xF090 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btrl_2 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btrl_2 0xF094 0xF097 0xF098 0xF098 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btrl_3 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btrl_3 0xF09C 0xF0A7 0xF0A8 0xF0A8 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btperr spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btperr 0xF0AC 0xF0AF 0xF0B0 0xF0B0 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btperrm spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btperrm 0xF0B4 0xF11F 0xF120 0xF120 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_rxe spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_rxe 0xF124 0xF127 0xF128 0xF128 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_rxem spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_rxem 0xF12C 0xF12F 0xF130 0xF130 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_brs_0 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_brs_0 0xF134 0xF137 0xF138 0xF138 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_brs_1 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_brs_1 0xF13C 0xF1AF 0xF1B0 0xF1B0 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_brus spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_brus 0xF1B4 0xF1CF 0xF1D0 0xF1D0 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_brperr0 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_brperr0 0xF1D8 0xF1D8 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_brperr1 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_brperr1 0xF1E0 0xF1E0 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_brperrm0 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_brperrm0 0xF1E8 0xF1E8 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_brperrm1 spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_brperrm1 0xF1F0 0xFFFF 0x10000 0x10000 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 0x10008 0x10008 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 0x10010 0x1001F 0x10020 0x10020 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 0x10028 0x10028 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 0x10030 0x1003F 0x10040 0x10040 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 0x10048 0x10048 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 0x10050 0x1005F 0x10060 0x10060 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 0x10068 0x10068 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 0x10070 0x1007F 0x10080 0x10080 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 0x10088 0x10088 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 0x10090 0x1009F 0x100A0 0x100A0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 0x100A8 0x100A8 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 0x100B0 0x100BF 0x100C0 0x100C0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 0x100C8 0x100C8 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 0x100D0 0x100DF 0x100E0 0x100E0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 0x100E8 0x100E8 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 0x100F0 0x100FF 0x10100 0x10100 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 0x10108 0x10108 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 0x10110 0x1011F 0x10120 0x10120 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 0x10128 0x10128 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 0x10130 0x1013F 0x10140 0x10140 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 0x10148 0x10148 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 0x10150 0x1015F 0x10160 0x10160 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 0x10168 0x10168 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 0x10170 0x1017F 0x10180 0x10180 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 0x10188 0x10188 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 0x10190 0x1019F 0x101A0 0x101A0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 0x101A8 0x101A8 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 0x101B0 0x101BF 0x101C0 0x101C0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 0x101C8 0x101C8 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 0x101D0 0x101DF 0x101E0 0x101E0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 0x101E8 0x101E8 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 0x101F0 0x101FF 0x10200 0x10200 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 0x10208 0x10208 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 0x10210 0x1021F 0x10220 0x10220 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 0x10228 0x10228 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 0x10230 0x1023F 0x10240 0x10240 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 0x10248 0x10248 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 0x10250 0x1025F 0x10260 0x10260 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 0x10268 0x10268 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 0x10270 0x1027F 0x10280 0x10280 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 0x10288 0x10288 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 0x10290 0x1029F 0x102A0 0x102A0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 0x102A8 0x102A8 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 0x102B0 0x102BF 0x102C0 0x102C0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 0x102C8 0x102C8 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 0x102D0 0x102DF 0x102E0 0x102E0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 0x102E8 0x102E8 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 0x102F0 0x102FF 0x10300 0x10300 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 0x10308 0x10308 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 0x10310 0x1031F 0x10320 0x10320 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 0x10328 0x10328 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 0x10330 0x1033F 0x10340 0x10340 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 0x10348 0x10348 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 0x10350 0x1035F 0x10360 0x10360 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 0x10368 0x10368 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 0x10370 0x1037F 0x10380 0x10380 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 0x10388 0x10388 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 0x10390 0x1039F 0x103A0 0x103A0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 0x103A8 0x103A8 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 0x103B0 0x103BF 0x103C0 0x103C0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 0x103C8 0x103C8 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 0x103D0 0x103DF 0x103E0 0x103E0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 0x103E8 0x103E8 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 0x103F0 0x103FF 0x10400 0x10400 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 0x10408 0x10408 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 0x10410 0x1041F 0x10420 0x10420 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 0x10428 0x10428 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 0x10430 0x1043F 0x10440 0x10440 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 0x10448 0x10448 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 0x10450 0x1045F 0x10460 0x10460 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 0x10468 0x10468 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 0x10470 0x1047F 0x10480 0x10480 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 0x10488 0x10488 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 0x10490 0x1049F 0x104A0 0x104A0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 0x104A8 0x104A8 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 0x104B0 0x104BF 0x104C0 0x104C0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 0x104C8 0x104C8 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 0x104D0 0x104DF 0x104E0 0x104E0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 0x104E8 0x104E8 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 0x104F0 0x104FF 0x10500 0x10500 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 0x10508 0x10508 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 0x10510 0x1051F 0x10520 0x10520 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 0x10528 0x10528 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 0x10530 0x1053F 0x10540 0x10540 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 0x10548 0x10548 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 0x10550 0x1055F 0x10560 0x10560 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 0x10568 0x10568 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 0x10570 0x1057F 0x10580 0x10580 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 0x10588 0x10588 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 0x10590 0x1059F 0x105A0 0x105A0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 0x105A8 0x105A8 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 0x105B0 0x105BF 0x105C0 0x105C0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 0x105C8 0x105C8 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 0x105D0 0x105DF 0x105E0 0x105E0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 0x105E8 0x105E8 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 0x105F0 0x105FF 0x10600 0x10600 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 0x10608 0x10608 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 0x10610 0x1061F 0x10620 0x10620 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 0x10628 0x10628 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 0x10630 0x1063F 0x10640 0x10640 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 0x10648 0x10648 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 0x10650 0x1065F 0x10660 0x10660 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 0x10668 0x10668 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 0x10670 0x1067F 0x10680 0x10680 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 0x10688 0x10688 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 0x10690 0x1069F 0x106A0 0x106A0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 0x106A8 0x106A8 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 0x106B0 0x106BF 0x106C0 0x106C0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 0x106C8 0x106C8 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 0x106D0 0x106DF 0x106E0 0x106E0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 0x106E8 0x106E8 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 0x106F0 0x106FF 0x10700 0x10700 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 0x10708 0x10708 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 0x10710 0x1071F 0x10720 0x10720 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 0x10728 0x10728 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 0x10730 0x1073F 0x10740 0x10740 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 0x10748 0x10748 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 0x10750 0x1075F 0x10760 0x10760 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 0x10768 0x10768 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 0x10770 0x1077F 0x10780 0x10780 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 0x10788 0x10788 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 0x10790 0x1079F 0x107A0 0x107A0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 0x107A8 0x107A8 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 0x107B0 0x107BF 0x107C0 0x107C0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 0x107C8 0x107C8 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 0x107D0 0x107DF 0x107E0 0x107E0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 0x107E8 0x107E8 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 0x107F0 0x107FF 0x10800 0x10800 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 0x10808 0x10808 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 0x10810 0x1081F 0x10820 0x10820 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 0x10828 0x10828 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 0x10830 0x1083F 0x10840 0x10840 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 0x10848 0x10848 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 0x10850 0x1085F 0x10860 0x10860 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 0x10868 0x10868 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 0x10870 0x1087F 0x10880 0x10880 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 0x10888 0x10888 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 0x10890 0x12FFF 0x13000 0x13000 spio_noc.bridge_spio_p00_dma_am_m_0_7_p_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_p_0 0x13004 0x13007 0x13008 0x13008 spio_noc.bridge_spio_p00_dma_am_m_0_7_p_1 spio_noc.bridge_spio_p00_dma_am_m_0_7_p_1 0x1300C 0x1300F 0x13010 0x13010 spio_noc.bridge_spio_p00_dma_am_m_0_7_p_2 spio_noc.bridge_spio_p00_dma_am_m_0_7_p_2 0x13014 0x13017 0x13018 0x13018 spio_noc.bridge_spio_p00_dma_am_m_0_7_p_3 spio_noc.bridge_spio_p00_dma_am_m_0_7_p_3 0x1301C 0x1303F 0x13040 0x13040 spio_noc.bridge_spio_p00_dma_am_m_0_7_txe spio_noc.bridge_spio_p00_dma_am_m_0_7_txe 0x13044 0x13047 0x13048 0x13048 spio_noc.bridge_spio_p00_dma_am_m_0_7_txem spio_noc.bridge_spio_p00_dma_am_m_0_7_txem 0x1304C 0x13057 0x13058 0x13058 spio_noc.bridge_spio_p00_dma_am_m_0_7_btus_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_btus_0 0x1305C 0x1305F 0x13060 0x13060 spio_noc.bridge_spio_p00_dma_am_m_0_7_btus_1 spio_noc.bridge_spio_p00_dma_am_m_0_7_btus_1 0x13064 0x1307F 0x13080 0x13080 spio_noc.bridge_spio_p00_dma_am_m_0_7_btrl_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_btrl_0 0x13084 0x13087 0x13088 0x13088 spio_noc.bridge_spio_p00_dma_am_m_0_7_btrl_1 spio_noc.bridge_spio_p00_dma_am_m_0_7_btrl_1 0x1308C 0x1308F 0x13090 0x13090 spio_noc.bridge_spio_p00_dma_am_m_0_7_btrl_2 spio_noc.bridge_spio_p00_dma_am_m_0_7_btrl_2 0x13094 0x13097 0x13098 0x13098 spio_noc.bridge_spio_p00_dma_am_m_0_7_btrl_3 spio_noc.bridge_spio_p00_dma_am_m_0_7_btrl_3 0x1309C 0x130A7 0x130A8 0x130A8 spio_noc.bridge_spio_p00_dma_am_m_0_7_btperr spio_noc.bridge_spio_p00_dma_am_m_0_7_btperr 0x130AC 0x130AF 0x130B0 0x130B0 spio_noc.bridge_spio_p00_dma_am_m_0_7_btperrm spio_noc.bridge_spio_p00_dma_am_m_0_7_btperrm 0x130B4 0x1311F 0x13120 0x13120 spio_noc.bridge_spio_p00_dma_am_m_0_7_rxe spio_noc.bridge_spio_p00_dma_am_m_0_7_rxe 0x13124 0x13127 0x13128 0x13128 spio_noc.bridge_spio_p00_dma_am_m_0_7_rxem spio_noc.bridge_spio_p00_dma_am_m_0_7_rxem 0x1312C 0x1312F 0x13130 0x13130 spio_noc.bridge_spio_p00_dma_am_m_0_7_brs_0 spio_noc.bridge_spio_p00_dma_am_m_0_7_brs_0 0x13134 0x13137 0x13138 0x13138 spio_noc.bridge_spio_p00_dma_am_m_0_7_brs_1 spio_noc.bridge_spio_p00_dma_am_m_0_7_brs_1 0x1313C 0x131AF 0x131B0 0x131B0 spio_noc.bridge_spio_p00_dma_am_m_0_7_brus spio_noc.bridge_spio_p00_dma_am_m_0_7_brus 0x131B4 0x131CF 0x131D0 0x131D0 spio_noc.bridge_spio_p00_dma_am_m_0_7_brperr0 spio_noc.bridge_spio_p00_dma_am_m_0_7_brperr0 0x131D8 0x131D8 spio_noc.bridge_spio_p00_dma_am_m_0_7_brperr1 spio_noc.bridge_spio_p00_dma_am_m_0_7_brperr1 0x131E0 0x131E0 spio_noc.bridge_spio_p00_dma_am_m_0_7_brperrm0 spio_noc.bridge_spio_p00_dma_am_m_0_7_brperrm0 0x131E8 0x131E8 spio_noc.bridge_spio_p00_dma_am_m_0_7_brperrm1 spio_noc.bridge_spio_p00_dma_am_m_0_7_brperrm1 0x131F0 0x13BFF 0x13C00 0x13C00 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_tocfg spio_noc.bridge_spio_p00_dma_am_m_0_7_am_tocfg 0x13C08 0x13C08 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_osslv spio_noc.bridge_spio_p00_dma_am_m_0_7_am_osslv 0x13C10 0x13C10 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_cgc spio_noc.bridge_spio_p00_dma_am_m_0_7_am_cgc 0x13C18 0x13C18 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_cgo spio_noc.bridge_spio_p00_dma_am_m_0_7_am_cgo 0x13C20 0x13C20 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_cfg spio_noc.bridge_spio_p00_dma_am_m_0_7_am_cfg 0x13C28 0x13CFF 0x13D00 0x13D00 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_sts spio_noc.bridge_spio_p00_dma_am_m_0_7_am_sts 0x13D08 0x13D08 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_bridge_id spio_noc.bridge_spio_p00_dma_am_m_0_7_am_bridge_id 0x13D10 0x13DFF 0x13E00 0x13E00 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_err spio_noc.bridge_spio_p00_dma_am_m_0_7_am_err 0x13E08 0x13E08 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_toslvid spio_noc.bridge_spio_p00_dma_am_m_0_7_am_toslvid 0x13E10 0x13E10 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_era spio_noc.bridge_spio_p00_dma_am_m_0_7_am_era 0x13E18 0x13E18 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_ewa spio_noc.bridge_spio_p00_dma_am_m_0_7_am_ewa 0x13E20 0x13E3F 0x13E40 0x13E40 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_intm spio_noc.bridge_spio_p00_dma_am_m_0_7_am_intm 0x13E48 0x13EFF 0x13F00 0x13F00 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_caddr spio_noc.bridge_spio_p00_dma_am_m_0_7_am_caddr 0x13F08 0x13F08 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_caddrmsk spio_noc.bridge_spio_p00_dma_am_m_0_7_am_caddrmsk 0x13F10 0x13F10 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_ccmd0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_ccmd0 0x13F18 0x13F18 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_ccmdmsk0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_ccmdmsk0 0x13F20 0x13F20 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_cntr0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_cntr0 0x13F28 0x13F28 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_latnum0 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_latnum0 0x13F30 0x13F30 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_ccmd1 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_ccmd1 0x13F38 0x13F38 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_ccmdmsk1 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_ccmdmsk1 0x13F40 0x13F40 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_cntr1 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_cntr1 0x13F48 0x13F48 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_latnum1 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_latnum1 0x13F50 0x13F5F 0x13F60 0x13F60 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_arovrd spio_noc.bridge_spio_p00_dma_am_m_0_7_am_arovrd 0x13F68 0x13F68 spio_noc.bridge_spio_p00_dma_am_m_0_7_am_awovrd spio_noc.bridge_spio_p00_dma_am_m_0_7_am_awovrd 0x13F70 0x13FFF 0x14000 0x14000 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 0x14008 0x14008 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 0x14010 0x1401F 0x14020 0x14020 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 0x14028 0x14028 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 0x14030 0x1403F 0x14040 0x14040 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 0x14048 0x14048 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 0x14050 0x1405F 0x14060 0x14060 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 0x14068 0x14068 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 0x14070 0x1407F 0x14080 0x14080 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 0x14088 0x14088 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 0x14090 0x1409F 0x140A0 0x140A0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 0x140A8 0x140A8 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 0x140B0 0x140BF 0x140C0 0x140C0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 0x140C8 0x140C8 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 0x140D0 0x140DF 0x140E0 0x140E0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 0x140E8 0x140E8 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 0x140F0 0x140FF 0x14100 0x14100 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 0x14108 0x14108 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 0x14110 0x1411F 0x14120 0x14120 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 0x14128 0x14128 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 0x14130 0x1413F 0x14140 0x14140 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 0x14148 0x14148 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 0x14150 0x1415F 0x14160 0x14160 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 0x14168 0x14168 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 0x14170 0x1417F 0x14180 0x14180 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 0x14188 0x14188 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 0x14190 0x1419F 0x141A0 0x141A0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 0x141A8 0x141A8 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 0x141B0 0x141BF 0x141C0 0x141C0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 0x141C8 0x141C8 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 0x141D0 0x141DF 0x141E0 0x141E0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 0x141E8 0x141E8 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 0x141F0 0x141FF 0x14200 0x14200 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 0x14208 0x14208 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 0x14210 0x1421F 0x14220 0x14220 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 0x14228 0x14228 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 0x14230 0x1423F 0x14240 0x14240 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 0x14248 0x14248 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 0x14250 0x1425F 0x14260 0x14260 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 0x14268 0x14268 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 0x14270 0x1427F 0x14280 0x14280 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 0x14288 0x14288 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 0x14290 0x1429F 0x142A0 0x142A0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 0x142A8 0x142A8 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 0x142B0 0x142BF 0x142C0 0x142C0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 0x142C8 0x142C8 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 0x142D0 0x142DF 0x142E0 0x142E0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 0x142E8 0x142E8 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 0x142F0 0x142FF 0x14300 0x14300 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 0x14308 0x14308 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 0x14310 0x1431F 0x14320 0x14320 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 0x14328 0x14328 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 0x14330 0x1433F 0x14340 0x14340 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 0x14348 0x14348 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 0x14350 0x1435F 0x14360 0x14360 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 0x14368 0x14368 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 0x14370 0x1437F 0x14380 0x14380 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 0x14388 0x14388 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 0x14390 0x1439F 0x143A0 0x143A0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 0x143A8 0x143A8 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 0x143B0 0x143BF 0x143C0 0x143C0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 0x143C8 0x143C8 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 0x143D0 0x143DF 0x143E0 0x143E0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 0x143E8 0x143E8 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 0x143F0 0x143FF 0x14400 0x14400 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 0x14408 0x14408 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 0x14410 0x1441F 0x14420 0x14420 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 0x14428 0x14428 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 0x14430 0x1443F 0x14440 0x14440 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 0x14448 0x14448 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 0x14450 0x1445F 0x14460 0x14460 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 0x14468 0x14468 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 0x14470 0x1447F 0x14480 0x14480 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 0x14488 0x14488 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 0x14490 0x1449F 0x144A0 0x144A0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 0x144A8 0x144A8 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 0x144B0 0x144BF 0x144C0 0x144C0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 0x144C8 0x144C8 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 0x144D0 0x144DF 0x144E0 0x144E0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 0x144E8 0x144E8 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 0x144F0 0x144FF 0x14500 0x14500 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 0x14508 0x14508 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 0x14510 0x1451F 0x14520 0x14520 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 0x14528 0x14528 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 0x14530 0x1453F 0x14540 0x14540 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 0x14548 0x14548 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 0x14550 0x1455F 0x14560 0x14560 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 0x14568 0x14568 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 0x14570 0x1457F 0x14580 0x14580 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 0x14588 0x14588 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 0x14590 0x1459F 0x145A0 0x145A0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 0x145A8 0x145A8 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 0x145B0 0x145BF 0x145C0 0x145C0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 0x145C8 0x145C8 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 0x145D0 0x145DF 0x145E0 0x145E0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 0x145E8 0x145E8 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 0x145F0 0x145FF 0x14600 0x14600 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 0x14608 0x14608 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 0x14610 0x1461F 0x14620 0x14620 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 0x14628 0x14628 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 0x14630 0x1463F 0x14640 0x14640 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 0x14648 0x14648 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 0x14650 0x1465F 0x14660 0x14660 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 0x14668 0x14668 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 0x14670 0x1467F 0x14680 0x14680 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 0x14688 0x14688 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 0x14690 0x1469F 0x146A0 0x146A0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 0x146A8 0x146A8 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 0x146B0 0x146BF 0x146C0 0x146C0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 0x146C8 0x146C8 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 0x146D0 0x146DF 0x146E0 0x146E0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 0x146E8 0x146E8 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 0x146F0 0x146FF 0x14700 0x14700 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 0x14708 0x14708 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 0x14710 0x1471F 0x14720 0x14720 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 0x14728 0x14728 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 0x14730 0x1473F 0x14740 0x14740 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 0x14748 0x14748 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 0x14750 0x1475F 0x14760 0x14760 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 0x14768 0x14768 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 0x14770 0x1477F 0x14780 0x14780 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 0x14788 0x14788 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 0x14790 0x1479F 0x147A0 0x147A0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 0x147A8 0x147A8 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 0x147B0 0x147BF 0x147C0 0x147C0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 0x147C8 0x147C8 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 0x147D0 0x147DF 0x147E0 0x147E0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 0x147E8 0x147E8 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 0x147F0 0x147FF 0x14800 0x14800 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 0x14808 0x14808 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 0x14810 0x1481F 0x14820 0x14820 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 0x14828 0x14828 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 0x14830 0x1483F 0x14840 0x14840 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 0x14848 0x14848 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 0x14850 0x1485F 0x14860 0x14860 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 0x14868 0x14868 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 0x14870 0x1487F 0x14880 0x14880 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 0x14888 0x14888 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 0x14890 0x16FFF 0x17000 0x17000 spio_noc.bridge_spio_p00_dma_m_1_7_p_0 spio_noc.bridge_spio_p00_dma_m_1_7_p_0 0x17004 0x17007 0x17008 0x17008 spio_noc.bridge_spio_p00_dma_m_1_7_p_1 spio_noc.bridge_spio_p00_dma_m_1_7_p_1 0x1700C 0x1700F 0x17010 0x17010 spio_noc.bridge_spio_p00_dma_m_1_7_p_2 spio_noc.bridge_spio_p00_dma_m_1_7_p_2 0x17014 0x17017 0x17018 0x17018 spio_noc.bridge_spio_p00_dma_m_1_7_p_3 spio_noc.bridge_spio_p00_dma_m_1_7_p_3 0x1701C 0x1703F 0x17040 0x17040 spio_noc.bridge_spio_p00_dma_m_1_7_txe spio_noc.bridge_spio_p00_dma_m_1_7_txe 0x17044 0x17047 0x17048 0x17048 spio_noc.bridge_spio_p00_dma_m_1_7_txem spio_noc.bridge_spio_p00_dma_m_1_7_txem 0x1704C 0x17057 0x17058 0x17058 spio_noc.bridge_spio_p00_dma_m_1_7_btus_0 spio_noc.bridge_spio_p00_dma_m_1_7_btus_0 0x1705C 0x1705F 0x17060 0x17060 spio_noc.bridge_spio_p00_dma_m_1_7_btus_1 spio_noc.bridge_spio_p00_dma_m_1_7_btus_1 0x17064 0x1707F 0x17080 0x17080 spio_noc.bridge_spio_p00_dma_m_1_7_btrl_0 spio_noc.bridge_spio_p00_dma_m_1_7_btrl_0 0x17084 0x17087 0x17088 0x17088 spio_noc.bridge_spio_p00_dma_m_1_7_btrl_1 spio_noc.bridge_spio_p00_dma_m_1_7_btrl_1 0x1708C 0x1708F 0x17090 0x17090 spio_noc.bridge_spio_p00_dma_m_1_7_btrl_2 spio_noc.bridge_spio_p00_dma_m_1_7_btrl_2 0x17094 0x17097 0x17098 0x17098 spio_noc.bridge_spio_p00_dma_m_1_7_btrl_3 spio_noc.bridge_spio_p00_dma_m_1_7_btrl_3 0x1709C 0x170A7 0x170A8 0x170A8 spio_noc.bridge_spio_p00_dma_m_1_7_btperr spio_noc.bridge_spio_p00_dma_m_1_7_btperr 0x170AC 0x170AF 0x170B0 0x170B0 spio_noc.bridge_spio_p00_dma_m_1_7_btperrm spio_noc.bridge_spio_p00_dma_m_1_7_btperrm 0x170B4 0x1711F 0x17120 0x17120 spio_noc.bridge_spio_p00_dma_m_1_7_rxe spio_noc.bridge_spio_p00_dma_m_1_7_rxe 0x17124 0x17127 0x17128 0x17128 spio_noc.bridge_spio_p00_dma_m_1_7_rxem spio_noc.bridge_spio_p00_dma_m_1_7_rxem 0x1712C 0x1712F 0x17130 0x17130 spio_noc.bridge_spio_p00_dma_m_1_7_brs_0 spio_noc.bridge_spio_p00_dma_m_1_7_brs_0 0x17134 0x17137 0x17138 0x17138 spio_noc.bridge_spio_p00_dma_m_1_7_brs_1 spio_noc.bridge_spio_p00_dma_m_1_7_brs_1 0x1713C 0x171AF 0x171B0 0x171B0 spio_noc.bridge_spio_p00_dma_m_1_7_brus spio_noc.bridge_spio_p00_dma_m_1_7_brus 0x171B4 0x171CF 0x171D0 0x171D0 spio_noc.bridge_spio_p00_dma_m_1_7_brperr0 spio_noc.bridge_spio_p00_dma_m_1_7_brperr0 0x171D8 0x171D8 spio_noc.bridge_spio_p00_dma_m_1_7_brperr1 spio_noc.bridge_spio_p00_dma_m_1_7_brperr1 0x171E0 0x171E0 spio_noc.bridge_spio_p00_dma_m_1_7_brperrm0 spio_noc.bridge_spio_p00_dma_m_1_7_brperrm0 0x171E8 0x171E8 spio_noc.bridge_spio_p00_dma_m_1_7_brperrm1 spio_noc.bridge_spio_p00_dma_m_1_7_brperrm1 0x171F0 0x17BFF 0x17C00 0x17C00 spio_noc.bridge_spio_p00_dma_m_1_7_am_tocfg spio_noc.bridge_spio_p00_dma_m_1_7_am_tocfg 0x17C08 0x17C08 spio_noc.bridge_spio_p00_dma_m_1_7_am_osslv spio_noc.bridge_spio_p00_dma_m_1_7_am_osslv 0x17C10 0x17C10 spio_noc.bridge_spio_p00_dma_m_1_7_am_cgc spio_noc.bridge_spio_p00_dma_m_1_7_am_cgc 0x17C18 0x17C18 spio_noc.bridge_spio_p00_dma_m_1_7_am_cgo spio_noc.bridge_spio_p00_dma_m_1_7_am_cgo 0x17C20 0x17C20 spio_noc.bridge_spio_p00_dma_m_1_7_am_cfg spio_noc.bridge_spio_p00_dma_m_1_7_am_cfg 0x17C28 0x17CFF 0x17D00 0x17D00 spio_noc.bridge_spio_p00_dma_m_1_7_am_sts spio_noc.bridge_spio_p00_dma_m_1_7_am_sts 0x17D08 0x17D08 spio_noc.bridge_spio_p00_dma_m_1_7_am_bridge_id spio_noc.bridge_spio_p00_dma_m_1_7_am_bridge_id 0x17D10 0x17DFF 0x17E00 0x17E00 spio_noc.bridge_spio_p00_dma_m_1_7_am_err spio_noc.bridge_spio_p00_dma_m_1_7_am_err 0x17E08 0x17E08 spio_noc.bridge_spio_p00_dma_m_1_7_am_toslvid spio_noc.bridge_spio_p00_dma_m_1_7_am_toslvid 0x17E10 0x17E10 spio_noc.bridge_spio_p00_dma_m_1_7_am_era spio_noc.bridge_spio_p00_dma_m_1_7_am_era 0x17E18 0x17E18 spio_noc.bridge_spio_p00_dma_m_1_7_am_ewa spio_noc.bridge_spio_p00_dma_m_1_7_am_ewa 0x17E20 0x17E3F 0x17E40 0x17E40 spio_noc.bridge_spio_p00_dma_m_1_7_am_intm spio_noc.bridge_spio_p00_dma_m_1_7_am_intm 0x17E48 0x17EFF 0x17F00 0x17F00 spio_noc.bridge_spio_p00_dma_m_1_7_am_caddr spio_noc.bridge_spio_p00_dma_m_1_7_am_caddr 0x17F08 0x17F08 spio_noc.bridge_spio_p00_dma_m_1_7_am_caddrmsk spio_noc.bridge_spio_p00_dma_m_1_7_am_caddrmsk 0x17F10 0x17F10 spio_noc.bridge_spio_p00_dma_m_1_7_am_ccmd0 spio_noc.bridge_spio_p00_dma_m_1_7_am_ccmd0 0x17F18 0x17F18 spio_noc.bridge_spio_p00_dma_m_1_7_am_ccmdmsk0 spio_noc.bridge_spio_p00_dma_m_1_7_am_ccmdmsk0 0x17F20 0x17F20 spio_noc.bridge_spio_p00_dma_m_1_7_am_cntr0 spio_noc.bridge_spio_p00_dma_m_1_7_am_cntr0 0x17F28 0x17F28 spio_noc.bridge_spio_p00_dma_m_1_7_am_latnum0 spio_noc.bridge_spio_p00_dma_m_1_7_am_latnum0 0x17F30 0x17F30 spio_noc.bridge_spio_p00_dma_m_1_7_am_ccmd1 spio_noc.bridge_spio_p00_dma_m_1_7_am_ccmd1 0x17F38 0x17F38 spio_noc.bridge_spio_p00_dma_m_1_7_am_ccmdmsk1 spio_noc.bridge_spio_p00_dma_m_1_7_am_ccmdmsk1 0x17F40 0x17F40 spio_noc.bridge_spio_p00_dma_m_1_7_am_cntr1 spio_noc.bridge_spio_p00_dma_m_1_7_am_cntr1 0x17F48 0x17F48 spio_noc.bridge_spio_p00_dma_m_1_7_am_latnum1 spio_noc.bridge_spio_p00_dma_m_1_7_am_latnum1 0x17F50 0x17F5F 0x17F60 0x17F60 spio_noc.bridge_spio_p00_dma_m_1_7_am_arovrd spio_noc.bridge_spio_p00_dma_m_1_7_am_arovrd 0x17F68 0x17F68 spio_noc.bridge_spio_p00_dma_m_1_7_am_awovrd spio_noc.bridge_spio_p00_dma_m_1_7_am_awovrd 0x17F70 0x17FFF 0x18000 0x18000 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 0x18008 0x18008 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 0x18010 0x1801F 0x18020 0x18020 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 0x18028 0x18028 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 0x18030 0x1803F 0x18040 0x18040 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 0x18048 0x18048 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 0x18050 0x1805F 0x18060 0x18060 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 0x18068 0x18068 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 0x18070 0x1807F 0x18080 0x18080 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 0x18088 0x18088 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 0x18090 0x1809F 0x180A0 0x180A0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 0x180A8 0x180A8 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 0x180B0 0x180BF 0x180C0 0x180C0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 0x180C8 0x180C8 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 0x180D0 0x180DF 0x180E0 0x180E0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 0x180E8 0x180E8 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 0x180F0 0x180FF 0x18100 0x18100 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 0x18108 0x18108 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 0x18110 0x1811F 0x18120 0x18120 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 0x18128 0x18128 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 0x18130 0x1813F 0x18140 0x18140 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 0x18148 0x18148 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 0x18150 0x1815F 0x18160 0x18160 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 0x18168 0x18168 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 0x18170 0x1817F 0x18180 0x18180 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 0x18188 0x18188 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 0x18190 0x1819F 0x181A0 0x181A0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 0x181A8 0x181A8 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 0x181B0 0x181BF 0x181C0 0x181C0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 0x181C8 0x181C8 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 0x181D0 0x181DF 0x181E0 0x181E0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 0x181E8 0x181E8 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 0x181F0 0x181FF 0x18200 0x18200 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 0x18208 0x18208 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 0x18210 0x1821F 0x18220 0x18220 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 0x18228 0x18228 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 0x18230 0x1823F 0x18240 0x18240 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 0x18248 0x18248 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 0x18250 0x1825F 0x18260 0x18260 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 0x18268 0x18268 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 0x18270 0x1827F 0x18280 0x18280 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 0x18288 0x18288 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 0x18290 0x1829F 0x182A0 0x182A0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 0x182A8 0x182A8 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 0x182B0 0x182BF 0x182C0 0x182C0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 0x182C8 0x182C8 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 0x182D0 0x182DF 0x182E0 0x182E0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 0x182E8 0x182E8 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 0x182F0 0x182FF 0x18300 0x18300 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 0x18308 0x18308 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 0x18310 0x1831F 0x18320 0x18320 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 0x18328 0x18328 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 0x18330 0x1833F 0x18340 0x18340 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 0x18348 0x18348 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 0x18350 0x1835F 0x18360 0x18360 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 0x18368 0x18368 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 0x18370 0x1837F 0x18380 0x18380 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 0x18388 0x18388 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 0x18390 0x1839F 0x183A0 0x183A0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 0x183A8 0x183A8 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 0x183B0 0x183BF 0x183C0 0x183C0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 0x183C8 0x183C8 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 0x183D0 0x183DF 0x183E0 0x183E0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 0x183E8 0x183E8 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 0x183F0 0x183FF 0x18400 0x18400 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 0x18408 0x18408 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 0x18410 0x1841F 0x18420 0x18420 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 0x18428 0x18428 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 0x18430 0x1843F 0x18440 0x18440 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 0x18448 0x18448 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 0x18450 0x1845F 0x18460 0x18460 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 0x18468 0x18468 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 0x18470 0x1847F 0x18480 0x18480 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 0x18488 0x18488 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 0x18490 0x1849F 0x184A0 0x184A0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 0x184A8 0x184A8 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 0x184B0 0x184BF 0x184C0 0x184C0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 0x184C8 0x184C8 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 0x184D0 0x184DF 0x184E0 0x184E0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 0x184E8 0x184E8 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 0x184F0 0x184FF 0x18500 0x18500 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 0x18508 0x18508 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 0x18510 0x1851F 0x18520 0x18520 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 0x18528 0x18528 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 0x18530 0x1853F 0x18540 0x18540 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 0x18548 0x18548 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 0x18550 0x1855F 0x18560 0x18560 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 0x18568 0x18568 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 0x18570 0x1857F 0x18580 0x18580 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 0x18588 0x18588 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 0x18590 0x1859F 0x185A0 0x185A0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 0x185A8 0x185A8 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 0x185B0 0x185BF 0x185C0 0x185C0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 0x185C8 0x185C8 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 0x185D0 0x185DF 0x185E0 0x185E0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 0x185E8 0x185E8 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 0x185F0 0x185FF 0x18600 0x18600 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 0x18608 0x18608 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 0x18610 0x1861F 0x18620 0x18620 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 0x18628 0x18628 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 0x18630 0x1863F 0x18640 0x18640 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 0x18648 0x18648 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 0x18650 0x1865F 0x18660 0x18660 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 0x18668 0x18668 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 0x18670 0x1867F 0x18680 0x18680 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 0x18688 0x18688 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 0x18690 0x1869F 0x186A0 0x186A0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 0x186A8 0x186A8 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 0x186B0 0x186BF 0x186C0 0x186C0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 0x186C8 0x186C8 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 0x186D0 0x186DF 0x186E0 0x186E0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 0x186E8 0x186E8 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 0x186F0 0x186FF 0x18700 0x18700 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 0x18708 0x18708 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 0x18710 0x1871F 0x18720 0x18720 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 0x18728 0x18728 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 0x18730 0x1873F 0x18740 0x18740 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 0x18748 0x18748 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 0x18750 0x1875F 0x18760 0x18760 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 0x18768 0x18768 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 0x18770 0x1877F 0x18780 0x18780 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 0x18788 0x18788 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 0x18790 0x1879F 0x187A0 0x187A0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 0x187A8 0x187A8 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 0x187B0 0x187BF 0x187C0 0x187C0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 0x187C8 0x187C8 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 0x187D0 0x187DF 0x187E0 0x187E0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 0x187E8 0x187E8 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 0x187F0 0x187FF 0x18800 0x18800 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 0x18808 0x18808 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 0x18810 0x1881F 0x18820 0x18820 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 0x18828 0x18828 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 0x18830 0x1883F 0x18840 0x18840 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 0x18848 0x18848 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 0x18850 0x1885F 0x18860 0x18860 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 0x18868 0x18868 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 0x18870 0x1887F 0x18880 0x18880 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 0x18888 0x18888 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 0x18890 0x1AFFF 0x1B000 0x1B000 spio_noc.bridge_spio_p00_rot_m_2_7_p_0 spio_noc.bridge_spio_p00_rot_m_2_7_p_0 0x1B004 0x1B007 0x1B008 0x1B008 spio_noc.bridge_spio_p00_rot_m_2_7_p_1 spio_noc.bridge_spio_p00_rot_m_2_7_p_1 0x1B00C 0x1B00F 0x1B010 0x1B010 spio_noc.bridge_spio_p00_rot_m_2_7_p_2 spio_noc.bridge_spio_p00_rot_m_2_7_p_2 0x1B014 0x1B017 0x1B018 0x1B018 spio_noc.bridge_spio_p00_rot_m_2_7_p_3 spio_noc.bridge_spio_p00_rot_m_2_7_p_3 0x1B01C 0x1B03F 0x1B040 0x1B040 spio_noc.bridge_spio_p00_rot_m_2_7_txe spio_noc.bridge_spio_p00_rot_m_2_7_txe 0x1B044 0x1B047 0x1B048 0x1B048 spio_noc.bridge_spio_p00_rot_m_2_7_txem spio_noc.bridge_spio_p00_rot_m_2_7_txem 0x1B04C 0x1B057 0x1B058 0x1B058 spio_noc.bridge_spio_p00_rot_m_2_7_btus_0 spio_noc.bridge_spio_p00_rot_m_2_7_btus_0 0x1B05C 0x1B05F 0x1B060 0x1B060 spio_noc.bridge_spio_p00_rot_m_2_7_btus_1 spio_noc.bridge_spio_p00_rot_m_2_7_btus_1 0x1B064 0x1B07F 0x1B080 0x1B080 spio_noc.bridge_spio_p00_rot_m_2_7_btrl_0 spio_noc.bridge_spio_p00_rot_m_2_7_btrl_0 0x1B084 0x1B087 0x1B088 0x1B088 spio_noc.bridge_spio_p00_rot_m_2_7_btrl_1 spio_noc.bridge_spio_p00_rot_m_2_7_btrl_1 0x1B08C 0x1B08F 0x1B090 0x1B090 spio_noc.bridge_spio_p00_rot_m_2_7_btrl_2 spio_noc.bridge_spio_p00_rot_m_2_7_btrl_2 0x1B094 0x1B097 0x1B098 0x1B098 spio_noc.bridge_spio_p00_rot_m_2_7_btrl_3 spio_noc.bridge_spio_p00_rot_m_2_7_btrl_3 0x1B09C 0x1B0A7 0x1B0A8 0x1B0A8 spio_noc.bridge_spio_p00_rot_m_2_7_btperr spio_noc.bridge_spio_p00_rot_m_2_7_btperr 0x1B0AC 0x1B0AF 0x1B0B0 0x1B0B0 spio_noc.bridge_spio_p00_rot_m_2_7_btperrm spio_noc.bridge_spio_p00_rot_m_2_7_btperrm 0x1B0B4 0x1B11F 0x1B120 0x1B120 spio_noc.bridge_spio_p00_rot_m_2_7_rxe spio_noc.bridge_spio_p00_rot_m_2_7_rxe 0x1B124 0x1B127 0x1B128 0x1B128 spio_noc.bridge_spio_p00_rot_m_2_7_rxem spio_noc.bridge_spio_p00_rot_m_2_7_rxem 0x1B12C 0x1B12F 0x1B130 0x1B130 spio_noc.bridge_spio_p00_rot_m_2_7_brs_0 spio_noc.bridge_spio_p00_rot_m_2_7_brs_0 0x1B134 0x1B137 0x1B138 0x1B138 spio_noc.bridge_spio_p00_rot_m_2_7_brs_1 spio_noc.bridge_spio_p00_rot_m_2_7_brs_1 0x1B13C 0x1B1AF 0x1B1B0 0x1B1B0 spio_noc.bridge_spio_p00_rot_m_2_7_brus spio_noc.bridge_spio_p00_rot_m_2_7_brus 0x1B1B4 0x1B1CF 0x1B1D0 0x1B1D0 spio_noc.bridge_spio_p00_rot_m_2_7_brperr0 spio_noc.bridge_spio_p00_rot_m_2_7_brperr0 0x1B1D8 0x1B1D8 spio_noc.bridge_spio_p00_rot_m_2_7_brperr1 spio_noc.bridge_spio_p00_rot_m_2_7_brperr1 0x1B1E0 0x1B1E0 spio_noc.bridge_spio_p00_rot_m_2_7_brperrm0 spio_noc.bridge_spio_p00_rot_m_2_7_brperrm0 0x1B1E8 0x1B1E8 spio_noc.bridge_spio_p00_rot_m_2_7_brperrm1 spio_noc.bridge_spio_p00_rot_m_2_7_brperrm1 0x1B1F0 0x1BBFF 0x1BC00 0x1BC00 spio_noc.bridge_spio_p00_rot_m_2_7_am_tocfg spio_noc.bridge_spio_p00_rot_m_2_7_am_tocfg 0x1BC08 0x1BC08 spio_noc.bridge_spio_p00_rot_m_2_7_am_osslv spio_noc.bridge_spio_p00_rot_m_2_7_am_osslv 0x1BC10 0x1BC10 spio_noc.bridge_spio_p00_rot_m_2_7_am_cgc spio_noc.bridge_spio_p00_rot_m_2_7_am_cgc 0x1BC18 0x1BC18 spio_noc.bridge_spio_p00_rot_m_2_7_am_cgo spio_noc.bridge_spio_p00_rot_m_2_7_am_cgo 0x1BC20 0x1BC20 spio_noc.bridge_spio_p00_rot_m_2_7_am_cfg spio_noc.bridge_spio_p00_rot_m_2_7_am_cfg 0x1BC28 0x1BCFF 0x1BD00 0x1BD00 spio_noc.bridge_spio_p00_rot_m_2_7_am_sts spio_noc.bridge_spio_p00_rot_m_2_7_am_sts 0x1BD08 0x1BD08 spio_noc.bridge_spio_p00_rot_m_2_7_am_bridge_id spio_noc.bridge_spio_p00_rot_m_2_7_am_bridge_id 0x1BD10 0x1BDFF 0x1BE00 0x1BE00 spio_noc.bridge_spio_p00_rot_m_2_7_am_err spio_noc.bridge_spio_p00_rot_m_2_7_am_err 0x1BE08 0x1BE08 spio_noc.bridge_spio_p00_rot_m_2_7_am_toslvid spio_noc.bridge_spio_p00_rot_m_2_7_am_toslvid 0x1BE10 0x1BE10 spio_noc.bridge_spio_p00_rot_m_2_7_am_era spio_noc.bridge_spio_p00_rot_m_2_7_am_era 0x1BE18 0x1BE18 spio_noc.bridge_spio_p00_rot_m_2_7_am_ewa spio_noc.bridge_spio_p00_rot_m_2_7_am_ewa 0x1BE20 0x1BE3F 0x1BE40 0x1BE40 spio_noc.bridge_spio_p00_rot_m_2_7_am_intm spio_noc.bridge_spio_p00_rot_m_2_7_am_intm 0x1BE48 0x1BEFF 0x1BF00 0x1BF00 spio_noc.bridge_spio_p00_rot_m_2_7_am_caddr spio_noc.bridge_spio_p00_rot_m_2_7_am_caddr 0x1BF08 0x1BF08 spio_noc.bridge_spio_p00_rot_m_2_7_am_caddrmsk spio_noc.bridge_spio_p00_rot_m_2_7_am_caddrmsk 0x1BF10 0x1BF10 spio_noc.bridge_spio_p00_rot_m_2_7_am_ccmd0 spio_noc.bridge_spio_p00_rot_m_2_7_am_ccmd0 0x1BF18 0x1BF18 spio_noc.bridge_spio_p00_rot_m_2_7_am_ccmdmsk0 spio_noc.bridge_spio_p00_rot_m_2_7_am_ccmdmsk0 0x1BF20 0x1BF20 spio_noc.bridge_spio_p00_rot_m_2_7_am_cntr0 spio_noc.bridge_spio_p00_rot_m_2_7_am_cntr0 0x1BF28 0x1BF28 spio_noc.bridge_spio_p00_rot_m_2_7_am_latnum0 spio_noc.bridge_spio_p00_rot_m_2_7_am_latnum0 0x1BF30 0x1BF30 spio_noc.bridge_spio_p00_rot_m_2_7_am_ccmd1 spio_noc.bridge_spio_p00_rot_m_2_7_am_ccmd1 0x1BF38 0x1BF38 spio_noc.bridge_spio_p00_rot_m_2_7_am_ccmdmsk1 spio_noc.bridge_spio_p00_rot_m_2_7_am_ccmdmsk1 0x1BF40 0x1BF40 spio_noc.bridge_spio_p00_rot_m_2_7_am_cntr1 spio_noc.bridge_spio_p00_rot_m_2_7_am_cntr1 0x1BF48 0x1BF48 spio_noc.bridge_spio_p00_rot_m_2_7_am_latnum1 spio_noc.bridge_spio_p00_rot_m_2_7_am_latnum1 0x1BF50 0x1BF5F 0x1BF60 0x1BF60 spio_noc.bridge_spio_p00_rot_m_2_7_am_arovrd spio_noc.bridge_spio_p00_rot_m_2_7_am_arovrd 0x1BF68 0x1BF68 spio_noc.bridge_spio_p00_rot_m_2_7_am_awovrd spio_noc.bridge_spio_p00_rot_m_2_7_am_awovrd 0x1BF70 0x1C1FF 0x1C200 0x1C200 spio_noc.bridge_spio_p10_apb0_s_7_8_apbslv_bridge_version spio_noc.bridge_spio_p10_apb0_s_7_8_apbslv_bridge_version 0x1C208 0x1C208 spio_noc.bridge_spio_p10_apb0_s_7_8_apbslv_bridge_id spio_noc.bridge_spio_p10_apb0_s_7_8_apbslv_bridge_id 0x1C210 0x1C210 spio_noc.bridge_spio_p10_apb0_s_7_8_apbslv_slvs_sleep_status spio_noc.bridge_spio_p10_apb0_s_7_8_apbslv_slvs_sleep_status 0x1C218 0x1DC0F 0x1DC10 0x1DC10 spio_noc.bridge_spio_p10_apb0_s_7_8_as_cgc spio_noc.bridge_spio_p10_apb0_s_7_8_as_cgc 0x1DC18 0x1DC18 spio_noc.bridge_spio_p10_apb0_s_7_8_as_cgo spio_noc.bridge_spio_p10_apb0_s_7_8_as_cgo 0x1DC20 0x1DCFF 0x1DD00 0x1DD00 spio_noc.bridge_spio_p10_apb0_s_7_8_as_sts spio_noc.bridge_spio_p10_apb0_s_7_8_as_sts 0x1DD08 0x1DD08 spio_noc.bridge_spio_p10_apb0_s_7_8_as_bridge_id spio_noc.bridge_spio_p10_apb0_s_7_8_as_bridge_id 0x1DD10 0x1DDFF 0x1DE00 0x1DE00 spio_noc.bridge_spio_p10_apb0_s_7_8_as_err spio_noc.bridge_spio_p10_apb0_s_7_8_as_err 0x1DE08 0x1DE3F 0x1DE40 0x1DE40 spio_noc.bridge_spio_p10_apb0_s_7_8_as_intm spio_noc.bridge_spio_p10_apb0_s_7_8_as_intm 0x1DE48 0x1DEFF 0x1DF00 0x1DF00 spio_noc.bridge_spio_p10_apb0_s_7_8_as_ccmd spio_noc.bridge_spio_p10_apb0_s_7_8_as_ccmd 0x1DF08 0x1DF08 spio_noc.bridge_spio_p10_apb0_s_7_8_as_ccmdmsk spio_noc.bridge_spio_p10_apb0_s_7_8_as_ccmdmsk 0x1DF10 0x1DF10 spio_noc.bridge_spio_p10_apb0_s_7_8_as_cntr spio_noc.bridge_spio_p10_apb0_s_7_8_as_cntr 0x1DF18 0x1DF18 spio_noc.bridge_spio_p10_apb0_s_7_8_as_arovrd spio_noc.bridge_spio_p10_apb0_s_7_8_as_arovrd 0x1DF20 0x1DF20 spio_noc.bridge_spio_p10_apb0_s_7_8_as_awovrd spio_noc.bridge_spio_p10_apb0_s_7_8_as_awovrd 0x1DF28 0x1EFFF 0x1F000 0x1F000 spio_noc.bridge_spio_p10_apb0_s_7_8_p_0 spio_noc.bridge_spio_p10_apb0_s_7_8_p_0 0x1F004 0x1F007 0x1F008 0x1F008 spio_noc.bridge_spio_p10_apb0_s_7_8_p_1 spio_noc.bridge_spio_p10_apb0_s_7_8_p_1 0x1F00C 0x1F00F 0x1F010 0x1F010 spio_noc.bridge_spio_p10_apb0_s_7_8_p_2 spio_noc.bridge_spio_p10_apb0_s_7_8_p_2 0x1F014 0x1F017 0x1F018 0x1F018 spio_noc.bridge_spio_p10_apb0_s_7_8_p_3 spio_noc.bridge_spio_p10_apb0_s_7_8_p_3 0x1F01C 0x1F03F 0x1F040 0x1F040 spio_noc.bridge_spio_p10_apb0_s_7_8_txe spio_noc.bridge_spio_p10_apb0_s_7_8_txe 0x1F044 0x1F047 0x1F048 0x1F048 spio_noc.bridge_spio_p10_apb0_s_7_8_txem spio_noc.bridge_spio_p10_apb0_s_7_8_txem 0x1F04C 0x1F057 0x1F058 0x1F058 spio_noc.bridge_spio_p10_apb0_s_7_8_btus_0 spio_noc.bridge_spio_p10_apb0_s_7_8_btus_0 0x1F05C 0x1F05F 0x1F060 0x1F060 spio_noc.bridge_spio_p10_apb0_s_7_8_btus_1 spio_noc.bridge_spio_p10_apb0_s_7_8_btus_1 0x1F064 0x1F07F 0x1F080 0x1F080 spio_noc.bridge_spio_p10_apb0_s_7_8_btrl_0 spio_noc.bridge_spio_p10_apb0_s_7_8_btrl_0 0x1F084 0x1F087 0x1F088 0x1F088 spio_noc.bridge_spio_p10_apb0_s_7_8_btrl_1 spio_noc.bridge_spio_p10_apb0_s_7_8_btrl_1 0x1F08C 0x1F08F 0x1F090 0x1F090 spio_noc.bridge_spio_p10_apb0_s_7_8_btrl_2 spio_noc.bridge_spio_p10_apb0_s_7_8_btrl_2 0x1F094 0x1F097 0x1F098 0x1F098 spio_noc.bridge_spio_p10_apb0_s_7_8_btrl_3 spio_noc.bridge_spio_p10_apb0_s_7_8_btrl_3 0x1F09C 0x1F0A7 0x1F0A8 0x1F0A8 spio_noc.bridge_spio_p10_apb0_s_7_8_btperr spio_noc.bridge_spio_p10_apb0_s_7_8_btperr 0x1F0AC 0x1F0AF 0x1F0B0 0x1F0B0 spio_noc.bridge_spio_p10_apb0_s_7_8_btperrm spio_noc.bridge_spio_p10_apb0_s_7_8_btperrm 0x1F0B4 0x1F11F 0x1F120 0x1F120 spio_noc.bridge_spio_p10_apb0_s_7_8_rxe spio_noc.bridge_spio_p10_apb0_s_7_8_rxe 0x1F124 0x1F127 0x1F128 0x1F128 spio_noc.bridge_spio_p10_apb0_s_7_8_rxem spio_noc.bridge_spio_p10_apb0_s_7_8_rxem 0x1F12C 0x1F12F 0x1F130 0x1F130 spio_noc.bridge_spio_p10_apb0_s_7_8_brs_0 spio_noc.bridge_spio_p10_apb0_s_7_8_brs_0 0x1F134 0x1F137 0x1F138 0x1F138 spio_noc.bridge_spio_p10_apb0_s_7_8_brs_1 spio_noc.bridge_spio_p10_apb0_s_7_8_brs_1 0x1F13C 0x1F1AF 0x1F1B0 0x1F1B0 spio_noc.bridge_spio_p10_apb0_s_7_8_brus spio_noc.bridge_spio_p10_apb0_s_7_8_brus 0x1F1B4 0x1F1CF 0x1F1D0 0x1F1D0 spio_noc.bridge_spio_p10_apb0_s_7_8_brperr0 spio_noc.bridge_spio_p10_apb0_s_7_8_brperr0 0x1F1D8 0x1F1D8 spio_noc.bridge_spio_p10_apb0_s_7_8_brperr1 spio_noc.bridge_spio_p10_apb0_s_7_8_brperr1 0x1F1E0 0x1F1E0 spio_noc.bridge_spio_p10_apb0_s_7_8_brperrm0 spio_noc.bridge_spio_p10_apb0_s_7_8_brperrm0 0x1F1E8 0x1F1E8 spio_noc.bridge_spio_p10_apb0_s_7_8_brperrm1 spio_noc.bridge_spio_p10_apb0_s_7_8_brperrm1 0x1F1F0 0x201FF 0x20200 0x20200 spio_noc.bridge_spio_p10_apb1_s_8_8_apbslv_bridge_version spio_noc.bridge_spio_p10_apb1_s_8_8_apbslv_bridge_version 0x20208 0x20208 spio_noc.bridge_spio_p10_apb1_s_8_8_apbslv_bridge_id spio_noc.bridge_spio_p10_apb1_s_8_8_apbslv_bridge_id 0x20210 0x20210 spio_noc.bridge_spio_p10_apb1_s_8_8_apbslv_slvs_sleep_status spio_noc.bridge_spio_p10_apb1_s_8_8_apbslv_slvs_sleep_status 0x20218 0x21C0F 0x21C10 0x21C10 spio_noc.bridge_spio_p10_apb1_s_8_8_as_cgc spio_noc.bridge_spio_p10_apb1_s_8_8_as_cgc 0x21C18 0x21C18 spio_noc.bridge_spio_p10_apb1_s_8_8_as_cgo spio_noc.bridge_spio_p10_apb1_s_8_8_as_cgo 0x21C20 0x21CFF 0x21D00 0x21D00 spio_noc.bridge_spio_p10_apb1_s_8_8_as_sts spio_noc.bridge_spio_p10_apb1_s_8_8_as_sts 0x21D08 0x21D08 spio_noc.bridge_spio_p10_apb1_s_8_8_as_bridge_id spio_noc.bridge_spio_p10_apb1_s_8_8_as_bridge_id 0x21D10 0x21DFF 0x21E00 0x21E00 spio_noc.bridge_spio_p10_apb1_s_8_8_as_err spio_noc.bridge_spio_p10_apb1_s_8_8_as_err 0x21E08 0x21E3F 0x21E40 0x21E40 spio_noc.bridge_spio_p10_apb1_s_8_8_as_intm spio_noc.bridge_spio_p10_apb1_s_8_8_as_intm 0x21E48 0x21EFF 0x21F00 0x21F00 spio_noc.bridge_spio_p10_apb1_s_8_8_as_ccmd spio_noc.bridge_spio_p10_apb1_s_8_8_as_ccmd 0x21F08 0x21F08 spio_noc.bridge_spio_p10_apb1_s_8_8_as_ccmdmsk spio_noc.bridge_spio_p10_apb1_s_8_8_as_ccmdmsk 0x21F10 0x21F10 spio_noc.bridge_spio_p10_apb1_s_8_8_as_cntr spio_noc.bridge_spio_p10_apb1_s_8_8_as_cntr 0x21F18 0x21F18 spio_noc.bridge_spio_p10_apb1_s_8_8_as_arovrd spio_noc.bridge_spio_p10_apb1_s_8_8_as_arovrd 0x21F20 0x21F20 spio_noc.bridge_spio_p10_apb1_s_8_8_as_awovrd spio_noc.bridge_spio_p10_apb1_s_8_8_as_awovrd 0x21F28 0x22FFF 0x23000 0x23000 spio_noc.bridge_spio_p10_apb1_s_8_8_p_0 spio_noc.bridge_spio_p10_apb1_s_8_8_p_0 0x23004 0x23007 0x23008 0x23008 spio_noc.bridge_spio_p10_apb1_s_8_8_p_1 spio_noc.bridge_spio_p10_apb1_s_8_8_p_1 0x2300C 0x2300F 0x23010 0x23010 spio_noc.bridge_spio_p10_apb1_s_8_8_p_2 spio_noc.bridge_spio_p10_apb1_s_8_8_p_2 0x23014 0x23017 0x23018 0x23018 spio_noc.bridge_spio_p10_apb1_s_8_8_p_3 spio_noc.bridge_spio_p10_apb1_s_8_8_p_3 0x2301C 0x2303F 0x23040 0x23040 spio_noc.bridge_spio_p10_apb1_s_8_8_txe spio_noc.bridge_spio_p10_apb1_s_8_8_txe 0x23044 0x23047 0x23048 0x23048 spio_noc.bridge_spio_p10_apb1_s_8_8_txem spio_noc.bridge_spio_p10_apb1_s_8_8_txem 0x2304C 0x23057 0x23058 0x23058 spio_noc.bridge_spio_p10_apb1_s_8_8_btus_0 spio_noc.bridge_spio_p10_apb1_s_8_8_btus_0 0x2305C 0x2305F 0x23060 0x23060 spio_noc.bridge_spio_p10_apb1_s_8_8_btus_1 spio_noc.bridge_spio_p10_apb1_s_8_8_btus_1 0x23064 0x2307F 0x23080 0x23080 spio_noc.bridge_spio_p10_apb1_s_8_8_btrl_0 spio_noc.bridge_spio_p10_apb1_s_8_8_btrl_0 0x23084 0x23087 0x23088 0x23088 spio_noc.bridge_spio_p10_apb1_s_8_8_btrl_1 spio_noc.bridge_spio_p10_apb1_s_8_8_btrl_1 0x2308C 0x2308F 0x23090 0x23090 spio_noc.bridge_spio_p10_apb1_s_8_8_btrl_2 spio_noc.bridge_spio_p10_apb1_s_8_8_btrl_2 0x23094 0x23097 0x23098 0x23098 spio_noc.bridge_spio_p10_apb1_s_8_8_btrl_3 spio_noc.bridge_spio_p10_apb1_s_8_8_btrl_3 0x2309C 0x230A7 0x230A8 0x230A8 spio_noc.bridge_spio_p10_apb1_s_8_8_btperr spio_noc.bridge_spio_p10_apb1_s_8_8_btperr 0x230AC 0x230AF 0x230B0 0x230B0 spio_noc.bridge_spio_p10_apb1_s_8_8_btperrm spio_noc.bridge_spio_p10_apb1_s_8_8_btperrm 0x230B4 0x2311F 0x23120 0x23120 spio_noc.bridge_spio_p10_apb1_s_8_8_rxe spio_noc.bridge_spio_p10_apb1_s_8_8_rxe 0x23124 0x23127 0x23128 0x23128 spio_noc.bridge_spio_p10_apb1_s_8_8_rxem spio_noc.bridge_spio_p10_apb1_s_8_8_rxem 0x2312C 0x2312F 0x23130 0x23130 spio_noc.bridge_spio_p10_apb1_s_8_8_brs_0 spio_noc.bridge_spio_p10_apb1_s_8_8_brs_0 0x23134 0x23137 0x23138 0x23138 spio_noc.bridge_spio_p10_apb1_s_8_8_brs_1 spio_noc.bridge_spio_p10_apb1_s_8_8_brs_1 0x2313C 0x231AF 0x231B0 0x231B0 spio_noc.bridge_spio_p10_apb1_s_8_8_brus spio_noc.bridge_spio_p10_apb1_s_8_8_brus 0x231B4 0x231CF 0x231D0 0x231D0 spio_noc.bridge_spio_p10_apb1_s_8_8_brperr0 spio_noc.bridge_spio_p10_apb1_s_8_8_brperr0 0x231D8 0x231D8 spio_noc.bridge_spio_p10_apb1_s_8_8_brperr1 spio_noc.bridge_spio_p10_apb1_s_8_8_brperr1 0x231E0 0x231E0 spio_noc.bridge_spio_p10_apb1_s_8_8_brperrm0 spio_noc.bridge_spio_p10_apb1_s_8_8_brperrm0 0x231E8 0x231E8 spio_noc.bridge_spio_p10_apb1_s_8_8_brperrm1 spio_noc.bridge_spio_p10_apb1_s_8_8_brperrm1 0x231F0 0x25C0F 0x25C10 0x25C10 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_cgc spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_cgc 0x25C18 0x25C18 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_cgo spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_cgo 0x25C20 0x25CFF 0x25D00 0x25D00 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_sts spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_sts 0x25D08 0x25D08 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_bridge_id spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_bridge_id 0x25D10 0x25DFF 0x25E00 0x25E00 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_err spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_err 0x25E08 0x25E3F 0x25E40 0x25E40 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_intm spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_intm 0x25E48 0x25EFF 0x25F00 0x25F00 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_ccmd spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_ccmd 0x25F08 0x25F08 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_ccmdmsk spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_ccmdmsk 0x25F10 0x25F10 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_cntr spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_cntr 0x25F18 0x25F18 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_arovrd spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_arovrd 0x25F20 0x25F20 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_awovrd spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_awovrd 0x25F28 0x26FFF 0x27000 0x27000 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_p_0 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_p_0 0x27004 0x27007 0x27008 0x27008 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_p_1 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_p_1 0x2700C 0x2700F 0x27010 0x27010 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_p_2 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_p_2 0x27014 0x27017 0x27018 0x27018 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_p_3 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_p_3 0x2701C 0x2703F 0x27040 0x27040 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_txe spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_txe 0x27044 0x27047 0x27048 0x27048 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_txem spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_txem 0x2704C 0x27057 0x27058 0x27058 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btus_0 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btus_0 0x2705C 0x2705F 0x27060 0x27060 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btus_1 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btus_1 0x27064 0x2707F 0x27080 0x27080 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btrl_0 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btrl_0 0x27084 0x27087 0x27088 0x27088 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btrl_1 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btrl_1 0x2708C 0x2708F 0x27090 0x27090 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btrl_2 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btrl_2 0x27094 0x27097 0x27098 0x27098 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btrl_3 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btrl_3 0x2709C 0x270A7 0x270A8 0x270A8 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btperr spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btperr 0x270AC 0x270AF 0x270B0 0x270B0 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btperrm spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btperrm 0x270B4 0x2711F 0x27120 0x27120 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_rxe spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_rxe 0x27124 0x27127 0x27128 0x27128 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_rxem spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_rxem 0x2712C 0x2712F 0x27130 0x27130 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_brs_0 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_brs_0 0x27134 0x27137 0x27138 0x27138 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_brs_1 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_brs_1 0x2713C 0x271AF 0x271B0 0x271B0 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_brus spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_brus 0x271B4 0x271CF 0x271D0 0x271D0 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_brperr0 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_brperr0 0x271D8 0x271D8 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_brperr1 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_brperr1 0x271E0 0x271E0 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_brperrm0 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_brperrm0 0x271E8 0x271E8 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_brperrm1 spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_brperrm1 0x271F0 0x29C0F 0x29C10 0x29C10 spio_noc.bridge_spio_p10_pcie_s_10_9_as_cgc spio_noc.bridge_spio_p10_pcie_s_10_9_as_cgc 0x29C18 0x29C18 spio_noc.bridge_spio_p10_pcie_s_10_9_as_cgo spio_noc.bridge_spio_p10_pcie_s_10_9_as_cgo 0x29C20 0x29CFF 0x29D00 0x29D00 spio_noc.bridge_spio_p10_pcie_s_10_9_as_sts spio_noc.bridge_spio_p10_pcie_s_10_9_as_sts 0x29D08 0x29D08 spio_noc.bridge_spio_p10_pcie_s_10_9_as_bridge_id spio_noc.bridge_spio_p10_pcie_s_10_9_as_bridge_id 0x29D10 0x29DFF 0x29E00 0x29E00 spio_noc.bridge_spio_p10_pcie_s_10_9_as_err spio_noc.bridge_spio_p10_pcie_s_10_9_as_err 0x29E08 0x29E3F 0x29E40 0x29E40 spio_noc.bridge_spio_p10_pcie_s_10_9_as_intm spio_noc.bridge_spio_p10_pcie_s_10_9_as_intm 0x29E48 0x29EFF 0x29F00 0x29F00 spio_noc.bridge_spio_p10_pcie_s_10_9_as_ccmd spio_noc.bridge_spio_p10_pcie_s_10_9_as_ccmd 0x29F08 0x29F08 spio_noc.bridge_spio_p10_pcie_s_10_9_as_ccmdmsk spio_noc.bridge_spio_p10_pcie_s_10_9_as_ccmdmsk 0x29F10 0x29F10 spio_noc.bridge_spio_p10_pcie_s_10_9_as_cntr spio_noc.bridge_spio_p10_pcie_s_10_9_as_cntr 0x29F18 0x29F18 spio_noc.bridge_spio_p10_pcie_s_10_9_as_arovrd spio_noc.bridge_spio_p10_pcie_s_10_9_as_arovrd 0x29F20 0x29F20 spio_noc.bridge_spio_p10_pcie_s_10_9_as_awovrd spio_noc.bridge_spio_p10_pcie_s_10_9_as_awovrd 0x29F28 0x2AFFF 0x2B000 0x2B000 spio_noc.bridge_spio_p10_pcie_s_10_9_p_0 spio_noc.bridge_spio_p10_pcie_s_10_9_p_0 0x2B004 0x2B007 0x2B008 0x2B008 spio_noc.bridge_spio_p10_pcie_s_10_9_p_1 spio_noc.bridge_spio_p10_pcie_s_10_9_p_1 0x2B00C 0x2B00F 0x2B010 0x2B010 spio_noc.bridge_spio_p10_pcie_s_10_9_p_2 spio_noc.bridge_spio_p10_pcie_s_10_9_p_2 0x2B014 0x2B017 0x2B018 0x2B018 spio_noc.bridge_spio_p10_pcie_s_10_9_p_3 spio_noc.bridge_spio_p10_pcie_s_10_9_p_3 0x2B01C 0x2B03F 0x2B040 0x2B040 spio_noc.bridge_spio_p10_pcie_s_10_9_txe spio_noc.bridge_spio_p10_pcie_s_10_9_txe 0x2B044 0x2B047 0x2B048 0x2B048 spio_noc.bridge_spio_p10_pcie_s_10_9_txem spio_noc.bridge_spio_p10_pcie_s_10_9_txem 0x2B04C 0x2B057 0x2B058 0x2B058 spio_noc.bridge_spio_p10_pcie_s_10_9_btus_0 spio_noc.bridge_spio_p10_pcie_s_10_9_btus_0 0x2B05C 0x2B05F 0x2B060 0x2B060 spio_noc.bridge_spio_p10_pcie_s_10_9_btus_1 spio_noc.bridge_spio_p10_pcie_s_10_9_btus_1 0x2B064 0x2B07F 0x2B080 0x2B080 spio_noc.bridge_spio_p10_pcie_s_10_9_btrl_0 spio_noc.bridge_spio_p10_pcie_s_10_9_btrl_0 0x2B084 0x2B087 0x2B088 0x2B088 spio_noc.bridge_spio_p10_pcie_s_10_9_btrl_1 spio_noc.bridge_spio_p10_pcie_s_10_9_btrl_1 0x2B08C 0x2B08F 0x2B090 0x2B090 spio_noc.bridge_spio_p10_pcie_s_10_9_btrl_2 spio_noc.bridge_spio_p10_pcie_s_10_9_btrl_2 0x2B094 0x2B097 0x2B098 0x2B098 spio_noc.bridge_spio_p10_pcie_s_10_9_btrl_3 spio_noc.bridge_spio_p10_pcie_s_10_9_btrl_3 0x2B09C 0x2B0A7 0x2B0A8 0x2B0A8 spio_noc.bridge_spio_p10_pcie_s_10_9_btperr spio_noc.bridge_spio_p10_pcie_s_10_9_btperr 0x2B0AC 0x2B0AF 0x2B0B0 0x2B0B0 spio_noc.bridge_spio_p10_pcie_s_10_9_btperrm spio_noc.bridge_spio_p10_pcie_s_10_9_btperrm 0x2B0B4 0x2B11F 0x2B120 0x2B120 spio_noc.bridge_spio_p10_pcie_s_10_9_rxe spio_noc.bridge_spio_p10_pcie_s_10_9_rxe 0x2B124 0x2B127 0x2B128 0x2B128 spio_noc.bridge_spio_p10_pcie_s_10_9_rxem spio_noc.bridge_spio_p10_pcie_s_10_9_rxem 0x2B12C 0x2B12F 0x2B130 0x2B130 spio_noc.bridge_spio_p10_pcie_s_10_9_brs_0 spio_noc.bridge_spio_p10_pcie_s_10_9_brs_0 0x2B134 0x2B137 0x2B138 0x2B138 spio_noc.bridge_spio_p10_pcie_s_10_9_brs_1 spio_noc.bridge_spio_p10_pcie_s_10_9_brs_1 0x2B13C 0x2B1AF 0x2B1B0 0x2B1B0 spio_noc.bridge_spio_p10_pcie_s_10_9_brus spio_noc.bridge_spio_p10_pcie_s_10_9_brus 0x2B1B4 0x2B1CF 0x2B1D0 0x2B1D0 spio_noc.bridge_spio_p10_pcie_s_10_9_brperr0 spio_noc.bridge_spio_p10_pcie_s_10_9_brperr0 0x2B1D8 0x2B1D8 spio_noc.bridge_spio_p10_pcie_s_10_9_brperr1 spio_noc.bridge_spio_p10_pcie_s_10_9_brperr1 0x2B1E0 0x2B1E0 spio_noc.bridge_spio_p10_pcie_s_10_9_brperrm0 spio_noc.bridge_spio_p10_pcie_s_10_9_brperrm0 0x2B1E8 0x2B1E8 spio_noc.bridge_spio_p10_pcie_s_10_9_brperrm1 spio_noc.bridge_spio_p10_pcie_s_10_9_brperrm1 0x2B1F0 0x2C1FF 0x2C200 0x2C200 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_ahbs_ctl spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_ahbs_ctl 0x2C208 0x2C208 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_ahbs_sts spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_ahbs_sts 0x2C210 0x2C210 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_ahbs_im spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_ahbs_im 0x2C218 0x2DC0F 0x2DC10 0x2DC10 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_cgc spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_cgc 0x2DC18 0x2DC18 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_cgo spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_cgo 0x2DC20 0x2DCFF 0x2DD00 0x2DD00 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_sts spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_sts 0x2DD08 0x2DD08 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_bridge_id spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_bridge_id 0x2DD10 0x2DDFF 0x2DE00 0x2DE00 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_err spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_err 0x2DE08 0x2DE3F 0x2DE40 0x2DE40 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_intm spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_intm 0x2DE48 0x2DEFF 0x2DF00 0x2DF00 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_ccmd spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_ccmd 0x2DF08 0x2DF08 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_ccmdmsk spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_ccmdmsk 0x2DF10 0x2DF10 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_cntr spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_cntr 0x2DF18 0x2DF18 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_arovrd spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_arovrd 0x2DF20 0x2DF20 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_awovrd spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_awovrd 0x2DF28 0x2EFFF 0x2F000 0x2F000 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_p_0 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_p_0 0x2F004 0x2F007 0x2F008 0x2F008 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_p_1 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_p_1 0x2F00C 0x2F00F 0x2F010 0x2F010 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_p_2 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_p_2 0x2F014 0x2F017 0x2F018 0x2F018 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_p_3 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_p_3 0x2F01C 0x2F03F 0x2F040 0x2F040 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_txe spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_txe 0x2F044 0x2F047 0x2F048 0x2F048 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_txem spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_txem 0x2F04C 0x2F057 0x2F058 0x2F058 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btus_0 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btus_0 0x2F05C 0x2F05F 0x2F060 0x2F060 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btus_1 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btus_1 0x2F064 0x2F07F 0x2F080 0x2F080 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btrl_0 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btrl_0 0x2F084 0x2F087 0x2F088 0x2F088 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btrl_1 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btrl_1 0x2F08C 0x2F08F 0x2F090 0x2F090 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btrl_2 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btrl_2 0x2F094 0x2F097 0x2F098 0x2F098 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btrl_3 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btrl_3 0x2F09C 0x2F0A7 0x2F0A8 0x2F0A8 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btperr spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btperr 0x2F0AC 0x2F0AF 0x2F0B0 0x2F0B0 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btperrm spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btperrm 0x2F0B4 0x2F11F 0x2F120 0x2F120 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_rxe spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_rxe 0x2F124 0x2F127 0x2F128 0x2F128 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_rxem spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_rxem 0x2F12C 0x2F12F 0x2F130 0x2F130 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_brs_0 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_brs_0 0x2F134 0x2F137 0x2F138 0x2F138 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_brs_1 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_brs_1 0x2F13C 0x2F1AF 0x2F1B0 0x2F1B0 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_brus spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_brus 0x2F1B4 0x2F1CF 0x2F1D0 0x2F1D0 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_brperr0 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_brperr0 0x2F1D8 0x2F1D8 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_brperr1 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_brperr1 0x2F1E0 0x2F1E0 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_brperrm0 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_brperrm0 0x2F1E8 0x2F1E8 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_brperrm1 spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_brperrm1 0x2F1F0 0x31C0F 0x31C10 0x31C10 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_cgc spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_cgc 0x31C18 0x31C18 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_cgo spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_cgo 0x31C20 0x31CFF 0x31D00 0x31D00 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_sts spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_sts 0x31D08 0x31D08 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_bridge_id spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_bridge_id 0x31D10 0x31DFF 0x31E00 0x31E00 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_err spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_err 0x31E08 0x31E3F 0x31E40 0x31E40 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_intm spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_intm 0x31E48 0x31EFF 0x31F00 0x31F00 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_ccmd spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_ccmd 0x31F08 0x31F08 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_ccmdmsk spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_ccmdmsk 0x31F10 0x31F10 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_cntr spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_cntr 0x31F18 0x31F18 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_arovrd spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_arovrd 0x31F20 0x31F20 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_awovrd spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_awovrd 0x31F28 0x32FFF 0x33000 0x33000 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_p_0 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_p_0 0x33004 0x33007 0x33008 0x33008 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_p_1 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_p_1 0x3300C 0x3300F 0x33010 0x33010 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_p_2 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_p_2 0x33014 0x33017 0x33018 0x33018 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_p_3 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_p_3 0x3301C 0x3303F 0x33040 0x33040 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_txe spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_txe 0x33044 0x33047 0x33048 0x33048 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_txem spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_txem 0x3304C 0x33057 0x33058 0x33058 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btus_0 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btus_0 0x3305C 0x3305F 0x33060 0x33060 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btus_1 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btus_1 0x33064 0x3307F 0x33080 0x33080 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btrl_0 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btrl_0 0x33084 0x33087 0x33088 0x33088 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btrl_1 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btrl_1 0x3308C 0x3308F 0x33090 0x33090 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btrl_2 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btrl_2 0x33094 0x33097 0x33098 0x33098 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btrl_3 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btrl_3 0x3309C 0x330A7 0x330A8 0x330A8 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btperr spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btperr 0x330AC 0x330AF 0x330B0 0x330B0 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btperrm spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btperrm 0x330B4 0x3311F 0x33120 0x33120 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_rxe spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_rxe 0x33124 0x33127 0x33128 0x33128 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_rxem spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_rxem 0x3312C 0x3312F 0x33130 0x33130 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_brs_0 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_brs_0 0x33134 0x33137 0x33138 0x33138 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_brs_1 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_brs_1 0x3313C 0x331AF 0x331B0 0x331B0 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_brus spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_brus 0x331B4 0x331CF 0x331D0 0x331D0 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_brperr0 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_brperr0 0x331D8 0x331D8 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_brperr1 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_brperr1 0x331E0 0x331E0 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_brperrm0 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_brperrm0 0x331E8 0x331E8 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_brperrm1 spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_brperrm1 0x331F0 0x35C0F 0x35C10 0x35C10 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_cgc spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_cgc 0x35C18 0x35C18 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_cgo spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_cgo 0x35C20 0x35CFF 0x35D00 0x35D00 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_sts spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_sts 0x35D08 0x35D08 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_bridge_id spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_bridge_id 0x35D10 0x35DFF 0x35E00 0x35E00 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_err spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_err 0x35E08 0x35E3F 0x35E40 0x35E40 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_intm spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_intm 0x35E48 0x35EFF 0x35F00 0x35F00 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_ccmd spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_ccmd 0x35F08 0x35F08 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_ccmdmsk spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_ccmdmsk 0x35F10 0x35F10 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_cntr spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_cntr 0x35F18 0x35F18 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_arovrd spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_arovrd 0x35F20 0x35F20 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_awovrd spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_awovrd 0x35F28 0x36FFF 0x37000 0x37000 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_p_0 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_p_0 0x37004 0x37007 0x37008 0x37008 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_p_1 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_p_1 0x3700C 0x3700F 0x37010 0x37010 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_p_2 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_p_2 0x37014 0x37017 0x37018 0x37018 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_p_3 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_p_3 0x3701C 0x3703F 0x37040 0x37040 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_txe spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_txe 0x37044 0x37047 0x37048 0x37048 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_txem spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_txem 0x3704C 0x37057 0x37058 0x37058 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btus_0 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btus_0 0x3705C 0x3705F 0x37060 0x37060 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btus_1 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btus_1 0x37064 0x3707F 0x37080 0x37080 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btrl_0 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btrl_0 0x37084 0x37087 0x37088 0x37088 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btrl_1 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btrl_1 0x3708C 0x3708F 0x37090 0x37090 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btrl_2 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btrl_2 0x37094 0x37097 0x37098 0x37098 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btrl_3 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btrl_3 0x3709C 0x370A7 0x370A8 0x370A8 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btperr spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btperr 0x370AC 0x370AF 0x370B0 0x370B0 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btperrm spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btperrm 0x370B4 0x3711F 0x37120 0x37120 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_rxe spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_rxe 0x37124 0x37127 0x37128 0x37128 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_rxem spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_rxem 0x3712C 0x3712F 0x37130 0x37130 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_brs_0 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_brs_0 0x37134 0x37137 0x37138 0x37138 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_brs_1 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_brs_1 0x3713C 0x371AF 0x371B0 0x371B0 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_brus spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_brus 0x371B4 0x371CF 0x371D0 0x371D0 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_brperr0 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_brperr0 0x371D8 0x371D8 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_brperr1 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_brperr1 0x371E0 0x371E0 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_brperrm0 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_brperrm0 0x371E8 0x371E8 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_brperrm1 spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_brperrm1 0x371F0 0x39C0F 0x39C10 0x39C10 spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_cgc spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_cgc 0x39C18 0x39C18 spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_cgo spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_cgo 0x39C20 0x39CFF 0x39D00 0x39D00 spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_sts spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_sts 0x39D08 0x39D08 spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_bridge_id spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_bridge_id 0x39D10 0x39DFF 0x39E00 0x39E00 spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_err spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_err 0x39E08 0x39E3F 0x39E40 0x39E40 spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_intm spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_intm 0x39E48 0x39EFF 0x39F00 0x39F00 spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_ccmd spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_ccmd 0x39F08 0x39F08 spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_ccmdmsk spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_ccmdmsk 0x39F10 0x39F10 spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_cntr spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_cntr 0x39F18 0x39F18 spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_arovrd spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_arovrd 0x39F20 0x39F20 spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_awovrd spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_awovrd 0x39F28 0x3AFFF 0x3B000 0x3B000 spio_noc.bridge_spio_sp_main0_ram_s_14_11_p_0 spio_noc.bridge_spio_sp_main0_ram_s_14_11_p_0 0x3B004 0x3B007 0x3B008 0x3B008 spio_noc.bridge_spio_sp_main0_ram_s_14_11_p_1 spio_noc.bridge_spio_sp_main0_ram_s_14_11_p_1 0x3B00C 0x3B00F 0x3B010 0x3B010 spio_noc.bridge_spio_sp_main0_ram_s_14_11_p_2 spio_noc.bridge_spio_sp_main0_ram_s_14_11_p_2 0x3B014 0x3B017 0x3B018 0x3B018 spio_noc.bridge_spio_sp_main0_ram_s_14_11_p_3 spio_noc.bridge_spio_sp_main0_ram_s_14_11_p_3 0x3B01C 0x3B03F 0x3B040 0x3B040 spio_noc.bridge_spio_sp_main0_ram_s_14_11_txe spio_noc.bridge_spio_sp_main0_ram_s_14_11_txe 0x3B044 0x3B047 0x3B048 0x3B048 spio_noc.bridge_spio_sp_main0_ram_s_14_11_txem spio_noc.bridge_spio_sp_main0_ram_s_14_11_txem 0x3B04C 0x3B057 0x3B058 0x3B058 spio_noc.bridge_spio_sp_main0_ram_s_14_11_btus_0 spio_noc.bridge_spio_sp_main0_ram_s_14_11_btus_0 0x3B05C 0x3B05F 0x3B060 0x3B060 spio_noc.bridge_spio_sp_main0_ram_s_14_11_btus_1 spio_noc.bridge_spio_sp_main0_ram_s_14_11_btus_1 0x3B064 0x3B07F 0x3B080 0x3B080 spio_noc.bridge_spio_sp_main0_ram_s_14_11_btrl_0 spio_noc.bridge_spio_sp_main0_ram_s_14_11_btrl_0 0x3B084 0x3B087 0x3B088 0x3B088 spio_noc.bridge_spio_sp_main0_ram_s_14_11_btrl_1 spio_noc.bridge_spio_sp_main0_ram_s_14_11_btrl_1 0x3B08C 0x3B08F 0x3B090 0x3B090 spio_noc.bridge_spio_sp_main0_ram_s_14_11_btrl_2 spio_noc.bridge_spio_sp_main0_ram_s_14_11_btrl_2 0x3B094 0x3B097 0x3B098 0x3B098 spio_noc.bridge_spio_sp_main0_ram_s_14_11_btrl_3 spio_noc.bridge_spio_sp_main0_ram_s_14_11_btrl_3 0x3B09C 0x3B0A7 0x3B0A8 0x3B0A8 spio_noc.bridge_spio_sp_main0_ram_s_14_11_btperr spio_noc.bridge_spio_sp_main0_ram_s_14_11_btperr 0x3B0AC 0x3B0AF 0x3B0B0 0x3B0B0 spio_noc.bridge_spio_sp_main0_ram_s_14_11_btperrm spio_noc.bridge_spio_sp_main0_ram_s_14_11_btperrm 0x3B0B4 0x3B11F 0x3B120 0x3B120 spio_noc.bridge_spio_sp_main0_ram_s_14_11_rxe spio_noc.bridge_spio_sp_main0_ram_s_14_11_rxe 0x3B124 0x3B127 0x3B128 0x3B128 spio_noc.bridge_spio_sp_main0_ram_s_14_11_rxem spio_noc.bridge_spio_sp_main0_ram_s_14_11_rxem 0x3B12C 0x3B12F 0x3B130 0x3B130 spio_noc.bridge_spio_sp_main0_ram_s_14_11_brs_0 spio_noc.bridge_spio_sp_main0_ram_s_14_11_brs_0 0x3B134 0x3B137 0x3B138 0x3B138 spio_noc.bridge_spio_sp_main0_ram_s_14_11_brs_1 spio_noc.bridge_spio_sp_main0_ram_s_14_11_brs_1 0x3B13C 0x3B1AF 0x3B1B0 0x3B1B0 spio_noc.bridge_spio_sp_main0_ram_s_14_11_brus spio_noc.bridge_spio_sp_main0_ram_s_14_11_brus 0x3B1B4 0x3B1CF 0x3B1D0 0x3B1D0 spio_noc.bridge_spio_sp_main0_ram_s_14_11_brperr0 spio_noc.bridge_spio_sp_main0_ram_s_14_11_brperr0 0x3B1D8 0x3B1D8 spio_noc.bridge_spio_sp_main0_ram_s_14_11_brperr1 spio_noc.bridge_spio_sp_main0_ram_s_14_11_brperr1 0x3B1E0 0x3B1E0 spio_noc.bridge_spio_sp_main0_ram_s_14_11_brperrm0 spio_noc.bridge_spio_sp_main0_ram_s_14_11_brperrm0 0x3B1E8 0x3B1E8 spio_noc.bridge_spio_sp_main0_ram_s_14_11_brperrm1 spio_noc.bridge_spio_sp_main0_ram_s_14_11_brperrm1 0x3B1F0 0x3DC0F 0x3DC10 0x3DC10 spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_cgc spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_cgc 0x3DC18 0x3DC18 spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_cgo spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_cgo 0x3DC20 0x3DCFF 0x3DD00 0x3DD00 spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_sts spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_sts 0x3DD08 0x3DD08 spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_bridge_id spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_bridge_id 0x3DD10 0x3DDFF 0x3DE00 0x3DE00 spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_err spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_err 0x3DE08 0x3DE3F 0x3DE40 0x3DE40 spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_intm spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_intm 0x3DE48 0x3DEFF 0x3DF00 0x3DF00 spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_ccmd spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_ccmd 0x3DF08 0x3DF08 spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_ccmdmsk spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_ccmdmsk 0x3DF10 0x3DF10 spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_cntr spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_cntr 0x3DF18 0x3DF18 spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_arovrd spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_arovrd 0x3DF20 0x3DF20 spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_awovrd spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_awovrd 0x3DF28 0x3EFFF 0x3F000 0x3F000 spio_noc.bridge_spio_sp_main0_rom_s_15_6_p_0 spio_noc.bridge_spio_sp_main0_rom_s_15_6_p_0 0x3F004 0x3F007 0x3F008 0x3F008 spio_noc.bridge_spio_sp_main0_rom_s_15_6_p_1 spio_noc.bridge_spio_sp_main0_rom_s_15_6_p_1 0x3F00C 0x3F00F 0x3F010 0x3F010 spio_noc.bridge_spio_sp_main0_rom_s_15_6_p_2 spio_noc.bridge_spio_sp_main0_rom_s_15_6_p_2 0x3F014 0x3F017 0x3F018 0x3F018 spio_noc.bridge_spio_sp_main0_rom_s_15_6_p_3 spio_noc.bridge_spio_sp_main0_rom_s_15_6_p_3 0x3F01C 0x3F03F 0x3F040 0x3F040 spio_noc.bridge_spio_sp_main0_rom_s_15_6_txe spio_noc.bridge_spio_sp_main0_rom_s_15_6_txe 0x3F044 0x3F047 0x3F048 0x3F048 spio_noc.bridge_spio_sp_main0_rom_s_15_6_txem spio_noc.bridge_spio_sp_main0_rom_s_15_6_txem 0x3F04C 0x3F057 0x3F058 0x3F058 spio_noc.bridge_spio_sp_main0_rom_s_15_6_btus_0 spio_noc.bridge_spio_sp_main0_rom_s_15_6_btus_0 0x3F05C 0x3F05F 0x3F060 0x3F060 spio_noc.bridge_spio_sp_main0_rom_s_15_6_btus_1 spio_noc.bridge_spio_sp_main0_rom_s_15_6_btus_1 0x3F064 0x3F07F 0x3F080 0x3F080 spio_noc.bridge_spio_sp_main0_rom_s_15_6_btrl_0 spio_noc.bridge_spio_sp_main0_rom_s_15_6_btrl_0 0x3F084 0x3F087 0x3F088 0x3F088 spio_noc.bridge_spio_sp_main0_rom_s_15_6_btrl_1 spio_noc.bridge_spio_sp_main0_rom_s_15_6_btrl_1 0x3F08C 0x3F08F 0x3F090 0x3F090 spio_noc.bridge_spio_sp_main0_rom_s_15_6_btrl_2 spio_noc.bridge_spio_sp_main0_rom_s_15_6_btrl_2 0x3F094 0x3F097 0x3F098 0x3F098 spio_noc.bridge_spio_sp_main0_rom_s_15_6_btrl_3 spio_noc.bridge_spio_sp_main0_rom_s_15_6_btrl_3 0x3F09C 0x3F0A7 0x3F0A8 0x3F0A8 spio_noc.bridge_spio_sp_main0_rom_s_15_6_btperr spio_noc.bridge_spio_sp_main0_rom_s_15_6_btperr 0x3F0AC 0x3F0AF 0x3F0B0 0x3F0B0 spio_noc.bridge_spio_sp_main0_rom_s_15_6_btperrm spio_noc.bridge_spio_sp_main0_rom_s_15_6_btperrm 0x3F0B4 0x3F11F 0x3F120 0x3F120 spio_noc.bridge_spio_sp_main0_rom_s_15_6_rxe spio_noc.bridge_spio_sp_main0_rom_s_15_6_rxe 0x3F124 0x3F127 0x3F128 0x3F128 spio_noc.bridge_spio_sp_main0_rom_s_15_6_rxem spio_noc.bridge_spio_sp_main0_rom_s_15_6_rxem 0x3F12C 0x3F12F 0x3F130 0x3F130 spio_noc.bridge_spio_sp_main0_rom_s_15_6_brs_0 spio_noc.bridge_spio_sp_main0_rom_s_15_6_brs_0 0x3F134 0x3F137 0x3F138 0x3F138 spio_noc.bridge_spio_sp_main0_rom_s_15_6_brs_1 spio_noc.bridge_spio_sp_main0_rom_s_15_6_brs_1 0x3F13C 0x3F1AF 0x3F1B0 0x3F1B0 spio_noc.bridge_spio_sp_main0_rom_s_15_6_brus spio_noc.bridge_spio_sp_main0_rom_s_15_6_brus 0x3F1B4 0x3F1CF 0x3F1D0 0x3F1D0 spio_noc.bridge_spio_sp_main0_rom_s_15_6_brperr0 spio_noc.bridge_spio_sp_main0_rom_s_15_6_brperr0 0x3F1D8 0x3F1D8 spio_noc.bridge_spio_sp_main0_rom_s_15_6_brperr1 spio_noc.bridge_spio_sp_main0_rom_s_15_6_brperr1 0x3F1E0 0x3F1E0 spio_noc.bridge_spio_sp_main0_rom_s_15_6_brperrm0 spio_noc.bridge_spio_sp_main0_rom_s_15_6_brperrm0 0x3F1E8 0x3F1E8 spio_noc.bridge_spio_sp_main0_rom_s_15_6_brperrm1 spio_noc.bridge_spio_sp_main0_rom_s_15_6_brperrm1 0x3F1F0 0x41C0F 0x41C10 0x41C10 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_cgc spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_cgc 0x41C18 0x41C18 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_cgo spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_cgo 0x41C20 0x41CFF 0x41D00 0x41D00 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_sts spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_sts 0x41D08 0x41D08 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_bridge_id spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_bridge_id 0x41D10 0x41DFF 0x41E00 0x41E00 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_err spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_err 0x41E08 0x41E3F 0x41E40 0x41E40 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_intm spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_intm 0x41E48 0x41EFF 0x41F00 0x41F00 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_ccmd spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_ccmd 0x41F08 0x41F08 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_ccmdmsk spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_ccmdmsk 0x41F10 0x41F10 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_cntr spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_cntr 0x41F18 0x41F18 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_arovrd spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_arovrd 0x41F20 0x41F20 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_awovrd spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_awovrd 0x41F28 0x42FFF 0x43000 0x43000 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_p_0 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_p_0 0x43004 0x43007 0x43008 0x43008 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_p_1 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_p_1 0x4300C 0x4300F 0x43010 0x43010 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_p_2 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_p_2 0x43014 0x43017 0x43018 0x43018 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_p_3 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_p_3 0x4301C 0x4303F 0x43040 0x43040 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_txe spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_txe 0x43044 0x43047 0x43048 0x43048 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_txem spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_txem 0x4304C 0x43057 0x43058 0x43058 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btus_0 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btus_0 0x4305C 0x4305F 0x43060 0x43060 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btus_1 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btus_1 0x43064 0x4307F 0x43080 0x43080 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btrl_0 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btrl_0 0x43084 0x43087 0x43088 0x43088 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btrl_1 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btrl_1 0x4308C 0x4308F 0x43090 0x43090 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btrl_2 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btrl_2 0x43094 0x43097 0x43098 0x43098 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btrl_3 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btrl_3 0x4309C 0x430A7 0x430A8 0x430A8 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btperr spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btperr 0x430AC 0x430AF 0x430B0 0x430B0 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btperrm spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btperrm 0x430B4 0x4311F 0x43120 0x43120 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_rxe spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_rxe 0x43124 0x43127 0x43128 0x43128 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_rxem spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_rxem 0x4312C 0x4312F 0x43130 0x43130 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_brs_0 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_brs_0 0x43134 0x43137 0x43138 0x43138 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_brs_1 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_brs_1 0x4313C 0x431AF 0x431B0 0x431B0 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_brus spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_brus 0x431B4 0x431CF 0x431D0 0x431D0 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_brperr0 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_brperr0 0x431D8 0x431D8 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_brperr1 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_brperr1 0x431E0 0x431E0 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_brperrm0 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_brperrm0 0x431E8 0x431E8 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_brperrm1 spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_brperrm1 0x431F0 0x43FFF 0x44000 0x44000 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 0x44008 0x44008 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 0x44010 0x4401F 0x44020 0x44020 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 0x44028 0x44028 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 0x44030 0x4403F 0x44040 0x44040 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 0x44048 0x44048 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 0x44050 0x4405F 0x44060 0x44060 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 0x44068 0x44068 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 0x44070 0x4407F 0x44080 0x44080 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 0x44088 0x44088 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 0x44090 0x4409F 0x440A0 0x440A0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 0x440A8 0x440A8 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 0x440B0 0x440BF 0x440C0 0x440C0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 0x440C8 0x440C8 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 0x440D0 0x440DF 0x440E0 0x440E0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 0x440E8 0x440E8 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 0x440F0 0x440FF 0x44100 0x44100 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 0x44108 0x44108 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 0x44110 0x4411F 0x44120 0x44120 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 0x44128 0x44128 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 0x44130 0x4413F 0x44140 0x44140 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 0x44148 0x44148 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 0x44150 0x4415F 0x44160 0x44160 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 0x44168 0x44168 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 0x44170 0x4417F 0x44180 0x44180 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 0x44188 0x44188 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 0x44190 0x4419F 0x441A0 0x441A0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 0x441A8 0x441A8 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 0x441B0 0x441BF 0x441C0 0x441C0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 0x441C8 0x441C8 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 0x441D0 0x441DF 0x441E0 0x441E0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 0x441E8 0x441E8 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 0x441F0 0x441FF 0x44200 0x44200 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 0x44208 0x44208 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 0x44210 0x4421F 0x44220 0x44220 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 0x44228 0x44228 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 0x44230 0x4423F 0x44240 0x44240 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 0x44248 0x44248 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 0x44250 0x4425F 0x44260 0x44260 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 0x44268 0x44268 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 0x44270 0x4427F 0x44280 0x44280 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 0x44288 0x44288 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 0x44290 0x4429F 0x442A0 0x442A0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 0x442A8 0x442A8 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 0x442B0 0x442BF 0x442C0 0x442C0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 0x442C8 0x442C8 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 0x442D0 0x442DF 0x442E0 0x442E0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 0x442E8 0x442E8 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 0x442F0 0x442FF 0x44300 0x44300 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 0x44308 0x44308 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 0x44310 0x4431F 0x44320 0x44320 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 0x44328 0x44328 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 0x44330 0x4433F 0x44340 0x44340 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 0x44348 0x44348 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 0x44350 0x4435F 0x44360 0x44360 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 0x44368 0x44368 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 0x44370 0x4437F 0x44380 0x44380 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 0x44388 0x44388 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 0x44390 0x4439F 0x443A0 0x443A0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 0x443A8 0x443A8 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 0x443B0 0x443BF 0x443C0 0x443C0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 0x443C8 0x443C8 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 0x443D0 0x443DF 0x443E0 0x443E0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 0x443E8 0x443E8 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 0x443F0 0x443FF 0x44400 0x44400 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 0x44408 0x44408 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 0x44410 0x4441F 0x44420 0x44420 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 0x44428 0x44428 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 0x44430 0x4443F 0x44440 0x44440 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 0x44448 0x44448 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 0x44450 0x4445F 0x44460 0x44460 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 0x44468 0x44468 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 0x44470 0x4447F 0x44480 0x44480 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 0x44488 0x44488 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 0x44490 0x4449F 0x444A0 0x444A0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 0x444A8 0x444A8 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 0x444B0 0x444BF 0x444C0 0x444C0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 0x444C8 0x444C8 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 0x444D0 0x444DF 0x444E0 0x444E0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 0x444E8 0x444E8 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 0x444F0 0x444FF 0x44500 0x44500 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 0x44508 0x44508 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 0x44510 0x4451F 0x44520 0x44520 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 0x44528 0x44528 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 0x44530 0x4453F 0x44540 0x44540 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 0x44548 0x44548 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 0x44550 0x4455F 0x44560 0x44560 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 0x44568 0x44568 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 0x44570 0x4457F 0x44580 0x44580 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 0x44588 0x44588 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 0x44590 0x4459F 0x445A0 0x445A0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 0x445A8 0x445A8 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 0x445B0 0x445BF 0x445C0 0x445C0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 0x445C8 0x445C8 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 0x445D0 0x445DF 0x445E0 0x445E0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 0x445E8 0x445E8 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 0x445F0 0x445FF 0x44600 0x44600 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 0x44608 0x44608 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 0x44610 0x4461F 0x44620 0x44620 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 0x44628 0x44628 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 0x44630 0x4463F 0x44640 0x44640 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 0x44648 0x44648 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 0x44650 0x4465F 0x44660 0x44660 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 0x44668 0x44668 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 0x44670 0x4467F 0x44680 0x44680 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 0x44688 0x44688 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 0x44690 0x4469F 0x446A0 0x446A0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 0x446A8 0x446A8 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 0x446B0 0x446BF 0x446C0 0x446C0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 0x446C8 0x446C8 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 0x446D0 0x446DF 0x446E0 0x446E0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 0x446E8 0x446E8 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 0x446F0 0x446FF 0x44700 0x44700 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 0x44708 0x44708 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 0x44710 0x4471F 0x44720 0x44720 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 0x44728 0x44728 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 0x44730 0x4473F 0x44740 0x44740 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 0x44748 0x44748 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 0x44750 0x4475F 0x44760 0x44760 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 0x44768 0x44768 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 0x44770 0x4477F 0x44780 0x44780 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 0x44788 0x44788 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 0x44790 0x4479F 0x447A0 0x447A0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 0x447A8 0x447A8 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 0x447B0 0x447BF 0x447C0 0x447C0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 0x447C8 0x447C8 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 0x447D0 0x447DF 0x447E0 0x447E0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 0x447E8 0x447E8 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 0x447F0 0x447FF 0x44800 0x44800 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 0x44808 0x44808 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 0x44810 0x4481F 0x44820 0x44820 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 0x44828 0x44828 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 0x44830 0x4483F 0x44840 0x44840 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 0x44848 0x44848 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 0x44850 0x4485F 0x44860 0x44860 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 0x44868 0x44868 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 0x44870 0x4487F 0x44880 0x44880 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 0x44888 0x44888 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 0x44890 0x46FFF 0x47000 0x47000 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_p_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_p_0 0x47004 0x47007 0x47008 0x47008 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_p_1 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_p_1 0x4700C 0x4700F 0x47010 0x47010 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_p_2 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_p_2 0x47014 0x47017 0x47018 0x47018 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_p_3 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_p_3 0x4701C 0x4703F 0x47040 0x47040 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_txe spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_txe 0x47044 0x47047 0x47048 0x47048 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_txem spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_txem 0x4704C 0x47057 0x47058 0x47058 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btus_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btus_0 0x4705C 0x4705F 0x47060 0x47060 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btus_1 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btus_1 0x47064 0x4707F 0x47080 0x47080 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btrl_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btrl_0 0x47084 0x47087 0x47088 0x47088 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btrl_1 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btrl_1 0x4708C 0x4708F 0x47090 0x47090 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btrl_2 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btrl_2 0x47094 0x47097 0x47098 0x47098 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btrl_3 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btrl_3 0x4709C 0x470A7 0x470A8 0x470A8 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btperr spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btperr 0x470AC 0x470AF 0x470B0 0x470B0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btperrm spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btperrm 0x470B4 0x4711F 0x47120 0x47120 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_rxe spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_rxe 0x47124 0x47127 0x47128 0x47128 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_rxem spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_rxem 0x4712C 0x4712F 0x47130 0x47130 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_brs_0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_brs_0 0x47134 0x47137 0x47138 0x47138 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_brs_1 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_brs_1 0x4713C 0x471AF 0x471B0 0x471B0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_brus spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_brus 0x471B4 0x471CF 0x471D0 0x471D0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_brperr0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_brperr0 0x471D8 0x471D8 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_brperr1 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_brperr1 0x471E0 0x471E0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_brperrm0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_brperrm0 0x471E8 0x471E8 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_brperrm1 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_brperrm1 0x471F0 0x47BFF 0x47C00 0x47C00 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_tocfg spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_tocfg 0x47C08 0x47C08 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_osslv spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_osslv 0x47C10 0x47C10 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_cgc spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_cgc 0x47C18 0x47C18 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_cgo spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_cgo 0x47C20 0x47C20 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_cfg spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_cfg 0x47C28 0x47CFF 0x47D00 0x47D00 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_sts spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_sts 0x47D08 0x47D08 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_bridge_id spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_bridge_id 0x47D10 0x47DFF 0x47E00 0x47E00 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_err spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_err 0x47E08 0x47E08 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_toslvid spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_toslvid 0x47E10 0x47E10 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_era spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_era 0x47E18 0x47E18 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_ewa spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_ewa 0x47E20 0x47E3F 0x47E40 0x47E40 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_intm spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_intm 0x47E48 0x47EFF 0x47F00 0x47F00 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_caddr spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_caddr 0x47F08 0x47F08 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_caddrmsk spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_caddrmsk 0x47F10 0x47F10 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_ccmd0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_ccmd0 0x47F18 0x47F18 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_ccmdmsk0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_ccmdmsk0 0x47F20 0x47F20 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_cntr0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_cntr0 0x47F28 0x47F28 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_latnum0 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_latnum0 0x47F30 0x47F30 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_ccmd1 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_ccmd1 0x47F38 0x47F38 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_ccmdmsk1 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_ccmdmsk1 0x47F40 0x47F40 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_cntr1 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_cntr1 0x47F48 0x47F48 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_latnum1 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_latnum1 0x47F50 0x47F5F 0x47F60 0x47F60 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_arovrd spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_arovrd 0x47F68 0x47F68 spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_awovrd spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_awovrd 0x47F70 0x47FFF 0x48000 0x48000 spio_noc.router_0_6_6_rivcs_h spio_noc.router_0_6_6_rivcs_h 0x48004 0x48007 0x48008 0x48008 spio_noc.router_0_6_6_rivcs_e spio_noc.router_0_6_6_rivcs_e 0x4800C 0x4800F 0x48010 0x48010 spio_noc.router_0_6_6_rivcs_s spio_noc.router_0_6_6_rivcs_s 0x48014 0x48017 0x48018 0x48018 spio_noc.router_0_6_6_rivcs_w spio_noc.router_0_6_6_rivcs_w 0x4801C 0x4801F 0x48020 0x48020 spio_noc.router_0_6_6_rivcs_n spio_noc.router_0_6_6_rivcs_n 0x48024 0x48027 0x48028 0x48028 spio_noc.router_0_6_6_rivcs_i spio_noc.router_0_6_6_rivcs_i 0x4802C 0x4802F 0x48030 0x48030 spio_noc.router_0_6_6_rivcs_j spio_noc.router_0_6_6_rivcs_j 0x48034 0x48037 0x48038 0x48038 spio_noc.router_0_6_6_rivcs_k spio_noc.router_0_6_6_rivcs_k 0x4803C 0x4803F 0x48040 0x48040 spio_noc.router_0_6_6_rovcs_h spio_noc.router_0_6_6_rovcs_h 0x48044 0x48047 0x48048 0x48048 spio_noc.router_0_6_6_rovcs_e spio_noc.router_0_6_6_rovcs_e 0x4804C 0x4804F 0x48050 0x48050 spio_noc.router_0_6_6_rovcs_s spio_noc.router_0_6_6_rovcs_s 0x48054 0x48057 0x48058 0x48058 spio_noc.router_0_6_6_rovcs_w spio_noc.router_0_6_6_rovcs_w 0x4805C 0x4805F 0x48060 0x48060 spio_noc.router_0_6_6_rovcs_n spio_noc.router_0_6_6_rovcs_n 0x48064 0x48067 0x48068 0x48068 spio_noc.router_0_6_6_rovcs_i spio_noc.router_0_6_6_rovcs_i 0x4806C 0x4806F 0x48070 0x48070 spio_noc.router_0_6_6_rovcs_j spio_noc.router_0_6_6_rovcs_j 0x48074 0x48077 0x48078 0x48078 spio_noc.router_0_6_6_rovcs_k spio_noc.router_0_6_6_rovcs_k 0x4807C 0x4807F 0x48080 0x48080 spio_noc.router_0_6_6_re spio_noc.router_0_6_6_re 0x48084 0x48087 0x48088 0x48088 spio_noc.router_0_6_6_rem spio_noc.router_0_6_6_rem 0x4808C 0x4808F 0x48090 0x48090 spio_noc.router_0_6_6_recc spio_noc.router_0_6_6_recc 0x48094 0x48097 0x48098 0x48098 spio_noc.router_0_6_6_rec spio_noc.router_0_6_6_rec 0x4809C 0x4809F 0x480A0 0x480A0 spio_noc.router_0_6_6_id spio_noc.router_0_6_6_id 0x480A4 0x480A7 0x480A8 0x480A8 spio_noc.router_0_6_6_rcgc spio_noc.router_0_6_6_rcgc 0x480AC 0x480AF 0x480B0 0x480B0 spio_noc.router_0_6_6_rcgo spio_noc.router_0_6_6_rcgo 0x480B4 0x480B7 0x480B8 0x480B8 spio_noc.router_0_6_6_p0_rperr spio_noc.router_0_6_6_p0_rperr 0x480BC 0x480BF 0x480C0 0x480C0 spio_noc.router_0_6_6_p1_rperr spio_noc.router_0_6_6_p1_rperr 0x480C4 0x480C7 0x480C8 0x480C8 spio_noc.router_0_6_6_p2_rperr spio_noc.router_0_6_6_p2_rperr 0x480CC 0x480CF 0x480D0 0x480D0 spio_noc.router_0_6_6_p3_rperr spio_noc.router_0_6_6_p3_rperr 0x480D4 0x480D7 0x480D8 0x480D8 spio_noc.router_0_6_6_p4_rperr spio_noc.router_0_6_6_p4_rperr 0x480DC 0x480DF 0x480E0 0x480E0 spio_noc.router_0_6_6_p5_rperr spio_noc.router_0_6_6_p5_rperr 0x480E4 0x480E7 0x480E8 0x480E8 spio_noc.router_0_6_6_p6_rperr spio_noc.router_0_6_6_p6_rperr 0x480EC 0x480EF 0x480F0 0x480F0 spio_noc.router_0_6_6_p7_rperr spio_noc.router_0_6_6_p7_rperr 0x480F4 0x480F7 0x480F8 0x480F8 spio_noc.router_0_6_6_p0_rperrm spio_noc.router_0_6_6_p0_rperrm 0x480FC 0x480FF 0x48100 0x48100 spio_noc.router_0_6_6_p1_rperrm spio_noc.router_0_6_6_p1_rperrm 0x48104 0x48107 0x48108 0x48108 spio_noc.router_0_6_6_p2_rperrm spio_noc.router_0_6_6_p2_rperrm 0x4810C 0x4810F 0x48110 0x48110 spio_noc.router_0_6_6_p3_rperrm spio_noc.router_0_6_6_p3_rperrm 0x48114 0x48117 0x48118 0x48118 spio_noc.router_0_6_6_p4_rperrm spio_noc.router_0_6_6_p4_rperrm 0x4811C 0x4811F 0x48120 0x48120 spio_noc.router_0_6_6_p5_rperrm spio_noc.router_0_6_6_p5_rperrm 0x48124 0x48127 0x48128 0x48128 spio_noc.router_0_6_6_p6_rperrm spio_noc.router_0_6_6_p6_rperrm 0x4812C 0x4812F 0x48130 0x48130 spio_noc.router_0_6_6_p7_rperrm spio_noc.router_0_6_6_p7_rperrm 0x48134 0x48137 0x48138 0x48138 spio_noc.router_0_6_6_roecc spio_noc.router_0_6_6_roecc 0x4813C 0x4813F 0x48140 0x48140 spio_noc.router_0_6_6_roec spio_noc.router_0_6_6_roec 0x48144 0x4BFFF 0x4C000 0x4C000 spio_noc.router_0_7_7_rivcs_h spio_noc.router_0_7_7_rivcs_h 0x4C004 0x4C007 0x4C008 0x4C008 spio_noc.router_0_7_7_rivcs_e spio_noc.router_0_7_7_rivcs_e 0x4C00C 0x4C017 0x4C018 0x4C018 spio_noc.router_0_7_7_rivcs_w spio_noc.router_0_7_7_rivcs_w 0x4C01C 0x4C01F 0x4C020 0x4C020 spio_noc.router_0_7_7_rivcs_n spio_noc.router_0_7_7_rivcs_n 0x4C024 0x4C027 0x4C028 0x4C028 spio_noc.router_0_7_7_rivcs_i spio_noc.router_0_7_7_rivcs_i 0x4C02C 0x4C02F 0x4C030 0x4C030 spio_noc.router_0_7_7_rivcs_j spio_noc.router_0_7_7_rivcs_j 0x4C034 0x4C037 0x4C038 0x4C038 spio_noc.router_0_7_7_rivcs_k spio_noc.router_0_7_7_rivcs_k 0x4C03C 0x4C03F 0x4C040 0x4C040 spio_noc.router_0_7_7_rovcs_h spio_noc.router_0_7_7_rovcs_h 0x4C044 0x4C047 0x4C048 0x4C048 spio_noc.router_0_7_7_rovcs_e spio_noc.router_0_7_7_rovcs_e 0x4C04C 0x4C057 0x4C058 0x4C058 spio_noc.router_0_7_7_rovcs_w spio_noc.router_0_7_7_rovcs_w 0x4C05C 0x4C05F 0x4C060 0x4C060 spio_noc.router_0_7_7_rovcs_n spio_noc.router_0_7_7_rovcs_n 0x4C064 0x4C067 0x4C068 0x4C068 spio_noc.router_0_7_7_rovcs_i spio_noc.router_0_7_7_rovcs_i 0x4C06C 0x4C06F 0x4C070 0x4C070 spio_noc.router_0_7_7_rovcs_j spio_noc.router_0_7_7_rovcs_j 0x4C074 0x4C077 0x4C078 0x4C078 spio_noc.router_0_7_7_rovcs_k spio_noc.router_0_7_7_rovcs_k 0x4C07C 0x4C07F 0x4C080 0x4C080 spio_noc.router_0_7_7_re spio_noc.router_0_7_7_re 0x4C084 0x4C087 0x4C088 0x4C088 spio_noc.router_0_7_7_rem spio_noc.router_0_7_7_rem 0x4C08C 0x4C08F 0x4C090 0x4C090 spio_noc.router_0_7_7_recc spio_noc.router_0_7_7_recc 0x4C094 0x4C097 0x4C098 0x4C098 spio_noc.router_0_7_7_rec spio_noc.router_0_7_7_rec 0x4C09C 0x4C09F 0x4C0A0 0x4C0A0 spio_noc.router_0_7_7_id spio_noc.router_0_7_7_id 0x4C0A4 0x4C0A7 0x4C0A8 0x4C0A8 spio_noc.router_0_7_7_rcgc spio_noc.router_0_7_7_rcgc 0x4C0AC 0x4C0AF 0x4C0B0 0x4C0B0 spio_noc.router_0_7_7_rcgo spio_noc.router_0_7_7_rcgo 0x4C0B4 0x4C0B7 0x4C0B8 0x4C0B8 spio_noc.router_0_7_7_p0_rperr spio_noc.router_0_7_7_p0_rperr 0x4C0BC 0x4C0BF 0x4C0C0 0x4C0C0 spio_noc.router_0_7_7_p1_rperr spio_noc.router_0_7_7_p1_rperr 0x4C0C4 0x4C0C7 0x4C0C8 0x4C0C8 spio_noc.router_0_7_7_p2_rperr spio_noc.router_0_7_7_p2_rperr 0x4C0CC 0x4C0D7 0x4C0D8 0x4C0D8 spio_noc.router_0_7_7_p4_rperr spio_noc.router_0_7_7_p4_rperr 0x4C0DC 0x4C0DF 0x4C0E0 0x4C0E0 spio_noc.router_0_7_7_p5_rperr spio_noc.router_0_7_7_p5_rperr 0x4C0E4 0x4C0E7 0x4C0E8 0x4C0E8 spio_noc.router_0_7_7_p6_rperr spio_noc.router_0_7_7_p6_rperr 0x4C0EC 0x4C0EF 0x4C0F0 0x4C0F0 spio_noc.router_0_7_7_p7_rperr spio_noc.router_0_7_7_p7_rperr 0x4C0F4 0x4C0F7 0x4C0F8 0x4C0F8 spio_noc.router_0_7_7_p0_rperrm spio_noc.router_0_7_7_p0_rperrm 0x4C0FC 0x4C0FF 0x4C100 0x4C100 spio_noc.router_0_7_7_p1_rperrm spio_noc.router_0_7_7_p1_rperrm 0x4C104 0x4C107 0x4C108 0x4C108 spio_noc.router_0_7_7_p2_rperrm spio_noc.router_0_7_7_p2_rperrm 0x4C10C 0x4C117 0x4C118 0x4C118 spio_noc.router_0_7_7_p4_rperrm spio_noc.router_0_7_7_p4_rperrm 0x4C11C 0x4C11F 0x4C120 0x4C120 spio_noc.router_0_7_7_p5_rperrm spio_noc.router_0_7_7_p5_rperrm 0x4C124 0x4C127 0x4C128 0x4C128 spio_noc.router_0_7_7_p6_rperrm spio_noc.router_0_7_7_p6_rperrm 0x4C12C 0x4C12F 0x4C130 0x4C130 spio_noc.router_0_7_7_p7_rperrm spio_noc.router_0_7_7_p7_rperrm 0x4C134 0x4C137 0x4C138 0x4C138 spio_noc.router_0_7_7_roecc spio_noc.router_0_7_7_roecc 0x4C13C 0x4C13F 0x4C140 0x4C140 spio_noc.router_0_7_7_roec spio_noc.router_0_7_7_roec 0x4C144 0x4FFFF 0x50000 0x50000 spio_noc.router_0_8_8_rivcs_h spio_noc.router_0_8_8_rivcs_h 0x50004 0x50017 0x50018 0x50018 spio_noc.router_0_8_8_rivcs_w spio_noc.router_0_8_8_rivcs_w 0x5001C 0x5001F 0x50020 0x50020 spio_noc.router_0_8_8_rivcs_n spio_noc.router_0_8_8_rivcs_n 0x50024 0x50027 0x50028 0x50028 spio_noc.router_0_8_8_rivcs_i spio_noc.router_0_8_8_rivcs_i 0x5002C 0x5002F 0x50030 0x50030 spio_noc.router_0_8_8_rivcs_j spio_noc.router_0_8_8_rivcs_j 0x50034 0x50037 0x50038 0x50038 spio_noc.router_0_8_8_rivcs_k spio_noc.router_0_8_8_rivcs_k 0x5003C 0x5003F 0x50040 0x50040 spio_noc.router_0_8_8_rovcs_h spio_noc.router_0_8_8_rovcs_h 0x50044 0x50057 0x50058 0x50058 spio_noc.router_0_8_8_rovcs_w spio_noc.router_0_8_8_rovcs_w 0x5005C 0x5005F 0x50060 0x50060 spio_noc.router_0_8_8_rovcs_n spio_noc.router_0_8_8_rovcs_n 0x50064 0x50067 0x50068 0x50068 spio_noc.router_0_8_8_rovcs_i spio_noc.router_0_8_8_rovcs_i 0x5006C 0x5006F 0x50070 0x50070 spio_noc.router_0_8_8_rovcs_j spio_noc.router_0_8_8_rovcs_j 0x50074 0x50077 0x50078 0x50078 spio_noc.router_0_8_8_rovcs_k spio_noc.router_0_8_8_rovcs_k 0x5007C 0x5007F 0x50080 0x50080 spio_noc.router_0_8_8_re spio_noc.router_0_8_8_re 0x50084 0x50087 0x50088 0x50088 spio_noc.router_0_8_8_rem spio_noc.router_0_8_8_rem 0x5008C 0x5008F 0x50090 0x50090 spio_noc.router_0_8_8_recc spio_noc.router_0_8_8_recc 0x50094 0x50097 0x50098 0x50098 spio_noc.router_0_8_8_rec spio_noc.router_0_8_8_rec 0x5009C 0x5009F 0x500A0 0x500A0 spio_noc.router_0_8_8_id spio_noc.router_0_8_8_id 0x500A4 0x500A7 0x500A8 0x500A8 spio_noc.router_0_8_8_rcgc spio_noc.router_0_8_8_rcgc 0x500AC 0x500AF 0x500B0 0x500B0 spio_noc.router_0_8_8_rcgo spio_noc.router_0_8_8_rcgo 0x500B4 0x500B7 0x500B8 0x500B8 spio_noc.router_0_8_8_p0_rperr spio_noc.router_0_8_8_p0_rperr 0x500BC 0x500C7 0x500C8 0x500C8 spio_noc.router_0_8_8_p2_rperr spio_noc.router_0_8_8_p2_rperr 0x500CC 0x500D7 0x500D8 0x500D8 spio_noc.router_0_8_8_p4_rperr spio_noc.router_0_8_8_p4_rperr 0x500DC 0x500DF 0x500E0 0x500E0 spio_noc.router_0_8_8_p5_rperr spio_noc.router_0_8_8_p5_rperr 0x500E4 0x500E7 0x500E8 0x500E8 spio_noc.router_0_8_8_p6_rperr spio_noc.router_0_8_8_p6_rperr 0x500EC 0x500EF 0x500F0 0x500F0 spio_noc.router_0_8_8_p7_rperr spio_noc.router_0_8_8_p7_rperr 0x500F4 0x500F7 0x500F8 0x500F8 spio_noc.router_0_8_8_p0_rperrm spio_noc.router_0_8_8_p0_rperrm 0x500FC 0x50107 0x50108 0x50108 spio_noc.router_0_8_8_p2_rperrm spio_noc.router_0_8_8_p2_rperrm 0x5010C 0x50117 0x50118 0x50118 spio_noc.router_0_8_8_p4_rperrm spio_noc.router_0_8_8_p4_rperrm 0x5011C 0x5011F 0x50120 0x50120 spio_noc.router_0_8_8_p5_rperrm spio_noc.router_0_8_8_p5_rperrm 0x50124 0x50127 0x50128 0x50128 spio_noc.router_0_8_8_p6_rperrm spio_noc.router_0_8_8_p6_rperrm 0x5012C 0x5012F 0x50130 0x50130 spio_noc.router_0_8_8_p7_rperrm spio_noc.router_0_8_8_p7_rperrm 0x50134 0x50137 0x50138 0x50138 spio_noc.router_0_8_8_roecc spio_noc.router_0_8_8_roecc 0x5013C 0x5013F 0x50140 0x50140 spio_noc.router_0_8_8_roec spio_noc.router_0_8_8_roec 0x50144 0x53FFF 0x54000 0x54000 spio_noc.router_1_6_6_rivcs_h spio_noc.router_1_6_6_rivcs_h 0x54004 0x54007 0x54008 0x54008 spio_noc.router_1_6_6_rivcs_e spio_noc.router_1_6_6_rivcs_e 0x5400C 0x5400F 0x54010 0x54010 spio_noc.router_1_6_6_rivcs_s spio_noc.router_1_6_6_rivcs_s 0x54014 0x54017 0x54018 0x54018 spio_noc.router_1_6_6_rivcs_w spio_noc.router_1_6_6_rivcs_w 0x5401C 0x5401F 0x54020 0x54020 spio_noc.router_1_6_6_rivcs_n spio_noc.router_1_6_6_rivcs_n 0x54024 0x54027 0x54028 0x54028 spio_noc.router_1_6_6_rivcs_i spio_noc.router_1_6_6_rivcs_i 0x5402C 0x5402F 0x54030 0x54030 spio_noc.router_1_6_6_rivcs_j spio_noc.router_1_6_6_rivcs_j 0x54034 0x54037 0x54038 0x54038 spio_noc.router_1_6_6_rivcs_k spio_noc.router_1_6_6_rivcs_k 0x5403C 0x5403F 0x54040 0x54040 spio_noc.router_1_6_6_rovcs_h spio_noc.router_1_6_6_rovcs_h 0x54044 0x54047 0x54048 0x54048 spio_noc.router_1_6_6_rovcs_e spio_noc.router_1_6_6_rovcs_e 0x5404C 0x5404F 0x54050 0x54050 spio_noc.router_1_6_6_rovcs_s spio_noc.router_1_6_6_rovcs_s 0x54054 0x54057 0x54058 0x54058 spio_noc.router_1_6_6_rovcs_w spio_noc.router_1_6_6_rovcs_w 0x5405C 0x5405F 0x54060 0x54060 spio_noc.router_1_6_6_rovcs_n spio_noc.router_1_6_6_rovcs_n 0x54064 0x54067 0x54068 0x54068 spio_noc.router_1_6_6_rovcs_i spio_noc.router_1_6_6_rovcs_i 0x5406C 0x5406F 0x54070 0x54070 spio_noc.router_1_6_6_rovcs_j spio_noc.router_1_6_6_rovcs_j 0x54074 0x54077 0x54078 0x54078 spio_noc.router_1_6_6_rovcs_k spio_noc.router_1_6_6_rovcs_k 0x5407C 0x5407F 0x54080 0x54080 spio_noc.router_1_6_6_re spio_noc.router_1_6_6_re 0x54084 0x54087 0x54088 0x54088 spio_noc.router_1_6_6_rem spio_noc.router_1_6_6_rem 0x5408C 0x5408F 0x54090 0x54090 spio_noc.router_1_6_6_recc spio_noc.router_1_6_6_recc 0x54094 0x54097 0x54098 0x54098 spio_noc.router_1_6_6_rec spio_noc.router_1_6_6_rec 0x5409C 0x5409F 0x540A0 0x540A0 spio_noc.router_1_6_6_id spio_noc.router_1_6_6_id 0x540A4 0x540A7 0x540A8 0x540A8 spio_noc.router_1_6_6_rcgc spio_noc.router_1_6_6_rcgc 0x540AC 0x540AF 0x540B0 0x540B0 spio_noc.router_1_6_6_rcgo spio_noc.router_1_6_6_rcgo 0x540B4 0x540B7 0x540B8 0x540B8 spio_noc.router_1_6_6_p0_rperr spio_noc.router_1_6_6_p0_rperr 0x540BC 0x540BF 0x540C0 0x540C0 spio_noc.router_1_6_6_p1_rperr spio_noc.router_1_6_6_p1_rperr 0x540C4 0x540C7 0x540C8 0x540C8 spio_noc.router_1_6_6_p2_rperr spio_noc.router_1_6_6_p2_rperr 0x540CC 0x540CF 0x540D0 0x540D0 spio_noc.router_1_6_6_p3_rperr spio_noc.router_1_6_6_p3_rperr 0x540D4 0x540D7 0x540D8 0x540D8 spio_noc.router_1_6_6_p4_rperr spio_noc.router_1_6_6_p4_rperr 0x540DC 0x540DF 0x540E0 0x540E0 spio_noc.router_1_6_6_p5_rperr spio_noc.router_1_6_6_p5_rperr 0x540E4 0x540E7 0x540E8 0x540E8 spio_noc.router_1_6_6_p6_rperr spio_noc.router_1_6_6_p6_rperr 0x540EC 0x540EF 0x540F0 0x540F0 spio_noc.router_1_6_6_p7_rperr spio_noc.router_1_6_6_p7_rperr 0x540F4 0x540F7 0x540F8 0x540F8 spio_noc.router_1_6_6_p0_rperrm spio_noc.router_1_6_6_p0_rperrm 0x540FC 0x540FF 0x54100 0x54100 spio_noc.router_1_6_6_p1_rperrm spio_noc.router_1_6_6_p1_rperrm 0x54104 0x54107 0x54108 0x54108 spio_noc.router_1_6_6_p2_rperrm spio_noc.router_1_6_6_p2_rperrm 0x5410C 0x5410F 0x54110 0x54110 spio_noc.router_1_6_6_p3_rperrm spio_noc.router_1_6_6_p3_rperrm 0x54114 0x54117 0x54118 0x54118 spio_noc.router_1_6_6_p4_rperrm spio_noc.router_1_6_6_p4_rperrm 0x5411C 0x5411F 0x54120 0x54120 spio_noc.router_1_6_6_p5_rperrm spio_noc.router_1_6_6_p5_rperrm 0x54124 0x54127 0x54128 0x54128 spio_noc.router_1_6_6_p6_rperrm spio_noc.router_1_6_6_p6_rperrm 0x5412C 0x5412F 0x54130 0x54130 spio_noc.router_1_6_6_p7_rperrm spio_noc.router_1_6_6_p7_rperrm 0x54134 0x54137 0x54138 0x54138 spio_noc.router_1_6_6_roecc spio_noc.router_1_6_6_roecc 0x5413C 0x5413F 0x54140 0x54140 spio_noc.router_1_6_6_roec spio_noc.router_1_6_6_roec 0x54144 0x57FFF 0x58000 0x58000 spio_noc.router_1_7_7_rivcs_h spio_noc.router_1_7_7_rivcs_h 0x58004 0x58007 0x58008 0x58008 spio_noc.router_1_7_7_rivcs_e spio_noc.router_1_7_7_rivcs_e 0x5800C 0x58017 0x58018 0x58018 spio_noc.router_1_7_7_rivcs_w spio_noc.router_1_7_7_rivcs_w 0x5801C 0x5801F 0x58020 0x58020 spio_noc.router_1_7_7_rivcs_n spio_noc.router_1_7_7_rivcs_n 0x58024 0x58027 0x58028 0x58028 spio_noc.router_1_7_7_rivcs_i spio_noc.router_1_7_7_rivcs_i 0x5802C 0x5802F 0x58030 0x58030 spio_noc.router_1_7_7_rivcs_j spio_noc.router_1_7_7_rivcs_j 0x58034 0x58037 0x58038 0x58038 spio_noc.router_1_7_7_rivcs_k spio_noc.router_1_7_7_rivcs_k 0x5803C 0x5803F 0x58040 0x58040 spio_noc.router_1_7_7_rovcs_h spio_noc.router_1_7_7_rovcs_h 0x58044 0x58047 0x58048 0x58048 spio_noc.router_1_7_7_rovcs_e spio_noc.router_1_7_7_rovcs_e 0x5804C 0x58057 0x58058 0x58058 spio_noc.router_1_7_7_rovcs_w spio_noc.router_1_7_7_rovcs_w 0x5805C 0x5805F 0x58060 0x58060 spio_noc.router_1_7_7_rovcs_n spio_noc.router_1_7_7_rovcs_n 0x58064 0x58067 0x58068 0x58068 spio_noc.router_1_7_7_rovcs_i spio_noc.router_1_7_7_rovcs_i 0x5806C 0x5806F 0x58070 0x58070 spio_noc.router_1_7_7_rovcs_j spio_noc.router_1_7_7_rovcs_j 0x58074 0x58077 0x58078 0x58078 spio_noc.router_1_7_7_rovcs_k spio_noc.router_1_7_7_rovcs_k 0x5807C 0x5807F 0x58080 0x58080 spio_noc.router_1_7_7_re spio_noc.router_1_7_7_re 0x58084 0x58087 0x58088 0x58088 spio_noc.router_1_7_7_rem spio_noc.router_1_7_7_rem 0x5808C 0x5808F 0x58090 0x58090 spio_noc.router_1_7_7_recc spio_noc.router_1_7_7_recc 0x58094 0x58097 0x58098 0x58098 spio_noc.router_1_7_7_rec spio_noc.router_1_7_7_rec 0x5809C 0x5809F 0x580A0 0x580A0 spio_noc.router_1_7_7_id spio_noc.router_1_7_7_id 0x580A4 0x580A7 0x580A8 0x580A8 spio_noc.router_1_7_7_rcgc spio_noc.router_1_7_7_rcgc 0x580AC 0x580AF 0x580B0 0x580B0 spio_noc.router_1_7_7_rcgo spio_noc.router_1_7_7_rcgo 0x580B4 0x580B7 0x580B8 0x580B8 spio_noc.router_1_7_7_p0_rperr spio_noc.router_1_7_7_p0_rperr 0x580BC 0x580BF 0x580C0 0x580C0 spio_noc.router_1_7_7_p1_rperr spio_noc.router_1_7_7_p1_rperr 0x580C4 0x580C7 0x580C8 0x580C8 spio_noc.router_1_7_7_p2_rperr spio_noc.router_1_7_7_p2_rperr 0x580CC 0x580D7 0x580D8 0x580D8 spio_noc.router_1_7_7_p4_rperr spio_noc.router_1_7_7_p4_rperr 0x580DC 0x580DF 0x580E0 0x580E0 spio_noc.router_1_7_7_p5_rperr spio_noc.router_1_7_7_p5_rperr 0x580E4 0x580E7 0x580E8 0x580E8 spio_noc.router_1_7_7_p6_rperr spio_noc.router_1_7_7_p6_rperr 0x580EC 0x580EF 0x580F0 0x580F0 spio_noc.router_1_7_7_p7_rperr spio_noc.router_1_7_7_p7_rperr 0x580F4 0x580F7 0x580F8 0x580F8 spio_noc.router_1_7_7_p0_rperrm spio_noc.router_1_7_7_p0_rperrm 0x580FC 0x580FF 0x58100 0x58100 spio_noc.router_1_7_7_p1_rperrm spio_noc.router_1_7_7_p1_rperrm 0x58104 0x58107 0x58108 0x58108 spio_noc.router_1_7_7_p2_rperrm spio_noc.router_1_7_7_p2_rperrm 0x5810C 0x58117 0x58118 0x58118 spio_noc.router_1_7_7_p4_rperrm spio_noc.router_1_7_7_p4_rperrm 0x5811C 0x5811F 0x58120 0x58120 spio_noc.router_1_7_7_p5_rperrm spio_noc.router_1_7_7_p5_rperrm 0x58124 0x58127 0x58128 0x58128 spio_noc.router_1_7_7_p6_rperrm spio_noc.router_1_7_7_p6_rperrm 0x5812C 0x5812F 0x58130 0x58130 spio_noc.router_1_7_7_p7_rperrm spio_noc.router_1_7_7_p7_rperrm 0x58134 0x58137 0x58138 0x58138 spio_noc.router_1_7_7_roecc spio_noc.router_1_7_7_roecc 0x5813C 0x5813F 0x58140 0x58140 spio_noc.router_1_7_7_roec spio_noc.router_1_7_7_roec 0x58144 0x5BFFF 0x5C000 0x5C000 spio_noc.router_1_8_8_rivcs_h spio_noc.router_1_8_8_rivcs_h 0x5C004 0x5C017 0x5C018 0x5C018 spio_noc.router_1_8_8_rivcs_w spio_noc.router_1_8_8_rivcs_w 0x5C01C 0x5C01F 0x5C020 0x5C020 spio_noc.router_1_8_8_rivcs_n spio_noc.router_1_8_8_rivcs_n 0x5C024 0x5C027 0x5C028 0x5C028 spio_noc.router_1_8_8_rivcs_i spio_noc.router_1_8_8_rivcs_i 0x5C02C 0x5C02F 0x5C030 0x5C030 spio_noc.router_1_8_8_rivcs_j spio_noc.router_1_8_8_rivcs_j 0x5C034 0x5C037 0x5C038 0x5C038 spio_noc.router_1_8_8_rivcs_k spio_noc.router_1_8_8_rivcs_k 0x5C03C 0x5C03F 0x5C040 0x5C040 spio_noc.router_1_8_8_rovcs_h spio_noc.router_1_8_8_rovcs_h 0x5C044 0x5C057 0x5C058 0x5C058 spio_noc.router_1_8_8_rovcs_w spio_noc.router_1_8_8_rovcs_w 0x5C05C 0x5C05F 0x5C060 0x5C060 spio_noc.router_1_8_8_rovcs_n spio_noc.router_1_8_8_rovcs_n 0x5C064 0x5C067 0x5C068 0x5C068 spio_noc.router_1_8_8_rovcs_i spio_noc.router_1_8_8_rovcs_i 0x5C06C 0x5C06F 0x5C070 0x5C070 spio_noc.router_1_8_8_rovcs_j spio_noc.router_1_8_8_rovcs_j 0x5C074 0x5C077 0x5C078 0x5C078 spio_noc.router_1_8_8_rovcs_k spio_noc.router_1_8_8_rovcs_k 0x5C07C 0x5C07F 0x5C080 0x5C080 spio_noc.router_1_8_8_re spio_noc.router_1_8_8_re 0x5C084 0x5C087 0x5C088 0x5C088 spio_noc.router_1_8_8_rem spio_noc.router_1_8_8_rem 0x5C08C 0x5C08F 0x5C090 0x5C090 spio_noc.router_1_8_8_recc spio_noc.router_1_8_8_recc 0x5C094 0x5C097 0x5C098 0x5C098 spio_noc.router_1_8_8_rec spio_noc.router_1_8_8_rec 0x5C09C 0x5C09F 0x5C0A0 0x5C0A0 spio_noc.router_1_8_8_id spio_noc.router_1_8_8_id 0x5C0A4 0x5C0A7 0x5C0A8 0x5C0A8 spio_noc.router_1_8_8_rcgc spio_noc.router_1_8_8_rcgc 0x5C0AC 0x5C0AF 0x5C0B0 0x5C0B0 spio_noc.router_1_8_8_rcgo spio_noc.router_1_8_8_rcgo 0x5C0B4 0x5C0B7 0x5C0B8 0x5C0B8 spio_noc.router_1_8_8_p0_rperr spio_noc.router_1_8_8_p0_rperr 0x5C0BC 0x5C0C7 0x5C0C8 0x5C0C8 spio_noc.router_1_8_8_p2_rperr spio_noc.router_1_8_8_p2_rperr 0x5C0CC 0x5C0D7 0x5C0D8 0x5C0D8 spio_noc.router_1_8_8_p4_rperr spio_noc.router_1_8_8_p4_rperr 0x5C0DC 0x5C0DF 0x5C0E0 0x5C0E0 spio_noc.router_1_8_8_p5_rperr spio_noc.router_1_8_8_p5_rperr 0x5C0E4 0x5C0E7 0x5C0E8 0x5C0E8 spio_noc.router_1_8_8_p6_rperr spio_noc.router_1_8_8_p6_rperr 0x5C0EC 0x5C0EF 0x5C0F0 0x5C0F0 spio_noc.router_1_8_8_p7_rperr spio_noc.router_1_8_8_p7_rperr 0x5C0F4 0x5C0F7 0x5C0F8 0x5C0F8 spio_noc.router_1_8_8_p0_rperrm spio_noc.router_1_8_8_p0_rperrm 0x5C0FC 0x5C107 0x5C108 0x5C108 spio_noc.router_1_8_8_p2_rperrm spio_noc.router_1_8_8_p2_rperrm 0x5C10C 0x5C117 0x5C118 0x5C118 spio_noc.router_1_8_8_p4_rperrm spio_noc.router_1_8_8_p4_rperrm 0x5C11C 0x5C11F 0x5C120 0x5C120 spio_noc.router_1_8_8_p5_rperrm spio_noc.router_1_8_8_p5_rperrm 0x5C124 0x5C127 0x5C128 0x5C128 spio_noc.router_1_8_8_p6_rperrm spio_noc.router_1_8_8_p6_rperrm 0x5C12C 0x5C12F 0x5C130 0x5C130 spio_noc.router_1_8_8_p7_rperrm spio_noc.router_1_8_8_p7_rperrm 0x5C134 0x5C137 0x5C138 0x5C138 spio_noc.router_1_8_8_roecc spio_noc.router_1_8_8_roecc 0x5C13C 0x5C13F 0x5C140 0x5C140 spio_noc.router_1_8_8_roec spio_noc.router_1_8_8_roec 0x5C144 0x6007F 0x60080 0x60080 spio_noc.router_2_1_1_re spio_noc.router_2_1_1_re 0x60084 0x60087 0x60088 0x60088 spio_noc.router_2_1_1_rem spio_noc.router_2_1_1_rem 0x6008C 0x6009F 0x600A0 0x600A0 spio_noc.router_2_1_1_id spio_noc.router_2_1_1_id 0x600A4 0x600AF 0x600B0 0x600B0 spio_noc.router_2_1_1_rcgo spio_noc.router_2_1_1_rcgo 0x600B4 0x600BF 0x600C0 0x600C0 spio_noc.router_2_1_1_p1_rperr spio_noc.router_2_1_1_p1_rperr 0x600C4 0x600C7 0x600C8 0x600C8 spio_noc.router_2_1_1_p2_rperr spio_noc.router_2_1_1_p2_rperr 0x600CC 0x600CF 0x600D0 0x600D0 spio_noc.router_2_1_1_p3_rperr spio_noc.router_2_1_1_p3_rperr 0x600D4 0x600D7 0x600D8 0x600D8 spio_noc.router_2_1_1_p4_rperr spio_noc.router_2_1_1_p4_rperr 0x600DC 0x600FF 0x60100 0x60100 spio_noc.router_2_1_1_p1_rperrm spio_noc.router_2_1_1_p1_rperrm 0x60104 0x60107 0x60108 0x60108 spio_noc.router_2_1_1_p2_rperrm spio_noc.router_2_1_1_p2_rperrm 0x6010C 0x6010F 0x60110 0x60110 spio_noc.router_2_1_1_p3_rperrm spio_noc.router_2_1_1_p3_rperrm 0x60114 0x60117 0x60118 0x60118 spio_noc.router_2_1_1_p4_rperrm spio_noc.router_2_1_1_p4_rperrm 0x6011C 0x6407F 0x64080 0x64080 spio_noc.router_2_6_6_re spio_noc.router_2_6_6_re 0x64084 0x64087 0x64088 0x64088 spio_noc.router_2_6_6_rem spio_noc.router_2_6_6_rem 0x6408C 0x6409F 0x640A0 0x640A0 spio_noc.router_2_6_6_id spio_noc.router_2_6_6_id 0x640A4 0x640AF 0x640B0 0x640B0 spio_noc.router_2_6_6_rcgo spio_noc.router_2_6_6_rcgo 0x640B4 0x640B7 0x640B8 0x640B8 spio_noc.router_2_6_6_p0_rperr spio_noc.router_2_6_6_p0_rperr 0x640BC 0x640BF 0x640C0 0x640C0 spio_noc.router_2_6_6_p1_rperr spio_noc.router_2_6_6_p1_rperr 0x640C4 0x640D7 0x640D8 0x640D8 spio_noc.router_2_6_6_p4_rperr spio_noc.router_2_6_6_p4_rperr 0x640DC 0x640F7 0x640F8 0x640F8 spio_noc.router_2_6_6_p0_rperrm spio_noc.router_2_6_6_p0_rperrm 0x640FC 0x640FF 0x64100 0x64100 spio_noc.router_2_6_6_p1_rperrm spio_noc.router_2_6_6_p1_rperrm 0x64104 0x64117 0x64118 0x64118 spio_noc.router_2_6_6_p4_rperrm spio_noc.router_2_6_6_p4_rperrm 0x6411C 0x6807F 0x68080 0x68080 spio_noc.router_2_7_7_re spio_noc.router_2_7_7_re 0x68084 0x68087 0x68088 0x68088 spio_noc.router_2_7_7_rem spio_noc.router_2_7_7_rem 0x6808C 0x6809F 0x680A0 0x680A0 spio_noc.router_2_7_7_id spio_noc.router_2_7_7_id 0x680A4 0x680AF 0x680B0 0x680B0 spio_noc.router_2_7_7_rcgo spio_noc.router_2_7_7_rcgo 0x680B4 0x680BF 0x680C0 0x680C0 spio_noc.router_2_7_7_p1_rperr spio_noc.router_2_7_7_p1_rperr 0x680C4 0x680C7 0x680C8 0x680C8 spio_noc.router_2_7_7_p2_rperr spio_noc.router_2_7_7_p2_rperr 0x680CC 0x680D7 0x680D8 0x680D8 spio_noc.router_2_7_7_p4_rperr spio_noc.router_2_7_7_p4_rperr 0x680DC 0x680FF 0x68100 0x68100 spio_noc.router_2_7_7_p1_rperrm spio_noc.router_2_7_7_p1_rperrm 0x68104 0x68107 0x68108 0x68108 spio_noc.router_2_7_7_p2_rperrm spio_noc.router_2_7_7_p2_rperrm 0x6810C 0x68117 0x68118 0x68118 spio_noc.router_2_7_7_p4_rperrm spio_noc.router_2_7_7_p4_rperrm 0x6811C 0x68137 register spio_noc.bridge_rbm_m_17_1_p_0 bridge_rbm_m_17_1_p_0 SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 93 rbm_m register p_0 0x3000 R 0x00000000 Spio_noc_bridge_rbm_m_17_1_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_0_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_0_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_0_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_0_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_0_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_0_GET SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_0_SET ns_noc_io_spio_soc_ip.csr 56 WT_QOS_0 Weight of QoS profile 0 7 0 0x00 R WT_QOS_1 SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_1_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_1_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_1_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_1_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_1_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_1_GET SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_1_SET ns_noc_io_spio_soc_ip.csr 68 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_2_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_2_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_2_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_2_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_2_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_2_GET SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_2_SET ns_noc_io_spio_soc_ip.csr 80 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_3_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_3_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_3_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_3_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_3_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_3_GET SPIO_NOC_BRIDGE_RBM_M_17_1_P_0_WT_QOS_3_SET ns_noc_io_spio_soc_ip.csr 92 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register spio_noc.bridge_rbm_m_17_1_p_1 bridge_rbm_m_17_1_p_1 SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 159 rbm_m register p_1 0x3008 R 0x00000000 Spio_noc_bridge_rbm_m_17_1_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_4_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_4_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_4_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_4_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_4_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_4_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_4_GET SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_4_SET ns_noc_io_spio_soc_ip.csr 122 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_5_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_5_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_5_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_5_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_5_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_5_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_5_GET SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_5_SET ns_noc_io_spio_soc_ip.csr 134 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_6_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_6_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_6_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_6_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_6_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_6_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_6_GET SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_6_SET ns_noc_io_spio_soc_ip.csr 146 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_7_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_7_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_7_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_7_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_7_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_7_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_7_GET SPIO_NOC_BRIDGE_RBM_M_17_1_P_1_WT_QOS_7_SET ns_noc_io_spio_soc_ip.csr 158 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register spio_noc.bridge_rbm_m_17_1_p_2 bridge_rbm_m_17_1_p_2 SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 225 rbm_m register p_2 0x3010 R 0x00000000 Spio_noc_bridge_rbm_m_17_1_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_8_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_8_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_8_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_8_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_8_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_8_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_8_GET SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_8_SET ns_noc_io_spio_soc_ip.csr 188 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_9_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_9_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_9_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_9_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_9_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_9_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_9_GET SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_9_SET ns_noc_io_spio_soc_ip.csr 200 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_10_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_10_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_10_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_10_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_10_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_10_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_10_GET SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_10_SET ns_noc_io_spio_soc_ip.csr 212 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_11_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_11_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_11_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_11_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_11_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_11_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_11_GET SPIO_NOC_BRIDGE_RBM_M_17_1_P_2_WT_QOS_11_SET ns_noc_io_spio_soc_ip.csr 224 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register spio_noc.bridge_rbm_m_17_1_p_3 bridge_rbm_m_17_1_p_3 SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 291 rbm_m register p_3 0x3018 R 0x00000000 Spio_noc_bridge_rbm_m_17_1_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_12_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_12_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_12_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_12_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_12_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_12_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_12_GET SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_12_SET ns_noc_io_spio_soc_ip.csr 254 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_13_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_13_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_13_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_13_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_13_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_13_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_13_GET SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_13_SET ns_noc_io_spio_soc_ip.csr 266 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_14_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_14_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_14_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_14_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_14_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_14_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_14_GET SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_14_SET ns_noc_io_spio_soc_ip.csr 278 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_15_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_15_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_15_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_15_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_15_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_15_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_15_GET SPIO_NOC_BRIDGE_RBM_M_17_1_P_3_WT_QOS_15_SET ns_noc_io_spio_soc_ip.csr 290 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register spio_noc.bridge_rbm_m_17_1_txe bridge_rbm_m_17_1_txe SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 437 rbm_m register txe 0x3040 R/W 0x00000000 Spio_noc_bridge_rbm_m_17_1_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_TRANS_WITHOUT_SOP_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_TRANS_WITHOUT_SOP_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_TRANS_WITHOUT_SOP_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_TRANS_WITHOUT_SOP_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_TRANS_WITHOUT_SOP_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_TRANS_WITHOUT_SOP_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_TRANS_WITHOUT_SOP_GET SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_spio_soc_ip.csr 318 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_SOP_AFTER_SOP_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_SOP_AFTER_SOP_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_SOP_AFTER_SOP_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_SOP_AFTER_SOP_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_SOP_AFTER_SOP_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_SOP_AFTER_SOP_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_SOP_AFTER_SOP_GET SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_SOP_AFTER_SOP_SET ns_noc_io_spio_soc_ip.csr 330 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 345 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 358 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_A_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_A_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_A_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_A_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_A_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_A_GET SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_spio_soc_ip.csr 372 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_B_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_B_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_B_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_B_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_B_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_B_GET SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_spio_soc_ip.csr 386 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_C_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_C_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_C_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_C_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_C_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_C_GET SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_spio_soc_ip.csr 400 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_D_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_D_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_D_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_D_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_D_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_D_GET SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_spio_soc_ip.csr 414 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 425 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_UNSD_31_9_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_UNSD_31_9_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_UNSD_31_9_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_UNSD_31_9_GET SPIO_NOC_BRIDGE_RBM_M_17_1_TXE_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 436 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_rbm_m_17_1_txem bridge_rbm_m_17_1_txem SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 516 rbm_m register txem 0x3048 R/W 0x00000008 Spio_noc_bridge_rbm_m_17_1_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_UNSD_1_0_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_UNSD_1_0_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_UNSD_1_0_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_UNSD_1_0_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_UNSD_1_0_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_UNSD_1_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_UNSD_1_0_GET SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_UNSD_1_0_SET ns_noc_io_spio_soc_ip.csr 460 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 471 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 482 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_UNSD_7_4_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_UNSD_7_4_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_UNSD_7_4_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_UNSD_7_4_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_UNSD_7_4_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_UNSD_7_4_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_UNSD_7_4_GET SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_UNSD_7_4_SET ns_noc_io_spio_soc_ip.csr 493 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 504 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_UNSD_31_9_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_UNSD_31_9_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_UNSD_31_9_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_UNSD_31_9_GET SPIO_NOC_BRIDGE_RBM_M_17_1_TXEM_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 515 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_rbm_m_17_1_btus_0 bridge_rbm_m_17_1_btus_0 SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 884 rbm_m register btus_0 0x3058 R 0x00000000 Spio_noc_bridge_rbm_m_17_1_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_A_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_A_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_A_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_A_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_A_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_A_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_A_SET ns_noc_io_spio_soc_ip.csr 542 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_B_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_B_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_B_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_B_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_B_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_B_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_B_SET ns_noc_io_spio_soc_ip.csr 553 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_C_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_C_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_C_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_C_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_C_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_C_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_C_SET ns_noc_io_spio_soc_ip.csr 564 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_D_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_D_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_D_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_D_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_D_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_D_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L0_D_SET ns_noc_io_spio_soc_ip.csr 575 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_A_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_A_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_A_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_A_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_A_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_A_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_A_SET ns_noc_io_spio_soc_ip.csr 586 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_B_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_B_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_B_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_B_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_B_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_B_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_B_SET ns_noc_io_spio_soc_ip.csr 597 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_C_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_C_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_C_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_C_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_C_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_C_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_C_SET ns_noc_io_spio_soc_ip.csr 608 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_D_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_D_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_D_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_D_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_D_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_D_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L1_D_SET ns_noc_io_spio_soc_ip.csr 619 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_A_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_A_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_A_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_A_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_A_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_A_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_A_SET ns_noc_io_spio_soc_ip.csr 630 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_B_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_B_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_B_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_B_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_B_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_B_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_B_SET ns_noc_io_spio_soc_ip.csr 641 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_C_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_C_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_C_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_C_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_C_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_C_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_C_SET ns_noc_io_spio_soc_ip.csr 652 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_D_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_D_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_D_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_D_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_D_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_D_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L2_D_SET ns_noc_io_spio_soc_ip.csr 663 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_A_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_A_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_A_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_A_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_A_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_A_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_A_SET ns_noc_io_spio_soc_ip.csr 674 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_B_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_B_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_B_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_B_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_B_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_B_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_B_SET ns_noc_io_spio_soc_ip.csr 685 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_C_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_C_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_C_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_C_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_C_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_C_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_C_SET ns_noc_io_spio_soc_ip.csr 696 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_D_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_D_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_D_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_D_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_D_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_D_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L3_D_SET ns_noc_io_spio_soc_ip.csr 707 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_A_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_A_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_A_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_A_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_A_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_A_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_A_SET ns_noc_io_spio_soc_ip.csr 718 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_B_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_B_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_B_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_B_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_B_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_B_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_B_SET ns_noc_io_spio_soc_ip.csr 729 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_C_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_C_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_C_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_C_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_C_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_C_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_C_SET ns_noc_io_spio_soc_ip.csr 740 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_D_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_D_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_D_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_D_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_D_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_D_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L4_D_SET ns_noc_io_spio_soc_ip.csr 751 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_A_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_A_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_A_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_A_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_A_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_A_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_A_SET ns_noc_io_spio_soc_ip.csr 762 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_B_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_B_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_B_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_B_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_B_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_B_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_B_SET ns_noc_io_spio_soc_ip.csr 773 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_C_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_C_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_C_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_C_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_C_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_C_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_C_SET ns_noc_io_spio_soc_ip.csr 784 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_D_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_D_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_D_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_D_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_D_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_D_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L5_D_SET ns_noc_io_spio_soc_ip.csr 795 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_A_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_A_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_A_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_A_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_A_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_A_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_A_SET ns_noc_io_spio_soc_ip.csr 806 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_B_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_B_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_B_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_B_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_B_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_B_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_B_SET ns_noc_io_spio_soc_ip.csr 817 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_C_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_C_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_C_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_C_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_C_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_C_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_C_SET ns_noc_io_spio_soc_ip.csr 828 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_D_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_D_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_D_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_D_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_D_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_D_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L6_D_SET ns_noc_io_spio_soc_ip.csr 839 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_A_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_A_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_A_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_A_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_A_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_A_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_A_SET ns_noc_io_spio_soc_ip.csr 850 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_B_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_B_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_B_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_B_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_B_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_B_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_B_SET ns_noc_io_spio_soc_ip.csr 861 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_C_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_C_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_C_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_C_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_C_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_C_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_C_SET ns_noc_io_spio_soc_ip.csr 872 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_D_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_D_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_D_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_D_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_D_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_D_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_0_L7_D_SET ns_noc_io_spio_soc_ip.csr 883 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register spio_noc.bridge_rbm_m_17_1_btus_1 bridge_rbm_m_17_1_btus_1 SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 1252 rbm_m register btus_1 0x3060 R 0x00000000 Spio_noc_bridge_rbm_m_17_1_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_A_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_A_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_A_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_A_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_A_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_A_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_A_SET ns_noc_io_spio_soc_ip.csr 910 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_B_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_B_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_B_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_B_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_B_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_B_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_B_SET ns_noc_io_spio_soc_ip.csr 921 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_C_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_C_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_C_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_C_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_C_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_C_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_C_SET ns_noc_io_spio_soc_ip.csr 932 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_D_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_D_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_D_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_D_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_D_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_D_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L8_D_SET ns_noc_io_spio_soc_ip.csr 943 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_A_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_A_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_A_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_A_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_A_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_A_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_A_SET ns_noc_io_spio_soc_ip.csr 954 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_B_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_B_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_B_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_B_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_B_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_B_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_B_SET ns_noc_io_spio_soc_ip.csr 965 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_C_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_C_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_C_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_C_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_C_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_C_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_C_SET ns_noc_io_spio_soc_ip.csr 976 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_D_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_D_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_D_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_D_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_D_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_D_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L9_D_SET ns_noc_io_spio_soc_ip.csr 987 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_A_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_A_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_A_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_A_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_A_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_A_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_A_SET ns_noc_io_spio_soc_ip.csr 998 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_B_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_B_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_B_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_B_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_B_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_B_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_B_SET ns_noc_io_spio_soc_ip.csr 1009 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_C_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_C_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_C_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_C_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_C_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_C_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_C_SET ns_noc_io_spio_soc_ip.csr 1020 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_D_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_D_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_D_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_D_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_D_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_D_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L10_D_SET ns_noc_io_spio_soc_ip.csr 1031 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_A_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_A_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_A_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_A_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_A_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_A_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_A_SET ns_noc_io_spio_soc_ip.csr 1042 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_B_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_B_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_B_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_B_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_B_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_B_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_B_SET ns_noc_io_spio_soc_ip.csr 1053 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_C_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_C_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_C_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_C_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_C_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_C_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_C_SET ns_noc_io_spio_soc_ip.csr 1064 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_D_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_D_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_D_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_D_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_D_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_D_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L11_D_SET ns_noc_io_spio_soc_ip.csr 1075 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_A_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_A_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_A_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_A_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_A_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_A_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_A_SET ns_noc_io_spio_soc_ip.csr 1086 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_B_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_B_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_B_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_B_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_B_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_B_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_B_SET ns_noc_io_spio_soc_ip.csr 1097 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_C_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_C_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_C_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_C_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_C_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_C_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_C_SET ns_noc_io_spio_soc_ip.csr 1108 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_D_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_D_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_D_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_D_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_D_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_D_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L12_D_SET ns_noc_io_spio_soc_ip.csr 1119 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_A_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_A_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_A_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_A_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_A_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_A_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_A_SET ns_noc_io_spio_soc_ip.csr 1130 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_B_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_B_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_B_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_B_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_B_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_B_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_B_SET ns_noc_io_spio_soc_ip.csr 1141 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_C_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_C_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_C_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_C_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_C_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_C_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_C_SET ns_noc_io_spio_soc_ip.csr 1152 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_D_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_D_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_D_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_D_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_D_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_D_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L13_D_SET ns_noc_io_spio_soc_ip.csr 1163 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_A_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_A_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_A_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_A_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_A_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_A_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_A_SET ns_noc_io_spio_soc_ip.csr 1174 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_B_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_B_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_B_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_B_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_B_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_B_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_B_SET ns_noc_io_spio_soc_ip.csr 1185 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_C_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_C_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_C_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_C_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_C_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_C_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_C_SET ns_noc_io_spio_soc_ip.csr 1196 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_D_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_D_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_D_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_D_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_D_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_D_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L14_D_SET ns_noc_io_spio_soc_ip.csr 1207 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_A_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_A_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_A_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_A_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_A_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_A_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_A_SET ns_noc_io_spio_soc_ip.csr 1218 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_B_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_B_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_B_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_B_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_B_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_B_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_B_SET ns_noc_io_spio_soc_ip.csr 1229 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_C_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_C_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_C_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_C_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_C_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_C_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_C_SET ns_noc_io_spio_soc_ip.csr 1240 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_D_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_D_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_D_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_D_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_D_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_D_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTUS_1_L15_D_SET ns_noc_io_spio_soc_ip.csr 1251 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register spio_noc.bridge_rbm_m_17_1_btrl_0 bridge_rbm_m_17_1_btrl_0 SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 1328 rbm_m register btrl_0 0x3080 R 0x00000000 Spio_noc_bridge_rbm_m_17_1_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_WT_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_WT_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_WT_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_WT_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_WT_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_WT_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_WT_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_WT_SET ns_noc_io_spio_soc_ip.csr 1276 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_RESV_15_12_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_RESV_15_12_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_RESV_15_12_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_RESV_15_12_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_RESV_15_12_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 1287 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_CNT_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_CNT_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_CNT_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_CNT_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_CNT_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_CNT_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_CNT_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_CNT_SET ns_noc_io_spio_soc_ip.csr 1302 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_EN_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_EN_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_EN_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_EN_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_EN_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_EN_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_EN_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_EN_SET ns_noc_io_spio_soc_ip.csr 1316 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_UNSD_31_21_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_UNSD_31_21_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_UNSD_31_21_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_UNSD_31_21_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_0_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 1327 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_rbm_m_17_1_btrl_1 bridge_rbm_m_17_1_btrl_1 SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 1404 rbm_m register btrl_1 0x3088 R 0x00000000 Spio_noc_bridge_rbm_m_17_1_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_WT_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_WT_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_WT_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_WT_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_WT_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_WT_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_WT_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_WT_SET ns_noc_io_spio_soc_ip.csr 1352 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_RESV_15_12_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_RESV_15_12_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_RESV_15_12_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_RESV_15_12_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_RESV_15_12_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 1363 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_CNT_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_CNT_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_CNT_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_CNT_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_CNT_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_CNT_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_CNT_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_CNT_SET ns_noc_io_spio_soc_ip.csr 1378 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_EN_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_EN_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_EN_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_EN_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_EN_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_EN_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_EN_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_EN_SET ns_noc_io_spio_soc_ip.csr 1392 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_UNSD_31_21_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_UNSD_31_21_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_UNSD_31_21_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_UNSD_31_21_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_1_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 1403 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_rbm_m_17_1_btrl_2 bridge_rbm_m_17_1_btrl_2 SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 1480 rbm_m register btrl_2 0x3090 R 0x00000000 Spio_noc_bridge_rbm_m_17_1_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_WT_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_WT_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_WT_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_WT_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_WT_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_WT_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_WT_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_WT_SET ns_noc_io_spio_soc_ip.csr 1428 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_RESV_15_12_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_RESV_15_12_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_RESV_15_12_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_RESV_15_12_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_RESV_15_12_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 1439 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_CNT_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_CNT_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_CNT_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_CNT_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_CNT_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_CNT_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_CNT_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_CNT_SET ns_noc_io_spio_soc_ip.csr 1454 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_EN_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_EN_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_EN_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_EN_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_EN_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_EN_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_EN_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_EN_SET ns_noc_io_spio_soc_ip.csr 1468 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_UNSD_31_21_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_UNSD_31_21_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_UNSD_31_21_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_UNSD_31_21_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_2_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 1479 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_rbm_m_17_1_btrl_3 bridge_rbm_m_17_1_btrl_3 SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 1556 rbm_m register btrl_3 0x3098 R 0x00000000 Spio_noc_bridge_rbm_m_17_1_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_WT_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_WT_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_WT_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_WT_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_WT_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_WT_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_WT_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_WT_SET ns_noc_io_spio_soc_ip.csr 1504 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_RESV_15_12_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_RESV_15_12_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_RESV_15_12_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_RESV_15_12_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_RESV_15_12_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 1515 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_CNT_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_CNT_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_CNT_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_CNT_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_CNT_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_CNT_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_CNT_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_CNT_SET ns_noc_io_spio_soc_ip.csr 1530 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_EN_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_EN_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_EN_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_EN_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_EN_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_EN_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_EN_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_EN_SET ns_noc_io_spio_soc_ip.csr 1544 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_UNSD_31_21_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_UNSD_31_21_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_UNSD_31_21_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_UNSD_31_21_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTRL_3_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 1555 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_rbm_m_17_1_btperr bridge_rbm_m_17_1_btperr SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 1758 rbm_m register btperr 0x30A8 R/W 0x00000000 Spio_noc_bridge_rbm_m_17_1_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L0_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L0_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L0_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L0_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L0_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L0_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L0_SET ns_noc_io_spio_soc_ip.csr 1581 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L1_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L1_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L1_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L1_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L1_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L1_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L1_SET ns_noc_io_spio_soc_ip.csr 1592 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L2_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L2_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L2_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L2_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L2_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L2_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L2_SET ns_noc_io_spio_soc_ip.csr 1603 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L3_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L3_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L3_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L3_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L3_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L3_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L3_SET ns_noc_io_spio_soc_ip.csr 1614 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L4_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L4_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L4_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L4_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L4_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L4_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L4_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L4_SET ns_noc_io_spio_soc_ip.csr 1625 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L5_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L5_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L5_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L5_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L5_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L5_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L5_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L5_SET ns_noc_io_spio_soc_ip.csr 1636 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L6_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L6_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L6_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L6_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L6_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L6_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L6_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L6_SET ns_noc_io_spio_soc_ip.csr 1647 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L7_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L7_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L7_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L7_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L7_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L7_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L7_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L7_SET ns_noc_io_spio_soc_ip.csr 1658 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L8_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L8_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L8_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L8_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L8_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L8_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L8_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L8_SET ns_noc_io_spio_soc_ip.csr 1669 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L9_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L9_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L9_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L9_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L9_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L9_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L9_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L9_SET ns_noc_io_spio_soc_ip.csr 1680 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L10_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L10_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L10_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L10_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L10_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L10_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L10_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L10_SET ns_noc_io_spio_soc_ip.csr 1691 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L11_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L11_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L11_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L11_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L11_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L11_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L11_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L11_SET ns_noc_io_spio_soc_ip.csr 1702 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L12_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L12_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L12_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L12_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L12_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L12_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L12_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L12_SET ns_noc_io_spio_soc_ip.csr 1713 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L13_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L13_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L13_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L13_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L13_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L13_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L13_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L13_SET ns_noc_io_spio_soc_ip.csr 1724 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L14_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L14_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L14_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L14_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L14_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L14_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L14_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L14_SET ns_noc_io_spio_soc_ip.csr 1735 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L15_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L15_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L15_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L15_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L15_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L15_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L15_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_L15_SET ns_noc_io_spio_soc_ip.csr 1746 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_UNSD_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_UNSD_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_UNSD_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_UNSD_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_UNSD_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_UNSD_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERR_UNSD_SET ns_noc_io_spio_soc_ip.csr 1757 UNSD 31 16 0x0000 R register spio_noc.bridge_rbm_m_17_1_btperrm bridge_rbm_m_17_1_btperrm SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 1958 rbm_m register btperrm 0x30B0 R/W 0x00000000 Spio_noc_bridge_rbm_m_17_1_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L0_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L0_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L0_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L0_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L0_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L0_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L0_SET ns_noc_io_spio_soc_ip.csr 1781 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L1_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L1_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L1_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L1_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L1_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L1_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L1_SET ns_noc_io_spio_soc_ip.csr 1792 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L2_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L2_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L2_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L2_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L2_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L2_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L2_SET ns_noc_io_spio_soc_ip.csr 1803 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L3_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L3_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L3_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L3_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L3_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L3_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L3_SET ns_noc_io_spio_soc_ip.csr 1814 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L4_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L4_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L4_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L4_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L4_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L4_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L4_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L4_SET ns_noc_io_spio_soc_ip.csr 1825 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L5_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L5_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L5_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L5_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L5_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L5_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L5_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L5_SET ns_noc_io_spio_soc_ip.csr 1836 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L6_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L6_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L6_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L6_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L6_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L6_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L6_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L6_SET ns_noc_io_spio_soc_ip.csr 1847 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L7_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L7_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L7_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L7_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L7_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L7_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L7_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L7_SET ns_noc_io_spio_soc_ip.csr 1858 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L8_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L8_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L8_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L8_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L8_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L8_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L8_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L8_SET ns_noc_io_spio_soc_ip.csr 1869 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L9_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L9_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L9_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L9_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L9_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L9_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L9_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L9_SET ns_noc_io_spio_soc_ip.csr 1880 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L10_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L10_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L10_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L10_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L10_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L10_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L10_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L10_SET ns_noc_io_spio_soc_ip.csr 1891 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L11_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L11_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L11_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L11_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L11_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L11_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L11_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L11_SET ns_noc_io_spio_soc_ip.csr 1902 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L12_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L12_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L12_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L12_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L12_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L12_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L12_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L12_SET ns_noc_io_spio_soc_ip.csr 1913 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L13_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L13_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L13_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L13_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L13_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L13_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L13_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L13_SET ns_noc_io_spio_soc_ip.csr 1924 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L14_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L14_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L14_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L14_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L14_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L14_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L14_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L14_SET ns_noc_io_spio_soc_ip.csr 1935 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L15_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L15_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L15_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L15_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L15_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L15_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L15_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_L15_SET ns_noc_io_spio_soc_ip.csr 1946 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_UNSD_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_UNSD_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_UNSD_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_UNSD_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_UNSD_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_UNSD_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BTPERRM_UNSD_SET ns_noc_io_spio_soc_ip.csr 1957 UNSD 31 16 0x0000 R register spio_noc.bridge_rbm_m_17_1_rxe bridge_rbm_m_17_1_rxe SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 2066 rbm_m register rxe 0x3120 R/W 0x00000000 Spio_noc_bridge_rbm_m_17_1_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_A_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_A_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_A_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_A_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_A_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_A_GET SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_A_SET ns_noc_io_spio_soc_ip.csr 1986 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_B_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_B_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_B_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_B_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_B_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_B_GET SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_B_SET ns_noc_io_spio_soc_ip.csr 1997 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_C_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_C_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_C_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_C_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_C_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_C_GET SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_C_SET ns_noc_io_spio_soc_ip.csr 2008 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_D_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_D_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_D_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_D_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_D_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_D_GET SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_CRC_OFLW_D_SET ns_noc_io_spio_soc_ip.csr 2019 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_EVC_OFLW_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_EVC_OFLW_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_EVC_OFLW_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_EVC_OFLW_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_EVC_OFLW_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_EVC_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_EVC_OFLW_GET SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_EVC_OFLW_SET ns_noc_io_spio_soc_ip.csr 2031 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 2042 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_EVC1_OFLW_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_EVC1_OFLW_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_EVC1_OFLW_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_EVC1_OFLW_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_EVC1_OFLW_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_EVC1_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_EVC1_OFLW_GET SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_EVC1_OFLW_SET ns_noc_io_spio_soc_ip.csr 2054 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_UNSD_31_7_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_UNSD_31_7_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_UNSD_31_7_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_UNSD_31_7_GET SPIO_NOC_BRIDGE_RBM_M_17_1_RXE_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 2065 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_rbm_m_17_1_rxem bridge_rbm_m_17_1_rxem SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 2138 rbm_m register rxem 0x3128 R/W 0x00000050 Spio_noc_bridge_rbm_m_17_1_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_UNSD_3_0_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_UNSD_3_0_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_UNSD_3_0_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_UNSD_3_0_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_UNSD_3_0_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_UNSD_3_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_UNSD_3_0_GET SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_UNSD_3_0_SET ns_noc_io_spio_soc_ip.csr 2087 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_EVC_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_EVC_OFLW_MASK_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_EVC_OFLW_MASK_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_EVC_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_EVC_OFLW_MASK_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_EVC_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_EVC_OFLW_MASK_GET SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_EVC_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 2101 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 2112 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_EVC1_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_EVC1_OFLW_MASK_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_EVC1_OFLW_MASK_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_EVC1_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_EVC1_OFLW_MASK_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_EVC1_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_EVC1_OFLW_MASK_GET SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 2126 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_UNSD_31_7_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_UNSD_31_7_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_UNSD_31_7_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_UNSD_31_7_GET SPIO_NOC_BRIDGE_RBM_M_17_1_RXEM_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 2137 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_rbm_m_17_1_brs_0 bridge_rbm_m_17_1_brs_0 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 2412 rbm_m register brs_0 0x3130 R 0x00000000 Spio_noc_bridge_rbm_m_17_1_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_0_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_0_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_0_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_0_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_0_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_0_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 2162 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_0_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_0_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_0_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_0_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_0_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_0_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_0_SET ns_noc_io_spio_soc_ip.csr 2173 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_0_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_0_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_0_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_0_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_0_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_0_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_0_SET ns_noc_io_spio_soc_ip.csr 2184 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_0_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_0_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_0_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_0_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_0_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_0_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_0_SET ns_noc_io_spio_soc_ip.csr 2195 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_0_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_0_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_0_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_0_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_0_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_0_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_0_SET ns_noc_io_spio_soc_ip.csr 2206 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_7_6_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_7_6_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_7_6_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_7_6_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 2216 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_1_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_1_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_1_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_1_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_1_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_1_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 2227 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_1_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_1_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_1_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_1_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_1_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_1_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_1_SET ns_noc_io_spio_soc_ip.csr 2238 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_1_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_1_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_1_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_1_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_1_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_1_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_1_SET ns_noc_io_spio_soc_ip.csr 2249 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_1_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_1_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_1_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_1_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_1_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_1_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_1_SET ns_noc_io_spio_soc_ip.csr 2260 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_1_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_1_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_1_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_1_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_1_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_1_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_1_SET ns_noc_io_spio_soc_ip.csr 2271 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_15_14_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_15_14_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_15_14_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_15_14_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 2281 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_2_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_2_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_2_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_2_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_2_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_2_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 2292 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_2_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_2_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_2_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_2_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_2_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_2_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_2_SET ns_noc_io_spio_soc_ip.csr 2303 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_2_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_2_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_2_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_2_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_2_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_2_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_2_SET ns_noc_io_spio_soc_ip.csr 2314 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_2_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_2_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_2_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_2_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_2_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_2_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_2_SET ns_noc_io_spio_soc_ip.csr 2325 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_2_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_2_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_2_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_2_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_2_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_2_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_2_SET ns_noc_io_spio_soc_ip.csr 2336 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_23_22_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_23_22_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_23_22_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_23_22_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 2346 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_3_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_3_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_3_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_3_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_3_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_3_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 2357 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_3_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_3_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_3_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_3_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_3_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_3_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_V_3_SET ns_noc_io_spio_soc_ip.csr 2368 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_3_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_3_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_3_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_3_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_3_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_3_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_S_3_SET ns_noc_io_spio_soc_ip.csr 2379 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_3_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_3_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_3_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_3_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_3_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_3_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_B_3_SET ns_noc_io_spio_soc_ip.csr 2390 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_3_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_3_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_3_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_3_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_3_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_3_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_F_3_SET ns_noc_io_spio_soc_ip.csr 2401 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_31_30_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_31_30_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_31_30_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_31_30_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_0_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 2411 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_rbm_m_17_1_brs_1 bridge_rbm_m_17_1_brs_1 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 2686 rbm_m register brs_1 0x3138 R 0x00000000 Spio_noc_bridge_rbm_m_17_1_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_0_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_0_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_0_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_0_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_0_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_0_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 2436 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_0_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_0_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_0_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_0_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_0_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_0_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_0_SET ns_noc_io_spio_soc_ip.csr 2447 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_0_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_0_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_0_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_0_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_0_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_0_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_0_SET ns_noc_io_spio_soc_ip.csr 2458 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_0_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_0_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_0_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_0_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_0_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_0_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_0_SET ns_noc_io_spio_soc_ip.csr 2469 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_0_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_0_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_0_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_0_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_0_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_0_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_0_SET ns_noc_io_spio_soc_ip.csr 2480 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_7_6_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_7_6_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_7_6_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_7_6_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 2490 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_1_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_1_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_1_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_1_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_1_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_1_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 2501 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_1_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_1_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_1_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_1_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_1_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_1_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_1_SET ns_noc_io_spio_soc_ip.csr 2512 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_1_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_1_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_1_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_1_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_1_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_1_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_1_SET ns_noc_io_spio_soc_ip.csr 2523 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_1_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_1_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_1_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_1_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_1_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_1_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_1_SET ns_noc_io_spio_soc_ip.csr 2534 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_1_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_1_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_1_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_1_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_1_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_1_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_1_SET ns_noc_io_spio_soc_ip.csr 2545 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_15_14_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_15_14_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_15_14_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_15_14_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 2555 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_2_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_2_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_2_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_2_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_2_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_2_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 2566 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_2_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_2_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_2_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_2_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_2_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_2_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_2_SET ns_noc_io_spio_soc_ip.csr 2577 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_2_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_2_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_2_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_2_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_2_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_2_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_2_SET ns_noc_io_spio_soc_ip.csr 2588 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_2_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_2_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_2_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_2_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_2_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_2_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_2_SET ns_noc_io_spio_soc_ip.csr 2599 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_2_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_2_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_2_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_2_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_2_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_2_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_2_SET ns_noc_io_spio_soc_ip.csr 2610 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_23_22_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_23_22_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_23_22_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_23_22_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 2620 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_3_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_3_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_3_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_3_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_3_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_3_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 2631 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_3_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_3_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_3_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_3_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_3_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_3_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_V_3_SET ns_noc_io_spio_soc_ip.csr 2642 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_3_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_3_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_3_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_3_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_3_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_3_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_S_3_SET ns_noc_io_spio_soc_ip.csr 2653 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_3_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_3_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_3_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_3_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_3_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_3_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_B_3_SET ns_noc_io_spio_soc_ip.csr 2664 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_3_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_3_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_3_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_3_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_3_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_3_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_F_3_SET ns_noc_io_spio_soc_ip.csr 2675 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_31_30_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_31_30_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_31_30_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_31_30_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRS_1_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 2685 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_rbm_m_17_1_brus bridge_rbm_m_17_1_brus SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 2755 rbm_m register brus 0x31B0 R 0x00000000 Spio_noc_bridge_rbm_m_17_1_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_A_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_A_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_A_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_A_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_A_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_A_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_A_SET ns_noc_io_spio_soc_ip.csr 2711 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_B_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_B_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_B_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_B_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_B_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_B_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_B_SET ns_noc_io_spio_soc_ip.csr 2722 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_C_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_C_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_C_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_C_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_C_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_C_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_C_SET ns_noc_io_spio_soc_ip.csr 2733 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_D_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_D_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_D_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_D_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_D_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_D_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_V_D_SET ns_noc_io_spio_soc_ip.csr 2744 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_UNSD_31_4_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_UNSD_31_4_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_UNSD_31_4_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_UNSD_31_4_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_UNSD_31_4_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_UNSD_31_4_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_UNSD_31_4_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRUS_UNSD_31_4_SET ns_noc_io_spio_soc_ip.csr 2754 UNSD_31_4 31 4 0x0000000 R register spio_noc.bridge_rbm_m_17_1_brperr0 bridge_rbm_m_17_1_brperr0 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 2983 rbm_m register brperr0 0x31D0 R/W 0x0000000000000000 Spio_noc_bridge_rbm_m_17_1_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_D0_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_D0_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_D0_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_D0_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_D0_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_D0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_D0_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_D0_SET ns_noc_io_spio_soc_ip.csr 2793 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_DC0_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_DC0_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_DC0_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_DC0_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_DC0_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_DC0_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_DC0_SET ns_noc_io_spio_soc_ip.csr 2804 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SB0_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SB0_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SB0_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SB0_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SB0_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SB0_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SB0_SET ns_noc_io_spio_soc_ip.csr 2815 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SBC0_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SBC0_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SBC0_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SBC0_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SBC0_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SBC0_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SBC0_SET ns_noc_io_spio_soc_ip.csr 2827 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_PK0_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_PK0_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_PK0_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_PK0_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_PK0_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_PK0_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_PK0_SET ns_noc_io_spio_soc_ip.csr 2838 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_7_5_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 2849 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_D1_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_D1_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_D1_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_D1_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_D1_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_D1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_D1_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_D1_SET ns_noc_io_spio_soc_ip.csr 2860 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_DC1_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_DC1_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_DC1_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_DC1_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_DC1_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_DC1_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_DC1_SET ns_noc_io_spio_soc_ip.csr 2871 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SB1_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SB1_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SB1_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SB1_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SB1_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SB1_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SB1_SET ns_noc_io_spio_soc_ip.csr 2882 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SBC1_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SBC1_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SBC1_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SBC1_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SBC1_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SBC1_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_SBC1_SET ns_noc_io_spio_soc_ip.csr 2894 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_PK1_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_PK1_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_PK1_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_PK1_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_PK1_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_PK1_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_PK1_SET ns_noc_io_spio_soc_ip.csr 2905 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_15_13_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 2916 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_23_16_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 2927 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_31_24_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 2938 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_39_32_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 2949 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_47_40_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 2960 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_55_48_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 2971 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_63_56_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 2982 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_rbm_m_17_1_brperr1 bridge_rbm_m_17_1_brperr1 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 3099 rbm_m register brperr1 0x31D8 R 0x0000000000000000 Spio_noc_bridge_rbm_m_17_1_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_7_0_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 3021 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_15_8_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 3032 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_23_16_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 3043 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_31_24_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 3054 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_39_32_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 3065 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_47_40_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 3076 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_55_48_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 3087 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_63_56_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERR1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 3098 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_rbm_m_17_1_brperrm0 bridge_rbm_m_17_1_brperrm0 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 3320 rbm_m register brperrm0 0x31E0 R/W 0x0000000000000000 Spio_noc_bridge_rbm_m_17_1_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_D0_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_D0_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_D0_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_D0_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_D0_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_D0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_D0_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_D0_SET ns_noc_io_spio_soc_ip.csr 3126 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_DC0_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_DC0_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_DC0_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_DC0_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_DC0_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_DC0_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_DC0_SET ns_noc_io_spio_soc_ip.csr 3138 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SB0_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SB0_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SB0_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SB0_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SB0_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SB0_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SB0_SET ns_noc_io_spio_soc_ip.csr 3149 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SBC0_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SBC0_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SBC0_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SBC0_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SBC0_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SBC0_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SBC0_SET ns_noc_io_spio_soc_ip.csr 3161 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_PK0_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_PK0_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_PK0_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_PK0_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_PK0_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_PK0_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_PK0_SET ns_noc_io_spio_soc_ip.csr 3173 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_7_5_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 3184 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_D1_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_D1_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_D1_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_D1_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_D1_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_D1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_D1_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_D1_SET ns_noc_io_spio_soc_ip.csr 3195 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_DC1_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_DC1_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_DC1_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_DC1_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_DC1_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_DC1_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_DC1_SET ns_noc_io_spio_soc_ip.csr 3207 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SB1_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SB1_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SB1_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SB1_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SB1_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SB1_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SB1_SET ns_noc_io_spio_soc_ip.csr 3218 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SBC1_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SBC1_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SBC1_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SBC1_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SBC1_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SBC1_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_SBC1_SET ns_noc_io_spio_soc_ip.csr 3230 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_PK1_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_PK1_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_PK1_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_PK1_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_PK1_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_PK1_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_PK1_SET ns_noc_io_spio_soc_ip.csr 3242 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_15_13_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 3253 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_23_16_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 3264 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_31_24_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 3275 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_39_32_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 3286 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_47_40_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 3297 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_55_48_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 3308 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_63_56_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 3319 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_rbm_m_17_1_brperrm1 bridge_rbm_m_17_1_brperrm1 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 3425 rbm_m register brperrm1 0x31E8 R 0x0000000000000000 Spio_noc_bridge_rbm_m_17_1_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_7_0_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 3347 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_15_8_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 3358 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_23_16_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 3369 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_31_24_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 3380 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_39_32_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 3391 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_47_40_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 3402 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_55_48_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 3413 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_63_56_GET SPIO_NOC_BRIDGE_RBM_M_17_1_BRPERRM1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 3424 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_rbm_m_17_1_am_tocfg bridge_rbm_m_17_1_am_tocfg SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 3499 rbm_m register am_tocfg 0x3C00 R/W 0x000000000000001f Spio_noc_bridge_rbm_m_17_1_am_tocfg This register is used to configure response timeouts. AM_TOCFG[8] (En) needs to be set for timeout tracking to be enabled. When this bit is 1'b0, no timestamps are recorded to generate timeout interrupts. A 64-bit free running counter is used to time the response interval. AM_TOCFG[5:0] (TI) specifies the lower bit index into this counter, from where 2-bits are picked up and recorded as the arrival time stamp of every incoming AR and AW command. If response for a command does not return before the current time stamp rolls to arrival time stamp minus 1, the response is assumed to have timedout and an interrupt is raised along with the slave ID to which the timed out request was sent. When changing the TI field, first write to the register with the En field cleared, then write a second time with the TI field to its new value, then a 3rd write to restore the En field to Enabled. During this update while the En field is cleared, existing timers will cancelled, and new timer starts will be inhibited. false false false false TI SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_TI_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_TI_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_TI_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_TI_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_TI_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_TI_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_TI_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_TI_SET ns_noc_io_spio_soc_ip.csr 3462 TI Timer index, index of a 64-bit counter from where timestamp is picked. The register value has to be 'd62 or smaller. 5 0 0x1f R/W UNSD_7_6 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_UNSD_7_6_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_UNSD_7_6_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_UNSD_7_6_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_UNSD_7_6_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 3473 UNSD_7_6 7 6 0x0 R EN SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_EN_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_EN_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_EN_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_EN_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_EN_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_EN_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_EN_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_EN_SET ns_noc_io_spio_soc_ip.csr 3487 EN 1'b1: Enabled timeout tracking, a 64-bit free running counter is used to time the response interval. 1'b0: No timestamps are recorded to generate timeout interrupts 8 8 0x0 R/W UNSD_63_9 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_UNSD_63_9_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_UNSD_63_9_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_UNSD_63_9_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_UNSD_63_9_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_UNSD_63_9_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_UNSD_63_9_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_UNSD_63_9_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOCFG_UNSD_63_9_SET ns_noc_io_spio_soc_ip.csr 3498 UNSD_63_9 63 9 0x00000000000000 R register spio_noc.bridge_rbm_m_17_1_am_osslv bridge_rbm_m_17_1_am_osslv SPIO_NOC_BRIDGE_RBM_M_17_1_AM_OSSLV_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_OSSLV_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_OSSLV_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_OSSLV_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 3534 rbm_m register am_osslv 0x3C08 R/W 0x0000000000000000 Spio_noc_bridge_rbm_m_17_1_am_osslv This register is used to check if there are any outstanding read/write commands to a slave specified by field slvid. NocStudio provides a table of slvids corresponding to the slave ports accessible from a master bridge. Outstanding status is reflected in AM_STS. false false false false SLVID SPIO_NOC_BRIDGE_RBM_M_17_1_AM_OSSLV_SLVID_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_OSSLV_SLVID_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_OSSLV_SLVID_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_OSSLV_SLVID_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_OSSLV_SLVID_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_OSSLV_SLVID_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_OSSLV_SLVID_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_OSSLV_SLVID_SET ns_noc_io_spio_soc_ip.csr 3522 SLVID A slave ID associated with the current master for command outstanding status 15 0 0x0000 R/W UNSD_63_16 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_OSSLV_UNSD_63_16_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_OSSLV_UNSD_63_16_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_OSSLV_UNSD_63_16_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_OSSLV_UNSD_63_16_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_OSSLV_UNSD_63_16_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_OSSLV_UNSD_63_16_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_OSSLV_UNSD_63_16_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_OSSLV_UNSD_63_16_SET ns_noc_io_spio_soc_ip.csr 3533 UNSD_63_16 63 16 0x000000000000 R register spio_noc.bridge_rbm_m_17_1_am_cgc bridge_rbm_m_17_1_am_cgc SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGC_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGC_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGC_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 3571 rbm_m register am_cgc 0x3C10 R/W 0x0000000000000064 Spio_noc_bridge_rbm_m_17_1_am_cgc Programmable interval used by coarse clock gating logic in master bridge.This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGC_HYSTERESIS_COUNTER_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGC_HYSTERESIS_COUNTER_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGC_HYSTERESIS_COUNTER_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGC_HYSTERESIS_COUNTER_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGC_HYSTERESIS_COUNTER_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGC_HYSTERESIS_COUNTER_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGC_HYSTERESIS_COUNTER_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_spio_soc_ip.csr 3559 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGC_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGC_UNSD_63_32_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGC_UNSD_63_32_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGC_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGC_UNSD_63_32_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGC_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGC_UNSD_63_32_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGC_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 3570 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_rbm_m_17_1_am_cgo bridge_rbm_m_17_1_am_cgo SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGO_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGO_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGO_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGO_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 3606 rbm_m register am_cgo 0x3C18 R/W 0x0000000000000000 Spio_noc_bridge_rbm_m_17_1_am_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the master bridge. false false false false FPO SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGO_FPO_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGO_FPO_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGO_FPO_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGO_FPO_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGO_FPO_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGO_FPO_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGO_FPO_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGO_FPO_SET ns_noc_io_spio_soc_ip.csr 3594 FPO 1'b1: Clock gating override is enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGO_UNSD_63_1_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGO_UNSD_63_1_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGO_UNSD_63_1_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGO_UNSD_63_1_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGO_UNSD_63_1_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGO_UNSD_63_1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGO_UNSD_63_1_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CGO_UNSD_63_1_SET ns_noc_io_spio_soc_ip.csr 3605 UNSD_63_1 63 1 0x0000000000000000 R register spio_noc.bridge_rbm_m_17_1_am_cfg bridge_rbm_m_17_1_am_cfg SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CFG_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CFG_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CFG_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CFG_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 3643 rbm_m register am_cfg 0x3C20 R/W 0x0000000000000001 Spio_noc_bridge_rbm_m_17_1_am_cfg Configures the master bridge's support for autowake of power domains. When set, master bridge halts a request and issues wakeup requests for power domains that need to powered up to complete the transaction. The power domains should support auto wake. When reset, master bridge issues DECERR for any transaction which has dependent power domains in sleep state. false false false false AW SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CFG_AW_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CFG_AW_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CFG_AW_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CFG_AW_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CFG_AW_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CFG_AW_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CFG_AW_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CFG_AW_SET ns_noc_io_spio_soc_ip.csr 3631 AW 1'b1: Autowake enabled 1'b0: Autowake disabled 0 0 0x1 R/W UNSD_63_1 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CFG_UNSD_63_1_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CFG_UNSD_63_1_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CFG_UNSD_63_1_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CFG_UNSD_63_1_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CFG_UNSD_63_1_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CFG_UNSD_63_1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CFG_UNSD_63_1_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CFG_UNSD_63_1_SET ns_noc_io_spio_soc_ip.csr 3642 UNSD_63_1 63 1 0x0000000000000000 R register spio_noc.bridge_rbm_m_17_1_am_sts bridge_rbm_m_17_1_am_sts SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 3771 rbm_m register am_sts 0x3D00 R 0x000000000000000c Spio_noc_bridge_rbm_m_17_1_am_sts When reordering is disabled on the master bridge, hazard stall occurs if the master tries to access a new slave device while response from a different slave is outstanding on the same AID. This is because the responses can arrive out of order and the bridge is not equipped to correct the order. Without re-order buffers, hazard stalls also occur if a new large command needs to be split while there are older commands outstanding, or a large command just finished sending all its split segments but all responses have not returned yet. When reordering is enabled, stall due to hazard occurs if a new command arrives, whose NoC QoS is different from the NoC QoS of commands outstanding on that AID. false false false false ROF SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ROF_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ROF_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ROF_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ROF_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ROF_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ROF_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ROF_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ROF_SET ns_noc_io_spio_soc_ip.csr 3676 ROF 1'b1: Maximum supported number of read commands are outstanding waiting for response and no more requests can be accepted 1'b0: Master bridge can accept more read requests 0 0 0x0 R WOF SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_WOF_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_WOF_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_WOF_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_WOF_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_WOF_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_WOF_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_WOF_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_WOF_SET ns_noc_io_spio_soc_ip.csr 3690 WOF 1'b1: Maximum supported number of write commands are outstanding waiting for response and no more requests can be accepted 1'b0: Master bridge can accept more write requests 1 1 0x0 R ROE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ROE_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ROE_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ROE_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ROE_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ROE_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ROE_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ROE_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ROE_SET ns_noc_io_spio_soc_ip.csr 3702 ROE 1'b1: There are no read commands outstanding from the attached master device 2 2 0x1 R WOE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_WOE_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_WOE_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_WOE_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_WOE_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_WOE_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_WOE_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_WOE_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_WOE_SET ns_noc_io_spio_soc_ip.csr 3714 WOE 1'b1: There are no write commands outstanding from the attached master device 3 3 0x1 R ARS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ARS_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ARS_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ARS_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ARS_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ARS_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ARS_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ARS_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ARS_SET ns_noc_io_spio_soc_ip.csr 3725 ARS 1'b1: AR channel is stalled on hazard 4 4 0x0 R AWS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_AWS_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_AWS_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_AWS_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_AWS_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_AWS_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_AWS_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_AWS_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_AWS_SET ns_noc_io_spio_soc_ip.csr 3736 AWS 1'b1: AW channel is stalled on hazard 5 5 0x0 R ARO SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ARO_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ARO_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ARO_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ARO_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ARO_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ARO_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ARO_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_ARO_SET ns_noc_io_spio_soc_ip.csr 3748 ARO 1'b1: Read commands are outstanding to the slave specified in OSSLV register 6 6 0x0 R AWO SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_AWO_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_AWO_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_AWO_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_AWO_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_AWO_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_AWO_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_AWO_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_AWO_SET ns_noc_io_spio_soc_ip.csr 3760 AWO 1'b1: Write commands are outstanding to the slave specified in OSSLV register 7 7 0x0 R UNSD_63_8 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_UNSD_63_8_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_UNSD_63_8_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_UNSD_63_8_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_UNSD_63_8_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_UNSD_63_8_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_UNSD_63_8_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_UNSD_63_8_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_STS_UNSD_63_8_SET ns_noc_io_spio_soc_ip.csr 3770 UNSD_63_8 63 8 0x00000000000000 R register spio_noc.bridge_rbm_m_17_1_am_bridge_id bridge_rbm_m_17_1_am_bridge_id SPIO_NOC_BRIDGE_RBM_M_17_1_AM_BRIDGE_ID_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_BRIDGE_ID_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_BRIDGE_ID_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_BRIDGE_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 3801 rbm_m register am_bridge_id 0x3D08 R 0x0000000000000011 Spio_noc_bridge_rbm_m_17_1_am_bridge_id Unique identifier assigned to the master bridge. false false false false ID SPIO_NOC_BRIDGE_RBM_M_17_1_AM_BRIDGE_ID_ID_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_BRIDGE_ID_ID_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_BRIDGE_ID_ID_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_BRIDGE_ID_ID_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_BRIDGE_ID_ID_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_BRIDGE_ID_ID_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_BRIDGE_ID_ID_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_BRIDGE_ID_ID_SET ns_noc_io_spio_soc_ip.csr 3790 ID Unique bridge ID 15 0 0x0011 R UNSD_63_16 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_BRIDGE_ID_UNSD_63_16_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_BRIDGE_ID_UNSD_63_16_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_BRIDGE_ID_UNSD_63_16_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_BRIDGE_ID_UNSD_63_16_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_BRIDGE_ID_UNSD_63_16_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_BRIDGE_ID_UNSD_63_16_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_BRIDGE_ID_UNSD_63_16_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_spio_soc_ip.csr 3800 UNSD_63_16 63 16 0x000000000000 R register spio_noc.bridge_rbm_m_17_1_am_nocver_id bridge_rbm_m_17_1_am_nocver_id SPIO_NOC_BRIDGE_RBM_M_17_1_AM_NOCVER_ID_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_NOCVER_ID_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_NOCVER_ID_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_NOCVER_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 3834 rbm_m register am_nocver_id 0x3D10 R 0x0000000000000000 Spio_noc_bridge_rbm_m_17_1_am_nocver_id Version identifier for the NoC. This read-only register is available only on the regbus master. This register is not available on pother master bridges and access will result in decode error response. false false false false NOC_VERSION_ID SPIO_NOC_BRIDGE_RBM_M_17_1_AM_NOCVER_ID_NOC_VERSION_ID_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_NOCVER_ID_NOC_VERSION_ID_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_NOCVER_ID_NOC_VERSION_ID_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_NOCVER_ID_NOC_VERSION_ID_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_NOCVER_ID_NOC_VERSION_ID_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_NOCVER_ID_NOC_VERSION_ID_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_NOCVER_ID_NOC_VERSION_ID_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_NOCVER_ID_NOC_VERSION_ID_SET ns_noc_io_spio_soc_ip.csr 3823 NOC_VERSION_ID NoC version ID 31 0 0x00000000 R UNSD_63_32 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_NOCVER_ID_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_NOCVER_ID_UNSD_63_32_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_NOCVER_ID_UNSD_63_32_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_NOCVER_ID_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_NOCVER_ID_UNSD_63_32_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_NOCVER_ID_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_NOCVER_ID_UNSD_63_32_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_NOCVER_ID_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 3833 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_rbm_m_17_1_am_err bridge_rbm_m_17_1_am_err SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 4330 rbm_m register am_err 0x3E00 R/W 0x0000000000000000 Spio_noc_bridge_rbm_m_17_1_am_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E0_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E0_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E0_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E0_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E0_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E0_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E0_SET ns_noc_io_spio_soc_ip.csr 3856 E0 1'b1: Local read address decode error: ARADDR did not find a match in the master bridges address table and a decode error was issued 0 0 0x0 R/W E1 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E1_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E1_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E1_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E1_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E1_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E1_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E1_SET ns_noc_io_spio_soc_ip.csr 3868 E1 1'b1: Read address decode error from slave: A decode error response was received from a slave device 1 1 0x0 R/W E2 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E2_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E2_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E2_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E2_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E2_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E2_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E2_SET ns_noc_io_spio_soc_ip.csr 3880 E2 1'b1: Read slave error: A slave error response was received from a slave device 2 2 0x0 R/W E3 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E3_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E3_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E3_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E3_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E3_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E3_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E3_SET ns_noc_io_spio_soc_ip.csr 3892 E3 1'b1: Non modifiable WRAP: A WRAP command marked as non-modifiable (ARCACHE[0]=0) was detected 3 3 0x0 R/W E4 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E4_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E4_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E4_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E4_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E4_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E4_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E4_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E4_SET ns_noc_io_spio_soc_ip.csr 3904 E4 1'b1: [FATAL] Read exclusive split: An AR command of FIXED burst type was detected 4 4 0x0 R/W E5 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E5_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E5_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E5_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E5_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E5_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E5_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E5_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E5_SET ns_noc_io_spio_soc_ip.csr 3916 E5 1'b1: [FATAL] Read address multi-hit: An AR command matched against multiple entries in the address table 5 5 0x0 R/W E6 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E6_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E6_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E6_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E6_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E6_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E6_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E6_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E6_SET ns_noc_io_spio_soc_ip.csr 3929 E6 1'b1: Read response timeout: Read response timeout occurred. With timeout enabled, a response wasn't received within the expected interval 6 6 0x0 R/W E7 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E7_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E7_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E7_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E7_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E7_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E7_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E7_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E7_SET ns_noc_io_spio_soc_ip.csr 3942 E7 1'b1: [FATAL] Read WRAP not equal to supported cacheline size: A WRAP command of unupported cache line size was detected 7 7 0x0 R/W E8 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E8_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E8_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E8_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E8_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E8_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E8_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E8_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E8_SET ns_noc_io_spio_soc_ip.csr 3953 E8 1'b1: [FATAL] Unexpected narrow read detected 8 8 0x0 R/W UNSD_15_9 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_15_9_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_15_9_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_15_9_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_15_9_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_15_9_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_15_9_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_15_9_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_15_9_SET ns_noc_io_spio_soc_ip.csr 3964 UNSD_15_9 15 9 0x00 R E16 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E16_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E16_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E16_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E16_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E16_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E16_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E16_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E16_SET ns_noc_io_spio_soc_ip.csr 3975 E16 1'b1: Local write address decode error 16 16 0x0 R/W E17 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E17_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E17_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E17_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E17_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E17_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E17_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E17_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E17_SET ns_noc_io_spio_soc_ip.csr 3986 E17 1'b1: Write address decode error from slave 17 17 0x0 R/W E18 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E18_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E18_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E18_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E18_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E18_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E18_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E18_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E18_SET ns_noc_io_spio_soc_ip.csr 3997 E18 1'b1: Write slave error 18 18 0x0 R/W E19 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E19_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E19_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E19_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E19_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E19_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E19_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E19_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E19_SET ns_noc_io_spio_soc_ip.csr 4008 E19 1'b1: Non modifiable WRAP 19 19 0x0 R/W E20 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E20_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E20_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E20_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E20_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E20_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E20_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E20_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E20_SET ns_noc_io_spio_soc_ip.csr 4019 E20 1'b1: [FATAL] Write exclusive split 20 20 0x0 R/W E21 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E21_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E21_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E21_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E21_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E21_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E21_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E21_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E21_SET ns_noc_io_spio_soc_ip.csr 4030 E21 1'b1: [FATAL] Write address multi-hit 21 21 0x0 R/W E22 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E22_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E22_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E22_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E22_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E22_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E22_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E22_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E22_SET ns_noc_io_spio_soc_ip.csr 4041 E22 1'b1: Write respone timeout 22 22 0x0 R/W E23 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E23_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E23_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E23_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E23_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E23_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E23_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E23_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E23_SET ns_noc_io_spio_soc_ip.csr 4053 E23 1'b1: [FATAL] Write WRAP not equal to supported cacheline size 23 23 0x0 R/W E24 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E24_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E24_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E24_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E24_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E24_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E24_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E24_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E24_SET ns_noc_io_spio_soc_ip.csr 4064 E24 1'b1: [FATAL] Unexpected narrow write detected 24 24 0x0 R/W UNSD_31_25 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_31_25_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_31_25_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_31_25_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_31_25_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_31_25_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_31_25_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_31_25_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_31_25_SET ns_noc_io_spio_soc_ip.csr 4075 UNSD_31_25 31 25 0x00 R E32 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E32_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E32_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E32_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E32_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E32_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E32_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E32_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E32_SET ns_noc_io_spio_soc_ip.csr 4086 E32 1'b1: Capture counter0 overflow 32 32 0x0 R/W E33 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E33_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E33_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E33_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E33_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E33_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E33_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E33_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E33_SET ns_noc_io_spio_soc_ip.csr 4097 E33 1'b1: Capture counter1 overflow 33 33 0x0 R/W E34 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E34_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E34_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E34_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E34_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E34_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E34_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E34_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E34_SET ns_noc_io_spio_soc_ip.csr 4109 E34 1'b1: [FATAL] Traffic sent to a noc layer which is power gate 34 34 0x0 R/W E35 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E35_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E35_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E35_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E35_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E35_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E35_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E35_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E35_SET ns_noc_io_spio_soc_ip.csr 4121 E35 1'b1: [FATAL] Parity error in configuration/status registers 35 35 0x0 R/W UNSD_39_36 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_39_36_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_39_36_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_39_36_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_39_36_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_39_36_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_39_36_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_39_36_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_39_36_SET ns_noc_io_spio_soc_ip.csr 4132 UNSD_39_36 39 36 0x0 R E40 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E40_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E40_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E40_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E40_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E40_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E40_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E40_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E40_SET ns_noc_io_spio_soc_ip.csr 4144 E40 1'b1: [FATAL] Indicates that portcheck detected error (SIB mode only) 40 40 0x0 R/W E41 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E41_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E41_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E41_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E41_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E41_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E41_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E41_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E41_SET ns_noc_io_spio_soc_ip.csr 4155 E41 1'b1: [FATAL] AR Parity Err 41 41 0x0 R/W E42 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E42_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E42_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E42_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E42_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E42_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E42_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E42_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E42_SET ns_noc_io_spio_soc_ip.csr 4166 E42 1'b1: [FATAL] ARADDR Parity Err 42 42 0x0 R/W E43 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E43_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E43_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E43_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E43_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E43_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E43_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E43_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E43_SET ns_noc_io_spio_soc_ip.csr 4177 E43 1'b1: [FATAL] AW Parity Err 43 43 0x0 R/W E44 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E44_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E44_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E44_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E44_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E44_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E44_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E44_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E44_SET ns_noc_io_spio_soc_ip.csr 4188 E44 1'b1: [FATAL] AWADDR Parity Err 44 44 0x0 R/W E45 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E45_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E45_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E45_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E45_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E45_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E45_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E45_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E45_SET ns_noc_io_spio_soc_ip.csr 4199 E45 1'b1: [FATAL] WDATA Parity Err 45 45 0x0 R/W E46 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E46_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E46_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E46_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E46_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E46_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E46_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E46_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E46_SET ns_noc_io_spio_soc_ip.csr 4210 E46 1'b1: [FATAL] CDDATA Parity Err 46 46 0x0 R/W E47 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E47_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E47_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E47_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E47_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E47_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E47_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E47_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E47_SET ns_noc_io_spio_soc_ip.csr 4222 E47 1'b1: [FATAL] Ridtbl Entry Parity Err 47 47 0x0 R E48 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E48_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E48_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E48_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E48_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E48_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E48_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E48_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E48_SET ns_noc_io_spio_soc_ip.csr 4234 E48 1'b1: [FATAL] Widtbl Entry Parity Err 48 48 0x0 R E49 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E49_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E49_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E49_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E49_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E49_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E49_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E49_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E49_SET ns_noc_io_spio_soc_ip.csr 4246 E49 1'b1: [FATAL] Read Reorder Buffer Parity Err 49 49 0x0 R E50 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E50_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E50_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E50_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E50_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E50_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E50_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E50_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E50_SET ns_noc_io_spio_soc_ip.csr 4258 E50 1'b1: [FATAL] Write Reorder Buffer Parity Err 50 50 0x0 R E51 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E51_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E51_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E51_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E51_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E51_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E51_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E51_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E51_SET ns_noc_io_spio_soc_ip.csr 4270 E51 1'b1: [FATAL] Rx Fifo Parity Err 51 51 0x0 R E52 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E52_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E52_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E52_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E52_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E52_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E52_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E52_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E52_SET ns_noc_io_spio_soc_ip.csr 4282 E52 1'b1: [FATAL] Ack Channel Wack Fifo Parity Error 52 52 0x0 R E53 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E53_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E53_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E53_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E53_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E53_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E53_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E53_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E53_SET ns_noc_io_spio_soc_ip.csr 4294 E53 1'b1: [FATAL] Ack Channel Rack Fifo Parity Error 53 53 0x0 R E54 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E54_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E54_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E54_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E54_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E54_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E54_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E54_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E54_SET ns_noc_io_spio_soc_ip.csr 4306 E54 1'b1: [FATAL] CRCD Channel Crid Fifo Parity Error 54 54 0x0 R E55 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E55_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E55_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E55_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E55_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E55_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E55_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E55_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_E55_SET ns_noc_io_spio_soc_ip.csr 4318 E55 1'b1: [FATAL] R Channel Cpkt Fifo Parity Error 55 55 0x0 R UNSD_63_56 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_63_56_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_63_56_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_63_56_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_63_56_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERR_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 4329 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_rbm_m_17_1_am_toslvid bridge_rbm_m_17_1_am_toslvid SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOSLVID_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOSLVID_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOSLVID_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOSLVID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 4375 rbm_m register am_toslvid 0x3E08 R 0x0000000000000000 Spio_noc_bridge_rbm_m_17_1_am_toslvid AR slvid and AW slvid fields indicate slave IDs to which a read, write response timeout was detected. Note that slvid encoding is not same as the bridge ID of the slave. NocStudio provides a table mapping the slvids to the actual slave ports accessible from the master bridge. false false false false AR_SLVID SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOSLVID_AR_SLVID_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOSLVID_AR_SLVID_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOSLVID_AR_SLVID_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOSLVID_AR_SLVID_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOSLVID_AR_SLVID_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOSLVID_AR_SLVID_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOSLVID_AR_SLVID_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOSLVID_AR_SLVID_SET ns_noc_io_spio_soc_ip.csr 4353 AR_SLVID Slave ID of timed out AR request 15 0 0x0000 R AW_SLVID SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOSLVID_AW_SLVID_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOSLVID_AW_SLVID_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOSLVID_AW_SLVID_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOSLVID_AW_SLVID_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOSLVID_AW_SLVID_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOSLVID_AW_SLVID_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOSLVID_AW_SLVID_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOSLVID_AW_SLVID_SET ns_noc_io_spio_soc_ip.csr 4364 AW_SLVID Slave ID of timed out AW request 31 16 0x0000 R UNSD_63_32 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOSLVID_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOSLVID_UNSD_63_32_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOSLVID_UNSD_63_32_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOSLVID_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOSLVID_UNSD_63_32_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOSLVID_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOSLVID_UNSD_63_32_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_TOSLVID_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 4374 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_rbm_m_17_1_am_era bridge_rbm_m_17_1_am_era SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERA_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERA_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERA_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERA_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 4397 rbm_m register am_era 0x3E10 R 0x0000000000000000 Spio_noc_bridge_rbm_m_17_1_am_era This is the address on AR channel for which a decode error was detected. This corresponds to the status register bit e0 in AM_ERR. false false false false READ_DECERR_ADDRS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERA_READ_DECERR_ADDRS_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERA_READ_DECERR_ADDRS_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERA_READ_DECERR_ADDRS_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERA_READ_DECERR_ADDRS_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERA_READ_DECERR_ADDRS_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERA_READ_DECERR_ADDRS_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERA_READ_DECERR_ADDRS_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_ERA_READ_DECERR_ADDRS_SET ns_noc_io_spio_soc_ip.csr 4396 READ_DECERR_ADDRS Read decerr address 63 0 0x0000000000000000 R register spio_noc.bridge_rbm_m_17_1_am_ewa bridge_rbm_m_17_1_am_ewa SPIO_NOC_BRIDGE_RBM_M_17_1_AM_EWA_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_EWA_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_EWA_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_EWA_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 4419 rbm_m register am_ewa 0x3E18 R 0x0000000000000000 Spio_noc_bridge_rbm_m_17_1_am_ewa This is the address on AW channel for which a decode error was detected. This corresponds to the status register bit e16 in AM_ERR. false false false false WRITE_DECERR_ADDRS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_EWA_WRITE_DECERR_ADDRS_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_EWA_WRITE_DECERR_ADDRS_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_EWA_WRITE_DECERR_ADDRS_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_EWA_WRITE_DECERR_ADDRS_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_EWA_WRITE_DECERR_ADDRS_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_EWA_WRITE_DECERR_ADDRS_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_EWA_WRITE_DECERR_ADDRS_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_EWA_WRITE_DECERR_ADDRS_SET ns_noc_io_spio_soc_ip.csr 4418 WRITE_DECERR_ADDRS Write decerr address 63 0 0x0000000000000000 R register spio_noc.bridge_rbm_m_17_1_am_intm bridge_rbm_m_17_1_am_intm SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 4903 rbm_m register am_intm 0x3E40 R/W 0x00007e07004f004f Spio_noc_bridge_rbm_m_17_1_am_intm Interrupt mask register. Individual bit position matches the error bit positions in AM_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M0_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M0_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M0_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M0_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M0_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M0_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M0_SET ns_noc_io_spio_soc_ip.csr 4441 M0 1'b1: Mask interrupt for read channel 0 0 0x1 R/W M1 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M1_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M1_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M1_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M1_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M1_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M1_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M1_SET ns_noc_io_spio_soc_ip.csr 4452 M1 1'b1: Mask interrupt for read channel 1 1 0x1 R/W M2 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M2_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M2_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M2_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M2_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M2_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M2_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M2_SET ns_noc_io_spio_soc_ip.csr 4463 M2 1'b1: Mask interrupt for read channel 2 2 0x1 R/W M3 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M3_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M3_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M3_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M3_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M3_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M3_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M3_SET ns_noc_io_spio_soc_ip.csr 4474 M3 1'b1: Mask interrupt for read channel 3 3 0x1 R/W M4 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M4_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M4_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M4_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M4_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M4_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M4_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M4_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M4_SET ns_noc_io_spio_soc_ip.csr 4485 M4 1'b1: Mask interrupt for read channel 4 4 0x0 R/W M5 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M5_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M5_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M5_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M5_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M5_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M5_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M5_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M5_SET ns_noc_io_spio_soc_ip.csr 4496 M5 1'b1: Mask interrupt for read channel 5 5 0x0 R/W M6 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M6_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M6_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M6_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M6_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M6_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M6_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M6_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M6_SET ns_noc_io_spio_soc_ip.csr 4507 M6 1'b1: Mask interrupt for read channel 6 6 0x1 R/W M7 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M7_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M7_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M7_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M7_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M7_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M7_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M7_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M7_SET ns_noc_io_spio_soc_ip.csr 4518 M7 1'b1: Mask interrupt for read channel 7 7 0x0 R/W M8 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M8_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M8_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M8_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M8_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M8_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M8_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M8_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M8_SET ns_noc_io_spio_soc_ip.csr 4529 M8 1'b1: Mask interrupt for read channel 8 8 0x0 R/W UNSD_15_9 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_15_9_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_15_9_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_15_9_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_15_9_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_15_9_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_15_9_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_15_9_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_15_9_SET ns_noc_io_spio_soc_ip.csr 4540 UNSD_15_9 15 9 0x00 R M16 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M16_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M16_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M16_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M16_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M16_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M16_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M16_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M16_SET ns_noc_io_spio_soc_ip.csr 4551 M16 1'b1: Mask interrupt for write channel 16 16 0x1 R/W M17 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M17_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M17_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M17_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M17_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M17_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M17_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M17_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M17_SET ns_noc_io_spio_soc_ip.csr 4562 M17 1'b1: Mask interrupt for write channel 17 17 0x1 R/W M18 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M18_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M18_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M18_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M18_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M18_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M18_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M18_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M18_SET ns_noc_io_spio_soc_ip.csr 4573 M18 1'b1: Mask interrupt for write channel 18 18 0x1 R/W M19 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M19_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M19_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M19_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M19_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M19_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M19_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M19_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M19_SET ns_noc_io_spio_soc_ip.csr 4584 M19 1'b1: Mask interrupt for write channel 19 19 0x1 R/W M20 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M20_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M20_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M20_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M20_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M20_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M20_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M20_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M20_SET ns_noc_io_spio_soc_ip.csr 4595 M20 1'b1: Mask interrupt for write channel 20 20 0x0 R/W M21 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M21_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M21_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M21_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M21_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M21_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M21_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M21_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M21_SET ns_noc_io_spio_soc_ip.csr 4606 M21 1'b1: Mask interrupt for write channel 21 21 0x0 R/W M22 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M22_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M22_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M22_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M22_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M22_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M22_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M22_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M22_SET ns_noc_io_spio_soc_ip.csr 4617 M22 1'b1: Mask interrupt for write channel 22 22 0x1 R/W M23 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M23_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M23_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M23_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M23_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M23_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M23_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M23_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M23_SET ns_noc_io_spio_soc_ip.csr 4628 M23 1'b1: Mask interrupt for write channel 23 23 0x0 R/W M24 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M24_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M24_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M24_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M24_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M24_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M24_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M24_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M24_SET ns_noc_io_spio_soc_ip.csr 4639 M24 1'b1: Mask interrupt for write channel 24 24 0x0 R/W UNSD_31_25 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_31_25_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_31_25_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_31_25_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_31_25_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_31_25_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_31_25_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_31_25_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_31_25_SET ns_noc_io_spio_soc_ip.csr 4650 UNSD_31_25 31 25 0x00 R M32 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M32_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M32_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M32_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M32_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M32_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M32_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M32_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M32_SET ns_noc_io_spio_soc_ip.csr 4661 M32 1'b1: Counter 0 overflow interrupt mask 32 32 0x1 R/W M33 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M33_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M33_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M33_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M33_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M33_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M33_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M33_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M33_SET ns_noc_io_spio_soc_ip.csr 4672 M33 1'b1: Counter 1 overflow interrupt mask 33 33 0x1 R/W M34 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M34_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M34_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M34_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M34_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M34_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M34_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M34_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M34_SET ns_noc_io_spio_soc_ip.csr 4683 M34 1'b1: Mask interrupt on traffic to PG layer 34 34 0x1 R/W M35 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M35_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M35_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M35_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M35_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M35_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M35_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M35_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M35_SET ns_noc_io_spio_soc_ip.csr 4694 M35 1'b1: Mask interrupt on csr parity errors 35 35 0x0 R/W UNSD_39_36 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_39_36_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_39_36_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_39_36_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_39_36_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_39_36_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_39_36_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_39_36_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_39_36_SET ns_noc_io_spio_soc_ip.csr 4705 UNSD_39_36 39 36 0x0 R M40 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M40_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M40_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M40_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M40_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M40_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M40_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M40_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M40_SET ns_noc_io_spio_soc_ip.csr 4717 M40 1'b1: Mask interrupt for SIB portcheck error (SIB mode only) 40 40 0x0 R/W M41 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M41_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M41_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M41_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M41_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M41_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M41_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M41_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M41_SET ns_noc_io_spio_soc_ip.csr 4728 M41 1'b1: AR Parity Intr Mask 41 41 0x1 R/W M42 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M42_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M42_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M42_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M42_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M42_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M42_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M42_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M42_SET ns_noc_io_spio_soc_ip.csr 4739 M42 1'b1: ARADDR Parity Intr Mask 42 42 0x1 R/W M43 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M43_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M43_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M43_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M43_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M43_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M43_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M43_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M43_SET ns_noc_io_spio_soc_ip.csr 4750 M43 1'b1: AW Parity Intr Mask 43 43 0x1 R/W M44 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M44_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M44_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M44_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M44_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M44_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M44_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M44_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M44_SET ns_noc_io_spio_soc_ip.csr 4761 M44 1'b1: AWADDR Parity Intr Mask 44 44 0x1 R/W M45 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M45_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M45_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M45_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M45_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M45_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M45_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M45_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M45_SET ns_noc_io_spio_soc_ip.csr 4772 M45 1'b1: WDATA Parity Intr Mask 45 45 0x1 R/W M46 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M46_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M46_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M46_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M46_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M46_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M46_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M46_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_M46_SET ns_noc_io_spio_soc_ip.csr 4783 M46 1'b1: CDDATA Parity Intr Mask 46 46 0x1 R/W E47 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E47_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E47_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E47_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E47_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E47_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E47_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E47_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E47_SET ns_noc_io_spio_soc_ip.csr 4795 E47 1'b1: Ridtbl Parity Intr Mask 47 47 0x0 R E48 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E48_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E48_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E48_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E48_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E48_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E48_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E48_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E48_SET ns_noc_io_spio_soc_ip.csr 4807 E48 1'b1: Widtbl Parity Intr Mask 48 48 0x0 R E49 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E49_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E49_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E49_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E49_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E49_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E49_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E49_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E49_SET ns_noc_io_spio_soc_ip.csr 4819 E49 1'b1: Read Reorder Buffer Parity Intr Mask 49 49 0x0 R E50 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E50_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E50_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E50_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E50_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E50_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E50_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E50_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E50_SET ns_noc_io_spio_soc_ip.csr 4831 E50 1'b1: Write Reorder Buffer Parity Intr Mask 50 50 0x0 R E51 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E51_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E51_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E51_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E51_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E51_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E51_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E51_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E51_SET ns_noc_io_spio_soc_ip.csr 4843 E51 1'b1: Rx Fifo Parity Intr Mask 51 51 0x0 R E52 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E52_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E52_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E52_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E52_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E52_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E52_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E52_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E52_SET ns_noc_io_spio_soc_ip.csr 4855 E52 1'b1: Ack Channel Wack Fifo Parity Intr Mask 52 52 0x0 R E53 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E53_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E53_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E53_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E53_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E53_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E53_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E53_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E53_SET ns_noc_io_spio_soc_ip.csr 4867 E53 1'b1: Ack Channel Rack Fifo Parity Intr Mask 53 53 0x0 R E54 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E54_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E54_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E54_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E54_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E54_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E54_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E54_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E54_SET ns_noc_io_spio_soc_ip.csr 4879 E54 1'b1: CRCD Channel Crid Fifo Parity Intr Mask 54 54 0x0 R E55 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E55_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E55_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E55_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E55_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E55_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E55_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E55_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_E55_SET ns_noc_io_spio_soc_ip.csr 4891 E55 1'b1: R Channel Cpkt Fifo Parity Intr Mask 55 55 0x0 R UNSD_63_56 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_63_56_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_63_56_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_63_56_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_63_56_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_INTM_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 4902 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_rbm_m_17_1_am_caddr bridge_rbm_m_17_1_am_caddr SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CADDR_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CADDR_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CADDR_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CADDR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 4925 rbm_m register am_caddr 0x3F00 R/W 0xffffffffffffffff Spio_noc_bridge_rbm_m_17_1_am_caddr This register is part of statistics gathering on the AR and AW command channels. This is the address value which is checked against AR, AW command channels in conjunction with the mask below to filter commands for statistics gathering. false false false false CAPTURE_ADDR SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CADDR_CAPTURE_ADDR_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CADDR_CAPTURE_ADDR_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CADDR_CAPTURE_ADDR_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CADDR_CAPTURE_ADDR_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CADDR_CAPTURE_ADDR_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CADDR_CAPTURE_ADDR_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CADDR_CAPTURE_ADDR_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CADDR_CAPTURE_ADDR_SET ns_noc_io_spio_soc_ip.csr 4924 CAPTURE_ADDR Capture address 63 0 0xffffffffffffffff R/W register spio_noc.bridge_rbm_m_17_1_am_caddrmsk bridge_rbm_m_17_1_am_caddrmsk SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CADDRMSK_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CADDRMSK_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CADDRMSK_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CADDRMSK_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 4948 rbm_m register am_caddrmsk 0x3F08 R/W 0x0000000000000000 Spio_noc_bridge_rbm_m_17_1_am_caddrmsk If command address on the AR, AW channel logically ANDed with this mask is equal to the value specified in AM_CADDR, then an address match has occurred. Note that only lowest significant bits equal to the master's address width are used in the comparison. false false false false CAPTURE_ADDR_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CADDRMSK_CAPTURE_ADDR_MASK_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CADDRMSK_CAPTURE_ADDR_MASK_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CADDRMSK_CAPTURE_ADDR_MASK_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CADDRMSK_CAPTURE_ADDR_MASK_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CADDRMSK_CAPTURE_ADDR_MASK_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CADDRMSK_CAPTURE_ADDR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CADDRMSK_CAPTURE_ADDR_MASK_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CADDRMSK_CAPTURE_ADDR_MASK_SET ns_noc_io_spio_soc_ip.csr 4947 CAPTURE_ADDR_MASK Capture address mask 63 0 0x0000000000000000 R/W register spio_noc.bridge_rbm_m_17_1_am_ccmd0 bridge_rbm_m_17_1_am_ccmd0 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 5138 rbm_m register am_ccmd0 0x3F10 R/W 0x0000000003fff33f Spio_noc_bridge_rbm_m_17_1_am_ccmd0 Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands. false false false false SNOOP SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_SNOOP_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_SNOOP_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_SNOOP_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_SNOOP_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_SNOOP_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_SNOOP_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_SNOOP_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_SNOOP_SET ns_noc_io_spio_soc_ip.csr 4970 SNOOP Snoop 3 0 0xf R/W DOMAIN SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_DOMAIN_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_DOMAIN_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_DOMAIN_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_DOMAIN_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_DOMAIN_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_DOMAIN_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_DOMAIN_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_DOMAIN_SET ns_noc_io_spio_soc_ip.csr 4981 DOMAIN Domain 5 4 0x3 R/W UNSD_7_6 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_7_6_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_7_6_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_7_6_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_7_6_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 4992 UNSD_7_6 7 6 0x0 R BAR SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_BAR_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_BAR_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_BAR_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_BAR_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_BAR_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_BAR_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_BAR_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_BAR_SET ns_noc_io_spio_soc_ip.csr 5003 BAR Bar 9 8 0x3 R/W UNSD_11_10 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_11_10_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_11_10_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_11_10_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_11_10_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_11_10_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_11_10_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_11_10_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_11_10_SET ns_noc_io_spio_soc_ip.csr 5014 UNSD_11_10 11 10 0x0 R CACHE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_CACHE_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_CACHE_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_CACHE_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_CACHE_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_CACHE_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_CACHE_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_CACHE_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_CACHE_SET ns_noc_io_spio_soc_ip.csr 5025 CACHE Cache 15 12 0xf R/W QOS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_QOS_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_QOS_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_QOS_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_QOS_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_QOS_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_QOS_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_QOS_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_QOS_SET ns_noc_io_spio_soc_ip.csr 5036 QOS QoS 19 16 0xf R/W PROT SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_PROT_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_PROT_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_PROT_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_PROT_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_PROT_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_PROT_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_PROT_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_PROT_SET ns_noc_io_spio_soc_ip.csr 5047 PROT Prot 22 20 0x7 R/W LOC SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_LOC_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_LOC_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_LOC_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_LOC_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_LOC_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_LOC_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_LOC_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_LOC_SET ns_noc_io_spio_soc_ip.csr 5058 LOC 1'b1: Lock 23 23 0x1 R/W RDY SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_RDY_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_RDY_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_RDY_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_RDY_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_RDY_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_RDY_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_RDY_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_RDY_SET ns_noc_io_spio_soc_ip.csr 5069 RDY 1'b1: Ready 24 24 0x1 R/W VAL SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_VAL_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_VAL_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_VAL_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_VAL_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_VAL_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_VAL_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_VAL_SET ns_noc_io_spio_soc_ip.csr 5080 VAL 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_27_26_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_27_26_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_27_26_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_27_26_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_27_26_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_27_26_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_27_26_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_27_26_SET ns_noc_io_spio_soc_ip.csr 5091 UNSD_27_26 27 26 0x0 R INTFID SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_INTFID_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_INTFID_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_INTFID_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_INTFID_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_INTFID_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_INTFID_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_INTFID_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_INTFID_SET ns_noc_io_spio_soc_ip.csr 5103 INTFID 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_31_31 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_31_31_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_31_31_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_31_31_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_31_31_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_31_31_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_31_31_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_31_31_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_31_31_SET ns_noc_io_spio_soc_ip.csr 5114 UNSD_31_31 31 31 0x0 R TYP SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_TYP_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_TYP_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_TYP_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_TYP_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_TYP_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_TYP_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_TYP_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_TYP_SET ns_noc_io_spio_soc_ip.csr 5126 TYP 1'b1: Count response latency of captured command 1'b0: Count captured command 32 32 0x0 R/W UNSD_63_33 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_63_33_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_63_33_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_63_33_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_63_33_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_63_33_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_63_33_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_63_33_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD0_UNSD_63_33_SET ns_noc_io_spio_soc_ip.csr 5137 UNSD_63_33 63 33 0x00000000 R register spio_noc.bridge_rbm_m_17_1_am_ccmdmsk0 bridge_rbm_m_17_1_am_ccmdmsk0 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 5282 rbm_m register am_ccmdmsk0 0x3F18 R/W 0x0000000000000000 Spio_noc_bridge_rbm_m_17_1_am_ccmdmsk0 If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters. false false false false SNOOP SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_SNOOP_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_SNOOP_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_SNOOP_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_SNOOP_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_SNOOP_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_SNOOP_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_SNOOP_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_SNOOP_SET ns_noc_io_spio_soc_ip.csr 5160 SNOOP Snoop 3 0 0x0 R/W DOMAIN SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_DOMAIN_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_DOMAIN_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_DOMAIN_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_DOMAIN_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_DOMAIN_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_DOMAIN_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_DOMAIN_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_DOMAIN_SET ns_noc_io_spio_soc_ip.csr 5171 DOMAIN Domain 5 4 0x0 R/W UNSD_7_6 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_UNSD_7_6_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_UNSD_7_6_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_UNSD_7_6_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_UNSD_7_6_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 5182 UNSD_7_6 7 6 0x0 R BAR SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_BAR_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_BAR_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_BAR_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_BAR_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_BAR_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_BAR_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_BAR_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_BAR_SET ns_noc_io_spio_soc_ip.csr 5193 BAR Bar 9 8 0x0 R/W UNSD_11_10 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_UNSD_11_10_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_UNSD_11_10_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_UNSD_11_10_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_UNSD_11_10_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_UNSD_11_10_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_UNSD_11_10_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_UNSD_11_10_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_UNSD_11_10_SET ns_noc_io_spio_soc_ip.csr 5204 UNSD_11_10 11 10 0x0 R CACHE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_CACHE_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_CACHE_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_CACHE_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_CACHE_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_CACHE_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_CACHE_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_CACHE_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_CACHE_SET ns_noc_io_spio_soc_ip.csr 5215 CACHE Cache 15 12 0x0 R/W QOS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_QOS_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_QOS_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_QOS_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_QOS_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_QOS_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_QOS_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_QOS_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_QOS_SET ns_noc_io_spio_soc_ip.csr 5226 QOS QoS 19 16 0x0 R/W PROT SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_PROT_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_PROT_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_PROT_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_PROT_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_PROT_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_PROT_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_PROT_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_PROT_SET ns_noc_io_spio_soc_ip.csr 5237 PROT Prot 22 20 0x0 R/W LOC SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_LOC_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_LOC_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_LOC_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_LOC_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_LOC_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_LOC_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_LOC_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_LOC_SET ns_noc_io_spio_soc_ip.csr 5248 LOC 1'b1: Lock 23 23 0x0 R/W RDY SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_RDY_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_RDY_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_RDY_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_RDY_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_RDY_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_RDY_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_RDY_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_RDY_SET ns_noc_io_spio_soc_ip.csr 5259 RDY 1'b1: Ready 24 24 0x0 R/W VAL SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_VAL_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_VAL_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_VAL_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_VAL_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_VAL_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_VAL_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_VAL_SET ns_noc_io_spio_soc_ip.csr 5270 VAL 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_UNSD_63_26_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_UNSD_63_26_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_UNSD_63_26_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_UNSD_63_26_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_UNSD_63_26_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_UNSD_63_26_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_UNSD_63_26_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK0_UNSD_63_26_SET ns_noc_io_spio_soc_ip.csr 5281 UNSD_63_26 63 26 0x0000000000 R register spio_noc.bridge_rbm_m_17_1_am_cntr0 bridge_rbm_m_17_1_am_cntr0 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR0_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR0_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR0_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 5317 rbm_m register am_cntr0 0x3F20 R/W 0x0000000000000000 Spio_noc_bridge_rbm_m_17_1_am_cntr0 32-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured. false false false false CNTR SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR0_CNTR_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR0_CNTR_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR0_CNTR_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR0_CNTR_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR0_CNTR_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR0_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR0_CNTR_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR0_CNTR_SET ns_noc_io_spio_soc_ip.csr 5305 CNTR Counter 31 0 0x00000000 R/W UNSD_63_32 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR0_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR0_UNSD_63_32_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR0_UNSD_63_32_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR0_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR0_UNSD_63_32_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR0_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR0_UNSD_63_32_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR0_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 5316 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_rbm_m_17_1_am_latnum0 bridge_rbm_m_17_1_am_latnum0 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM0_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM0_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM0_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 5356 rbm_m register am_latnum0 0x3F28 R/W 0x0000000000000007 Spio_noc_bridge_rbm_m_17_1_am_latnum0 This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using: Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0 There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set. false false false false CNTR SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM0_CNTR_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM0_CNTR_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM0_CNTR_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM0_CNTR_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM0_CNTR_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM0_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM0_CNTR_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM0_CNTR_SET ns_noc_io_spio_soc_ip.csr 5344 CNTR Counter 31 0 0x00000007 R/W UNSD_63_32 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM0_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM0_UNSD_63_32_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM0_UNSD_63_32_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM0_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM0_UNSD_63_32_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM0_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM0_UNSD_63_32_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM0_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 5355 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_rbm_m_17_1_am_ccmd1 bridge_rbm_m_17_1_am_ccmd1 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 5546 rbm_m register am_ccmd1 0x3F30 R/W 0x0000000003fff33f Spio_noc_bridge_rbm_m_17_1_am_ccmd1 Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands. false false false false SNOOP SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_SNOOP_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_SNOOP_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_SNOOP_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_SNOOP_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_SNOOP_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_SNOOP_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_SNOOP_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_SNOOP_SET ns_noc_io_spio_soc_ip.csr 5378 SNOOP Snoop 3 0 0xf R/W DOMAIN SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_DOMAIN_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_DOMAIN_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_DOMAIN_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_DOMAIN_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_DOMAIN_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_DOMAIN_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_DOMAIN_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_DOMAIN_SET ns_noc_io_spio_soc_ip.csr 5389 DOMAIN Domain 5 4 0x3 R/W UNSD_7_6 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_7_6_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_7_6_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_7_6_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_7_6_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 5400 UNSD_7_6 7 6 0x0 R BAR SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_BAR_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_BAR_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_BAR_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_BAR_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_BAR_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_BAR_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_BAR_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_BAR_SET ns_noc_io_spio_soc_ip.csr 5411 BAR Bar 9 8 0x3 R/W UNSD_11_10 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_11_10_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_11_10_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_11_10_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_11_10_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_11_10_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_11_10_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_11_10_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_11_10_SET ns_noc_io_spio_soc_ip.csr 5422 UNSD_11_10 11 10 0x0 R CACHE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_CACHE_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_CACHE_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_CACHE_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_CACHE_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_CACHE_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_CACHE_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_CACHE_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_CACHE_SET ns_noc_io_spio_soc_ip.csr 5433 CACHE Cache 15 12 0xf R/W QOS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_QOS_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_QOS_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_QOS_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_QOS_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_QOS_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_QOS_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_QOS_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_QOS_SET ns_noc_io_spio_soc_ip.csr 5444 QOS QoS 19 16 0xf R/W PROT SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_PROT_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_PROT_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_PROT_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_PROT_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_PROT_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_PROT_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_PROT_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_PROT_SET ns_noc_io_spio_soc_ip.csr 5455 PROT Prot 22 20 0x7 R/W LOC SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_LOC_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_LOC_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_LOC_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_LOC_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_LOC_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_LOC_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_LOC_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_LOC_SET ns_noc_io_spio_soc_ip.csr 5466 LOC 1'b1: Lock 23 23 0x1 R/W RDY SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_RDY_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_RDY_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_RDY_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_RDY_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_RDY_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_RDY_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_RDY_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_RDY_SET ns_noc_io_spio_soc_ip.csr 5477 RDY 1'b1: Ready 24 24 0x1 R/W VAL SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_VAL_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_VAL_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_VAL_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_VAL_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_VAL_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_VAL_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_VAL_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_VAL_SET ns_noc_io_spio_soc_ip.csr 5488 VAL 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_27_26_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_27_26_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_27_26_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_27_26_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_27_26_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_27_26_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_27_26_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_27_26_SET ns_noc_io_spio_soc_ip.csr 5499 UNSD_27_26 27 26 0x0 R INTFID SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_INTFID_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_INTFID_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_INTFID_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_INTFID_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_INTFID_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_INTFID_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_INTFID_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_INTFID_SET ns_noc_io_spio_soc_ip.csr 5511 INTFID 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_31_31 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_31_31_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_31_31_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_31_31_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_31_31_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_31_31_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_31_31_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_31_31_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_31_31_SET ns_noc_io_spio_soc_ip.csr 5522 UNSD_31_31 31 31 0x0 R TYP SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_TYP_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_TYP_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_TYP_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_TYP_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_TYP_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_TYP_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_TYP_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_TYP_SET ns_noc_io_spio_soc_ip.csr 5534 TYP 1'b1: Count response latency of captured command 1'b0: Count captured command 32 32 0x0 R/W UNSD_63_33 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_63_33_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_63_33_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_63_33_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_63_33_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_63_33_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_63_33_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_63_33_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMD1_UNSD_63_33_SET ns_noc_io_spio_soc_ip.csr 5545 UNSD_63_33 63 33 0x00000000 R register spio_noc.bridge_rbm_m_17_1_am_ccmdmsk1 bridge_rbm_m_17_1_am_ccmdmsk1 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 5690 rbm_m register am_ccmdmsk1 0x3F38 R/W 0x0000000000000000 Spio_noc_bridge_rbm_m_17_1_am_ccmdmsk1 If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters. false false false false SNOOP SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_SNOOP_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_SNOOP_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_SNOOP_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_SNOOP_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_SNOOP_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_SNOOP_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_SNOOP_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_SNOOP_SET ns_noc_io_spio_soc_ip.csr 5568 SNOOP Snoop 3 0 0x0 R/W DOMAIN SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_DOMAIN_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_DOMAIN_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_DOMAIN_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_DOMAIN_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_DOMAIN_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_DOMAIN_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_DOMAIN_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_DOMAIN_SET ns_noc_io_spio_soc_ip.csr 5579 DOMAIN Domain 5 4 0x0 R/W UNSD_7_6 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_UNSD_7_6_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_UNSD_7_6_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_UNSD_7_6_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_UNSD_7_6_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 5590 UNSD_7_6 7 6 0x0 R BAR SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_BAR_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_BAR_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_BAR_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_BAR_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_BAR_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_BAR_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_BAR_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_BAR_SET ns_noc_io_spio_soc_ip.csr 5601 BAR Bar 9 8 0x0 R/W UNSD_11_10 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_UNSD_11_10_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_UNSD_11_10_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_UNSD_11_10_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_UNSD_11_10_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_UNSD_11_10_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_UNSD_11_10_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_UNSD_11_10_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_UNSD_11_10_SET ns_noc_io_spio_soc_ip.csr 5612 UNSD_11_10 11 10 0x0 R CACHE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_CACHE_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_CACHE_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_CACHE_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_CACHE_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_CACHE_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_CACHE_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_CACHE_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_CACHE_SET ns_noc_io_spio_soc_ip.csr 5623 CACHE Cache 15 12 0x0 R/W QOS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_QOS_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_QOS_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_QOS_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_QOS_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_QOS_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_QOS_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_QOS_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_QOS_SET ns_noc_io_spio_soc_ip.csr 5634 QOS QoS 19 16 0x0 R/W PROT SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_PROT_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_PROT_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_PROT_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_PROT_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_PROT_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_PROT_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_PROT_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_PROT_SET ns_noc_io_spio_soc_ip.csr 5645 PROT Prot 22 20 0x0 R/W LOC SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_LOC_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_LOC_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_LOC_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_LOC_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_LOC_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_LOC_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_LOC_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_LOC_SET ns_noc_io_spio_soc_ip.csr 5656 LOC 1'b1: Lock 23 23 0x0 R/W RDY SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_RDY_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_RDY_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_RDY_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_RDY_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_RDY_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_RDY_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_RDY_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_RDY_SET ns_noc_io_spio_soc_ip.csr 5667 RDY 1'b1: Ready 24 24 0x0 R/W VAL SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_VAL_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_VAL_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_VAL_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_VAL_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_VAL_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_VAL_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_VAL_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_VAL_SET ns_noc_io_spio_soc_ip.csr 5678 VAL 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_UNSD_63_26_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_UNSD_63_26_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_UNSD_63_26_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_UNSD_63_26_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_UNSD_63_26_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_UNSD_63_26_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_UNSD_63_26_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CCMDMSK1_UNSD_63_26_SET ns_noc_io_spio_soc_ip.csr 5689 UNSD_63_26 63 26 0x0000000000 R register spio_noc.bridge_rbm_m_17_1_am_cntr1 bridge_rbm_m_17_1_am_cntr1 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR1_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR1_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR1_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 5725 rbm_m register am_cntr1 0x3F40 R/W 0x0000000000000000 Spio_noc_bridge_rbm_m_17_1_am_cntr1 32-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured. false false false false CNTR SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR1_CNTR_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR1_CNTR_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR1_CNTR_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR1_CNTR_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR1_CNTR_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR1_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR1_CNTR_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR1_CNTR_SET ns_noc_io_spio_soc_ip.csr 5713 CNTR Counter 31 0 0x00000000 R/W UNSD_63_32 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR1_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR1_UNSD_63_32_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR1_UNSD_63_32_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR1_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR1_UNSD_63_32_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR1_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR1_UNSD_63_32_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_CNTR1_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 5724 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_rbm_m_17_1_am_latnum1 bridge_rbm_m_17_1_am_latnum1 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM1_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM1_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM1_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 5764 rbm_m register am_latnum1 0x3F48 R/W 0x0000000000000007 Spio_noc_bridge_rbm_m_17_1_am_latnum1 This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using: Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0 There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set. false false false false CNTR SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM1_CNTR_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM1_CNTR_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM1_CNTR_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM1_CNTR_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM1_CNTR_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM1_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM1_CNTR_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM1_CNTR_SET ns_noc_io_spio_soc_ip.csr 5752 CNTR Counter 31 0 0x00000007 R/W UNSD_63_32 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM1_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM1_UNSD_63_32_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM1_UNSD_63_32_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM1_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM1_UNSD_63_32_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM1_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM1_UNSD_63_32_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_LATNUM1_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 5763 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_rbm_m_17_1_am_arovrd bridge_rbm_m_17_1_am_arovrd SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 5877 rbm_m register am_arovrd 0x3F60 R/W 0x0000000000000000 Spio_noc_bridge_rbm_m_17_1_am_arovrd AR override. false false false false arcache_val SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARCACHE_VAL_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARCACHE_VAL_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARCACHE_VAL_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARCACHE_VAL_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARCACHE_VAL_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 5782 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARCACHE_ENB_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARCACHE_ENB_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARCACHE_ENB_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARCACHE_ENB_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARCACHE_ENB_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 5795 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARPROT_VAL_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARPROT_VAL_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARPROT_VAL_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARPROT_VAL_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARPROT_VAL_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARPROT_VAL_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 5806 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 5817 UNSD_11_11 11 11 0x0 R arprot_enb SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARPROT_ENB_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARPROT_ENB_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARPROT_ENB_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARPROT_ENB_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARPROT_ENB_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARPROT_ENB_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 5830 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 5841 UNSD_15_15 15 15 0x0 R arqos_val SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARQOS_VAL_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARQOS_VAL_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARQOS_VAL_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARQOS_VAL_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARQOS_VAL_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARQOS_VAL_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 5852 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARQOS_ENB_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARQOS_ENB_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARQOS_ENB_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARQOS_ENB_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARQOS_ENB_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARQOS_ENB_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_ARQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 5865 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AROVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 5876 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_rbm_m_17_1_am_awovrd bridge_rbm_m_17_1_am_awovrd SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_OFFSET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 5990 rbm_m register am_awovrd 0x3F68 R/W 0x0000000000000000 Spio_noc_bridge_rbm_m_17_1_am_awovrd AW override. false false false false awcache_val SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWCACHE_VAL_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWCACHE_VAL_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWCACHE_VAL_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWCACHE_VAL_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWCACHE_VAL_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 5895 awcache_val Value to override incoming ARCACHE 3 0 0x0 R/W awcache_enb SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWCACHE_ENB_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWCACHE_ENB_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWCACHE_ENB_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWCACHE_ENB_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWCACHE_ENB_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 5908 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWPROT_VAL_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWPROT_VAL_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWPROT_VAL_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWPROT_VAL_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWPROT_VAL_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWPROT_VAL_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 5919 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 5930 UNSD_11_11 11 11 0x0 R awprot_enb SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWPROT_ENB_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWPROT_ENB_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWPROT_ENB_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWPROT_ENB_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWPROT_ENB_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWPROT_ENB_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 5943 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 5954 UNSD_15_15 15 15 0x0 R awqos_val SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWQOS_VAL_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWQOS_VAL_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWQOS_VAL_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWQOS_VAL_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWQOS_VAL_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWQOS_VAL_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 5965 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWQOS_ENB_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWQOS_ENB_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWQOS_ENB_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWQOS_ENB_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWQOS_ENB_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWQOS_ENB_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_AWQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 5978 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_RBM_M_17_1_AM_AWOVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 5989 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_rbm_s_4_1_as_cgc bridge_rbm_s_4_1_as_cgc SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGC_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGC_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGC_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 6027 rbm_s register as_cgc 0x5C10 R/W 0x0000000000000064 Spio_noc_bridge_rbm_s_4_1_as_cgc Programmable intervals used by coarse clock gating logic. This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGC_HYSTERESIS_COUNTER_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGC_HYSTERESIS_COUNTER_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGC_HYSTERESIS_COUNTER_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGC_HYSTERESIS_COUNTER_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGC_HYSTERESIS_COUNTER_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGC_HYSTERESIS_COUNTER_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGC_HYSTERESIS_COUNTER_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_spio_soc_ip.csr 6015 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGC_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGC_UNSD_63_32_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGC_UNSD_63_32_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGC_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGC_UNSD_63_32_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGC_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGC_UNSD_63_32_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGC_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 6026 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_rbm_s_4_1_as_cgo bridge_rbm_s_4_1_as_cgo SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGO_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGO_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGO_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGO_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 6062 rbm_s register as_cgo 0x5C18 R/W 0x0000000000000000 Spio_noc_bridge_rbm_s_4_1_as_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the slave bridge. false false false false FPO SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGO_FPO_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGO_FPO_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGO_FPO_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGO_FPO_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGO_FPO_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGO_FPO_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGO_FPO_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGO_FPO_SET ns_noc_io_spio_soc_ip.csr 6050 FPO 1'b1: Clock gating override enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGO_UNSD_63_1_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGO_UNSD_63_1_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGO_UNSD_63_1_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGO_UNSD_63_1_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGO_UNSD_63_1_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGO_UNSD_63_1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGO_UNSD_63_1_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CGO_UNSD_63_1_SET ns_noc_io_spio_soc_ip.csr 6061 UNSD_63_1 63 1 0x0000000000000000 R register spio_noc.bridge_rbm_s_4_1_as_sts bridge_rbm_s_4_1_as_sts SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 6136 rbm_s register as_sts 0x5D00 R 0x000000000000000c Spio_noc_bridge_rbm_s_4_1_as_sts Slave bridge status bits. false false false false WOF SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_WOF_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_WOF_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_WOF_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_WOF_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_WOF_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_WOF_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_WOF_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_WOF_SET ns_noc_io_spio_soc_ip.csr 6085 WOF 1'b1: Maximum number of supported write commands are outstanding to the attached slave device awaiting response, no more write commands will be issued to slave till responses are received. 1'b0: Slave device can expect more write commands from NoC 0 0 0x0 R ROF SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_ROF_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_ROF_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_ROF_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_ROF_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_ROF_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_ROF_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_ROF_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_ROF_SET ns_noc_io_spio_soc_ip.csr 6101 ROF 1'b1: Maximum number of supported read commands are outstanding to the attached slave device awaiting response, no more read commands will be issued to slave till responses are received. 1'b0: Slave bridge can accept more read commands from the NoC 1 1 0x0 R WOE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_WOE_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_WOE_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_WOE_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_WOE_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_WOE_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_WOE_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_WOE_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_WOE_SET ns_noc_io_spio_soc_ip.csr 6113 WOE 1'b1: There are no write commands outstanding to the attached slave device 2 2 0x1 R ROE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_ROE_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_ROE_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_ROE_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_ROE_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_ROE_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_ROE_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_ROE_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_ROE_SET ns_noc_io_spio_soc_ip.csr 6125 ROE 1'b1: There are no read commands outstanding to the attached slave device 3 3 0x1 R UNSD_63_4 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_UNSD_63_4_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_UNSD_63_4_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_UNSD_63_4_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_UNSD_63_4_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_UNSD_63_4_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_UNSD_63_4_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_UNSD_63_4_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_STS_UNSD_63_4_SET ns_noc_io_spio_soc_ip.csr 6135 UNSD_63_4 63 4 0x000000000000000 R register spio_noc.bridge_rbm_s_4_1_as_bridge_id bridge_rbm_s_4_1_as_bridge_id SPIO_NOC_BRIDGE_RBM_S_4_1_AS_BRIDGE_ID_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_AS_BRIDGE_ID_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_AS_BRIDGE_ID_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_BRIDGE_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 6166 rbm_s register as_bridge_id 0x5D08 R 0x0000000000000004 Spio_noc_bridge_rbm_s_4_1_as_bridge_id Unique identifier assigned to the slave bridge. false false false false ID SPIO_NOC_BRIDGE_RBM_S_4_1_AS_BRIDGE_ID_ID_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_BRIDGE_ID_ID_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_BRIDGE_ID_ID_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_BRIDGE_ID_ID_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_BRIDGE_ID_ID_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_BRIDGE_ID_ID_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_BRIDGE_ID_ID_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_BRIDGE_ID_ID_SET ns_noc_io_spio_soc_ip.csr 6155 ID Unique bridge ID 15 0 0x0004 R UNSD_63_16 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_BRIDGE_ID_UNSD_63_16_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_BRIDGE_ID_UNSD_63_16_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_BRIDGE_ID_UNSD_63_16_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_BRIDGE_ID_UNSD_63_16_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_BRIDGE_ID_UNSD_63_16_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_BRIDGE_ID_UNSD_63_16_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_BRIDGE_ID_UNSD_63_16_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_spio_soc_ip.csr 6165 UNSD_63_16 63 16 0x000000000000 R register spio_noc.bridge_rbm_s_4_1_as_err bridge_rbm_s_4_1_as_err SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 6519 rbm_s register as_err 0x5E00 R/W 0x0000000000000000 Spio_noc_bridge_rbm_s_4_1_as_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E0_SET ns_noc_io_spio_soc_ip.csr 6187 E0 1'b1: Read decode error response: Decode error response received from slave device for read command 0 0 0x0 R/W E1 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E1_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E1_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E1_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E1_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E1_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E1_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E1_SET ns_noc_io_spio_soc_ip.csr 6199 E1 1'b1: Read slave error response: Slave error response received from slave device for read command 1 1 0x0 R/W E2 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E2_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E2_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E2_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E2_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E2_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E2_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E2_SET ns_noc_io_spio_soc_ip.csr 6212 E2 1'b1: [FATAL] Unknown read response destination: RID from read response produces a destination which is not present in the routing table 2 2 0x0 R/W E3 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E3_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E3_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E3_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E3_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E3_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E3_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E3_SET ns_noc_io_spio_soc_ip.csr 6226 E3 1'b1: [FATAL] Interleaved read response: Interleaved read response. This can occur if interleaved read response is received from a slave device for which a de-interleaver was not specified 3 3 0x0 R/W E4 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E4_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E4_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E4_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E4_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E4_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E4_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E4_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E4_SET ns_noc_io_spio_soc_ip.csr 6238 E4 1'b1: Read command modified: A read command which was marked as non-modifiable was modified by the slave bridge 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_UNSD_15_5_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_UNSD_15_5_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_UNSD_15_5_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_UNSD_15_5_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_UNSD_15_5_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_UNSD_15_5_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_UNSD_15_5_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 6249 UNSD_15_5 15 5 0x000 R E16 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E16_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E16_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E16_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E16_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E16_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E16_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E16_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E16_SET ns_noc_io_spio_soc_ip.csr 6261 E16 1'b1: Write decode error response: Decode error response received from slave device for write command 16 16 0x0 R/W E17 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E17_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E17_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E17_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E17_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E17_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E17_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E17_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E17_SET ns_noc_io_spio_soc_ip.csr 6273 E17 1'b1: Write slave error response: Slave error response received from slave device for write command 17 17 0x0 R/W E18 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E18_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E18_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E18_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E18_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E18_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E18_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E18_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E18_SET ns_noc_io_spio_soc_ip.csr 6286 E18 1'b1: [FATAL] Unknown write response destination: BID from write response produces a destination which is not present in the routing table 18 18 0x0 R/W E19 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E19_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E19_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E19_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E19_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E19_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E19_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E19_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E19_SET ns_noc_io_spio_soc_ip.csr 6298 E19 1'b1: Write command modified: A write command which was marked as non-modifiable was modified by the slave bridge 19 19 0x0 R/W UNSD_31_20 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_UNSD_31_20_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_UNSD_31_20_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_UNSD_31_20_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_UNSD_31_20_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_UNSD_31_20_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_UNSD_31_20_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_UNSD_31_20_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_UNSD_31_20_SET ns_noc_io_spio_soc_ip.csr 6309 UNSD_31_20 31 20 0x000 R E32 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E32_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E32_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E32_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E32_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E32_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E32_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E32_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E32_SET ns_noc_io_spio_soc_ip.csr 6321 E32 1'b1: [FATAL] Traffic sent to a noc layer which is power gated 32 32 0x0 R/W E33 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E33_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E33_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E33_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E33_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E33_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E33_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E33_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E33_SET ns_noc_io_spio_soc_ip.csr 6332 E33 1'b1: [FATAL] Parity error in config/status registers 33 33 0x0 R/W E34 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E34_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E34_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E34_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E34_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E34_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E34_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E34_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E34_SET ns_noc_io_spio_soc_ip.csr 6343 E34 1'b1: [FATAL] RDATA Parity error 34 34 0x0 R/W E35 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E35_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E35_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E35_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E35_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E35_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E35_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E35_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E35_SET ns_noc_io_spio_soc_ip.csr 6354 E35 1'b1: [FATAL] RRESP Parity error 35 35 0x0 R/W E36 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E36_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E36_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E36_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E36_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E36_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E36_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E36_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E36_SET ns_noc_io_spio_soc_ip.csr 6365 E36 1'b1: [FATAL] BRESP Parity error 36 36 0x0 R/W E37 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E37_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E37_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E37_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E37_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E37_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E37_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E37_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E37_SET ns_noc_io_spio_soc_ip.csr 6376 E37 1'b1: [FATAL] AC Parity error 37 37 0x0 R/W E38 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E38_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E38_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E38_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E38_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E38_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E38_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E38_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E38_SET ns_noc_io_spio_soc_ip.csr 6387 E38 1'b1: [FATAL] ACADDR Parity error 38 38 0x0 R/W E39 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E39_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E39_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E39_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E39_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E39_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E39_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E39_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E39_SET ns_noc_io_spio_soc_ip.csr 6399 E39 1'b1: [FATAL] R Ch Cmdtbl Parity Err 39 39 0x0 R E40 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E40_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E40_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E40_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E40_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E40_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E40_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E40_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E40_SET ns_noc_io_spio_soc_ip.csr 6411 E40 1'b1: [FATAL] B Ch Cmdtbl Parity Err 40 40 0x0 R E41 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E41_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E41_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E41_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E41_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E41_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E41_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E41_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E41_SET ns_noc_io_spio_soc_ip.csr 6423 E41 1'b1: [FATAL] Rx Fifo Parity Err 41 41 0x0 R E42 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E42_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E42_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E42_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E42_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E42_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E42_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E42_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E42_SET ns_noc_io_spio_soc_ip.csr 6435 E42 1'b1: [FATAL] CRCD Ch Reorder Buffer Parity Err 42 42 0x0 R E43 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E43_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E43_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E43_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E43_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E43_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E43_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E43_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E43_SET ns_noc_io_spio_soc_ip.csr 6447 E43 1'b1: [FATAL] Ack Ch Wack Reorder Buffer Parity Err 43 43 0x0 R E44 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E44_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E44_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E44_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E44_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E44_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E44_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E44_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E44_SET ns_noc_io_spio_soc_ip.csr 6459 E44 1'b1: [FATAL] Ack Ch Rack Reorder Buffer Parity Err 44 44 0x0 R E45 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E45_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E45_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E45_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E45_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E45_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E45_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E45_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E45_SET ns_noc_io_spio_soc_ip.csr 6471 E45 1'b1: [FATAL] B Ch Drain Fifo Parity Err 45 45 0x0 R E46 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E46_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E46_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E46_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E46_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E46_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E46_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E46_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E46_SET ns_noc_io_spio_soc_ip.csr 6483 E46 1'b1: [FATAL] R Ch Flush Fifo Parity Err 46 46 0x0 R E47 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E47_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E47_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E47_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E47_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E47_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E47_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E47_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E47_SET ns_noc_io_spio_soc_ip.csr 6495 E47 1'b1: [FATAL] R Ch Deinterleaver Cmdtbl Parity Err 47 47 0x0 R E48 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E48_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E48_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E48_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E48_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E48_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E48_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E48_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_E48_SET ns_noc_io_spio_soc_ip.csr 6507 E48 1'b1: [FATAL] R Ch Deinterleaver Data Buffer Parity Err 48 48 0x0 R UNSD_63_49 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_UNSD_63_49_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_UNSD_63_49_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_UNSD_63_49_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_UNSD_63_49_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_UNSD_63_49_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_UNSD_63_49_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_UNSD_63_49_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_ERR_UNSD_63_49_SET ns_noc_io_spio_soc_ip.csr 6518 UNSD_63_49 63 49 0x0000 R register spio_noc.bridge_rbm_s_4_1_as_intm bridge_rbm_s_4_1_as_intm SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 6859 rbm_s register as_intm 0x5E40 R/W 0x0000007d000b0013 Spio_noc_bridge_rbm_s_4_1_as_intm Interrupt mask register.Individual bit positions match the error bit positions in AS_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M0_SET ns_noc_io_spio_soc_ip.csr 6540 M0 Mask interrupts for read channel 0 0 0x1 R/W M1 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M1_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M1_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M1_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M1_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M1_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M1_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M1_SET ns_noc_io_spio_soc_ip.csr 6551 M1 Mask interrupts for read channel 1 1 0x1 R/W M2 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M2_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M2_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M2_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M2_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M2_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M2_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M2_SET ns_noc_io_spio_soc_ip.csr 6562 M2 Mask interrupts for read channel 2 2 0x0 R/W M3 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M3_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M3_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M3_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M3_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M3_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M3_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M3_SET ns_noc_io_spio_soc_ip.csr 6573 M3 Mask interrupts for read channel 3 3 0x0 R/W M4 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M4_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M4_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M4_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M4_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M4_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M4_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M4_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M4_SET ns_noc_io_spio_soc_ip.csr 6584 M4 Mask interrupts for read channel 4 4 0x1 R/W UNSD_15_5 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_UNSD_15_5_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_UNSD_15_5_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_UNSD_15_5_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_UNSD_15_5_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_UNSD_15_5_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_UNSD_15_5_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_UNSD_15_5_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 6595 UNSD_15_5 15 5 0x000 R M16 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M16_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M16_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M16_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M16_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M16_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M16_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M16_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M16_SET ns_noc_io_spio_soc_ip.csr 6606 M16 Mask interrupts for write channel 16 16 0x1 R/W M17 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M17_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M17_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M17_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M17_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M17_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M17_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M17_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M17_SET ns_noc_io_spio_soc_ip.csr 6617 M17 Mask interrupts for write channel 17 17 0x1 R/W M18 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M18_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M18_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M18_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M18_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M18_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M18_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M18_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M18_SET ns_noc_io_spio_soc_ip.csr 6628 M18 Mask interrupts for write channel 18 18 0x0 R/W M19 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M19_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M19_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M19_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M19_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M19_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M19_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M19_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M19_SET ns_noc_io_spio_soc_ip.csr 6639 M19 Mask interrupts for write channel 19 19 0x1 R/W UNSD_31_20 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_UNSD_31_20_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_UNSD_31_20_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_UNSD_31_20_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_UNSD_31_20_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_UNSD_31_20_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_UNSD_31_20_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_UNSD_31_20_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_UNSD_31_20_SET ns_noc_io_spio_soc_ip.csr 6650 UNSD_31_20 31 20 0x000 R M32 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M32_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M32_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M32_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M32_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M32_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M32_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M32_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M32_SET ns_noc_io_spio_soc_ip.csr 6661 M32 Mask interrupt on traffic to PG layer 32 32 0x1 R/W M33 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M33_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M33_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M33_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M33_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M33_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M33_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M33_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M33_SET ns_noc_io_spio_soc_ip.csr 6672 M33 Mask interrupt on csr parity errors 33 33 0x0 R/W M34 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M34_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M34_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M34_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M34_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M34_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M34_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M34_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M34_SET ns_noc_io_spio_soc_ip.csr 6683 M34 RDATA parity interrupt Mask 34 34 0x1 R/W M35 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M35_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M35_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M35_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M35_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M35_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M35_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M35_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M35_SET ns_noc_io_spio_soc_ip.csr 6694 M35 RRESP parity interrupt Mask 35 35 0x1 R/W M36 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M36_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M36_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M36_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M36_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M36_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M36_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M36_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M36_SET ns_noc_io_spio_soc_ip.csr 6705 M36 BRESP parity interrupt Mask 36 36 0x1 R/W M37 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M37_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M37_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M37_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M37_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M37_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M37_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M37_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M37_SET ns_noc_io_spio_soc_ip.csr 6716 M37 AC parity interrupt Mask 37 37 0x1 R/W M38 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M38_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M38_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M38_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M38_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M38_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M38_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M38_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_M38_SET ns_noc_io_spio_soc_ip.csr 6727 M38 ACADDR parity interrupt Mask 38 38 0x1 R/W E39 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E39_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E39_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E39_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E39_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E39_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E39_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E39_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E39_SET ns_noc_io_spio_soc_ip.csr 6739 E39 1'b1: R Ch Cmdtbl Parity Err Intr Mask 39 39 0x0 R E40 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E40_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E40_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E40_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E40_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E40_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E40_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E40_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E40_SET ns_noc_io_spio_soc_ip.csr 6751 E40 1'b1: B Ch Cmdtbl Parity Err Intr Mask 40 40 0x0 R E41 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E41_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E41_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E41_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E41_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E41_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E41_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E41_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E41_SET ns_noc_io_spio_soc_ip.csr 6763 E41 1'b1: Rx Fifo Parity Err Intr Mask 41 41 0x0 R E42 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E42_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E42_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E42_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E42_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E42_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E42_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E42_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E42_SET ns_noc_io_spio_soc_ip.csr 6775 E42 1'b1: CRCD Ch Reorder Buffer Parity Err Intr Mask 42 42 0x0 R E43 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E43_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E43_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E43_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E43_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E43_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E43_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E43_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E43_SET ns_noc_io_spio_soc_ip.csr 6787 E43 1'b1: Ack Ch Wack Reorder Buffer Parity Err IntrMask 43 43 0x0 R E44 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E44_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E44_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E44_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E44_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E44_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E44_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E44_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E44_SET ns_noc_io_spio_soc_ip.csr 6799 E44 1'b1: Ack Ch Rack Reorder Buffer Parity Err Intr Mask 44 44 0x0 R E45 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E45_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E45_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E45_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E45_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E45_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E45_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E45_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E45_SET ns_noc_io_spio_soc_ip.csr 6811 E45 1'b1: B Ch Drain Fifo Parity Err Intr Mask 45 45 0x0 R E46 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E46_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E46_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E46_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E46_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E46_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E46_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E46_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E46_SET ns_noc_io_spio_soc_ip.csr 6823 E46 1'b1: R Ch Flush Fifo Parity Err Intr Mask 46 46 0x0 R E47 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E47_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E47_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E47_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E47_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E47_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E47_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E47_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E47_SET ns_noc_io_spio_soc_ip.csr 6835 E47 1'b1: R Ch Deinterleaver Cmdtbl Parity Err Intr Mask 47 47 0x0 R E48 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E48_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E48_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E48_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E48_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E48_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E48_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E48_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_E48_SET ns_noc_io_spio_soc_ip.csr 6847 E48 1'b1: R Ch Deinterleaver Data Buffer Parity Err Intr Mask 48 48 0x0 R UNSD_63_49 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_UNSD_63_49_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_UNSD_63_49_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_UNSD_63_49_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_UNSD_63_49_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_UNSD_63_49_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_UNSD_63_49_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_UNSD_63_49_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_INTM_UNSD_63_49_SET ns_noc_io_spio_soc_ip.csr 6858 UNSD_63_49 63 49 0x0000 R register spio_noc.bridge_rbm_s_4_1_as_ccmd bridge_rbm_s_4_1_as_ccmd SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 6934 rbm_s register as_ccmd 0x5F00 R/W 0x0000000003000000 Spio_noc_bridge_rbm_s_4_1_as_ccmd Not applicable for current release. false false false false UNSD_23_0 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_UNSD_23_0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_UNSD_23_0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_UNSD_23_0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_UNSD_23_0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_UNSD_23_0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_UNSD_23_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_UNSD_23_0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_UNSD_23_0_SET ns_noc_io_spio_soc_ip.csr 6877 UNSD_23_0 23 0 0x000000 R rdy SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_RDY_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_RDY_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_RDY_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_RDY_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_RDY_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_RDY_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_RDY_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_RDY_SET ns_noc_io_spio_soc_ip.csr 6888 rdy 1'b1: Ready 24 24 0x1 R/W val SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_VAL_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_VAL_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_VAL_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_VAL_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_VAL_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_VAL_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_VAL_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_VAL_SET ns_noc_io_spio_soc_ip.csr 6899 val 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_UNSD_27_26_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_UNSD_27_26_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_UNSD_27_26_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_UNSD_27_26_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_UNSD_27_26_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_UNSD_27_26_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_UNSD_27_26_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_UNSD_27_26_SET ns_noc_io_spio_soc_ip.csr 6910 UNSD_27_26 27 26 0x0 R intfid SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_INTFID_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_INTFID_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_INTFID_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_INTFID_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_INTFID_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_INTFID_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_INTFID_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_INTFID_SET ns_noc_io_spio_soc_ip.csr 6922 intfid 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_63_31 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_UNSD_63_31_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_UNSD_63_31_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_UNSD_63_31_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_UNSD_63_31_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_UNSD_63_31_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_UNSD_63_31_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_UNSD_63_31_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMD_UNSD_63_31_SET ns_noc_io_spio_soc_ip.csr 6933 UNSD_63_31 63 31 0x000000000 R register spio_noc.bridge_rbm_s_4_1_as_ccmdmsk bridge_rbm_s_4_1_as_ccmdmsk SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 6986 rbm_s register as_ccmdmsk 0x5F08 R/W 0x0000000000000000 Spio_noc_bridge_rbm_s_4_1_as_ccmdmsk Not applicable for current release. false false false false UNSD_23_0 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_UNSD_23_0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_UNSD_23_0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_UNSD_23_0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_UNSD_23_0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_UNSD_23_0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_UNSD_23_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_UNSD_23_0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_UNSD_23_0_SET ns_noc_io_spio_soc_ip.csr 6952 UNSD_23_0 23 0 0x000000 R rdy SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_RDY_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_RDY_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_RDY_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_RDY_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_RDY_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_RDY_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_RDY_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_RDY_SET ns_noc_io_spio_soc_ip.csr 6963 rdy 1'b1: Ready 24 24 0x0 R/W val SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_VAL_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_VAL_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_VAL_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_VAL_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_VAL_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_VAL_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_VAL_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_VAL_SET ns_noc_io_spio_soc_ip.csr 6974 val 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_UNSD_63_26_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_UNSD_63_26_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_UNSD_63_26_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_UNSD_63_26_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_UNSD_63_26_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_UNSD_63_26_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_UNSD_63_26_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CCMDMSK_UNSD_63_26_SET ns_noc_io_spio_soc_ip.csr 6985 UNSD_63_26 63 26 0x0000000000 R register spio_noc.bridge_rbm_s_4_1_as_cntr bridge_rbm_s_4_1_as_cntr SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CNTR_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CNTR_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CNTR_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CNTR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 7016 rbm_s register as_cntr 0x5F10 R 0x0000000000000000 Spio_noc_bridge_rbm_s_4_1_as_cntr Not applicable for current release. false false false false CNTR SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CNTR_CNTR_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CNTR_CNTR_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CNTR_CNTR_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CNTR_CNTR_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CNTR_CNTR_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CNTR_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CNTR_CNTR_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CNTR_CNTR_SET ns_noc_io_spio_soc_ip.csr 7005 CNTR Counter 31 0 0x00000000 R UNSD_63_32 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CNTR_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CNTR_UNSD_63_32_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CNTR_UNSD_63_32_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CNTR_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CNTR_UNSD_63_32_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CNTR_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CNTR_UNSD_63_32_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_CNTR_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 7015 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_rbm_s_4_1_as_arovrd bridge_rbm_s_4_1_as_arovrd SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 7129 rbm_s register as_arovrd 0x5F18 R/W 0x0000000000000000 Spio_noc_bridge_rbm_s_4_1_as_arovrd AR Overrides. false false false false arcache_val SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARCACHE_VAL_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARCACHE_VAL_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARCACHE_VAL_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARCACHE_VAL_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARCACHE_VAL_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 7034 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARCACHE_ENB_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARCACHE_ENB_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARCACHE_ENB_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARCACHE_ENB_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARCACHE_ENB_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 7047 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARPROT_VAL_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARPROT_VAL_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARPROT_VAL_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARPROT_VAL_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARPROT_VAL_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARPROT_VAL_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 7058 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 7069 UNSD_11_11 11 11 0x0 R arprot_enb SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARPROT_ENB_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARPROT_ENB_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARPROT_ENB_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARPROT_ENB_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARPROT_ENB_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARPROT_ENB_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 7082 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 7093 UNSD_15_15 15 15 0x0 R arqos_val SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARQOS_VAL_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARQOS_VAL_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARQOS_VAL_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARQOS_VAL_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARQOS_VAL_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARQOS_VAL_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 7104 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARQOS_ENB_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARQOS_ENB_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARQOS_ENB_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARQOS_ENB_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARQOS_ENB_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARQOS_ENB_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_ARQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 7117 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AROVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 7128 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_rbm_s_4_1_as_awovrd bridge_rbm_s_4_1_as_awovrd SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 7242 rbm_s register as_awovrd 0x5F20 R/W 0x0000000000000000 Spio_noc_bridge_rbm_s_4_1_as_awovrd AW Overrides. false false false false awcache_val SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWCACHE_VAL_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWCACHE_VAL_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWCACHE_VAL_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWCACHE_VAL_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWCACHE_VAL_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 7147 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWCACHE_ENB_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWCACHE_ENB_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWCACHE_ENB_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWCACHE_ENB_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWCACHE_ENB_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 7160 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWPROT_VAL_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWPROT_VAL_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWPROT_VAL_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWPROT_VAL_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWPROT_VAL_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWPROT_VAL_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 7171 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 7182 UNSD_11_11 11 11 0x0 R awprot_enb SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWPROT_ENB_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWPROT_ENB_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWPROT_ENB_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWPROT_ENB_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWPROT_ENB_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWPROT_ENB_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 7195 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 7206 UNSD_15_15 15 15 0x0 R awqos_val SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWQOS_VAL_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWQOS_VAL_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWQOS_VAL_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWQOS_VAL_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWQOS_VAL_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWQOS_VAL_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 7217 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWQOS_ENB_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWQOS_ENB_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWQOS_ENB_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWQOS_ENB_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWQOS_ENB_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWQOS_ENB_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_AWQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 7230 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_RBM_S_4_1_AS_AWOVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 7241 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_rbm_s_4_1_p_0 bridge_rbm_s_4_1_p_0 SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 7307 rbm_s register p_0 0x7000 R/W 0x00000003 Spio_noc_bridge_rbm_s_4_1_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_0_SET ns_noc_io_spio_soc_ip.csr 7270 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_1_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_1_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_1_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_1_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_1_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_1_GET SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_1_SET ns_noc_io_spio_soc_ip.csr 7282 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_2_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_2_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_2_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_2_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_2_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_2_GET SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_2_SET ns_noc_io_spio_soc_ip.csr 7294 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_3_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_3_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_3_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_3_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_3_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_3_GET SPIO_NOC_BRIDGE_RBM_S_4_1_P_0_WT_QOS_3_SET ns_noc_io_spio_soc_ip.csr 7306 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register spio_noc.bridge_rbm_s_4_1_p_1 bridge_rbm_s_4_1_p_1 SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 7373 rbm_s register p_1 0x7008 R 0x00000000 Spio_noc_bridge_rbm_s_4_1_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_4_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_4_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_4_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_4_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_4_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_4_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_4_GET SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_4_SET ns_noc_io_spio_soc_ip.csr 7336 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_5_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_5_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_5_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_5_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_5_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_5_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_5_GET SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_5_SET ns_noc_io_spio_soc_ip.csr 7348 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_6_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_6_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_6_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_6_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_6_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_6_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_6_GET SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_6_SET ns_noc_io_spio_soc_ip.csr 7360 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_7_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_7_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_7_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_7_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_7_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_7_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_7_GET SPIO_NOC_BRIDGE_RBM_S_4_1_P_1_WT_QOS_7_SET ns_noc_io_spio_soc_ip.csr 7372 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register spio_noc.bridge_rbm_s_4_1_p_2 bridge_rbm_s_4_1_p_2 SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 7439 rbm_s register p_2 0x7010 R 0x00000000 Spio_noc_bridge_rbm_s_4_1_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_8_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_8_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_8_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_8_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_8_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_8_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_8_GET SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_8_SET ns_noc_io_spio_soc_ip.csr 7402 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_9_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_9_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_9_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_9_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_9_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_9_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_9_GET SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_9_SET ns_noc_io_spio_soc_ip.csr 7414 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_10_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_10_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_10_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_10_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_10_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_10_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_10_GET SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_10_SET ns_noc_io_spio_soc_ip.csr 7426 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_11_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_11_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_11_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_11_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_11_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_11_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_11_GET SPIO_NOC_BRIDGE_RBM_S_4_1_P_2_WT_QOS_11_SET ns_noc_io_spio_soc_ip.csr 7438 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register spio_noc.bridge_rbm_s_4_1_p_3 bridge_rbm_s_4_1_p_3 SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 7505 rbm_s register p_3 0x7018 R 0x00000000 Spio_noc_bridge_rbm_s_4_1_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_12_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_12_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_12_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_12_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_12_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_12_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_12_GET SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_12_SET ns_noc_io_spio_soc_ip.csr 7468 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_13_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_13_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_13_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_13_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_13_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_13_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_13_GET SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_13_SET ns_noc_io_spio_soc_ip.csr 7480 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_14_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_14_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_14_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_14_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_14_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_14_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_14_GET SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_14_SET ns_noc_io_spio_soc_ip.csr 7492 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_15_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_15_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_15_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_15_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_15_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_15_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_15_GET SPIO_NOC_BRIDGE_RBM_S_4_1_P_3_WT_QOS_15_SET ns_noc_io_spio_soc_ip.csr 7504 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register spio_noc.bridge_rbm_s_4_1_txe bridge_rbm_s_4_1_txe SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 7651 rbm_s register txe 0x7040 R/W 0x00000000 Spio_noc_bridge_rbm_s_4_1_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_TRANS_WITHOUT_SOP_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_TRANS_WITHOUT_SOP_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_TRANS_WITHOUT_SOP_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_TRANS_WITHOUT_SOP_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_TRANS_WITHOUT_SOP_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_TRANS_WITHOUT_SOP_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_TRANS_WITHOUT_SOP_GET SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_spio_soc_ip.csr 7532 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_SOP_AFTER_SOP_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_SOP_AFTER_SOP_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_SOP_AFTER_SOP_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_SOP_AFTER_SOP_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_SOP_AFTER_SOP_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_SOP_AFTER_SOP_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_SOP_AFTER_SOP_GET SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_SOP_AFTER_SOP_SET ns_noc_io_spio_soc_ip.csr 7544 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 7559 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 7572 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_A_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_A_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_A_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_A_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_A_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_A_GET SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_spio_soc_ip.csr 7586 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_B_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_B_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_B_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_B_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_B_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_B_GET SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_spio_soc_ip.csr 7600 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_C_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_C_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_C_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_C_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_C_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_C_GET SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_spio_soc_ip.csr 7614 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_D_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_D_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_D_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_D_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_D_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_D_GET SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_spio_soc_ip.csr 7628 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 7639 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_UNSD_31_9_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_UNSD_31_9_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_UNSD_31_9_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_UNSD_31_9_GET SPIO_NOC_BRIDGE_RBM_S_4_1_TXE_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 7650 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_rbm_s_4_1_txem bridge_rbm_s_4_1_txem SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 7730 rbm_s register txem 0x7048 R/W 0x00000008 Spio_noc_bridge_rbm_s_4_1_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_UNSD_1_0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_UNSD_1_0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_UNSD_1_0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_UNSD_1_0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_UNSD_1_0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_UNSD_1_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_UNSD_1_0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_UNSD_1_0_SET ns_noc_io_spio_soc_ip.csr 7674 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 7685 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 7696 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_UNSD_7_4_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_UNSD_7_4_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_UNSD_7_4_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_UNSD_7_4_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_UNSD_7_4_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_UNSD_7_4_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_UNSD_7_4_GET SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_UNSD_7_4_SET ns_noc_io_spio_soc_ip.csr 7707 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 7718 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_UNSD_31_9_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_UNSD_31_9_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_UNSD_31_9_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_UNSD_31_9_GET SPIO_NOC_BRIDGE_RBM_S_4_1_TXEM_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 7729 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_rbm_s_4_1_btus_0 bridge_rbm_s_4_1_btus_0 SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 8098 rbm_s register btus_0 0x7058 R 0x00000000 Spio_noc_bridge_rbm_s_4_1_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_A_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_A_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_A_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_A_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_A_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_A_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_A_SET ns_noc_io_spio_soc_ip.csr 7756 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_B_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_B_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_B_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_B_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_B_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_B_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_B_SET ns_noc_io_spio_soc_ip.csr 7767 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_C_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_C_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_C_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_C_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_C_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_C_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_C_SET ns_noc_io_spio_soc_ip.csr 7778 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_D_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_D_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_D_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_D_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_D_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_D_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L0_D_SET ns_noc_io_spio_soc_ip.csr 7789 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_A_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_A_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_A_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_A_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_A_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_A_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_A_SET ns_noc_io_spio_soc_ip.csr 7800 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_B_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_B_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_B_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_B_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_B_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_B_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_B_SET ns_noc_io_spio_soc_ip.csr 7811 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_C_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_C_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_C_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_C_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_C_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_C_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_C_SET ns_noc_io_spio_soc_ip.csr 7822 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_D_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_D_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_D_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_D_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_D_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_D_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L1_D_SET ns_noc_io_spio_soc_ip.csr 7833 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_A_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_A_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_A_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_A_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_A_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_A_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_A_SET ns_noc_io_spio_soc_ip.csr 7844 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_B_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_B_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_B_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_B_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_B_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_B_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_B_SET ns_noc_io_spio_soc_ip.csr 7855 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_C_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_C_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_C_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_C_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_C_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_C_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_C_SET ns_noc_io_spio_soc_ip.csr 7866 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_D_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_D_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_D_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_D_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_D_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_D_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L2_D_SET ns_noc_io_spio_soc_ip.csr 7877 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_A_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_A_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_A_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_A_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_A_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_A_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_A_SET ns_noc_io_spio_soc_ip.csr 7888 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_B_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_B_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_B_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_B_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_B_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_B_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_B_SET ns_noc_io_spio_soc_ip.csr 7899 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_C_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_C_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_C_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_C_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_C_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_C_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_C_SET ns_noc_io_spio_soc_ip.csr 7910 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_D_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_D_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_D_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_D_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_D_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_D_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L3_D_SET ns_noc_io_spio_soc_ip.csr 7921 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_A_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_A_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_A_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_A_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_A_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_A_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_A_SET ns_noc_io_spio_soc_ip.csr 7932 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_B_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_B_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_B_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_B_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_B_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_B_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_B_SET ns_noc_io_spio_soc_ip.csr 7943 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_C_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_C_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_C_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_C_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_C_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_C_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_C_SET ns_noc_io_spio_soc_ip.csr 7954 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_D_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_D_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_D_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_D_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_D_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_D_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L4_D_SET ns_noc_io_spio_soc_ip.csr 7965 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_A_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_A_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_A_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_A_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_A_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_A_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_A_SET ns_noc_io_spio_soc_ip.csr 7976 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_B_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_B_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_B_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_B_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_B_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_B_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_B_SET ns_noc_io_spio_soc_ip.csr 7987 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_C_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_C_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_C_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_C_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_C_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_C_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_C_SET ns_noc_io_spio_soc_ip.csr 7998 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_D_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_D_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_D_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_D_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_D_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_D_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L5_D_SET ns_noc_io_spio_soc_ip.csr 8009 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_A_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_A_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_A_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_A_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_A_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_A_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_A_SET ns_noc_io_spio_soc_ip.csr 8020 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_B_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_B_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_B_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_B_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_B_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_B_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_B_SET ns_noc_io_spio_soc_ip.csr 8031 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_C_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_C_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_C_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_C_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_C_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_C_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_C_SET ns_noc_io_spio_soc_ip.csr 8042 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_D_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_D_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_D_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_D_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_D_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_D_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L6_D_SET ns_noc_io_spio_soc_ip.csr 8053 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_A_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_A_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_A_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_A_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_A_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_A_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_A_SET ns_noc_io_spio_soc_ip.csr 8064 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_B_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_B_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_B_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_B_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_B_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_B_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_B_SET ns_noc_io_spio_soc_ip.csr 8075 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_C_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_C_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_C_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_C_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_C_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_C_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_C_SET ns_noc_io_spio_soc_ip.csr 8086 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_D_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_D_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_D_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_D_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_D_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_D_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_0_L7_D_SET ns_noc_io_spio_soc_ip.csr 8097 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register spio_noc.bridge_rbm_s_4_1_btus_1 bridge_rbm_s_4_1_btus_1 SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 8466 rbm_s register btus_1 0x7060 R 0x00000000 Spio_noc_bridge_rbm_s_4_1_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_A_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_A_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_A_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_A_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_A_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_A_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_A_SET ns_noc_io_spio_soc_ip.csr 8124 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_B_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_B_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_B_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_B_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_B_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_B_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_B_SET ns_noc_io_spio_soc_ip.csr 8135 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_C_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_C_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_C_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_C_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_C_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_C_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_C_SET ns_noc_io_spio_soc_ip.csr 8146 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_D_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_D_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_D_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_D_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_D_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_D_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L8_D_SET ns_noc_io_spio_soc_ip.csr 8157 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_A_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_A_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_A_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_A_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_A_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_A_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_A_SET ns_noc_io_spio_soc_ip.csr 8168 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_B_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_B_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_B_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_B_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_B_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_B_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_B_SET ns_noc_io_spio_soc_ip.csr 8179 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_C_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_C_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_C_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_C_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_C_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_C_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_C_SET ns_noc_io_spio_soc_ip.csr 8190 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_D_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_D_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_D_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_D_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_D_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_D_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L9_D_SET ns_noc_io_spio_soc_ip.csr 8201 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_A_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_A_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_A_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_A_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_A_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_A_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_A_SET ns_noc_io_spio_soc_ip.csr 8212 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_B_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_B_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_B_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_B_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_B_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_B_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_B_SET ns_noc_io_spio_soc_ip.csr 8223 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_C_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_C_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_C_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_C_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_C_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_C_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_C_SET ns_noc_io_spio_soc_ip.csr 8234 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_D_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_D_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_D_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_D_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_D_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_D_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L10_D_SET ns_noc_io_spio_soc_ip.csr 8245 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_A_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_A_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_A_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_A_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_A_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_A_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_A_SET ns_noc_io_spio_soc_ip.csr 8256 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_B_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_B_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_B_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_B_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_B_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_B_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_B_SET ns_noc_io_spio_soc_ip.csr 8267 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_C_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_C_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_C_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_C_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_C_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_C_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_C_SET ns_noc_io_spio_soc_ip.csr 8278 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_D_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_D_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_D_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_D_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_D_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_D_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L11_D_SET ns_noc_io_spio_soc_ip.csr 8289 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_A_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_A_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_A_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_A_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_A_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_A_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_A_SET ns_noc_io_spio_soc_ip.csr 8300 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_B_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_B_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_B_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_B_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_B_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_B_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_B_SET ns_noc_io_spio_soc_ip.csr 8311 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_C_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_C_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_C_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_C_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_C_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_C_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_C_SET ns_noc_io_spio_soc_ip.csr 8322 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_D_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_D_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_D_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_D_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_D_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_D_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L12_D_SET ns_noc_io_spio_soc_ip.csr 8333 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_A_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_A_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_A_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_A_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_A_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_A_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_A_SET ns_noc_io_spio_soc_ip.csr 8344 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_B_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_B_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_B_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_B_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_B_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_B_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_B_SET ns_noc_io_spio_soc_ip.csr 8355 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_C_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_C_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_C_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_C_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_C_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_C_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_C_SET ns_noc_io_spio_soc_ip.csr 8366 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_D_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_D_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_D_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_D_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_D_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_D_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L13_D_SET ns_noc_io_spio_soc_ip.csr 8377 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_A_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_A_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_A_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_A_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_A_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_A_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_A_SET ns_noc_io_spio_soc_ip.csr 8388 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_B_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_B_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_B_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_B_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_B_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_B_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_B_SET ns_noc_io_spio_soc_ip.csr 8399 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_C_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_C_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_C_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_C_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_C_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_C_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_C_SET ns_noc_io_spio_soc_ip.csr 8410 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_D_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_D_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_D_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_D_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_D_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_D_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L14_D_SET ns_noc_io_spio_soc_ip.csr 8421 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_A_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_A_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_A_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_A_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_A_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_A_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_A_SET ns_noc_io_spio_soc_ip.csr 8432 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_B_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_B_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_B_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_B_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_B_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_B_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_B_SET ns_noc_io_spio_soc_ip.csr 8443 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_C_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_C_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_C_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_C_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_C_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_C_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_C_SET ns_noc_io_spio_soc_ip.csr 8454 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_D_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_D_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_D_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_D_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_D_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_D_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTUS_1_L15_D_SET ns_noc_io_spio_soc_ip.csr 8465 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register spio_noc.bridge_rbm_s_4_1_btrl_0 bridge_rbm_s_4_1_btrl_0 SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 8542 rbm_s register btrl_0 0x7080 R 0x00000000 Spio_noc_bridge_rbm_s_4_1_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_WT_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_WT_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_WT_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_WT_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_WT_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_WT_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_WT_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_WT_SET ns_noc_io_spio_soc_ip.csr 8490 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_RESV_15_12_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_RESV_15_12_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_RESV_15_12_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_RESV_15_12_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_RESV_15_12_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 8501 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_CNT_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_CNT_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_CNT_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_CNT_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_CNT_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_CNT_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_CNT_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_CNT_SET ns_noc_io_spio_soc_ip.csr 8516 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_EN_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_EN_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_EN_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_EN_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_EN_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_EN_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_EN_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_EN_SET ns_noc_io_spio_soc_ip.csr 8530 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_UNSD_31_21_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_UNSD_31_21_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_UNSD_31_21_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_UNSD_31_21_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_0_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 8541 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_rbm_s_4_1_btrl_1 bridge_rbm_s_4_1_btrl_1 SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 8618 rbm_s register btrl_1 0x7088 R 0x00000000 Spio_noc_bridge_rbm_s_4_1_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_WT_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_WT_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_WT_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_WT_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_WT_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_WT_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_WT_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_WT_SET ns_noc_io_spio_soc_ip.csr 8566 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_RESV_15_12_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_RESV_15_12_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_RESV_15_12_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_RESV_15_12_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_RESV_15_12_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 8577 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_CNT_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_CNT_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_CNT_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_CNT_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_CNT_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_CNT_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_CNT_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_CNT_SET ns_noc_io_spio_soc_ip.csr 8592 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_EN_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_EN_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_EN_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_EN_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_EN_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_EN_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_EN_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_EN_SET ns_noc_io_spio_soc_ip.csr 8606 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_UNSD_31_21_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_UNSD_31_21_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_UNSD_31_21_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_UNSD_31_21_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_1_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 8617 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_rbm_s_4_1_btrl_2 bridge_rbm_s_4_1_btrl_2 SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 8694 rbm_s register btrl_2 0x7090 R 0x00000000 Spio_noc_bridge_rbm_s_4_1_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_WT_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_WT_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_WT_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_WT_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_WT_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_WT_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_WT_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_WT_SET ns_noc_io_spio_soc_ip.csr 8642 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_RESV_15_12_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_RESV_15_12_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_RESV_15_12_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_RESV_15_12_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_RESV_15_12_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 8653 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_CNT_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_CNT_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_CNT_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_CNT_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_CNT_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_CNT_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_CNT_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_CNT_SET ns_noc_io_spio_soc_ip.csr 8668 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_EN_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_EN_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_EN_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_EN_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_EN_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_EN_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_EN_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_EN_SET ns_noc_io_spio_soc_ip.csr 8682 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_UNSD_31_21_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_UNSD_31_21_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_UNSD_31_21_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_UNSD_31_21_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_2_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 8693 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_rbm_s_4_1_btrl_3 bridge_rbm_s_4_1_btrl_3 SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 8770 rbm_s register btrl_3 0x7098 R 0x00000000 Spio_noc_bridge_rbm_s_4_1_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_WT_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_WT_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_WT_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_WT_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_WT_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_WT_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_WT_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_WT_SET ns_noc_io_spio_soc_ip.csr 8718 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_RESV_15_12_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_RESV_15_12_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_RESV_15_12_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_RESV_15_12_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_RESV_15_12_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 8729 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_CNT_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_CNT_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_CNT_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_CNT_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_CNT_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_CNT_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_CNT_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_CNT_SET ns_noc_io_spio_soc_ip.csr 8744 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_EN_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_EN_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_EN_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_EN_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_EN_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_EN_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_EN_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_EN_SET ns_noc_io_spio_soc_ip.csr 8758 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_UNSD_31_21_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_UNSD_31_21_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_UNSD_31_21_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_UNSD_31_21_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTRL_3_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 8769 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_rbm_s_4_1_btperr bridge_rbm_s_4_1_btperr SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 8972 rbm_s register btperr 0x70A8 R/W 0x00000000 Spio_noc_bridge_rbm_s_4_1_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L0_SET ns_noc_io_spio_soc_ip.csr 8795 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L1_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L1_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L1_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L1_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L1_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L1_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L1_SET ns_noc_io_spio_soc_ip.csr 8806 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L2_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L2_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L2_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L2_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L2_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L2_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L2_SET ns_noc_io_spio_soc_ip.csr 8817 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L3_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L3_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L3_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L3_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L3_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L3_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L3_SET ns_noc_io_spio_soc_ip.csr 8828 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L4_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L4_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L4_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L4_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L4_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L4_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L4_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L4_SET ns_noc_io_spio_soc_ip.csr 8839 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L5_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L5_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L5_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L5_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L5_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L5_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L5_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L5_SET ns_noc_io_spio_soc_ip.csr 8850 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L6_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L6_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L6_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L6_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L6_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L6_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L6_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L6_SET ns_noc_io_spio_soc_ip.csr 8861 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L7_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L7_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L7_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L7_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L7_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L7_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L7_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L7_SET ns_noc_io_spio_soc_ip.csr 8872 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L8_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L8_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L8_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L8_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L8_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L8_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L8_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L8_SET ns_noc_io_spio_soc_ip.csr 8883 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L9_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L9_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L9_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L9_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L9_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L9_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L9_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L9_SET ns_noc_io_spio_soc_ip.csr 8894 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L10_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L10_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L10_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L10_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L10_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L10_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L10_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L10_SET ns_noc_io_spio_soc_ip.csr 8905 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L11_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L11_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L11_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L11_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L11_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L11_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L11_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L11_SET ns_noc_io_spio_soc_ip.csr 8916 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L12_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L12_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L12_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L12_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L12_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L12_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L12_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L12_SET ns_noc_io_spio_soc_ip.csr 8927 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L13_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L13_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L13_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L13_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L13_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L13_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L13_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L13_SET ns_noc_io_spio_soc_ip.csr 8938 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L14_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L14_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L14_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L14_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L14_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L14_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L14_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L14_SET ns_noc_io_spio_soc_ip.csr 8949 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L15_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L15_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L15_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L15_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L15_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L15_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L15_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_L15_SET ns_noc_io_spio_soc_ip.csr 8960 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_UNSD_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_UNSD_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_UNSD_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_UNSD_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_UNSD_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_UNSD_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERR_UNSD_SET ns_noc_io_spio_soc_ip.csr 8971 UNSD 31 16 0x0000 R register spio_noc.bridge_rbm_s_4_1_btperrm bridge_rbm_s_4_1_btperrm SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 9172 rbm_s register btperrm 0x70B0 R/W 0x00000000 Spio_noc_bridge_rbm_s_4_1_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L0_SET ns_noc_io_spio_soc_ip.csr 8995 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L1_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L1_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L1_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L1_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L1_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L1_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L1_SET ns_noc_io_spio_soc_ip.csr 9006 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L2_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L2_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L2_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L2_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L2_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L2_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L2_SET ns_noc_io_spio_soc_ip.csr 9017 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L3_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L3_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L3_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L3_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L3_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L3_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L3_SET ns_noc_io_spio_soc_ip.csr 9028 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L4_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L4_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L4_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L4_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L4_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L4_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L4_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L4_SET ns_noc_io_spio_soc_ip.csr 9039 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L5_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L5_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L5_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L5_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L5_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L5_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L5_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L5_SET ns_noc_io_spio_soc_ip.csr 9050 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L6_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L6_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L6_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L6_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L6_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L6_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L6_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L6_SET ns_noc_io_spio_soc_ip.csr 9061 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L7_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L7_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L7_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L7_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L7_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L7_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L7_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L7_SET ns_noc_io_spio_soc_ip.csr 9072 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L8_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L8_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L8_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L8_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L8_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L8_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L8_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L8_SET ns_noc_io_spio_soc_ip.csr 9083 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L9_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L9_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L9_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L9_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L9_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L9_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L9_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L9_SET ns_noc_io_spio_soc_ip.csr 9094 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L10_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L10_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L10_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L10_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L10_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L10_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L10_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L10_SET ns_noc_io_spio_soc_ip.csr 9105 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L11_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L11_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L11_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L11_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L11_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L11_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L11_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L11_SET ns_noc_io_spio_soc_ip.csr 9116 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L12_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L12_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L12_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L12_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L12_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L12_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L12_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L12_SET ns_noc_io_spio_soc_ip.csr 9127 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L13_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L13_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L13_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L13_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L13_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L13_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L13_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L13_SET ns_noc_io_spio_soc_ip.csr 9138 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L14_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L14_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L14_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L14_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L14_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L14_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L14_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L14_SET ns_noc_io_spio_soc_ip.csr 9149 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L15_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L15_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L15_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L15_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L15_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L15_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L15_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_L15_SET ns_noc_io_spio_soc_ip.csr 9160 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_UNSD_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_UNSD_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_UNSD_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_UNSD_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_UNSD_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_UNSD_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BTPERRM_UNSD_SET ns_noc_io_spio_soc_ip.csr 9171 UNSD 31 16 0x0000 R register spio_noc.bridge_rbm_s_4_1_rxe bridge_rbm_s_4_1_rxe SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 9280 rbm_s register rxe 0x7120 R/W 0x00000000 Spio_noc_bridge_rbm_s_4_1_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_A_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_A_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_A_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_A_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_A_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_A_GET SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_A_SET ns_noc_io_spio_soc_ip.csr 9200 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_B_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_B_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_B_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_B_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_B_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_B_GET SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_B_SET ns_noc_io_spio_soc_ip.csr 9211 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_C_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_C_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_C_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_C_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_C_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_C_GET SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_C_SET ns_noc_io_spio_soc_ip.csr 9222 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_D_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_D_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_D_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_D_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_D_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_D_GET SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_CRC_OFLW_D_SET ns_noc_io_spio_soc_ip.csr 9233 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_EVC_OFLW_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_EVC_OFLW_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_EVC_OFLW_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_EVC_OFLW_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_EVC_OFLW_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_EVC_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_EVC_OFLW_GET SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_EVC_OFLW_SET ns_noc_io_spio_soc_ip.csr 9245 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 9256 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_EVC1_OFLW_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_EVC1_OFLW_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_EVC1_OFLW_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_EVC1_OFLW_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_EVC1_OFLW_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_EVC1_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_EVC1_OFLW_GET SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_EVC1_OFLW_SET ns_noc_io_spio_soc_ip.csr 9268 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_UNSD_31_7_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_UNSD_31_7_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_UNSD_31_7_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_UNSD_31_7_GET SPIO_NOC_BRIDGE_RBM_S_4_1_RXE_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 9279 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_rbm_s_4_1_rxem bridge_rbm_s_4_1_rxem SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 9352 rbm_s register rxem 0x7128 R/W 0x00000050 Spio_noc_bridge_rbm_s_4_1_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_UNSD_3_0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_UNSD_3_0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_UNSD_3_0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_UNSD_3_0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_UNSD_3_0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_UNSD_3_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_UNSD_3_0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_UNSD_3_0_SET ns_noc_io_spio_soc_ip.csr 9301 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_EVC_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_EVC_OFLW_MASK_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_EVC_OFLW_MASK_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_EVC_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_EVC_OFLW_MASK_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_EVC_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_EVC_OFLW_MASK_GET SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_EVC_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 9315 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 9326 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_EVC1_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_EVC1_OFLW_MASK_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_EVC1_OFLW_MASK_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_EVC1_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_EVC1_OFLW_MASK_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_EVC1_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_EVC1_OFLW_MASK_GET SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 9340 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_UNSD_31_7_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_UNSD_31_7_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_UNSD_31_7_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_UNSD_31_7_GET SPIO_NOC_BRIDGE_RBM_S_4_1_RXEM_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 9351 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_rbm_s_4_1_brs_0 bridge_rbm_s_4_1_brs_0 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 9626 rbm_s register brs_0 0x7130 R 0x00000000 Spio_noc_bridge_rbm_s_4_1_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 9376 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_0_SET ns_noc_io_spio_soc_ip.csr 9387 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_0_SET ns_noc_io_spio_soc_ip.csr 9398 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_0_SET ns_noc_io_spio_soc_ip.csr 9409 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_0_SET ns_noc_io_spio_soc_ip.csr 9420 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_7_6_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_7_6_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_7_6_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_7_6_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 9430 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_1_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_1_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_1_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_1_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_1_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_1_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 9441 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_1_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_1_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_1_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_1_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_1_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_1_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_1_SET ns_noc_io_spio_soc_ip.csr 9452 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_1_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_1_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_1_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_1_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_1_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_1_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_1_SET ns_noc_io_spio_soc_ip.csr 9463 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_1_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_1_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_1_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_1_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_1_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_1_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_1_SET ns_noc_io_spio_soc_ip.csr 9474 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_1_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_1_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_1_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_1_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_1_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_1_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_1_SET ns_noc_io_spio_soc_ip.csr 9485 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_15_14_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_15_14_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_15_14_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_15_14_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 9495 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_2_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_2_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_2_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_2_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_2_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_2_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 9506 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_2_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_2_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_2_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_2_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_2_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_2_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_2_SET ns_noc_io_spio_soc_ip.csr 9517 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_2_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_2_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_2_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_2_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_2_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_2_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_2_SET ns_noc_io_spio_soc_ip.csr 9528 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_2_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_2_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_2_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_2_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_2_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_2_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_2_SET ns_noc_io_spio_soc_ip.csr 9539 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_2_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_2_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_2_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_2_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_2_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_2_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_2_SET ns_noc_io_spio_soc_ip.csr 9550 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_23_22_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_23_22_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_23_22_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_23_22_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 9560 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_3_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_3_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_3_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_3_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_3_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_3_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 9571 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_3_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_3_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_3_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_3_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_3_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_3_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_V_3_SET ns_noc_io_spio_soc_ip.csr 9582 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_3_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_3_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_3_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_3_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_3_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_3_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_S_3_SET ns_noc_io_spio_soc_ip.csr 9593 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_3_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_3_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_3_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_3_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_3_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_3_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_B_3_SET ns_noc_io_spio_soc_ip.csr 9604 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_3_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_3_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_3_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_3_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_3_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_3_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_F_3_SET ns_noc_io_spio_soc_ip.csr 9615 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_31_30_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_31_30_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_31_30_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_31_30_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_0_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 9625 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_rbm_s_4_1_brs_1 bridge_rbm_s_4_1_brs_1 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 9900 rbm_s register brs_1 0x7138 R 0x00000000 Spio_noc_bridge_rbm_s_4_1_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 9650 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_0_SET ns_noc_io_spio_soc_ip.csr 9661 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_0_SET ns_noc_io_spio_soc_ip.csr 9672 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_0_SET ns_noc_io_spio_soc_ip.csr 9683 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_0_SET ns_noc_io_spio_soc_ip.csr 9694 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_7_6_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_7_6_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_7_6_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_7_6_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 9704 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_1_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_1_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_1_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_1_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_1_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_1_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 9715 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_1_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_1_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_1_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_1_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_1_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_1_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_1_SET ns_noc_io_spio_soc_ip.csr 9726 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_1_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_1_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_1_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_1_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_1_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_1_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_1_SET ns_noc_io_spio_soc_ip.csr 9737 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_1_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_1_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_1_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_1_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_1_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_1_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_1_SET ns_noc_io_spio_soc_ip.csr 9748 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_1_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_1_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_1_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_1_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_1_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_1_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_1_SET ns_noc_io_spio_soc_ip.csr 9759 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_15_14_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_15_14_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_15_14_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_15_14_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 9769 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_2_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_2_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_2_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_2_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_2_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_2_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 9780 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_2_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_2_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_2_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_2_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_2_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_2_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_2_SET ns_noc_io_spio_soc_ip.csr 9791 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_2_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_2_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_2_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_2_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_2_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_2_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_2_SET ns_noc_io_spio_soc_ip.csr 9802 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_2_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_2_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_2_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_2_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_2_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_2_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_2_SET ns_noc_io_spio_soc_ip.csr 9813 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_2_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_2_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_2_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_2_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_2_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_2_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_2_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_2_SET ns_noc_io_spio_soc_ip.csr 9824 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_23_22_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_23_22_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_23_22_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_23_22_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 9834 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_3_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_3_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_3_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_3_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_3_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_3_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 9845 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_3_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_3_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_3_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_3_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_3_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_3_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_V_3_SET ns_noc_io_spio_soc_ip.csr 9856 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_3_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_3_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_3_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_3_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_3_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_3_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_S_3_SET ns_noc_io_spio_soc_ip.csr 9867 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_3_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_3_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_3_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_3_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_3_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_3_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_B_3_SET ns_noc_io_spio_soc_ip.csr 9878 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_3_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_3_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_3_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_3_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_3_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_3_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_3_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_F_3_SET ns_noc_io_spio_soc_ip.csr 9889 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_31_30_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_31_30_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_31_30_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_31_30_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRS_1_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 9899 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_rbm_s_4_1_brus bridge_rbm_s_4_1_brus SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 9969 rbm_s register brus 0x71B0 R 0x00000000 Spio_noc_bridge_rbm_s_4_1_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_A_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_A_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_A_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_A_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_A_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_A_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_A_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_A_SET ns_noc_io_spio_soc_ip.csr 9925 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_B_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_B_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_B_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_B_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_B_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_B_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_B_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_B_SET ns_noc_io_spio_soc_ip.csr 9936 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_C_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_C_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_C_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_C_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_C_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_C_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_C_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_C_SET ns_noc_io_spio_soc_ip.csr 9947 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_D_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_D_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_D_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_D_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_D_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_D_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_D_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_V_D_SET ns_noc_io_spio_soc_ip.csr 9958 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_UNSD_31_4_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_UNSD_31_4_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_UNSD_31_4_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_UNSD_31_4_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_UNSD_31_4_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_UNSD_31_4_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_UNSD_31_4_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRUS_UNSD_31_4_SET ns_noc_io_spio_soc_ip.csr 9968 UNSD_31_4 31 4 0x0000000 R register spio_noc.bridge_rbm_s_4_1_brperr0 bridge_rbm_s_4_1_brperr0 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 10197 rbm_s register brperr0 0x71D0 R/W 0x0000000000000000 Spio_noc_bridge_rbm_s_4_1_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_D0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_D0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_D0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_D0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_D0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_D0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_D0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_D0_SET ns_noc_io_spio_soc_ip.csr 10007 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_DC0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_DC0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_DC0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_DC0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_DC0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_DC0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_DC0_SET ns_noc_io_spio_soc_ip.csr 10018 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SB0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SB0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SB0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SB0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SB0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SB0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SB0_SET ns_noc_io_spio_soc_ip.csr 10029 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SBC0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SBC0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SBC0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SBC0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SBC0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SBC0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SBC0_SET ns_noc_io_spio_soc_ip.csr 10041 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_PK0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_PK0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_PK0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_PK0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_PK0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_PK0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_PK0_SET ns_noc_io_spio_soc_ip.csr 10052 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_7_5_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 10063 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_D1_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_D1_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_D1_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_D1_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_D1_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_D1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_D1_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_D1_SET ns_noc_io_spio_soc_ip.csr 10074 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_DC1_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_DC1_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_DC1_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_DC1_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_DC1_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_DC1_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_DC1_SET ns_noc_io_spio_soc_ip.csr 10085 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SB1_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SB1_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SB1_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SB1_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SB1_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SB1_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SB1_SET ns_noc_io_spio_soc_ip.csr 10096 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SBC1_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SBC1_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SBC1_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SBC1_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SBC1_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SBC1_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_SBC1_SET ns_noc_io_spio_soc_ip.csr 10108 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_PK1_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_PK1_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_PK1_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_PK1_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_PK1_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_PK1_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_PK1_SET ns_noc_io_spio_soc_ip.csr 10119 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_15_13_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 10130 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_23_16_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 10141 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_31_24_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 10152 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_39_32_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 10163 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_47_40_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 10174 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_55_48_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 10185 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_63_56_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 10196 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_rbm_s_4_1_brperr1 bridge_rbm_s_4_1_brperr1 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 10313 rbm_s register brperr1 0x71D8 R 0x0000000000000000 Spio_noc_bridge_rbm_s_4_1_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_7_0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 10235 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_15_8_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 10246 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_23_16_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 10257 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_31_24_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 10268 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_39_32_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 10279 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_47_40_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 10290 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_55_48_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 10301 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_63_56_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERR1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 10312 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_rbm_s_4_1_brperrm0 bridge_rbm_s_4_1_brperrm0 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 10534 rbm_s register brperrm0 0x71E0 R/W 0x0000000000000000 Spio_noc_bridge_rbm_s_4_1_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_D0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_D0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_D0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_D0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_D0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_D0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_D0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_D0_SET ns_noc_io_spio_soc_ip.csr 10340 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_DC0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_DC0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_DC0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_DC0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_DC0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_DC0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_DC0_SET ns_noc_io_spio_soc_ip.csr 10352 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SB0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SB0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SB0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SB0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SB0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SB0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SB0_SET ns_noc_io_spio_soc_ip.csr 10363 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SBC0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SBC0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SBC0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SBC0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SBC0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SBC0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SBC0_SET ns_noc_io_spio_soc_ip.csr 10375 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_PK0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_PK0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_PK0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_PK0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_PK0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_PK0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_PK0_SET ns_noc_io_spio_soc_ip.csr 10387 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_7_5_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 10398 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_D1_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_D1_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_D1_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_D1_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_D1_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_D1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_D1_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_D1_SET ns_noc_io_spio_soc_ip.csr 10409 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_DC1_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_DC1_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_DC1_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_DC1_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_DC1_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_DC1_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_DC1_SET ns_noc_io_spio_soc_ip.csr 10421 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SB1_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SB1_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SB1_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SB1_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SB1_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SB1_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SB1_SET ns_noc_io_spio_soc_ip.csr 10432 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SBC1_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SBC1_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SBC1_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SBC1_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SBC1_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SBC1_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_SBC1_SET ns_noc_io_spio_soc_ip.csr 10444 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_PK1_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_PK1_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_PK1_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_PK1_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_PK1_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_PK1_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_PK1_SET ns_noc_io_spio_soc_ip.csr 10456 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_15_13_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 10467 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_23_16_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 10478 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_31_24_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 10489 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_39_32_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 10500 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_47_40_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 10511 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_55_48_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 10522 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_63_56_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 10533 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_rbm_s_4_1_brperrm1 bridge_rbm_s_4_1_brperrm1 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_BYTE_ADDRESS SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_OFFSET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 10639 rbm_s register brperrm1 0x71E8 R 0x0000000000000000 Spio_noc_bridge_rbm_s_4_1_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_7_0_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 10561 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_15_8_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 10572 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_23_16_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 10583 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_31_24_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 10594 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_39_32_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 10605 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_47_40_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 10616 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_55_48_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 10627 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_63_56_GET SPIO_NOC_BRIDGE_RBM_S_4_1_BRPERRM1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 10638 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_cgc bridge_spio_p00_axi_comm_s_5_7_as_cgc SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGC_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGC_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGC_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 10676 spio_p00_axi_comm_s register as_cgc 0x9C10 R/W 0x0000000000000064 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_as_cgc Programmable intervals used by coarse clock gating logic. This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGC_HYSTERESIS_COUNTER_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGC_HYSTERESIS_COUNTER_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGC_HYSTERESIS_COUNTER_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGC_HYSTERESIS_COUNTER_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGC_HYSTERESIS_COUNTER_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGC_HYSTERESIS_COUNTER_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGC_HYSTERESIS_COUNTER_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_spio_soc_ip.csr 10664 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGC_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGC_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGC_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGC_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGC_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGC_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGC_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGC_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 10675 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_cgo bridge_spio_p00_axi_comm_s_5_7_as_cgo SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGO_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGO_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGO_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGO_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 10711 spio_p00_axi_comm_s register as_cgo 0x9C18 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_as_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the slave bridge. false false false false FPO SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGO_FPO_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGO_FPO_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGO_FPO_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGO_FPO_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGO_FPO_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGO_FPO_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGO_FPO_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGO_FPO_SET ns_noc_io_spio_soc_ip.csr 10699 FPO 1'b1: Clock gating override enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGO_UNSD_63_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGO_UNSD_63_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGO_UNSD_63_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGO_UNSD_63_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGO_UNSD_63_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGO_UNSD_63_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGO_UNSD_63_1_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CGO_UNSD_63_1_SET ns_noc_io_spio_soc_ip.csr 10710 UNSD_63_1 63 1 0x0000000000000000 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_sts bridge_spio_p00_axi_comm_s_5_7_as_sts SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 10785 spio_p00_axi_comm_s register as_sts 0x9D00 R 0x000000000000000c Spio_noc_bridge_spio_p00_axi_comm_s_5_7_as_sts Slave bridge status bits. false false false false WOF SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_WOF_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_WOF_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_WOF_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_WOF_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_WOF_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_WOF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_WOF_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_WOF_SET ns_noc_io_spio_soc_ip.csr 10734 WOF 1'b1: Maximum number of supported write commands are outstanding to the attached slave device awaiting response, no more write commands will be issued to slave till responses are received. 1'b0: Slave device can expect more write commands from NoC 0 0 0x0 R ROF SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_ROF_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_ROF_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_ROF_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_ROF_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_ROF_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_ROF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_ROF_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_ROF_SET ns_noc_io_spio_soc_ip.csr 10750 ROF 1'b1: Maximum number of supported read commands are outstanding to the attached slave device awaiting response, no more read commands will be issued to slave till responses are received. 1'b0: Slave bridge can accept more read commands from the NoC 1 1 0x0 R WOE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_WOE_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_WOE_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_WOE_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_WOE_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_WOE_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_WOE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_WOE_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_WOE_SET ns_noc_io_spio_soc_ip.csr 10762 WOE 1'b1: There are no write commands outstanding to the attached slave device 2 2 0x1 R ROE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_ROE_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_ROE_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_ROE_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_ROE_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_ROE_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_ROE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_ROE_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_ROE_SET ns_noc_io_spio_soc_ip.csr 10774 ROE 1'b1: There are no read commands outstanding to the attached slave device 3 3 0x1 R UNSD_63_4 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_UNSD_63_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_UNSD_63_4_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_UNSD_63_4_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_UNSD_63_4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_UNSD_63_4_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_UNSD_63_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_UNSD_63_4_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_STS_UNSD_63_4_SET ns_noc_io_spio_soc_ip.csr 10784 UNSD_63_4 63 4 0x000000000000000 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_bridge_id bridge_spio_p00_axi_comm_s_5_7_as_bridge_id SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_BRIDGE_ID_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_BRIDGE_ID_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_BRIDGE_ID_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_BRIDGE_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 10815 spio_p00_axi_comm_s register as_bridge_id 0x9D08 R 0x0000000000000005 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_as_bridge_id Unique identifier assigned to the slave bridge. false false false false ID SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_BRIDGE_ID_ID_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_BRIDGE_ID_ID_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_BRIDGE_ID_ID_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_BRIDGE_ID_ID_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_BRIDGE_ID_ID_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_BRIDGE_ID_ID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_BRIDGE_ID_ID_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_BRIDGE_ID_ID_SET ns_noc_io_spio_soc_ip.csr 10804 ID Unique bridge ID 15 0 0x0005 R UNSD_63_16 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_BRIDGE_ID_UNSD_63_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_BRIDGE_ID_UNSD_63_16_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_BRIDGE_ID_UNSD_63_16_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_BRIDGE_ID_UNSD_63_16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_BRIDGE_ID_UNSD_63_16_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_BRIDGE_ID_UNSD_63_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_BRIDGE_ID_UNSD_63_16_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_spio_soc_ip.csr 10814 UNSD_63_16 63 16 0x000000000000 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_err bridge_spio_p00_axi_comm_s_5_7_as_err SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 11168 spio_p00_axi_comm_s register as_err 0x9E00 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_as_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E0_SET ns_noc_io_spio_soc_ip.csr 10836 E0 1'b1: Read decode error response: Decode error response received from slave device for read command 0 0 0x0 R/W E1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E1_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E1_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E1_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E1_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E1_SET ns_noc_io_spio_soc_ip.csr 10848 E1 1'b1: Read slave error response: Slave error response received from slave device for read command 1 1 0x0 R/W E2 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E2_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E2_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E2_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E2_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E2_SET ns_noc_io_spio_soc_ip.csr 10861 E2 1'b1: [FATAL] Unknown read response destination: RID from read response produces a destination which is not present in the routing table 2 2 0x0 R/W E3 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E3_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E3_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E3_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E3_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E3_SET ns_noc_io_spio_soc_ip.csr 10875 E3 1'b1: [FATAL] Interleaved read response: Interleaved read response. This can occur if interleaved read response is received from a slave device for which a de-interleaver was not specified 3 3 0x0 R/W E4 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E4_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E4_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E4_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E4_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E4_SET ns_noc_io_spio_soc_ip.csr 10887 E4 1'b1: Read command modified: A read command which was marked as non-modifiable was modified by the slave bridge 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_UNSD_15_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_UNSD_15_5_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_UNSD_15_5_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_UNSD_15_5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_UNSD_15_5_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_UNSD_15_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_UNSD_15_5_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 10898 UNSD_15_5 15 5 0x000 R E16 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E16_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E16_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E16_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E16_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E16_SET ns_noc_io_spio_soc_ip.csr 10910 E16 1'b1: Write decode error response: Decode error response received from slave device for write command 16 16 0x0 R/W E17 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E17_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E17_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E17_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E17_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E17_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E17_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E17_SET ns_noc_io_spio_soc_ip.csr 10922 E17 1'b1: Write slave error response: Slave error response received from slave device for write command 17 17 0x0 R/W E18 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E18_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E18_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E18_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E18_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E18_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E18_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E18_SET ns_noc_io_spio_soc_ip.csr 10935 E18 1'b1: [FATAL] Unknown write response destination: BID from write response produces a destination which is not present in the routing table 18 18 0x0 R/W E19 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E19_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E19_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E19_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E19_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E19_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E19_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E19_SET ns_noc_io_spio_soc_ip.csr 10947 E19 1'b1: Write command modified: A write command which was marked as non-modifiable was modified by the slave bridge 19 19 0x0 R/W UNSD_31_20 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_UNSD_31_20_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_UNSD_31_20_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_UNSD_31_20_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_UNSD_31_20_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_UNSD_31_20_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_UNSD_31_20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_UNSD_31_20_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_UNSD_31_20_SET ns_noc_io_spio_soc_ip.csr 10958 UNSD_31_20 31 20 0x000 R E32 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E32_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E32_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E32_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E32_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E32_SET ns_noc_io_spio_soc_ip.csr 10970 E32 1'b1: [FATAL] Traffic sent to a noc layer which is power gated 32 32 0x0 R/W E33 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E33_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E33_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E33_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E33_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E33_SET ns_noc_io_spio_soc_ip.csr 10981 E33 1'b1: [FATAL] Parity error in config/status registers 33 33 0x0 R/W E34 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E34_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E34_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E34_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E34_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E34_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E34_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E34_SET ns_noc_io_spio_soc_ip.csr 10992 E34 1'b1: [FATAL] RDATA Parity error 34 34 0x0 R/W E35 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E35_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E35_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E35_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E35_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E35_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E35_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E35_SET ns_noc_io_spio_soc_ip.csr 11003 E35 1'b1: [FATAL] RRESP Parity error 35 35 0x0 R/W E36 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E36_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E36_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E36_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E36_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E36_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E36_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E36_SET ns_noc_io_spio_soc_ip.csr 11014 E36 1'b1: [FATAL] BRESP Parity error 36 36 0x0 R/W E37 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E37_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E37_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E37_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E37_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E37_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E37_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E37_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E37_SET ns_noc_io_spio_soc_ip.csr 11025 E37 1'b1: [FATAL] AC Parity error 37 37 0x0 R/W E38 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E38_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E38_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E38_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E38_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E38_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E38_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E38_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E38_SET ns_noc_io_spio_soc_ip.csr 11036 E38 1'b1: [FATAL] ACADDR Parity error 38 38 0x0 R/W E39 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E39_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E39_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E39_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E39_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E39_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E39_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E39_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E39_SET ns_noc_io_spio_soc_ip.csr 11048 E39 1'b1: [FATAL] R Ch Cmdtbl Parity Err 39 39 0x0 R E40 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E40_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E40_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E40_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E40_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E40_SET ns_noc_io_spio_soc_ip.csr 11060 E40 1'b1: [FATAL] B Ch Cmdtbl Parity Err 40 40 0x0 R E41 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E41_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E41_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E41_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E41_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E41_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E41_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E41_SET ns_noc_io_spio_soc_ip.csr 11072 E41 1'b1: [FATAL] Rx Fifo Parity Err 41 41 0x0 R E42 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E42_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E42_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E42_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E42_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E42_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E42_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E42_SET ns_noc_io_spio_soc_ip.csr 11084 E42 1'b1: [FATAL] CRCD Ch Reorder Buffer Parity Err 42 42 0x0 R E43 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E43_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E43_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E43_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E43_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E43_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E43_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E43_SET ns_noc_io_spio_soc_ip.csr 11096 E43 1'b1: [FATAL] Ack Ch Wack Reorder Buffer Parity Err 43 43 0x0 R E44 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E44_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E44_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E44_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E44_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E44_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E44_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E44_SET ns_noc_io_spio_soc_ip.csr 11108 E44 1'b1: [FATAL] Ack Ch Rack Reorder Buffer Parity Err 44 44 0x0 R E45 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E45_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E45_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E45_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E45_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E45_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E45_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E45_SET ns_noc_io_spio_soc_ip.csr 11120 E45 1'b1: [FATAL] B Ch Drain Fifo Parity Err 45 45 0x0 R E46 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E46_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E46_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E46_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E46_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E46_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E46_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E46_SET ns_noc_io_spio_soc_ip.csr 11132 E46 1'b1: [FATAL] R Ch Flush Fifo Parity Err 46 46 0x0 R E47 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E47_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E47_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E47_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E47_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E47_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E47_SET ns_noc_io_spio_soc_ip.csr 11144 E47 1'b1: [FATAL] R Ch Deinterleaver Cmdtbl Parity Err 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E48_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E48_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E48_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E48_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_E48_SET ns_noc_io_spio_soc_ip.csr 11156 E48 1'b1: [FATAL] R Ch Deinterleaver Data Buffer Parity Err 48 48 0x0 R UNSD_63_49 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_UNSD_63_49_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_UNSD_63_49_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_UNSD_63_49_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_UNSD_63_49_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_UNSD_63_49_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_UNSD_63_49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_UNSD_63_49_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_ERR_UNSD_63_49_SET ns_noc_io_spio_soc_ip.csr 11167 UNSD_63_49 63 49 0x0000 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_intm bridge_spio_p00_axi_comm_s_5_7_as_intm SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 11508 spio_p00_axi_comm_s register as_intm 0x9E40 R/W 0x0000007d000b0013 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_as_intm Interrupt mask register.Individual bit positions match the error bit positions in AS_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M0_SET ns_noc_io_spio_soc_ip.csr 11189 M0 Mask interrupts for read channel 0 0 0x1 R/W M1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M1_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M1_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M1_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M1_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M1_SET ns_noc_io_spio_soc_ip.csr 11200 M1 Mask interrupts for read channel 1 1 0x1 R/W M2 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M2_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M2_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M2_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M2_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M2_SET ns_noc_io_spio_soc_ip.csr 11211 M2 Mask interrupts for read channel 2 2 0x0 R/W M3 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M3_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M3_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M3_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M3_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M3_SET ns_noc_io_spio_soc_ip.csr 11222 M3 Mask interrupts for read channel 3 3 0x0 R/W M4 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M4_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M4_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M4_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M4_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M4_SET ns_noc_io_spio_soc_ip.csr 11233 M4 Mask interrupts for read channel 4 4 0x1 R/W UNSD_15_5 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_UNSD_15_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_UNSD_15_5_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_UNSD_15_5_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_UNSD_15_5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_UNSD_15_5_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_UNSD_15_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_UNSD_15_5_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 11244 UNSD_15_5 15 5 0x000 R M16 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M16_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M16_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M16_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M16_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M16_SET ns_noc_io_spio_soc_ip.csr 11255 M16 Mask interrupts for write channel 16 16 0x1 R/W M17 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M17_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M17_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M17_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M17_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M17_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M17_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M17_SET ns_noc_io_spio_soc_ip.csr 11266 M17 Mask interrupts for write channel 17 17 0x1 R/W M18 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M18_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M18_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M18_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M18_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M18_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M18_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M18_SET ns_noc_io_spio_soc_ip.csr 11277 M18 Mask interrupts for write channel 18 18 0x0 R/W M19 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M19_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M19_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M19_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M19_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M19_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M19_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M19_SET ns_noc_io_spio_soc_ip.csr 11288 M19 Mask interrupts for write channel 19 19 0x1 R/W UNSD_31_20 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_UNSD_31_20_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_UNSD_31_20_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_UNSD_31_20_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_UNSD_31_20_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_UNSD_31_20_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_UNSD_31_20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_UNSD_31_20_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_UNSD_31_20_SET ns_noc_io_spio_soc_ip.csr 11299 UNSD_31_20 31 20 0x000 R M32 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M32_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M32_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M32_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M32_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M32_SET ns_noc_io_spio_soc_ip.csr 11310 M32 Mask interrupt on traffic to PG layer 32 32 0x1 R/W M33 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M33_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M33_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M33_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M33_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M33_SET ns_noc_io_spio_soc_ip.csr 11321 M33 Mask interrupt on csr parity errors 33 33 0x0 R/W M34 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M34_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M34_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M34_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M34_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M34_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M34_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M34_SET ns_noc_io_spio_soc_ip.csr 11332 M34 RDATA parity interrupt Mask 34 34 0x1 R/W M35 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M35_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M35_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M35_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M35_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M35_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M35_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M35_SET ns_noc_io_spio_soc_ip.csr 11343 M35 RRESP parity interrupt Mask 35 35 0x1 R/W M36 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M36_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M36_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M36_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M36_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M36_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M36_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M36_SET ns_noc_io_spio_soc_ip.csr 11354 M36 BRESP parity interrupt Mask 36 36 0x1 R/W M37 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M37_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M37_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M37_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M37_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M37_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M37_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M37_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M37_SET ns_noc_io_spio_soc_ip.csr 11365 M37 AC parity interrupt Mask 37 37 0x1 R/W M38 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M38_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M38_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M38_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M38_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M38_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M38_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M38_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_M38_SET ns_noc_io_spio_soc_ip.csr 11376 M38 ACADDR parity interrupt Mask 38 38 0x1 R/W E39 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E39_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E39_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E39_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E39_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E39_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E39_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E39_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E39_SET ns_noc_io_spio_soc_ip.csr 11388 E39 1'b1: R Ch Cmdtbl Parity Err Intr Mask 39 39 0x0 R E40 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E40_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E40_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E40_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E40_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E40_SET ns_noc_io_spio_soc_ip.csr 11400 E40 1'b1: B Ch Cmdtbl Parity Err Intr Mask 40 40 0x0 R E41 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E41_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E41_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E41_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E41_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E41_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E41_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E41_SET ns_noc_io_spio_soc_ip.csr 11412 E41 1'b1: Rx Fifo Parity Err Intr Mask 41 41 0x0 R E42 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E42_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E42_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E42_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E42_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E42_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E42_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E42_SET ns_noc_io_spio_soc_ip.csr 11424 E42 1'b1: CRCD Ch Reorder Buffer Parity Err Intr Mask 42 42 0x0 R E43 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E43_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E43_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E43_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E43_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E43_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E43_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E43_SET ns_noc_io_spio_soc_ip.csr 11436 E43 1'b1: Ack Ch Wack Reorder Buffer Parity Err IntrMask 43 43 0x0 R E44 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E44_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E44_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E44_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E44_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E44_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E44_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E44_SET ns_noc_io_spio_soc_ip.csr 11448 E44 1'b1: Ack Ch Rack Reorder Buffer Parity Err Intr Mask 44 44 0x0 R E45 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E45_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E45_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E45_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E45_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E45_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E45_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E45_SET ns_noc_io_spio_soc_ip.csr 11460 E45 1'b1: B Ch Drain Fifo Parity Err Intr Mask 45 45 0x0 R E46 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E46_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E46_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E46_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E46_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E46_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E46_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E46_SET ns_noc_io_spio_soc_ip.csr 11472 E46 1'b1: R Ch Flush Fifo Parity Err Intr Mask 46 46 0x0 R E47 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E47_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E47_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E47_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E47_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E47_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E47_SET ns_noc_io_spio_soc_ip.csr 11484 E47 1'b1: R Ch Deinterleaver Cmdtbl Parity Err Intr Mask 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E48_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E48_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E48_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E48_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_E48_SET ns_noc_io_spio_soc_ip.csr 11496 E48 1'b1: R Ch Deinterleaver Data Buffer Parity Err Intr Mask 48 48 0x0 R UNSD_63_49 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_UNSD_63_49_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_UNSD_63_49_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_UNSD_63_49_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_UNSD_63_49_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_UNSD_63_49_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_UNSD_63_49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_UNSD_63_49_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_INTM_UNSD_63_49_SET ns_noc_io_spio_soc_ip.csr 11507 UNSD_63_49 63 49 0x0000 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_ccmd bridge_spio_p00_axi_comm_s_5_7_as_ccmd SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 11583 spio_p00_axi_comm_s register as_ccmd 0x9F00 R/W 0x0000000003000000 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_as_ccmd Not applicable for current release. false false false false UNSD_23_0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_UNSD_23_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_UNSD_23_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_UNSD_23_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_UNSD_23_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_UNSD_23_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_UNSD_23_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_UNSD_23_0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_UNSD_23_0_SET ns_noc_io_spio_soc_ip.csr 11526 UNSD_23_0 23 0 0x000000 R rdy SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_RDY_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_RDY_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_RDY_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_RDY_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_RDY_SET ns_noc_io_spio_soc_ip.csr 11537 rdy 1'b1: Ready 24 24 0x1 R/W val SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_VAL_SET ns_noc_io_spio_soc_ip.csr 11548 val 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_UNSD_27_26_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_UNSD_27_26_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_UNSD_27_26_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_UNSD_27_26_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_UNSD_27_26_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_UNSD_27_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_UNSD_27_26_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_UNSD_27_26_SET ns_noc_io_spio_soc_ip.csr 11559 UNSD_27_26 27 26 0x0 R intfid SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_INTFID_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_INTFID_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_INTFID_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_INTFID_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_INTFID_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_INTFID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_INTFID_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_INTFID_SET ns_noc_io_spio_soc_ip.csr 11571 intfid 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_63_31 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_UNSD_63_31_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_UNSD_63_31_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_UNSD_63_31_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_UNSD_63_31_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_UNSD_63_31_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_UNSD_63_31_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_UNSD_63_31_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMD_UNSD_63_31_SET ns_noc_io_spio_soc_ip.csr 11582 UNSD_63_31 63 31 0x000000000 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_ccmdmsk bridge_spio_p00_axi_comm_s_5_7_as_ccmdmsk SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 11635 spio_p00_axi_comm_s register as_ccmdmsk 0x9F08 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_as_ccmdmsk Not applicable for current release. false false false false UNSD_23_0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_UNSD_23_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_UNSD_23_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_UNSD_23_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_UNSD_23_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_UNSD_23_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_UNSD_23_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_UNSD_23_0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_UNSD_23_0_SET ns_noc_io_spio_soc_ip.csr 11601 UNSD_23_0 23 0 0x000000 R rdy SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_RDY_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_RDY_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_RDY_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_RDY_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_RDY_SET ns_noc_io_spio_soc_ip.csr 11612 rdy 1'b1: Ready 24 24 0x0 R/W val SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_VAL_SET ns_noc_io_spio_soc_ip.csr 11623 val 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_UNSD_63_26_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_UNSD_63_26_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_UNSD_63_26_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_UNSD_63_26_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_UNSD_63_26_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_UNSD_63_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_UNSD_63_26_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CCMDMSK_UNSD_63_26_SET ns_noc_io_spio_soc_ip.csr 11634 UNSD_63_26 63 26 0x0000000000 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_cntr bridge_spio_p00_axi_comm_s_5_7_as_cntr SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CNTR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CNTR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CNTR_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CNTR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 11665 spio_p00_axi_comm_s register as_cntr 0x9F10 R 0x0000000000000000 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_as_cntr Not applicable for current release. false false false false CNTR SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CNTR_CNTR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CNTR_CNTR_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CNTR_CNTR_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CNTR_CNTR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CNTR_CNTR_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CNTR_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CNTR_CNTR_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CNTR_CNTR_SET ns_noc_io_spio_soc_ip.csr 11654 CNTR Counter 31 0 0x00000000 R UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CNTR_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CNTR_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CNTR_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CNTR_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CNTR_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CNTR_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CNTR_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_CNTR_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 11664 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_arovrd bridge_spio_p00_axi_comm_s_5_7_as_arovrd SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 11778 spio_p00_axi_comm_s register as_arovrd 0x9F18 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_as_arovrd AR Overrides. false false false false arcache_val SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 11683 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 11696 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 11707 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 11718 UNSD_11_11 11 11 0x0 R arprot_enb SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 11731 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 11742 UNSD_15_15 15 15 0x0 R arqos_val SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 11753 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_ARQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 11766 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AROVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 11777 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_as_awovrd bridge_spio_p00_axi_comm_s_5_7_as_awovrd SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 11891 spio_p00_axi_comm_s register as_awovrd 0x9F20 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_as_awovrd AW Overrides. false false false false awcache_val SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 11796 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 11809 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 11820 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 11831 UNSD_11_11 11 11 0x0 R awprot_enb SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 11844 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 11855 UNSD_15_15 15 15 0x0 R awqos_val SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 11866 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_AWQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 11879 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_AS_AWOVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 11890 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_p_0 bridge_spio_p00_axi_comm_s_5_7_p_0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 11956 spio_p00_axi_comm_s register p_0 0xB000 R/W 0x00000003 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_0_SET ns_noc_io_spio_soc_ip.csr 11919 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_1_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_1_SET ns_noc_io_spio_soc_ip.csr 11931 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_2_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_2_SET ns_noc_io_spio_soc_ip.csr 11943 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_3_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_0_WT_QOS_3_SET ns_noc_io_spio_soc_ip.csr 11955 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_p_1 bridge_spio_p00_axi_comm_s_5_7_p_1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 12022 spio_p00_axi_comm_s register p_1 0xB008 R 0x00000000 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_4_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_4_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_4_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_4_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_4_SET ns_noc_io_spio_soc_ip.csr 11985 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_5_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_5_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_5_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_5_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_5_SET ns_noc_io_spio_soc_ip.csr 11997 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_6_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_6_SET ns_noc_io_spio_soc_ip.csr 12009 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_7_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_7_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_7_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_7_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_1_WT_QOS_7_SET ns_noc_io_spio_soc_ip.csr 12021 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_p_2 bridge_spio_p00_axi_comm_s_5_7_p_2 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 12088 spio_p00_axi_comm_s register p_2 0xB010 R 0x00000000 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_8_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_8_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_8_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_8_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_8_SET ns_noc_io_spio_soc_ip.csr 12051 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_9_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_9_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_9_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_9_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_9_SET ns_noc_io_spio_soc_ip.csr 12063 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_10_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_10_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_10_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_10_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_10_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_10_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_10_SET ns_noc_io_spio_soc_ip.csr 12075 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_11_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_11_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_11_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_11_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_11_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_2_WT_QOS_11_SET ns_noc_io_spio_soc_ip.csr 12087 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_p_3 bridge_spio_p00_axi_comm_s_5_7_p_3 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 12154 spio_p00_axi_comm_s register p_3 0xB018 R 0x00000000 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_12_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_12_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_12_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_12_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_12_SET ns_noc_io_spio_soc_ip.csr 12117 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_13_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_13_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_13_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_13_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_13_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_13_SET ns_noc_io_spio_soc_ip.csr 12129 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_14_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_14_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_14_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_14_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_14_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_14_SET ns_noc_io_spio_soc_ip.csr 12141 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_15_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_15_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_15_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_15_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_15_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_P_3_WT_QOS_15_SET ns_noc_io_spio_soc_ip.csr 12153 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_txe bridge_spio_p00_axi_comm_s_5_7_txe SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 12300 spio_p00_axi_comm_s register txe 0xB040 R/W 0x00000000 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_TRANS_WITHOUT_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_TRANS_WITHOUT_SOP_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_TRANS_WITHOUT_SOP_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_TRANS_WITHOUT_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_TRANS_WITHOUT_SOP_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_TRANS_WITHOUT_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_TRANS_WITHOUT_SOP_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_spio_soc_ip.csr 12181 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_SOP_AFTER_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_SOP_AFTER_SOP_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_SOP_AFTER_SOP_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_SOP_AFTER_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_SOP_AFTER_SOP_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_SOP_AFTER_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_SOP_AFTER_SOP_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_SOP_AFTER_SOP_SET ns_noc_io_spio_soc_ip.csr 12193 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 12208 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 12221 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_A_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_spio_soc_ip.csr 12235 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_B_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_spio_soc_ip.csr 12249 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_C_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_spio_soc_ip.csr 12263 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_D_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_spio_soc_ip.csr 12277 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 12288 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXE_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 12299 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_txem bridge_spio_p00_axi_comm_s_5_7_txem SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 12379 spio_p00_axi_comm_s register txem 0xB048 R/W 0x00000008 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_UNSD_1_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_UNSD_1_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_UNSD_1_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_UNSD_1_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_UNSD_1_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_UNSD_1_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_UNSD_1_0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_UNSD_1_0_SET ns_noc_io_spio_soc_ip.csr 12323 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 12334 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 12345 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_UNSD_7_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_UNSD_7_4_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_UNSD_7_4_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_UNSD_7_4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_UNSD_7_4_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_UNSD_7_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_UNSD_7_4_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_UNSD_7_4_SET ns_noc_io_spio_soc_ip.csr 12356 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 12367 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_TXEM_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 12378 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_btus_0 bridge_spio_p00_axi_comm_s_5_7_btus_0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 12747 spio_p00_axi_comm_s register btus_0 0xB058 R 0x00000000 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_A_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_A_SET ns_noc_io_spio_soc_ip.csr 12405 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_B_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_B_SET ns_noc_io_spio_soc_ip.csr 12416 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_C_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_C_SET ns_noc_io_spio_soc_ip.csr 12427 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_D_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L0_D_SET ns_noc_io_spio_soc_ip.csr 12438 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_A_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_A_SET ns_noc_io_spio_soc_ip.csr 12449 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_B_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_B_SET ns_noc_io_spio_soc_ip.csr 12460 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_C_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_C_SET ns_noc_io_spio_soc_ip.csr 12471 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_D_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L1_D_SET ns_noc_io_spio_soc_ip.csr 12482 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_A_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_A_SET ns_noc_io_spio_soc_ip.csr 12493 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_B_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_B_SET ns_noc_io_spio_soc_ip.csr 12504 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_C_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_C_SET ns_noc_io_spio_soc_ip.csr 12515 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_D_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L2_D_SET ns_noc_io_spio_soc_ip.csr 12526 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_A_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_A_SET ns_noc_io_spio_soc_ip.csr 12537 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_B_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_B_SET ns_noc_io_spio_soc_ip.csr 12548 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_C_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_C_SET ns_noc_io_spio_soc_ip.csr 12559 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_D_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L3_D_SET ns_noc_io_spio_soc_ip.csr 12570 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_A_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_A_SET ns_noc_io_spio_soc_ip.csr 12581 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_B_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_B_SET ns_noc_io_spio_soc_ip.csr 12592 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_C_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_C_SET ns_noc_io_spio_soc_ip.csr 12603 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_D_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L4_D_SET ns_noc_io_spio_soc_ip.csr 12614 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_A_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_A_SET ns_noc_io_spio_soc_ip.csr 12625 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_B_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_B_SET ns_noc_io_spio_soc_ip.csr 12636 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_C_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_C_SET ns_noc_io_spio_soc_ip.csr 12647 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_D_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L5_D_SET ns_noc_io_spio_soc_ip.csr 12658 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_A_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_A_SET ns_noc_io_spio_soc_ip.csr 12669 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_B_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_B_SET ns_noc_io_spio_soc_ip.csr 12680 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_C_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_C_SET ns_noc_io_spio_soc_ip.csr 12691 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_D_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L6_D_SET ns_noc_io_spio_soc_ip.csr 12702 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_A_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_A_SET ns_noc_io_spio_soc_ip.csr 12713 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_B_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_B_SET ns_noc_io_spio_soc_ip.csr 12724 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_C_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_C_SET ns_noc_io_spio_soc_ip.csr 12735 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_D_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_0_L7_D_SET ns_noc_io_spio_soc_ip.csr 12746 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_btus_1 bridge_spio_p00_axi_comm_s_5_7_btus_1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 13115 spio_p00_axi_comm_s register btus_1 0xB060 R 0x00000000 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_A_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_A_SET ns_noc_io_spio_soc_ip.csr 12773 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_B_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_B_SET ns_noc_io_spio_soc_ip.csr 12784 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_C_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_C_SET ns_noc_io_spio_soc_ip.csr 12795 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_D_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L8_D_SET ns_noc_io_spio_soc_ip.csr 12806 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_A_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_A_SET ns_noc_io_spio_soc_ip.csr 12817 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_B_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_B_SET ns_noc_io_spio_soc_ip.csr 12828 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_C_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_C_SET ns_noc_io_spio_soc_ip.csr 12839 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_D_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L9_D_SET ns_noc_io_spio_soc_ip.csr 12850 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_A_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_A_SET ns_noc_io_spio_soc_ip.csr 12861 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_B_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_B_SET ns_noc_io_spio_soc_ip.csr 12872 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_C_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_C_SET ns_noc_io_spio_soc_ip.csr 12883 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_D_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L10_D_SET ns_noc_io_spio_soc_ip.csr 12894 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_A_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_A_SET ns_noc_io_spio_soc_ip.csr 12905 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_B_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_B_SET ns_noc_io_spio_soc_ip.csr 12916 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_C_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_C_SET ns_noc_io_spio_soc_ip.csr 12927 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_D_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L11_D_SET ns_noc_io_spio_soc_ip.csr 12938 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_A_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_A_SET ns_noc_io_spio_soc_ip.csr 12949 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_B_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_B_SET ns_noc_io_spio_soc_ip.csr 12960 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_C_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_C_SET ns_noc_io_spio_soc_ip.csr 12971 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_D_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L12_D_SET ns_noc_io_spio_soc_ip.csr 12982 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_A_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_A_SET ns_noc_io_spio_soc_ip.csr 12993 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_B_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_B_SET ns_noc_io_spio_soc_ip.csr 13004 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_C_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_C_SET ns_noc_io_spio_soc_ip.csr 13015 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_D_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L13_D_SET ns_noc_io_spio_soc_ip.csr 13026 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_A_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_A_SET ns_noc_io_spio_soc_ip.csr 13037 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_B_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_B_SET ns_noc_io_spio_soc_ip.csr 13048 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_C_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_C_SET ns_noc_io_spio_soc_ip.csr 13059 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_D_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L14_D_SET ns_noc_io_spio_soc_ip.csr 13070 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_A_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_A_SET ns_noc_io_spio_soc_ip.csr 13081 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_B_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_B_SET ns_noc_io_spio_soc_ip.csr 13092 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_C_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_C_SET ns_noc_io_spio_soc_ip.csr 13103 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_D_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTUS_1_L15_D_SET ns_noc_io_spio_soc_ip.csr 13114 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_btrl_0 bridge_spio_p00_axi_comm_s_5_7_btrl_0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 13191 spio_p00_axi_comm_s register btrl_0 0xB080 R 0x00000000 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_WT_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_WT_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_WT_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_WT_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_WT_SET ns_noc_io_spio_soc_ip.csr 13139 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 13150 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_CNT_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_CNT_SET ns_noc_io_spio_soc_ip.csr 13165 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_EN_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_EN_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_EN_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_EN_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_EN_SET ns_noc_io_spio_soc_ip.csr 13179 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_0_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 13190 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_btrl_1 bridge_spio_p00_axi_comm_s_5_7_btrl_1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 13267 spio_p00_axi_comm_s register btrl_1 0xB088 R 0x00000000 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_WT_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_WT_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_WT_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_WT_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_WT_SET ns_noc_io_spio_soc_ip.csr 13215 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 13226 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_CNT_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_CNT_SET ns_noc_io_spio_soc_ip.csr 13241 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_EN_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_EN_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_EN_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_EN_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_EN_SET ns_noc_io_spio_soc_ip.csr 13255 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_1_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 13266 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_btrl_2 bridge_spio_p00_axi_comm_s_5_7_btrl_2 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 13343 spio_p00_axi_comm_s register btrl_2 0xB090 R 0x00000000 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_WT_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_WT_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_WT_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_WT_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_WT_SET ns_noc_io_spio_soc_ip.csr 13291 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 13302 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_CNT_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_CNT_SET ns_noc_io_spio_soc_ip.csr 13317 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_EN_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_EN_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_EN_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_EN_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_EN_SET ns_noc_io_spio_soc_ip.csr 13331 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_2_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 13342 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_btrl_3 bridge_spio_p00_axi_comm_s_5_7_btrl_3 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 13419 spio_p00_axi_comm_s register btrl_3 0xB098 R 0x00000000 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_WT_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_WT_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_WT_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_WT_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_WT_SET ns_noc_io_spio_soc_ip.csr 13367 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 13378 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_CNT_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_CNT_SET ns_noc_io_spio_soc_ip.csr 13393 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_EN_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_EN_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_EN_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_EN_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_EN_SET ns_noc_io_spio_soc_ip.csr 13407 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTRL_3_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 13418 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_btperr bridge_spio_p00_axi_comm_s_5_7_btperr SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 13621 spio_p00_axi_comm_s register btperr 0xB0A8 R/W 0x00000000 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L0_SET ns_noc_io_spio_soc_ip.csr 13444 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L1_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L1_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L1_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L1_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L1_SET ns_noc_io_spio_soc_ip.csr 13455 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L2_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L2_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L2_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L2_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L2_SET ns_noc_io_spio_soc_ip.csr 13466 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L3_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L3_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L3_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L3_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L3_SET ns_noc_io_spio_soc_ip.csr 13477 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L4_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L4_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L4_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L4_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L4_SET ns_noc_io_spio_soc_ip.csr 13488 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L5_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L5_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L5_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L5_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L5_SET ns_noc_io_spio_soc_ip.csr 13499 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L6_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L6_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L6_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L6_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L6_SET ns_noc_io_spio_soc_ip.csr 13510 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L7_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L7_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L7_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L7_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L7_SET ns_noc_io_spio_soc_ip.csr 13521 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L8_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L8_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L8_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L8_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L8_SET ns_noc_io_spio_soc_ip.csr 13532 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L9_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L9_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L9_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L9_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L9_SET ns_noc_io_spio_soc_ip.csr 13543 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L10_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L10_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L10_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L10_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L10_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L10_SET ns_noc_io_spio_soc_ip.csr 13554 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L11_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L11_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L11_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L11_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L11_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L11_SET ns_noc_io_spio_soc_ip.csr 13565 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L12_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L12_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L12_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L12_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L12_SET ns_noc_io_spio_soc_ip.csr 13576 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L13_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L13_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L13_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L13_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L13_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L13_SET ns_noc_io_spio_soc_ip.csr 13587 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L14_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L14_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L14_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L14_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L14_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L14_SET ns_noc_io_spio_soc_ip.csr 13598 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L15_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L15_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L15_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L15_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L15_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_L15_SET ns_noc_io_spio_soc_ip.csr 13609 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_UNSD_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERR_UNSD_SET ns_noc_io_spio_soc_ip.csr 13620 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_btperrm bridge_spio_p00_axi_comm_s_5_7_btperrm SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 13821 spio_p00_axi_comm_s register btperrm 0xB0B0 R/W 0x00000000 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L0_SET ns_noc_io_spio_soc_ip.csr 13644 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L1_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L1_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L1_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L1_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L1_SET ns_noc_io_spio_soc_ip.csr 13655 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L2_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L2_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L2_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L2_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L2_SET ns_noc_io_spio_soc_ip.csr 13666 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L3_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L3_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L3_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L3_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L3_SET ns_noc_io_spio_soc_ip.csr 13677 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L4_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L4_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L4_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L4_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L4_SET ns_noc_io_spio_soc_ip.csr 13688 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L5_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L5_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L5_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L5_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L5_SET ns_noc_io_spio_soc_ip.csr 13699 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L6_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L6_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L6_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L6_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L6_SET ns_noc_io_spio_soc_ip.csr 13710 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L7_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L7_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L7_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L7_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L7_SET ns_noc_io_spio_soc_ip.csr 13721 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L8_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L8_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L8_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L8_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L8_SET ns_noc_io_spio_soc_ip.csr 13732 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L9_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L9_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L9_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L9_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L9_SET ns_noc_io_spio_soc_ip.csr 13743 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L10_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L10_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L10_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L10_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L10_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L10_SET ns_noc_io_spio_soc_ip.csr 13754 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L11_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L11_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L11_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L11_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L11_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L11_SET ns_noc_io_spio_soc_ip.csr 13765 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L12_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L12_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L12_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L12_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L12_SET ns_noc_io_spio_soc_ip.csr 13776 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L13_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L13_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L13_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L13_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L13_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L13_SET ns_noc_io_spio_soc_ip.csr 13787 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L14_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L14_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L14_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L14_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L14_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L14_SET ns_noc_io_spio_soc_ip.csr 13798 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L15_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L15_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L15_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L15_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L15_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_L15_SET ns_noc_io_spio_soc_ip.csr 13809 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_UNSD_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BTPERRM_UNSD_SET ns_noc_io_spio_soc_ip.csr 13820 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_rxe bridge_spio_p00_axi_comm_s_5_7_rxe SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 13929 spio_p00_axi_comm_s register rxe 0xB120 R/W 0x00000000 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_A_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_A_SET ns_noc_io_spio_soc_ip.csr 13849 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_B_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_B_SET ns_noc_io_spio_soc_ip.csr 13860 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_C_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_C_SET ns_noc_io_spio_soc_ip.csr 13871 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_D_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_CRC_OFLW_D_SET ns_noc_io_spio_soc_ip.csr 13882 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_EVC_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_EVC_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_EVC_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_EVC_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_EVC_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_EVC_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_EVC_OFLW_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_EVC_OFLW_SET ns_noc_io_spio_soc_ip.csr 13894 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 13905 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_EVC1_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_EVC1_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_EVC1_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_EVC1_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_EVC1_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_EVC1_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_EVC1_OFLW_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_EVC1_OFLW_SET ns_noc_io_spio_soc_ip.csr 13917 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXE_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 13928 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_rxem bridge_spio_p00_axi_comm_s_5_7_rxem SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 14001 spio_p00_axi_comm_s register rxem 0xB128 R/W 0x00000050 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_UNSD_3_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_UNSD_3_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_UNSD_3_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_UNSD_3_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_UNSD_3_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_UNSD_3_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_UNSD_3_0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_UNSD_3_0_SET ns_noc_io_spio_soc_ip.csr 13950 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_EVC_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_EVC_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_EVC_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_EVC_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_EVC_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_EVC_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_EVC_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_EVC_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 13964 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 13975 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_EVC1_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_EVC1_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_EVC1_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_EVC1_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_EVC1_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_EVC1_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_EVC1_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 13989 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_RXEM_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 14000 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_brs_0 bridge_spio_p00_axi_comm_s_5_7_brs_0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 14275 spio_p00_axi_comm_s register brs_0 0xB130 R 0x00000000 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 14025 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_0_SET ns_noc_io_spio_soc_ip.csr 14036 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_0_SET ns_noc_io_spio_soc_ip.csr 14047 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_0_SET ns_noc_io_spio_soc_ip.csr 14058 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_0_SET ns_noc_io_spio_soc_ip.csr 14069 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 14079 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 14090 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_1_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_1_SET ns_noc_io_spio_soc_ip.csr 14101 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_1_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_1_SET ns_noc_io_spio_soc_ip.csr 14112 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_1_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_1_SET ns_noc_io_spio_soc_ip.csr 14123 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_1_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_1_SET ns_noc_io_spio_soc_ip.csr 14134 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 14144 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 14155 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_2_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_2_SET ns_noc_io_spio_soc_ip.csr 14166 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_2_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_2_SET ns_noc_io_spio_soc_ip.csr 14177 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_2_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_2_SET ns_noc_io_spio_soc_ip.csr 14188 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_2_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_2_SET ns_noc_io_spio_soc_ip.csr 14199 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 14209 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 14220 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_3_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_V_3_SET ns_noc_io_spio_soc_ip.csr 14231 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_3_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_S_3_SET ns_noc_io_spio_soc_ip.csr 14242 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_3_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_B_3_SET ns_noc_io_spio_soc_ip.csr 14253 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_3_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_F_3_SET ns_noc_io_spio_soc_ip.csr 14264 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_0_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 14274 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_brs_1 bridge_spio_p00_axi_comm_s_5_7_brs_1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 14549 spio_p00_axi_comm_s register brs_1 0xB138 R 0x00000000 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 14299 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_0_SET ns_noc_io_spio_soc_ip.csr 14310 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_0_SET ns_noc_io_spio_soc_ip.csr 14321 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_0_SET ns_noc_io_spio_soc_ip.csr 14332 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_0_SET ns_noc_io_spio_soc_ip.csr 14343 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 14353 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 14364 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_1_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_1_SET ns_noc_io_spio_soc_ip.csr 14375 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_1_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_1_SET ns_noc_io_spio_soc_ip.csr 14386 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_1_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_1_SET ns_noc_io_spio_soc_ip.csr 14397 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_1_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_1_SET ns_noc_io_spio_soc_ip.csr 14408 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 14418 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 14429 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_2_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_2_SET ns_noc_io_spio_soc_ip.csr 14440 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_2_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_2_SET ns_noc_io_spio_soc_ip.csr 14451 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_2_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_2_SET ns_noc_io_spio_soc_ip.csr 14462 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_2_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_2_SET ns_noc_io_spio_soc_ip.csr 14473 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 14483 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 14494 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_3_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_V_3_SET ns_noc_io_spio_soc_ip.csr 14505 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_3_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_S_3_SET ns_noc_io_spio_soc_ip.csr 14516 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_3_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_B_3_SET ns_noc_io_spio_soc_ip.csr 14527 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_3_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_F_3_SET ns_noc_io_spio_soc_ip.csr 14538 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRS_1_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 14548 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_brus bridge_spio_p00_axi_comm_s_5_7_brus SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 14618 spio_p00_axi_comm_s register brus 0xB1B0 R 0x00000000 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_A_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_A_SET ns_noc_io_spio_soc_ip.csr 14574 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_B_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_B_SET ns_noc_io_spio_soc_ip.csr 14585 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_C_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_C_SET ns_noc_io_spio_soc_ip.csr 14596 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_D_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_V_D_SET ns_noc_io_spio_soc_ip.csr 14607 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_UNSD_31_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_UNSD_31_4_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_UNSD_31_4_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_UNSD_31_4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_UNSD_31_4_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_UNSD_31_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_UNSD_31_4_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRUS_UNSD_31_4_SET ns_noc_io_spio_soc_ip.csr 14617 UNSD_31_4 31 4 0x0000000 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_brperr0 bridge_spio_p00_axi_comm_s_5_7_brperr0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 14846 spio_p00_axi_comm_s register brperr0 0xB1D0 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_D0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_D0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_D0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_D0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_D0_SET ns_noc_io_spio_soc_ip.csr 14656 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_DC0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_DC0_SET ns_noc_io_spio_soc_ip.csr 14667 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SB0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SB0_SET ns_noc_io_spio_soc_ip.csr 14678 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SBC0_SET ns_noc_io_spio_soc_ip.csr 14690 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_PK0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_PK0_SET ns_noc_io_spio_soc_ip.csr 14701 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 14712 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_D1_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_D1_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_D1_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_D1_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_D1_SET ns_noc_io_spio_soc_ip.csr 14723 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_DC1_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_DC1_SET ns_noc_io_spio_soc_ip.csr 14734 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SB1_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SB1_SET ns_noc_io_spio_soc_ip.csr 14745 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_SBC1_SET ns_noc_io_spio_soc_ip.csr 14757 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_PK1_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_PK1_SET ns_noc_io_spio_soc_ip.csr 14768 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 14779 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 14790 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 14801 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 14812 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 14823 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 14834 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 14845 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_brperr1 bridge_spio_p00_axi_comm_s_5_7_brperr1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 14962 spio_p00_axi_comm_s register brperr1 0xB1D8 R 0x0000000000000000 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 14884 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 14895 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 14906 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 14917 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 14928 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 14939 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 14950 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERR1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 14961 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_brperrm0 bridge_spio_p00_axi_comm_s_5_7_brperrm0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 15183 spio_p00_axi_comm_s register brperrm0 0xB1E0 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_D0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_D0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_D0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_D0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_D0_SET ns_noc_io_spio_soc_ip.csr 14989 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_DC0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_DC0_SET ns_noc_io_spio_soc_ip.csr 15001 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SB0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SB0_SET ns_noc_io_spio_soc_ip.csr 15012 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SBC0_SET ns_noc_io_spio_soc_ip.csr 15024 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_PK0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_PK0_SET ns_noc_io_spio_soc_ip.csr 15036 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 15047 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_D1_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_D1_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_D1_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_D1_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_D1_SET ns_noc_io_spio_soc_ip.csr 15058 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_DC1_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_DC1_SET ns_noc_io_spio_soc_ip.csr 15070 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SB1_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SB1_SET ns_noc_io_spio_soc_ip.csr 15081 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_SBC1_SET ns_noc_io_spio_soc_ip.csr 15093 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_PK1_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_PK1_SET ns_noc_io_spio_soc_ip.csr 15105 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 15116 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 15127 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 15138 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 15149 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 15160 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 15171 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 15182 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p00_axi_comm_s_5_7_brperrm1 bridge_spio_p00_axi_comm_s_5_7_brperrm1 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 15288 spio_p00_axi_comm_s register brperrm1 0xB1E8 R 0x0000000000000000 Spio_noc_bridge_spio_p00_axi_comm_s_5_7_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 15210 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 15221 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 15232 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 15243 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 15254 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 15265 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 15276 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P00_AXI_COMM_S_5_7_BRPERRM1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 15287 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_ahbs_ctl bridge_spio_p00_dma_ahb0_s_6_8_ahbs_ctl SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_CTL_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_CTL_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_CTL_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_CTL_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 15329 spio_p00_dma_ahb0_s register ahbs_ctl 0xC200 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_ahbs_ctl Control Register. false false false false ZEROES SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_CTL_ZEROES_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_CTL_ZEROES_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_CTL_ZEROES_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_CTL_ZEROES_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_CTL_ZEROES_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_CTL_ZEROES_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_CTL_ZEROES_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_CTL_ZEROES_SET ns_noc_io_spio_soc_ip.csr 15304 ZEROES Zeroes 15 0 0x0000 R/W REG SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_CTL_REG_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_CTL_REG_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_CTL_REG_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_CTL_REG_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_CTL_REG_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_CTL_REG_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_CTL_REG_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_CTL_REG_SET ns_noc_io_spio_soc_ip.csr 15317 REG 1'b1: Issue error response on unaligned read address. 1'b0: Issue OK response even if unaligned adress was aligned and issued. 16 16 0x0 R/W UNSD_63_17 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_CTL_UNSD_63_17_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_CTL_UNSD_63_17_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_CTL_UNSD_63_17_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_CTL_UNSD_63_17_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_CTL_UNSD_63_17_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_CTL_UNSD_63_17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_CTL_UNSD_63_17_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_CTL_UNSD_63_17_SET ns_noc_io_spio_soc_ip.csr 15328 UNSD_63_17 63 17 0x000000000000 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_ahbs_sts bridge_spio_p00_dma_ahb0_s_6_8_ahbs_sts SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 15380 spio_p00_dma_ahb0_s register ahbs_sts 0xC208 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_ahbs_sts Status Register. false false false false ZEROES SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_ZEROES_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_ZEROES_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_ZEROES_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_ZEROES_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_ZEROES_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_ZEROES_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_ZEROES_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_ZEROES_SET ns_noc_io_spio_soc_ip.csr 15345 ZEROES Zeroes 15 0 0x0000 R/W WE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_WE_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_WE_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_WE_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_WE_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_WE_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_WE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_WE_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_WE_SET ns_noc_io_spio_soc_ip.csr 15357 WE 1'b1: Unaligned write address (wrt asize)., or partial write strobes (wrt asize) was received. 16 16 0x0 R/W RE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_RE_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_RE_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_RE_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_RE_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_RE_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_RE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_RE_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_RE_SET ns_noc_io_spio_soc_ip.csr 15368 RE 1'b1: Unaligned read address was received. 17 17 0x0 R/W UNSD_63_18 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_UNSD_63_18_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_UNSD_63_18_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_UNSD_63_18_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_UNSD_63_18_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_UNSD_63_18_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_UNSD_63_18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_UNSD_63_18_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_STS_UNSD_63_18_SET ns_noc_io_spio_soc_ip.csr 15379 UNSD_63_18 63 18 0x000000000000 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_ahbs_im bridge_spio_p00_dma_ahb0_s_6_8_ahbs_im SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 15432 spio_p00_dma_ahb0_s register ahbs_im 0xC210 R/W 0x0000000000030000 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_ahbs_im Interrupt Mask Register. false false false false ZEROES SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_ZEROES_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_ZEROES_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_ZEROES_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_ZEROES_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_ZEROES_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_ZEROES_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_ZEROES_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_ZEROES_SET ns_noc_io_spio_soc_ip.csr 15396 ZEROES Zeroes 15 0 0x0000 R/W WEM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_WEM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_WEM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_WEM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_WEM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_WEM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_WEM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_WEM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_WEM_SET ns_noc_io_spio_soc_ip.csr 15408 WEM 1'b1: No interrupt raised on WE. 1'b0: Interrupt raised on WE. 16 16 0x1 R/W REM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_REM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_REM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_REM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_REM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_REM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_REM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_REM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_REM_SET ns_noc_io_spio_soc_ip.csr 15420 REM 1'b1: No interrupt raised on RE. 1'b0: Interrupt raised on RE. 17 17 0x1 R/W UNSD_63_18 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_UNSD_63_18_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_UNSD_63_18_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_UNSD_63_18_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_UNSD_63_18_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_UNSD_63_18_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_UNSD_63_18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_UNSD_63_18_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AHBS_IM_UNSD_63_18_SET ns_noc_io_spio_soc_ip.csr 15431 UNSD_63_18 63 18 0x000000000000 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_cgc bridge_spio_p00_dma_ahb0_s_6_8_as_cgc SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGC_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGC_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGC_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 15469 spio_p00_dma_ahb0_s register as_cgc 0xDC10 R/W 0x0000000000000064 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_as_cgc Programmable intervals used by coarse clock gating logic. This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGC_HYSTERESIS_COUNTER_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGC_HYSTERESIS_COUNTER_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGC_HYSTERESIS_COUNTER_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGC_HYSTERESIS_COUNTER_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGC_HYSTERESIS_COUNTER_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGC_HYSTERESIS_COUNTER_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGC_HYSTERESIS_COUNTER_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_spio_soc_ip.csr 15457 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGC_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGC_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGC_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGC_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGC_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGC_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGC_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGC_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 15468 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_cgo bridge_spio_p00_dma_ahb0_s_6_8_as_cgo SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGO_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGO_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGO_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGO_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 15504 spio_p00_dma_ahb0_s register as_cgo 0xDC18 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_as_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the slave bridge. false false false false FPO SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGO_FPO_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGO_FPO_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGO_FPO_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGO_FPO_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGO_FPO_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGO_FPO_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGO_FPO_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGO_FPO_SET ns_noc_io_spio_soc_ip.csr 15492 FPO 1'b1: Clock gating override enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGO_UNSD_63_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGO_UNSD_63_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGO_UNSD_63_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGO_UNSD_63_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGO_UNSD_63_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGO_UNSD_63_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGO_UNSD_63_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CGO_UNSD_63_1_SET ns_noc_io_spio_soc_ip.csr 15503 UNSD_63_1 63 1 0x0000000000000000 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_sts bridge_spio_p00_dma_ahb0_s_6_8_as_sts SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 15578 spio_p00_dma_ahb0_s register as_sts 0xDD00 R 0x000000000000000c Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_as_sts Slave bridge status bits. false false false false WOF SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_WOF_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_WOF_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_WOF_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_WOF_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_WOF_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_WOF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_WOF_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_WOF_SET ns_noc_io_spio_soc_ip.csr 15527 WOF 1'b1: Maximum number of supported write commands are outstanding to the attached slave device awaiting response, no more write commands will be issued to slave till responses are received. 1'b0: Slave device can expect more write commands from NoC 0 0 0x0 R ROF SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_ROF_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_ROF_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_ROF_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_ROF_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_ROF_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_ROF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_ROF_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_ROF_SET ns_noc_io_spio_soc_ip.csr 15543 ROF 1'b1: Maximum number of supported read commands are outstanding to the attached slave device awaiting response, no more read commands will be issued to slave till responses are received. 1'b0: Slave bridge can accept more read commands from the NoC 1 1 0x0 R WOE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_WOE_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_WOE_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_WOE_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_WOE_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_WOE_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_WOE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_WOE_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_WOE_SET ns_noc_io_spio_soc_ip.csr 15555 WOE 1'b1: There are no write commands outstanding to the attached slave device 2 2 0x1 R ROE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_ROE_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_ROE_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_ROE_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_ROE_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_ROE_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_ROE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_ROE_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_ROE_SET ns_noc_io_spio_soc_ip.csr 15567 ROE 1'b1: There are no read commands outstanding to the attached slave device 3 3 0x1 R UNSD_63_4 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_UNSD_63_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_UNSD_63_4_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_UNSD_63_4_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_UNSD_63_4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_UNSD_63_4_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_UNSD_63_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_UNSD_63_4_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_STS_UNSD_63_4_SET ns_noc_io_spio_soc_ip.csr 15577 UNSD_63_4 63 4 0x000000000000000 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_bridge_id bridge_spio_p00_dma_ahb0_s_6_8_as_bridge_id SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_BRIDGE_ID_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_BRIDGE_ID_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_BRIDGE_ID_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_BRIDGE_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 15608 spio_p00_dma_ahb0_s register as_bridge_id 0xDD08 R 0x0000000000000006 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_as_bridge_id Unique identifier assigned to the slave bridge. false false false false ID SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_BRIDGE_ID_ID_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_BRIDGE_ID_ID_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_BRIDGE_ID_ID_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_BRIDGE_ID_ID_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_BRIDGE_ID_ID_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_BRIDGE_ID_ID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_BRIDGE_ID_ID_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_BRIDGE_ID_ID_SET ns_noc_io_spio_soc_ip.csr 15597 ID Unique bridge ID 15 0 0x0006 R UNSD_63_16 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_BRIDGE_ID_UNSD_63_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_BRIDGE_ID_UNSD_63_16_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_BRIDGE_ID_UNSD_63_16_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_BRIDGE_ID_UNSD_63_16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_BRIDGE_ID_UNSD_63_16_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_BRIDGE_ID_UNSD_63_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_BRIDGE_ID_UNSD_63_16_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_spio_soc_ip.csr 15607 UNSD_63_16 63 16 0x000000000000 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_err bridge_spio_p00_dma_ahb0_s_6_8_as_err SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 15961 spio_p00_dma_ahb0_s register as_err 0xDE00 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_as_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E0_SET ns_noc_io_spio_soc_ip.csr 15629 E0 1'b1: Read decode error response: Decode error response received from slave device for read command 0 0 0x0 R/W E1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E1_SET ns_noc_io_spio_soc_ip.csr 15641 E1 1'b1: Read slave error response: Slave error response received from slave device for read command 1 1 0x0 R/W E2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E2_SET ns_noc_io_spio_soc_ip.csr 15654 E2 1'b1: [FATAL] Unknown read response destination: RID from read response produces a destination which is not present in the routing table 2 2 0x0 R/W E3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E3_SET ns_noc_io_spio_soc_ip.csr 15668 E3 1'b1: [FATAL] Interleaved read response: Interleaved read response. This can occur if interleaved read response is received from a slave device for which a de-interleaver was not specified 3 3 0x0 R/W E4 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E4_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E4_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E4_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E4_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E4_SET ns_noc_io_spio_soc_ip.csr 15680 E4 1'b1: Read command modified: A read command which was marked as non-modifiable was modified by the slave bridge 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_UNSD_15_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_UNSD_15_5_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_UNSD_15_5_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_UNSD_15_5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_UNSD_15_5_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_UNSD_15_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_UNSD_15_5_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 15691 UNSD_15_5 15 5 0x000 R E16 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E16_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E16_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E16_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E16_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E16_SET ns_noc_io_spio_soc_ip.csr 15703 E16 1'b1: Write decode error response: Decode error response received from slave device for write command 16 16 0x0 R/W E17 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E17_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E17_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E17_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E17_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E17_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E17_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E17_SET ns_noc_io_spio_soc_ip.csr 15715 E17 1'b1: Write slave error response: Slave error response received from slave device for write command 17 17 0x0 R/W E18 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E18_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E18_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E18_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E18_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E18_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E18_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E18_SET ns_noc_io_spio_soc_ip.csr 15728 E18 1'b1: [FATAL] Unknown write response destination: BID from write response produces a destination which is not present in the routing table 18 18 0x0 R/W E19 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E19_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E19_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E19_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E19_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E19_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E19_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E19_SET ns_noc_io_spio_soc_ip.csr 15740 E19 1'b1: Write command modified: A write command which was marked as non-modifiable was modified by the slave bridge 19 19 0x0 R/W UNSD_31_20 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_UNSD_31_20_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_UNSD_31_20_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_UNSD_31_20_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_UNSD_31_20_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_UNSD_31_20_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_UNSD_31_20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_UNSD_31_20_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_UNSD_31_20_SET ns_noc_io_spio_soc_ip.csr 15751 UNSD_31_20 31 20 0x000 R E32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E32_SET ns_noc_io_spio_soc_ip.csr 15763 E32 1'b1: [FATAL] Traffic sent to a noc layer which is power gated 32 32 0x0 R/W E33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E33_SET ns_noc_io_spio_soc_ip.csr 15774 E33 1'b1: [FATAL] Parity error in config/status registers 33 33 0x0 R/W E34 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E34_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E34_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E34_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E34_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E34_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E34_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E34_SET ns_noc_io_spio_soc_ip.csr 15785 E34 1'b1: [FATAL] RDATA Parity error 34 34 0x0 R/W E35 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E35_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E35_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E35_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E35_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E35_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E35_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E35_SET ns_noc_io_spio_soc_ip.csr 15796 E35 1'b1: [FATAL] RRESP Parity error 35 35 0x0 R/W E36 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E36_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E36_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E36_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E36_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E36_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E36_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E36_SET ns_noc_io_spio_soc_ip.csr 15807 E36 1'b1: [FATAL] BRESP Parity error 36 36 0x0 R/W E37 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E37_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E37_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E37_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E37_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E37_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E37_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E37_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E37_SET ns_noc_io_spio_soc_ip.csr 15818 E37 1'b1: [FATAL] AC Parity error 37 37 0x0 R/W E38 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E38_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E38_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E38_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E38_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E38_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E38_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E38_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E38_SET ns_noc_io_spio_soc_ip.csr 15829 E38 1'b1: [FATAL] ACADDR Parity error 38 38 0x0 R/W E39 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E39_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E39_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E39_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E39_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E39_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E39_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E39_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E39_SET ns_noc_io_spio_soc_ip.csr 15841 E39 1'b1: [FATAL] R Ch Cmdtbl Parity Err 39 39 0x0 R E40 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E40_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E40_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E40_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E40_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E40_SET ns_noc_io_spio_soc_ip.csr 15853 E40 1'b1: [FATAL] B Ch Cmdtbl Parity Err 40 40 0x0 R E41 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E41_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E41_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E41_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E41_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E41_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E41_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E41_SET ns_noc_io_spio_soc_ip.csr 15865 E41 1'b1: [FATAL] Rx Fifo Parity Err 41 41 0x0 R E42 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E42_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E42_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E42_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E42_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E42_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E42_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E42_SET ns_noc_io_spio_soc_ip.csr 15877 E42 1'b1: [FATAL] CRCD Ch Reorder Buffer Parity Err 42 42 0x0 R E43 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E43_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E43_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E43_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E43_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E43_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E43_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E43_SET ns_noc_io_spio_soc_ip.csr 15889 E43 1'b1: [FATAL] Ack Ch Wack Reorder Buffer Parity Err 43 43 0x0 R E44 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E44_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E44_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E44_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E44_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E44_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E44_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E44_SET ns_noc_io_spio_soc_ip.csr 15901 E44 1'b1: [FATAL] Ack Ch Rack Reorder Buffer Parity Err 44 44 0x0 R E45 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E45_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E45_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E45_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E45_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E45_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E45_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E45_SET ns_noc_io_spio_soc_ip.csr 15913 E45 1'b1: [FATAL] B Ch Drain Fifo Parity Err 45 45 0x0 R E46 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E46_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E46_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E46_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E46_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E46_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E46_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E46_SET ns_noc_io_spio_soc_ip.csr 15925 E46 1'b1: [FATAL] R Ch Flush Fifo Parity Err 46 46 0x0 R E47 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E47_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E47_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E47_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E47_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E47_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E47_SET ns_noc_io_spio_soc_ip.csr 15937 E47 1'b1: [FATAL] R Ch Deinterleaver Cmdtbl Parity Err 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E48_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E48_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E48_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E48_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_E48_SET ns_noc_io_spio_soc_ip.csr 15949 E48 1'b1: [FATAL] R Ch Deinterleaver Data Buffer Parity Err 48 48 0x0 R UNSD_63_49 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_UNSD_63_49_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_UNSD_63_49_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_UNSD_63_49_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_UNSD_63_49_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_UNSD_63_49_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_UNSD_63_49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_UNSD_63_49_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_ERR_UNSD_63_49_SET ns_noc_io_spio_soc_ip.csr 15960 UNSD_63_49 63 49 0x0000 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_intm bridge_spio_p00_dma_ahb0_s_6_8_as_intm SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 16301 spio_p00_dma_ahb0_s register as_intm 0xDE40 R/W 0x0000007d000b0013 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_as_intm Interrupt mask register.Individual bit positions match the error bit positions in AS_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M0_SET ns_noc_io_spio_soc_ip.csr 15982 M0 Mask interrupts for read channel 0 0 0x1 R/W M1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M1_SET ns_noc_io_spio_soc_ip.csr 15993 M1 Mask interrupts for read channel 1 1 0x1 R/W M2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M2_SET ns_noc_io_spio_soc_ip.csr 16004 M2 Mask interrupts for read channel 2 2 0x0 R/W M3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M3_SET ns_noc_io_spio_soc_ip.csr 16015 M3 Mask interrupts for read channel 3 3 0x0 R/W M4 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M4_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M4_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M4_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M4_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M4_SET ns_noc_io_spio_soc_ip.csr 16026 M4 Mask interrupts for read channel 4 4 0x1 R/W UNSD_15_5 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_UNSD_15_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_UNSD_15_5_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_UNSD_15_5_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_UNSD_15_5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_UNSD_15_5_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_UNSD_15_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_UNSD_15_5_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 16037 UNSD_15_5 15 5 0x000 R M16 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M16_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M16_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M16_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M16_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M16_SET ns_noc_io_spio_soc_ip.csr 16048 M16 Mask interrupts for write channel 16 16 0x1 R/W M17 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M17_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M17_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M17_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M17_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M17_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M17_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M17_SET ns_noc_io_spio_soc_ip.csr 16059 M17 Mask interrupts for write channel 17 17 0x1 R/W M18 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M18_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M18_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M18_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M18_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M18_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M18_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M18_SET ns_noc_io_spio_soc_ip.csr 16070 M18 Mask interrupts for write channel 18 18 0x0 R/W M19 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M19_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M19_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M19_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M19_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M19_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M19_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M19_SET ns_noc_io_spio_soc_ip.csr 16081 M19 Mask interrupts for write channel 19 19 0x1 R/W UNSD_31_20 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_UNSD_31_20_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_UNSD_31_20_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_UNSD_31_20_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_UNSD_31_20_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_UNSD_31_20_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_UNSD_31_20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_UNSD_31_20_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_UNSD_31_20_SET ns_noc_io_spio_soc_ip.csr 16092 UNSD_31_20 31 20 0x000 R M32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M32_SET ns_noc_io_spio_soc_ip.csr 16103 M32 Mask interrupt on traffic to PG layer 32 32 0x1 R/W M33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M33_SET ns_noc_io_spio_soc_ip.csr 16114 M33 Mask interrupt on csr parity errors 33 33 0x0 R/W M34 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M34_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M34_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M34_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M34_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M34_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M34_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M34_SET ns_noc_io_spio_soc_ip.csr 16125 M34 RDATA parity interrupt Mask 34 34 0x1 R/W M35 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M35_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M35_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M35_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M35_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M35_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M35_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M35_SET ns_noc_io_spio_soc_ip.csr 16136 M35 RRESP parity interrupt Mask 35 35 0x1 R/W M36 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M36_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M36_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M36_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M36_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M36_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M36_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M36_SET ns_noc_io_spio_soc_ip.csr 16147 M36 BRESP parity interrupt Mask 36 36 0x1 R/W M37 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M37_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M37_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M37_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M37_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M37_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M37_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M37_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M37_SET ns_noc_io_spio_soc_ip.csr 16158 M37 AC parity interrupt Mask 37 37 0x1 R/W M38 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M38_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M38_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M38_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M38_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M38_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M38_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M38_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_M38_SET ns_noc_io_spio_soc_ip.csr 16169 M38 ACADDR parity interrupt Mask 38 38 0x1 R/W E39 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E39_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E39_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E39_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E39_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E39_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E39_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E39_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E39_SET ns_noc_io_spio_soc_ip.csr 16181 E39 1'b1: R Ch Cmdtbl Parity Err Intr Mask 39 39 0x0 R E40 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E40_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E40_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E40_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E40_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E40_SET ns_noc_io_spio_soc_ip.csr 16193 E40 1'b1: B Ch Cmdtbl Parity Err Intr Mask 40 40 0x0 R E41 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E41_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E41_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E41_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E41_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E41_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E41_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E41_SET ns_noc_io_spio_soc_ip.csr 16205 E41 1'b1: Rx Fifo Parity Err Intr Mask 41 41 0x0 R E42 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E42_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E42_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E42_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E42_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E42_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E42_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E42_SET ns_noc_io_spio_soc_ip.csr 16217 E42 1'b1: CRCD Ch Reorder Buffer Parity Err Intr Mask 42 42 0x0 R E43 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E43_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E43_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E43_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E43_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E43_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E43_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E43_SET ns_noc_io_spio_soc_ip.csr 16229 E43 1'b1: Ack Ch Wack Reorder Buffer Parity Err IntrMask 43 43 0x0 R E44 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E44_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E44_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E44_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E44_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E44_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E44_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E44_SET ns_noc_io_spio_soc_ip.csr 16241 E44 1'b1: Ack Ch Rack Reorder Buffer Parity Err Intr Mask 44 44 0x0 R E45 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E45_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E45_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E45_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E45_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E45_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E45_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E45_SET ns_noc_io_spio_soc_ip.csr 16253 E45 1'b1: B Ch Drain Fifo Parity Err Intr Mask 45 45 0x0 R E46 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E46_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E46_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E46_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E46_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E46_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E46_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E46_SET ns_noc_io_spio_soc_ip.csr 16265 E46 1'b1: R Ch Flush Fifo Parity Err Intr Mask 46 46 0x0 R E47 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E47_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E47_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E47_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E47_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E47_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E47_SET ns_noc_io_spio_soc_ip.csr 16277 E47 1'b1: R Ch Deinterleaver Cmdtbl Parity Err Intr Mask 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E48_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E48_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E48_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E48_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_E48_SET ns_noc_io_spio_soc_ip.csr 16289 E48 1'b1: R Ch Deinterleaver Data Buffer Parity Err Intr Mask 48 48 0x0 R UNSD_63_49 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_UNSD_63_49_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_UNSD_63_49_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_UNSD_63_49_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_UNSD_63_49_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_UNSD_63_49_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_UNSD_63_49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_UNSD_63_49_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_INTM_UNSD_63_49_SET ns_noc_io_spio_soc_ip.csr 16300 UNSD_63_49 63 49 0x0000 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_ccmd bridge_spio_p00_dma_ahb0_s_6_8_as_ccmd SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 16376 spio_p00_dma_ahb0_s register as_ccmd 0xDF00 R/W 0x0000000003000000 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_as_ccmd Not applicable for current release. false false false false UNSD_23_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_UNSD_23_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_UNSD_23_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_UNSD_23_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_UNSD_23_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_UNSD_23_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_UNSD_23_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_UNSD_23_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_UNSD_23_0_SET ns_noc_io_spio_soc_ip.csr 16319 UNSD_23_0 23 0 0x000000 R rdy SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_RDY_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_RDY_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_RDY_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_RDY_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_RDY_SET ns_noc_io_spio_soc_ip.csr 16330 rdy 1'b1: Ready 24 24 0x1 R/W val SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_VAL_SET ns_noc_io_spio_soc_ip.csr 16341 val 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_UNSD_27_26_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_UNSD_27_26_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_UNSD_27_26_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_UNSD_27_26_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_UNSD_27_26_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_UNSD_27_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_UNSD_27_26_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_UNSD_27_26_SET ns_noc_io_spio_soc_ip.csr 16352 UNSD_27_26 27 26 0x0 R intfid SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_INTFID_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_INTFID_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_INTFID_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_INTFID_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_INTFID_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_INTFID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_INTFID_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_INTFID_SET ns_noc_io_spio_soc_ip.csr 16364 intfid 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_63_31 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_UNSD_63_31_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_UNSD_63_31_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_UNSD_63_31_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_UNSD_63_31_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_UNSD_63_31_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_UNSD_63_31_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_UNSD_63_31_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMD_UNSD_63_31_SET ns_noc_io_spio_soc_ip.csr 16375 UNSD_63_31 63 31 0x000000000 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_ccmdmsk bridge_spio_p00_dma_ahb0_s_6_8_as_ccmdmsk SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 16428 spio_p00_dma_ahb0_s register as_ccmdmsk 0xDF08 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_as_ccmdmsk Not applicable for current release. false false false false UNSD_23_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_UNSD_23_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_UNSD_23_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_UNSD_23_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_UNSD_23_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_UNSD_23_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_UNSD_23_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_UNSD_23_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_UNSD_23_0_SET ns_noc_io_spio_soc_ip.csr 16394 UNSD_23_0 23 0 0x000000 R rdy SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_RDY_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_RDY_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_RDY_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_RDY_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_RDY_SET ns_noc_io_spio_soc_ip.csr 16405 rdy 1'b1: Ready 24 24 0x0 R/W val SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_VAL_SET ns_noc_io_spio_soc_ip.csr 16416 val 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_UNSD_63_26_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_UNSD_63_26_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_UNSD_63_26_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_UNSD_63_26_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_UNSD_63_26_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_UNSD_63_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_UNSD_63_26_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CCMDMSK_UNSD_63_26_SET ns_noc_io_spio_soc_ip.csr 16427 UNSD_63_26 63 26 0x0000000000 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_cntr bridge_spio_p00_dma_ahb0_s_6_8_as_cntr SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CNTR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CNTR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CNTR_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CNTR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 16458 spio_p00_dma_ahb0_s register as_cntr 0xDF10 R 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_as_cntr Not applicable for current release. false false false false CNTR SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CNTR_CNTR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CNTR_CNTR_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CNTR_CNTR_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CNTR_CNTR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CNTR_CNTR_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CNTR_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CNTR_CNTR_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CNTR_CNTR_SET ns_noc_io_spio_soc_ip.csr 16447 CNTR Counter 31 0 0x00000000 R UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CNTR_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CNTR_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CNTR_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CNTR_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CNTR_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CNTR_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CNTR_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_CNTR_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 16457 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_arovrd bridge_spio_p00_dma_ahb0_s_6_8_as_arovrd SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 16571 spio_p00_dma_ahb0_s register as_arovrd 0xDF18 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_as_arovrd AR Overrides. false false false false arcache_val SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 16476 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 16489 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 16500 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 16511 UNSD_11_11 11 11 0x0 R arprot_enb SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 16524 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 16535 UNSD_15_15 15 15 0x0 R arqos_val SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 16546 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_ARQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 16559 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AROVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 16570 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_as_awovrd bridge_spio_p00_dma_ahb0_s_6_8_as_awovrd SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 16684 spio_p00_dma_ahb0_s register as_awovrd 0xDF20 R/W 0x0000000000000020 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_as_awovrd AW Overrides. false false false false awcache_val SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 16589 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 16602 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x2 R/W awprot_val SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 16613 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 16624 UNSD_11_11 11 11 0x0 R awprot_enb SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 16637 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 16648 UNSD_15_15 15 15 0x0 R awqos_val SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 16659 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_AWQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 16672 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_AS_AWOVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 16683 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_p_0 bridge_spio_p00_dma_ahb0_s_6_8_p_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 16749 spio_p00_dma_ahb0_s register p_0 0xF000 R/W 0x00000003 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_0_SET ns_noc_io_spio_soc_ip.csr 16712 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_1_SET ns_noc_io_spio_soc_ip.csr 16724 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_2_SET ns_noc_io_spio_soc_ip.csr 16736 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_0_WT_QOS_3_SET ns_noc_io_spio_soc_ip.csr 16748 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_p_1 bridge_spio_p00_dma_ahb0_s_6_8_p_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 16815 spio_p00_dma_ahb0_s register p_1 0xF008 R 0x00000000 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_4_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_4_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_4_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_4_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_4_SET ns_noc_io_spio_soc_ip.csr 16778 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_5_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_5_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_5_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_5_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_5_SET ns_noc_io_spio_soc_ip.csr 16790 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_6_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_6_SET ns_noc_io_spio_soc_ip.csr 16802 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_7_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_7_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_7_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_7_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_1_WT_QOS_7_SET ns_noc_io_spio_soc_ip.csr 16814 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_p_2 bridge_spio_p00_dma_ahb0_s_6_8_p_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 16881 spio_p00_dma_ahb0_s register p_2 0xF010 R 0x00000000 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_8_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_8_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_8_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_8_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_8_SET ns_noc_io_spio_soc_ip.csr 16844 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_9_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_9_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_9_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_9_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_9_SET ns_noc_io_spio_soc_ip.csr 16856 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_10_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_10_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_10_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_10_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_10_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_10_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_10_SET ns_noc_io_spio_soc_ip.csr 16868 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_11_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_11_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_11_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_11_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_11_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_2_WT_QOS_11_SET ns_noc_io_spio_soc_ip.csr 16880 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_p_3 bridge_spio_p00_dma_ahb0_s_6_8_p_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 16947 spio_p00_dma_ahb0_s register p_3 0xF018 R 0x00000000 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_12_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_12_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_12_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_12_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_12_SET ns_noc_io_spio_soc_ip.csr 16910 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_13_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_13_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_13_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_13_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_13_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_13_SET ns_noc_io_spio_soc_ip.csr 16922 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_14_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_14_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_14_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_14_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_14_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_14_SET ns_noc_io_spio_soc_ip.csr 16934 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_15_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_15_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_15_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_15_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_15_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_P_3_WT_QOS_15_SET ns_noc_io_spio_soc_ip.csr 16946 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_txe bridge_spio_p00_dma_ahb0_s_6_8_txe SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 17093 spio_p00_dma_ahb0_s register txe 0xF040 R/W 0x00000000 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_TRANS_WITHOUT_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_TRANS_WITHOUT_SOP_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_TRANS_WITHOUT_SOP_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_TRANS_WITHOUT_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_TRANS_WITHOUT_SOP_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_TRANS_WITHOUT_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_TRANS_WITHOUT_SOP_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_spio_soc_ip.csr 16974 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_SOP_AFTER_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_SOP_AFTER_SOP_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_SOP_AFTER_SOP_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_SOP_AFTER_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_SOP_AFTER_SOP_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_SOP_AFTER_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_SOP_AFTER_SOP_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_SOP_AFTER_SOP_SET ns_noc_io_spio_soc_ip.csr 16986 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 17001 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 17014 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_spio_soc_ip.csr 17028 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_spio_soc_ip.csr 17042 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_spio_soc_ip.csr 17056 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_spio_soc_ip.csr 17070 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 17081 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXE_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 17092 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_txem bridge_spio_p00_dma_ahb0_s_6_8_txem SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 17172 spio_p00_dma_ahb0_s register txem 0xF048 R/W 0x00000008 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_UNSD_1_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_UNSD_1_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_UNSD_1_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_UNSD_1_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_UNSD_1_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_UNSD_1_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_UNSD_1_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_UNSD_1_0_SET ns_noc_io_spio_soc_ip.csr 17116 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 17127 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 17138 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_UNSD_7_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_UNSD_7_4_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_UNSD_7_4_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_UNSD_7_4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_UNSD_7_4_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_UNSD_7_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_UNSD_7_4_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_UNSD_7_4_SET ns_noc_io_spio_soc_ip.csr 17149 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 17160 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_TXEM_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 17171 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btus_0 bridge_spio_p00_dma_ahb0_s_6_8_btus_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 17540 spio_p00_dma_ahb0_s register btus_0 0xF058 R 0x00000000 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_A_SET ns_noc_io_spio_soc_ip.csr 17198 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_B_SET ns_noc_io_spio_soc_ip.csr 17209 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_C_SET ns_noc_io_spio_soc_ip.csr 17220 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L0_D_SET ns_noc_io_spio_soc_ip.csr 17231 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_A_SET ns_noc_io_spio_soc_ip.csr 17242 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_B_SET ns_noc_io_spio_soc_ip.csr 17253 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_C_SET ns_noc_io_spio_soc_ip.csr 17264 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L1_D_SET ns_noc_io_spio_soc_ip.csr 17275 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_A_SET ns_noc_io_spio_soc_ip.csr 17286 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_B_SET ns_noc_io_spio_soc_ip.csr 17297 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_C_SET ns_noc_io_spio_soc_ip.csr 17308 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L2_D_SET ns_noc_io_spio_soc_ip.csr 17319 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_A_SET ns_noc_io_spio_soc_ip.csr 17330 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_B_SET ns_noc_io_spio_soc_ip.csr 17341 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_C_SET ns_noc_io_spio_soc_ip.csr 17352 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L3_D_SET ns_noc_io_spio_soc_ip.csr 17363 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_A_SET ns_noc_io_spio_soc_ip.csr 17374 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_B_SET ns_noc_io_spio_soc_ip.csr 17385 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_C_SET ns_noc_io_spio_soc_ip.csr 17396 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L4_D_SET ns_noc_io_spio_soc_ip.csr 17407 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_A_SET ns_noc_io_spio_soc_ip.csr 17418 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_B_SET ns_noc_io_spio_soc_ip.csr 17429 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_C_SET ns_noc_io_spio_soc_ip.csr 17440 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L5_D_SET ns_noc_io_spio_soc_ip.csr 17451 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_A_SET ns_noc_io_spio_soc_ip.csr 17462 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_B_SET ns_noc_io_spio_soc_ip.csr 17473 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_C_SET ns_noc_io_spio_soc_ip.csr 17484 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L6_D_SET ns_noc_io_spio_soc_ip.csr 17495 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_A_SET ns_noc_io_spio_soc_ip.csr 17506 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_B_SET ns_noc_io_spio_soc_ip.csr 17517 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_C_SET ns_noc_io_spio_soc_ip.csr 17528 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_0_L7_D_SET ns_noc_io_spio_soc_ip.csr 17539 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btus_1 bridge_spio_p00_dma_ahb0_s_6_8_btus_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 17908 spio_p00_dma_ahb0_s register btus_1 0xF060 R 0x00000000 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_A_SET ns_noc_io_spio_soc_ip.csr 17566 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_B_SET ns_noc_io_spio_soc_ip.csr 17577 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_C_SET ns_noc_io_spio_soc_ip.csr 17588 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L8_D_SET ns_noc_io_spio_soc_ip.csr 17599 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_A_SET ns_noc_io_spio_soc_ip.csr 17610 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_B_SET ns_noc_io_spio_soc_ip.csr 17621 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_C_SET ns_noc_io_spio_soc_ip.csr 17632 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L9_D_SET ns_noc_io_spio_soc_ip.csr 17643 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_A_SET ns_noc_io_spio_soc_ip.csr 17654 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_B_SET ns_noc_io_spio_soc_ip.csr 17665 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_C_SET ns_noc_io_spio_soc_ip.csr 17676 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L10_D_SET ns_noc_io_spio_soc_ip.csr 17687 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_A_SET ns_noc_io_spio_soc_ip.csr 17698 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_B_SET ns_noc_io_spio_soc_ip.csr 17709 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_C_SET ns_noc_io_spio_soc_ip.csr 17720 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L11_D_SET ns_noc_io_spio_soc_ip.csr 17731 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_A_SET ns_noc_io_spio_soc_ip.csr 17742 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_B_SET ns_noc_io_spio_soc_ip.csr 17753 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_C_SET ns_noc_io_spio_soc_ip.csr 17764 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L12_D_SET ns_noc_io_spio_soc_ip.csr 17775 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_A_SET ns_noc_io_spio_soc_ip.csr 17786 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_B_SET ns_noc_io_spio_soc_ip.csr 17797 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_C_SET ns_noc_io_spio_soc_ip.csr 17808 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L13_D_SET ns_noc_io_spio_soc_ip.csr 17819 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_A_SET ns_noc_io_spio_soc_ip.csr 17830 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_B_SET ns_noc_io_spio_soc_ip.csr 17841 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_C_SET ns_noc_io_spio_soc_ip.csr 17852 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L14_D_SET ns_noc_io_spio_soc_ip.csr 17863 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_A_SET ns_noc_io_spio_soc_ip.csr 17874 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_B_SET ns_noc_io_spio_soc_ip.csr 17885 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_C_SET ns_noc_io_spio_soc_ip.csr 17896 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTUS_1_L15_D_SET ns_noc_io_spio_soc_ip.csr 17907 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btrl_0 bridge_spio_p00_dma_ahb0_s_6_8_btrl_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 17984 spio_p00_dma_ahb0_s register btrl_0 0xF080 R 0x00000000 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_WT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_WT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_WT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_WT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_WT_SET ns_noc_io_spio_soc_ip.csr 17932 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 17943 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_CNT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_CNT_SET ns_noc_io_spio_soc_ip.csr 17958 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_EN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_EN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_EN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_EN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_EN_SET ns_noc_io_spio_soc_ip.csr 17972 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_0_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 17983 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btrl_1 bridge_spio_p00_dma_ahb0_s_6_8_btrl_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 18060 spio_p00_dma_ahb0_s register btrl_1 0xF088 R 0x00000000 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_WT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_WT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_WT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_WT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_WT_SET ns_noc_io_spio_soc_ip.csr 18008 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 18019 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_CNT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_CNT_SET ns_noc_io_spio_soc_ip.csr 18034 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_EN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_EN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_EN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_EN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_EN_SET ns_noc_io_spio_soc_ip.csr 18048 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_1_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 18059 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btrl_2 bridge_spio_p00_dma_ahb0_s_6_8_btrl_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 18136 spio_p00_dma_ahb0_s register btrl_2 0xF090 R 0x00000000 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_WT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_WT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_WT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_WT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_WT_SET ns_noc_io_spio_soc_ip.csr 18084 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 18095 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_CNT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_CNT_SET ns_noc_io_spio_soc_ip.csr 18110 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_EN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_EN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_EN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_EN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_EN_SET ns_noc_io_spio_soc_ip.csr 18124 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_2_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 18135 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btrl_3 bridge_spio_p00_dma_ahb0_s_6_8_btrl_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 18212 spio_p00_dma_ahb0_s register btrl_3 0xF098 R 0x00000000 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_WT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_WT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_WT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_WT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_WT_SET ns_noc_io_spio_soc_ip.csr 18160 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 18171 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_CNT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_CNT_SET ns_noc_io_spio_soc_ip.csr 18186 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_EN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_EN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_EN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_EN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_EN_SET ns_noc_io_spio_soc_ip.csr 18200 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTRL_3_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 18211 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btperr bridge_spio_p00_dma_ahb0_s_6_8_btperr SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 18414 spio_p00_dma_ahb0_s register btperr 0xF0A8 R/W 0x00000000 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L0_SET ns_noc_io_spio_soc_ip.csr 18237 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L1_SET ns_noc_io_spio_soc_ip.csr 18248 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L2_SET ns_noc_io_spio_soc_ip.csr 18259 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L3_SET ns_noc_io_spio_soc_ip.csr 18270 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L4_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L4_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L4_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L4_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L4_SET ns_noc_io_spio_soc_ip.csr 18281 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L5_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L5_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L5_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L5_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L5_SET ns_noc_io_spio_soc_ip.csr 18292 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L6_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L6_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L6_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L6_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L6_SET ns_noc_io_spio_soc_ip.csr 18303 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L7_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L7_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L7_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L7_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L7_SET ns_noc_io_spio_soc_ip.csr 18314 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L8_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L8_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L8_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L8_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L8_SET ns_noc_io_spio_soc_ip.csr 18325 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L9_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L9_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L9_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L9_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L9_SET ns_noc_io_spio_soc_ip.csr 18336 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L10_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L10_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L10_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L10_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L10_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L10_SET ns_noc_io_spio_soc_ip.csr 18347 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L11_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L11_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L11_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L11_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L11_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L11_SET ns_noc_io_spio_soc_ip.csr 18358 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L12_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L12_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L12_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L12_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L12_SET ns_noc_io_spio_soc_ip.csr 18369 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L13_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L13_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L13_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L13_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L13_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L13_SET ns_noc_io_spio_soc_ip.csr 18380 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L14_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L14_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L14_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L14_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L14_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L14_SET ns_noc_io_spio_soc_ip.csr 18391 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L15_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L15_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L15_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L15_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L15_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_L15_SET ns_noc_io_spio_soc_ip.csr 18402 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_UNSD_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERR_UNSD_SET ns_noc_io_spio_soc_ip.csr 18413 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_btperrm bridge_spio_p00_dma_ahb0_s_6_8_btperrm SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 18614 spio_p00_dma_ahb0_s register btperrm 0xF0B0 R/W 0x00000000 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L0_SET ns_noc_io_spio_soc_ip.csr 18437 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L1_SET ns_noc_io_spio_soc_ip.csr 18448 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L2_SET ns_noc_io_spio_soc_ip.csr 18459 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L3_SET ns_noc_io_spio_soc_ip.csr 18470 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L4_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L4_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L4_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L4_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L4_SET ns_noc_io_spio_soc_ip.csr 18481 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L5_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L5_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L5_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L5_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L5_SET ns_noc_io_spio_soc_ip.csr 18492 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L6_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L6_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L6_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L6_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L6_SET ns_noc_io_spio_soc_ip.csr 18503 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L7_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L7_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L7_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L7_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L7_SET ns_noc_io_spio_soc_ip.csr 18514 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L8_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L8_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L8_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L8_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L8_SET ns_noc_io_spio_soc_ip.csr 18525 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L9_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L9_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L9_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L9_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L9_SET ns_noc_io_spio_soc_ip.csr 18536 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L10_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L10_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L10_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L10_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L10_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L10_SET ns_noc_io_spio_soc_ip.csr 18547 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L11_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L11_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L11_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L11_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L11_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L11_SET ns_noc_io_spio_soc_ip.csr 18558 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L12_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L12_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L12_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L12_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L12_SET ns_noc_io_spio_soc_ip.csr 18569 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L13_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L13_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L13_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L13_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L13_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L13_SET ns_noc_io_spio_soc_ip.csr 18580 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L14_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L14_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L14_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L14_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L14_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L14_SET ns_noc_io_spio_soc_ip.csr 18591 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L15_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L15_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L15_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L15_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L15_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_L15_SET ns_noc_io_spio_soc_ip.csr 18602 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_UNSD_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BTPERRM_UNSD_SET ns_noc_io_spio_soc_ip.csr 18613 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_rxe bridge_spio_p00_dma_ahb0_s_6_8_rxe SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 18722 spio_p00_dma_ahb0_s register rxe 0xF120 R/W 0x00000000 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_A_SET ns_noc_io_spio_soc_ip.csr 18642 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_B_SET ns_noc_io_spio_soc_ip.csr 18653 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_C_SET ns_noc_io_spio_soc_ip.csr 18664 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_CRC_OFLW_D_SET ns_noc_io_spio_soc_ip.csr 18675 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_EVC_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_EVC_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_EVC_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_EVC_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_EVC_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_EVC_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_EVC_OFLW_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_EVC_OFLW_SET ns_noc_io_spio_soc_ip.csr 18687 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 18698 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_EVC1_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_EVC1_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_EVC1_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_EVC1_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_EVC1_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_EVC1_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_EVC1_OFLW_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_EVC1_OFLW_SET ns_noc_io_spio_soc_ip.csr 18710 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXE_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 18721 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_rxem bridge_spio_p00_dma_ahb0_s_6_8_rxem SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 18794 spio_p00_dma_ahb0_s register rxem 0xF128 R/W 0x00000050 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_UNSD_3_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_UNSD_3_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_UNSD_3_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_UNSD_3_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_UNSD_3_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_UNSD_3_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_UNSD_3_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_UNSD_3_0_SET ns_noc_io_spio_soc_ip.csr 18743 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_EVC_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_EVC_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_EVC_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_EVC_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_EVC_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_EVC_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_EVC_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_EVC_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 18757 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 18768 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_EVC1_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_EVC1_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_EVC1_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_EVC1_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_EVC1_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_EVC1_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_EVC1_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 18782 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_RXEM_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 18793 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_brs_0 bridge_spio_p00_dma_ahb0_s_6_8_brs_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 19068 spio_p00_dma_ahb0_s register brs_0 0xF130 R 0x00000000 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 18818 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_0_SET ns_noc_io_spio_soc_ip.csr 18829 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_0_SET ns_noc_io_spio_soc_ip.csr 18840 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_0_SET ns_noc_io_spio_soc_ip.csr 18851 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_0_SET ns_noc_io_spio_soc_ip.csr 18862 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 18872 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 18883 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_1_SET ns_noc_io_spio_soc_ip.csr 18894 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_1_SET ns_noc_io_spio_soc_ip.csr 18905 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_1_SET ns_noc_io_spio_soc_ip.csr 18916 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_1_SET ns_noc_io_spio_soc_ip.csr 18927 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 18937 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 18948 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_2_SET ns_noc_io_spio_soc_ip.csr 18959 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_2_SET ns_noc_io_spio_soc_ip.csr 18970 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_2_SET ns_noc_io_spio_soc_ip.csr 18981 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_2_SET ns_noc_io_spio_soc_ip.csr 18992 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 19002 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 19013 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_V_3_SET ns_noc_io_spio_soc_ip.csr 19024 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_S_3_SET ns_noc_io_spio_soc_ip.csr 19035 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_B_3_SET ns_noc_io_spio_soc_ip.csr 19046 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_F_3_SET ns_noc_io_spio_soc_ip.csr 19057 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_0_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 19067 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_brs_1 bridge_spio_p00_dma_ahb0_s_6_8_brs_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 19342 spio_p00_dma_ahb0_s register brs_1 0xF138 R 0x00000000 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 19092 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_0_SET ns_noc_io_spio_soc_ip.csr 19103 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_0_SET ns_noc_io_spio_soc_ip.csr 19114 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_0_SET ns_noc_io_spio_soc_ip.csr 19125 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_0_SET ns_noc_io_spio_soc_ip.csr 19136 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 19146 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 19157 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_1_SET ns_noc_io_spio_soc_ip.csr 19168 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_1_SET ns_noc_io_spio_soc_ip.csr 19179 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_1_SET ns_noc_io_spio_soc_ip.csr 19190 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_1_SET ns_noc_io_spio_soc_ip.csr 19201 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 19211 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 19222 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_2_SET ns_noc_io_spio_soc_ip.csr 19233 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_2_SET ns_noc_io_spio_soc_ip.csr 19244 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_2_SET ns_noc_io_spio_soc_ip.csr 19255 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_2_SET ns_noc_io_spio_soc_ip.csr 19266 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 19276 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 19287 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_V_3_SET ns_noc_io_spio_soc_ip.csr 19298 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_S_3_SET ns_noc_io_spio_soc_ip.csr 19309 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_B_3_SET ns_noc_io_spio_soc_ip.csr 19320 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_F_3_SET ns_noc_io_spio_soc_ip.csr 19331 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRS_1_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 19341 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_brus bridge_spio_p00_dma_ahb0_s_6_8_brus SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 19411 spio_p00_dma_ahb0_s register brus 0xF1B0 R 0x00000000 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_A_SET ns_noc_io_spio_soc_ip.csr 19367 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_B_SET ns_noc_io_spio_soc_ip.csr 19378 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_C_SET ns_noc_io_spio_soc_ip.csr 19389 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_V_D_SET ns_noc_io_spio_soc_ip.csr 19400 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_UNSD_31_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_UNSD_31_4_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_UNSD_31_4_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_UNSD_31_4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_UNSD_31_4_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_UNSD_31_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_UNSD_31_4_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRUS_UNSD_31_4_SET ns_noc_io_spio_soc_ip.csr 19410 UNSD_31_4 31 4 0x0000000 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_brperr0 bridge_spio_p00_dma_ahb0_s_6_8_brperr0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 19639 spio_p00_dma_ahb0_s register brperr0 0xF1D0 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_D0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_D0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_D0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_D0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_D0_SET ns_noc_io_spio_soc_ip.csr 19449 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_DC0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_DC0_SET ns_noc_io_spio_soc_ip.csr 19460 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SB0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SB0_SET ns_noc_io_spio_soc_ip.csr 19471 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SBC0_SET ns_noc_io_spio_soc_ip.csr 19483 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_PK0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_PK0_SET ns_noc_io_spio_soc_ip.csr 19494 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 19505 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_D1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_D1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_D1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_D1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_D1_SET ns_noc_io_spio_soc_ip.csr 19516 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_DC1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_DC1_SET ns_noc_io_spio_soc_ip.csr 19527 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SB1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SB1_SET ns_noc_io_spio_soc_ip.csr 19538 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_SBC1_SET ns_noc_io_spio_soc_ip.csr 19550 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_PK1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_PK1_SET ns_noc_io_spio_soc_ip.csr 19561 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 19572 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 19583 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 19594 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 19605 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 19616 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 19627 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 19638 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_brperr1 bridge_spio_p00_dma_ahb0_s_6_8_brperr1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 19755 spio_p00_dma_ahb0_s register brperr1 0xF1D8 R 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 19677 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 19688 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 19699 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 19710 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 19721 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 19732 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 19743 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERR1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 19754 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_brperrm0 bridge_spio_p00_dma_ahb0_s_6_8_brperrm0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 19976 spio_p00_dma_ahb0_s register brperrm0 0xF1E0 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_D0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_D0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_D0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_D0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_D0_SET ns_noc_io_spio_soc_ip.csr 19782 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_DC0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_DC0_SET ns_noc_io_spio_soc_ip.csr 19794 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SB0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SB0_SET ns_noc_io_spio_soc_ip.csr 19805 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SBC0_SET ns_noc_io_spio_soc_ip.csr 19817 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_PK0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_PK0_SET ns_noc_io_spio_soc_ip.csr 19829 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 19840 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_D1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_D1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_D1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_D1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_D1_SET ns_noc_io_spio_soc_ip.csr 19851 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_DC1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_DC1_SET ns_noc_io_spio_soc_ip.csr 19863 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SB1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SB1_SET ns_noc_io_spio_soc_ip.csr 19874 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_SBC1_SET ns_noc_io_spio_soc_ip.csr 19886 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_PK1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_PK1_SET ns_noc_io_spio_soc_ip.csr 19898 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 19909 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 19920 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 19931 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 19942 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 19953 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 19964 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 19975 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p00_dma_ahb0_s_6_8_brperrm1 bridge_spio_p00_dma_ahb0_s_6_8_brperrm1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 20081 spio_p00_dma_ahb0_s register brperrm1 0xF1E8 R 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_ahb0_s_6_8_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 20003 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 20014 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 20025 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 20036 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 20047 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 20058 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 20069 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AHB0_S_6_8_BRPERRM1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 20080 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 20197 spio_p00_dma_am_m register am_adbase_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 0x10000 R/W 0x0000000040100000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 20121 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 20132 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 20143 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 20155 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 20166 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 20178 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 20189 BASE_ADDRESS_0_33 Base address 39 6 0x001004000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 20196 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 20289 spio_p00_dma_am_m register am_admask_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 0x10008 R/W 0x000000fffff00000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 20214 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 20225 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 20236 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 20247 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 20259 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 20270 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 20281 MASK_0_33 Mask 39 6 0x3ffffc000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 20288 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 20405 spio_p00_dma_am_m register am_adbase_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 0x10020 R/W 0x0000000056100000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 20329 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 20340 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 20351 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 20363 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 20374 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 20386 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 20397 BASE_ADDRESS_0_33 Base address 39 6 0x001584000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 20404 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 20497 spio_p00_dma_am_m register am_admask_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 0x10028 R/W 0x000000fffff00000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 20422 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 20433 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 20444 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 20455 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 20467 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 20478 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 20489 MASK_0_33 Mask 39 6 0x3ffffc000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 20496 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 20613 spio_p00_dma_am_m register am_adbase_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 0x10040 R/W 0x0000000056000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 20537 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 20548 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 20559 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 20571 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 20582 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 20594 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 20605 BASE_ADDRESS_0_33 Base address 39 6 0x001580000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 20612 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 20705 spio_p00_dma_am_m register am_admask_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 0x10048 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 20630 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 20641 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 20652 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 20663 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 20675 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 20686 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 20697 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 20704 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 20821 spio_p00_dma_am_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 0x10060 R/W 0x0000000054000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 20745 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 20756 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 20767 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 20779 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 20790 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 20802 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 20813 BASE_ADDRESS_0_33 Base address 39 6 0x001500000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 20820 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 20913 spio_p00_dma_am_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 0x10068 R/W 0x000000ffffff0000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 20838 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 20849 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 20860 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 20871 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 20883 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 20894 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 20905 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 20912 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 21029 spio_p00_dma_am_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 0x10080 R/W 0x0000000054010000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_SET ns_noc_io_spio_soc_ip.csr 20953 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 20964 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_SET ns_noc_io_spio_soc_ip.csr 20975 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 20987 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_SET ns_noc_io_spio_soc_ip.csr 20998 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_SET ns_noc_io_spio_soc_ip.csr 21010 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 21021 BASE_ADDRESS_0_33 Base address 39 6 0x001500400 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 21028 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 21121 spio_p00_dma_am_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 0x10088 R/W 0x000000ffffff0000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_SET ns_noc_io_spio_soc_ip.csr 21046 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 21057 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_SET ns_noc_io_spio_soc_ip.csr 21068 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_SET ns_noc_io_spio_soc_ip.csr 21079 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_SET ns_noc_io_spio_soc_ip.csr 21091 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_SET ns_noc_io_spio_soc_ip.csr 21102 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 21113 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 21120 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 21237 spio_p00_dma_am_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 0x100A0 R/W 0x0000000054020000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_SET ns_noc_io_spio_soc_ip.csr 21161 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 21172 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_SET ns_noc_io_spio_soc_ip.csr 21183 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 21195 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_SET ns_noc_io_spio_soc_ip.csr 21206 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_SET ns_noc_io_spio_soc_ip.csr 21218 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 21229 BASE_ADDRESS_0_33 Base address 39 6 0x001500800 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 21236 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 21329 spio_p00_dma_am_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 0x100A8 R/W 0x000000ffffff0000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_SET ns_noc_io_spio_soc_ip.csr 21254 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 21265 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_SET ns_noc_io_spio_soc_ip.csr 21276 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_SET ns_noc_io_spio_soc_ip.csr 21287 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_SET ns_noc_io_spio_soc_ip.csr 21299 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_SET ns_noc_io_spio_soc_ip.csr 21310 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 21321 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 21328 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 21445 spio_p00_dma_am_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 0x100C0 R/W 0x0000000054030000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_SET ns_noc_io_spio_soc_ip.csr 21369 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 21380 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_SET ns_noc_io_spio_soc_ip.csr 21391 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 21403 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_SET ns_noc_io_spio_soc_ip.csr 21414 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_SET ns_noc_io_spio_soc_ip.csr 21426 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 21437 BASE_ADDRESS_0_33 Base address 39 6 0x001500c00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 21444 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 21537 spio_p00_dma_am_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 0x100C8 R/W 0x000000ffffff0000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_SET ns_noc_io_spio_soc_ip.csr 21462 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 21473 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_SET ns_noc_io_spio_soc_ip.csr 21484 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_SET ns_noc_io_spio_soc_ip.csr 21495 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_SET ns_noc_io_spio_soc_ip.csr 21507 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_SET ns_noc_io_spio_soc_ip.csr 21518 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 21529 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 21536 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 21653 spio_p00_dma_am_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 0x100E0 R/W 0x0000000054040000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_SET ns_noc_io_spio_soc_ip.csr 21577 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 21588 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_SET ns_noc_io_spio_soc_ip.csr 21599 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 21611 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_SET ns_noc_io_spio_soc_ip.csr 21622 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_SET ns_noc_io_spio_soc_ip.csr 21634 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 21645 BASE_ADDRESS_0_33 Base address 39 6 0x001501000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 21652 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 21745 spio_p00_dma_am_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 0x100E8 R/W 0x000000ffffff0000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_SET ns_noc_io_spio_soc_ip.csr 21670 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 21681 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_SET ns_noc_io_spio_soc_ip.csr 21692 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_SET ns_noc_io_spio_soc_ip.csr 21703 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_SET ns_noc_io_spio_soc_ip.csr 21715 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_SET ns_noc_io_spio_soc_ip.csr 21726 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 21737 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 21744 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 21861 spio_p00_dma_am_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 0x10100 R/W 0x0000000054050000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_SET ns_noc_io_spio_soc_ip.csr 21785 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 21796 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_SET ns_noc_io_spio_soc_ip.csr 21807 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 21819 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_SET ns_noc_io_spio_soc_ip.csr 21830 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_SET ns_noc_io_spio_soc_ip.csr 21842 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 21853 BASE_ADDRESS_0_33 Base address 39 6 0x001501400 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 21860 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 21953 spio_p00_dma_am_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 0x10108 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_SET ns_noc_io_spio_soc_ip.csr 21878 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 21889 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_SET ns_noc_io_spio_soc_ip.csr 21900 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_SET ns_noc_io_spio_soc_ip.csr 21911 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_SET ns_noc_io_spio_soc_ip.csr 21923 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_SET ns_noc_io_spio_soc_ip.csr 21934 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 21945 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 21952 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 22069 spio_p00_dma_am_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 0x10120 R/W 0x0000000054051000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_SET ns_noc_io_spio_soc_ip.csr 21993 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 22004 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_SET ns_noc_io_spio_soc_ip.csr 22015 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 22027 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_SET ns_noc_io_spio_soc_ip.csr 22038 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_SET ns_noc_io_spio_soc_ip.csr 22050 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 22061 BASE_ADDRESS_0_33 Base address 39 6 0x001501440 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 22068 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 22161 spio_p00_dma_am_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 0x10128 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_SET ns_noc_io_spio_soc_ip.csr 22086 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 22097 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_SET ns_noc_io_spio_soc_ip.csr 22108 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_SET ns_noc_io_spio_soc_ip.csr 22119 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_SET ns_noc_io_spio_soc_ip.csr 22131 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_SET ns_noc_io_spio_soc_ip.csr 22142 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 22153 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 22160 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 22277 spio_p00_dma_am_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 0x10140 R/W 0x0000000054052000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_SET ns_noc_io_spio_soc_ip.csr 22201 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 22212 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_SET ns_noc_io_spio_soc_ip.csr 22223 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 22235 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_SET ns_noc_io_spio_soc_ip.csr 22246 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_SET ns_noc_io_spio_soc_ip.csr 22258 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 22269 BASE_ADDRESS_0_33 Base address 39 6 0x001501480 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 22276 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 22369 spio_p00_dma_am_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 0x10148 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_SET ns_noc_io_spio_soc_ip.csr 22294 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 22305 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_SET ns_noc_io_spio_soc_ip.csr 22316 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_SET ns_noc_io_spio_soc_ip.csr 22327 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_SET ns_noc_io_spio_soc_ip.csr 22339 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_SET ns_noc_io_spio_soc_ip.csr 22350 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 22361 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 22368 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 22485 spio_p00_dma_am_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 0x10160 R/W 0x0000000054053000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_SET ns_noc_io_spio_soc_ip.csr 22409 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 22420 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_SET ns_noc_io_spio_soc_ip.csr 22431 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 22443 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_SET ns_noc_io_spio_soc_ip.csr 22454 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_SET ns_noc_io_spio_soc_ip.csr 22466 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 22477 BASE_ADDRESS_0_33 Base address 39 6 0x0015014c0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 22484 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 22577 spio_p00_dma_am_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 0x10168 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_SET ns_noc_io_spio_soc_ip.csr 22502 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 22513 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_SET ns_noc_io_spio_soc_ip.csr 22524 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_SET ns_noc_io_spio_soc_ip.csr 22535 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_SET ns_noc_io_spio_soc_ip.csr 22547 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_SET ns_noc_io_spio_soc_ip.csr 22558 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 22569 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 22576 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 22693 spio_p00_dma_am_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 0x10180 R/W 0x0000000054054000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 22617 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 22628 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 22639 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 22651 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_SET ns_noc_io_spio_soc_ip.csr 22662 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_SET ns_noc_io_spio_soc_ip.csr 22674 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 22685 BASE_ADDRESS_0_33 Base address 39 6 0x001501500 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 22692 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 22785 spio_p00_dma_am_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 0x10188 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 22710 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 22721 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 22732 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_SET ns_noc_io_spio_soc_ip.csr 22743 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_SET ns_noc_io_spio_soc_ip.csr 22755 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_SET ns_noc_io_spio_soc_ip.csr 22766 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 22777 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 22784 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 22901 spio_p00_dma_am_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 0x101A0 R/W 0x0000000054055000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_SET ns_noc_io_spio_soc_ip.csr 22825 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_SET ns_noc_io_spio_soc_ip.csr 22836 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_SET ns_noc_io_spio_soc_ip.csr 22847 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 22859 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_SET ns_noc_io_spio_soc_ip.csr 22870 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_SET ns_noc_io_spio_soc_ip.csr 22882 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 22893 BASE_ADDRESS_0_33 Base address 39 6 0x001501540 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 22900 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 22993 spio_p00_dma_am_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 0x101A8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_SET ns_noc_io_spio_soc_ip.csr 22918 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_SET ns_noc_io_spio_soc_ip.csr 22929 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_SET ns_noc_io_spio_soc_ip.csr 22940 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_SET ns_noc_io_spio_soc_ip.csr 22951 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_SET ns_noc_io_spio_soc_ip.csr 22963 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_SET ns_noc_io_spio_soc_ip.csr 22974 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 22985 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 22992 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 23109 spio_p00_dma_am_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 0x101C0 R/W 0x0000000054056000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_SET ns_noc_io_spio_soc_ip.csr 23033 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_SET ns_noc_io_spio_soc_ip.csr 23044 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_SET ns_noc_io_spio_soc_ip.csr 23055 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 23067 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_SET ns_noc_io_spio_soc_ip.csr 23078 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_SET ns_noc_io_spio_soc_ip.csr 23090 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 23101 BASE_ADDRESS_0_33 Base address 39 6 0x001501580 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 23108 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 23201 spio_p00_dma_am_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 0x101C8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_SET ns_noc_io_spio_soc_ip.csr 23126 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_SET ns_noc_io_spio_soc_ip.csr 23137 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_SET ns_noc_io_spio_soc_ip.csr 23148 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_SET ns_noc_io_spio_soc_ip.csr 23159 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_SET ns_noc_io_spio_soc_ip.csr 23171 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_SET ns_noc_io_spio_soc_ip.csr 23182 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 23193 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 23200 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 23317 spio_p00_dma_am_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 0x101E0 R/W 0x0000000054057000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_SET ns_noc_io_spio_soc_ip.csr 23241 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_SET ns_noc_io_spio_soc_ip.csr 23252 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_SET ns_noc_io_spio_soc_ip.csr 23263 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 23275 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_SET ns_noc_io_spio_soc_ip.csr 23286 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_SET ns_noc_io_spio_soc_ip.csr 23298 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 23309 BASE_ADDRESS_0_33 Base address 39 6 0x0015015c0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 23316 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 23409 spio_p00_dma_am_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 0x101E8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_SET ns_noc_io_spio_soc_ip.csr 23334 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_SET ns_noc_io_spio_soc_ip.csr 23345 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_SET ns_noc_io_spio_soc_ip.csr 23356 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_SET ns_noc_io_spio_soc_ip.csr 23367 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_SET ns_noc_io_spio_soc_ip.csr 23379 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_SET ns_noc_io_spio_soc_ip.csr 23390 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 23401 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 23408 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 23525 spio_p00_dma_am_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 0x10200 R/W 0x0000000050000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_SET ns_noc_io_spio_soc_ip.csr 23449 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_SET ns_noc_io_spio_soc_ip.csr 23460 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_SET ns_noc_io_spio_soc_ip.csr 23471 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 23483 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_SET ns_noc_io_spio_soc_ip.csr 23494 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_SET ns_noc_io_spio_soc_ip.csr 23506 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 23517 BASE_ADDRESS_0_33 Base address 39 6 0x001400000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 23524 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 23617 spio_p00_dma_am_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 0x10208 R/W 0x000000fffe000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_SET ns_noc_io_spio_soc_ip.csr 23542 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_SET ns_noc_io_spio_soc_ip.csr 23553 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_SET ns_noc_io_spio_soc_ip.csr 23564 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_SET ns_noc_io_spio_soc_ip.csr 23575 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_SET ns_noc_io_spio_soc_ip.csr 23587 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_SET ns_noc_io_spio_soc_ip.csr 23598 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 23609 MASK_0_33 Mask 39 6 0x3fff80000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 23616 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 23733 spio_p00_dma_am_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 0x10220 R/W 0x0000000052000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 23657 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 23668 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 23679 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 23691 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_SET ns_noc_io_spio_soc_ip.csr 23702 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_SET ns_noc_io_spio_soc_ip.csr 23714 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 23725 BASE_ADDRESS_0_33 Base address 39 6 0x001480000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 23732 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 23825 spio_p00_dma_am_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 0x10228 R/W 0x000000fffffe0000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 23750 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 23761 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 23772 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_SET ns_noc_io_spio_soc_ip.csr 23783 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_SET ns_noc_io_spio_soc_ip.csr 23795 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_SET ns_noc_io_spio_soc_ip.csr 23806 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 23817 MASK_0_33 Mask 39 6 0x3fffff800 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 23824 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 23941 spio_p00_dma_am_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 0x10240 R/W 0x0000000052020000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_SET ns_noc_io_spio_soc_ip.csr 23865 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 23876 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_SET ns_noc_io_spio_soc_ip.csr 23887 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 23899 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_SET ns_noc_io_spio_soc_ip.csr 23910 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_SET ns_noc_io_spio_soc_ip.csr 23922 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 23933 BASE_ADDRESS_0_33 Base address 39 6 0x001480800 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 23940 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 24033 spio_p00_dma_am_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 0x10248 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_SET ns_noc_io_spio_soc_ip.csr 23958 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 23969 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_SET ns_noc_io_spio_soc_ip.csr 23980 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_SET ns_noc_io_spio_soc_ip.csr 23991 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_SET ns_noc_io_spio_soc_ip.csr 24003 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_SET ns_noc_io_spio_soc_ip.csr 24014 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 24025 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 24032 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 24149 spio_p00_dma_am_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 0x10260 R/W 0x0000000052021000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_SET ns_noc_io_spio_soc_ip.csr 24073 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 24084 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_SET ns_noc_io_spio_soc_ip.csr 24095 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 24107 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_SET ns_noc_io_spio_soc_ip.csr 24118 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_SET ns_noc_io_spio_soc_ip.csr 24130 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 24141 BASE_ADDRESS_0_33 Base address 39 6 0x001480840 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 24148 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 24241 spio_p00_dma_am_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 0x10268 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_SET ns_noc_io_spio_soc_ip.csr 24166 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 24177 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_SET ns_noc_io_spio_soc_ip.csr 24188 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_SET ns_noc_io_spio_soc_ip.csr 24199 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_SET ns_noc_io_spio_soc_ip.csr 24211 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_SET ns_noc_io_spio_soc_ip.csr 24222 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 24233 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 24240 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 24357 spio_p00_dma_am_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 0x10280 R/W 0x0000000052022000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_SET ns_noc_io_spio_soc_ip.csr 24281 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 24292 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_SET ns_noc_io_spio_soc_ip.csr 24303 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 24315 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_SET ns_noc_io_spio_soc_ip.csr 24326 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_SET ns_noc_io_spio_soc_ip.csr 24338 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 24349 BASE_ADDRESS_0_33 Base address 39 6 0x001480880 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 24356 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 24449 spio_p00_dma_am_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 0x10288 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_SET ns_noc_io_spio_soc_ip.csr 24374 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 24385 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_SET ns_noc_io_spio_soc_ip.csr 24396 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_SET ns_noc_io_spio_soc_ip.csr 24407 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_SET ns_noc_io_spio_soc_ip.csr 24419 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_SET ns_noc_io_spio_soc_ip.csr 24430 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 24441 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 24448 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 24565 spio_p00_dma_am_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 0x102A0 R/W 0x0000000052023000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 24489 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 24500 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 24511 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 24523 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 24534 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 24546 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 24557 BASE_ADDRESS_0_33 Base address 39 6 0x0014808c0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 24564 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 24657 spio_p00_dma_am_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 0x102A8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 24582 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 24593 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 24604 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 24615 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 24627 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 24638 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 24649 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 24656 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 24773 spio_p00_dma_am_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 0x102C0 R/W 0x0000000052024000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_SET ns_noc_io_spio_soc_ip.csr 24697 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 24708 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_SET ns_noc_io_spio_soc_ip.csr 24719 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 24731 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_SET ns_noc_io_spio_soc_ip.csr 24742 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_SET ns_noc_io_spio_soc_ip.csr 24754 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 24765 BASE_ADDRESS_0_33 Base address 39 6 0x001480900 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 24772 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 24865 spio_p00_dma_am_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 0x102C8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_SET ns_noc_io_spio_soc_ip.csr 24790 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 24801 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_SET ns_noc_io_spio_soc_ip.csr 24812 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_SET ns_noc_io_spio_soc_ip.csr 24823 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_SET ns_noc_io_spio_soc_ip.csr 24835 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_SET ns_noc_io_spio_soc_ip.csr 24846 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 24857 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 24864 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 24981 spio_p00_dma_am_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 0x102E0 R/W 0x0000000052025000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_SET ns_noc_io_spio_soc_ip.csr 24905 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 24916 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_SET ns_noc_io_spio_soc_ip.csr 24927 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 24939 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_SET ns_noc_io_spio_soc_ip.csr 24950 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_SET ns_noc_io_spio_soc_ip.csr 24962 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 24973 BASE_ADDRESS_0_33 Base address 39 6 0x001480940 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 24980 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 25073 spio_p00_dma_am_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 0x102E8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_SET ns_noc_io_spio_soc_ip.csr 24998 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 25009 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_SET ns_noc_io_spio_soc_ip.csr 25020 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_SET ns_noc_io_spio_soc_ip.csr 25031 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_SET ns_noc_io_spio_soc_ip.csr 25043 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_SET ns_noc_io_spio_soc_ip.csr 25054 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 25065 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 25072 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 25189 spio_p00_dma_am_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 0x10300 R/W 0x0000000052026000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_SET ns_noc_io_spio_soc_ip.csr 25113 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 25124 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_SET ns_noc_io_spio_soc_ip.csr 25135 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 25147 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_SET ns_noc_io_spio_soc_ip.csr 25158 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_SET ns_noc_io_spio_soc_ip.csr 25170 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 25181 BASE_ADDRESS_0_33 Base address 39 6 0x001480980 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 25188 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 25281 spio_p00_dma_am_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 0x10308 R/W 0x000000ffffffe000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_SET ns_noc_io_spio_soc_ip.csr 25206 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 25217 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_SET ns_noc_io_spio_soc_ip.csr 25228 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_SET ns_noc_io_spio_soc_ip.csr 25239 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_SET ns_noc_io_spio_soc_ip.csr 25251 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_SET ns_noc_io_spio_soc_ip.csr 25262 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 25273 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 25280 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 25397 spio_p00_dma_am_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 0x10320 R/W 0x0000000052028000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_SET ns_noc_io_spio_soc_ip.csr 25321 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 25332 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_SET ns_noc_io_spio_soc_ip.csr 25343 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 25355 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_SET ns_noc_io_spio_soc_ip.csr 25366 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_SET ns_noc_io_spio_soc_ip.csr 25378 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 25389 BASE_ADDRESS_0_33 Base address 39 6 0x001480a00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 25396 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 25489 spio_p00_dma_am_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 0x10328 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_SET ns_noc_io_spio_soc_ip.csr 25414 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 25425 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_SET ns_noc_io_spio_soc_ip.csr 25436 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_SET ns_noc_io_spio_soc_ip.csr 25447 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_SET ns_noc_io_spio_soc_ip.csr 25459 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_SET ns_noc_io_spio_soc_ip.csr 25470 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 25481 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 25488 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 25605 spio_p00_dma_am_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 0x10340 R/W 0x0000000052029000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_SET ns_noc_io_spio_soc_ip.csr 25529 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 25540 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_SET ns_noc_io_spio_soc_ip.csr 25551 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 25563 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_SET ns_noc_io_spio_soc_ip.csr 25574 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_SET ns_noc_io_spio_soc_ip.csr 25586 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 25597 BASE_ADDRESS_0_33 Base address 39 6 0x001480a40 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 25604 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 25697 spio_p00_dma_am_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 0x10348 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_SET ns_noc_io_spio_soc_ip.csr 25622 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 25633 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_SET ns_noc_io_spio_soc_ip.csr 25644 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_SET ns_noc_io_spio_soc_ip.csr 25655 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_SET ns_noc_io_spio_soc_ip.csr 25667 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_SET ns_noc_io_spio_soc_ip.csr 25678 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 25689 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 25696 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 25813 spio_p00_dma_am_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 0x10360 R/W 0x0000000054058000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_SET ns_noc_io_spio_soc_ip.csr 25737 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_SET ns_noc_io_spio_soc_ip.csr 25748 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_SET ns_noc_io_spio_soc_ip.csr 25759 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 25771 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_SET ns_noc_io_spio_soc_ip.csr 25782 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_SET ns_noc_io_spio_soc_ip.csr 25794 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 25805 BASE_ADDRESS_0_33 Base address 39 6 0x001501600 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 25812 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 25905 spio_p00_dma_am_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 0x10368 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_SET ns_noc_io_spio_soc_ip.csr 25830 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_SET ns_noc_io_spio_soc_ip.csr 25841 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_SET ns_noc_io_spio_soc_ip.csr 25852 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_SET ns_noc_io_spio_soc_ip.csr 25863 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_SET ns_noc_io_spio_soc_ip.csr 25875 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_SET ns_noc_io_spio_soc_ip.csr 25886 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 25897 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 25904 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 26021 spio_p00_dma_am_m register am_adbase_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 0x10380 R/W 0x0000000040300000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 25945 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 25956 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 25967 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 25979 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 25990 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 26002 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 26013 BASE_ADDRESS_0_33 Base address 39 6 0x00100c000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 26020 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 26113 spio_p00_dma_am_m register am_admask_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 0x10388 R/W 0x000000fffff00000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 26038 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 26049 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 26060 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 26071 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 26083 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 26094 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 26105 MASK_0_33 Mask 39 6 0x3ffffc000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 26112 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 26229 spio_p00_dma_am_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 0x103A0 R/W 0x0000000058200000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 26153 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 26164 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 26175 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 26187 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 26198 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 26210 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 26221 BASE_ADDRESS_0_33 Base address 39 6 0x001608000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 26228 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 26321 spio_p00_dma_am_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 0x103A8 R/W 0x000000ffffffe000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 26246 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 26257 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 26268 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 26279 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 26291 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 26302 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 26313 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 26320 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 26437 spio_p00_dma_am_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 0x103C0 R/W 0x0000000058400000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_SET ns_noc_io_spio_soc_ip.csr 26361 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 26372 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_SET ns_noc_io_spio_soc_ip.csr 26383 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 26395 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_SET ns_noc_io_spio_soc_ip.csr 26406 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_SET ns_noc_io_spio_soc_ip.csr 26418 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 26429 BASE_ADDRESS_0_33 Base address 39 6 0x001610000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 26436 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 26529 spio_p00_dma_am_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 0x103C8 R/W 0x000000ffffe00000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_SET ns_noc_io_spio_soc_ip.csr 26454 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 26465 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_SET ns_noc_io_spio_soc_ip.csr 26476 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_SET ns_noc_io_spio_soc_ip.csr 26487 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_SET ns_noc_io_spio_soc_ip.csr 26499 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_SET ns_noc_io_spio_soc_ip.csr 26510 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 26521 MASK_0_33 Mask 39 6 0x3ffff8000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 26528 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 26645 spio_p00_dma_am_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 0x103E0 R/W 0x0000004000000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_SET ns_noc_io_spio_soc_ip.csr 26569 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 26580 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_SET ns_noc_io_spio_soc_ip.csr 26591 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 26603 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_SET ns_noc_io_spio_soc_ip.csr 26614 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_SET ns_noc_io_spio_soc_ip.csr 26626 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 26637 BASE_ADDRESS_0_33 Base address 39 6 0x100000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 26644 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 26737 spio_p00_dma_am_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 0x103E8 R/W 0x000000e000000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_SET ns_noc_io_spio_soc_ip.csr 26662 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 26673 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_SET ns_noc_io_spio_soc_ip.csr 26684 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_SET ns_noc_io_spio_soc_ip.csr 26695 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_SET ns_noc_io_spio_soc_ip.csr 26707 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_SET ns_noc_io_spio_soc_ip.csr 26718 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 26729 MASK_0_33 Mask 39 6 0x380000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 26736 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 26853 spio_p00_dma_am_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 0x10400 R/W 0x0000006000000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_SET ns_noc_io_spio_soc_ip.csr 26777 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 26788 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_SET ns_noc_io_spio_soc_ip.csr 26799 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 26811 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_SET ns_noc_io_spio_soc_ip.csr 26822 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_SET ns_noc_io_spio_soc_ip.csr 26834 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 26845 BASE_ADDRESS_0_33 Base address 39 6 0x180000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 26852 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 26945 spio_p00_dma_am_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 0x10408 R/W 0x000000f000000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_SET ns_noc_io_spio_soc_ip.csr 26870 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 26881 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_SET ns_noc_io_spio_soc_ip.csr 26892 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_SET ns_noc_io_spio_soc_ip.csr 26903 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_SET ns_noc_io_spio_soc_ip.csr 26915 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_SET ns_noc_io_spio_soc_ip.csr 26926 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 26937 MASK_0_33 Mask 39 6 0x3c0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 26944 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 27061 spio_p00_dma_am_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 0x10420 R/W 0x0000007000000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_SET ns_noc_io_spio_soc_ip.csr 26985 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 26996 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_SET ns_noc_io_spio_soc_ip.csr 27007 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 27019 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_SET ns_noc_io_spio_soc_ip.csr 27030 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_SET ns_noc_io_spio_soc_ip.csr 27042 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 27053 BASE_ADDRESS_0_33 Base address 39 6 0x1c0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 27060 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 27153 spio_p00_dma_am_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 0x10428 R/W 0x000000f800000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_SET ns_noc_io_spio_soc_ip.csr 27078 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 27089 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_SET ns_noc_io_spio_soc_ip.csr 27100 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_SET ns_noc_io_spio_soc_ip.csr 27111 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_SET ns_noc_io_spio_soc_ip.csr 27123 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_SET ns_noc_io_spio_soc_ip.csr 27134 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 27145 MASK_0_33 Mask 39 6 0x3e0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 27152 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 27269 spio_p00_dma_am_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 0x10440 R/W 0x0000007800000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_SET ns_noc_io_spio_soc_ip.csr 27193 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 27204 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_SET ns_noc_io_spio_soc_ip.csr 27215 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 27227 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_SET ns_noc_io_spio_soc_ip.csr 27238 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_SET ns_noc_io_spio_soc_ip.csr 27250 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 27261 BASE_ADDRESS_0_33 Base address 39 6 0x1e0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 27268 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 27361 spio_p00_dma_am_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 0x10448 R/W 0x000000fc00000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_SET ns_noc_io_spio_soc_ip.csr 27286 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 27297 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_SET ns_noc_io_spio_soc_ip.csr 27308 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_SET ns_noc_io_spio_soc_ip.csr 27319 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_SET ns_noc_io_spio_soc_ip.csr 27331 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_SET ns_noc_io_spio_soc_ip.csr 27342 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 27353 MASK_0_33 Mask 39 6 0x3f0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 27360 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 27477 spio_p00_dma_am_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 0x10460 R/W 0x0000007c00000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_SET ns_noc_io_spio_soc_ip.csr 27401 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 27412 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_SET ns_noc_io_spio_soc_ip.csr 27423 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 27435 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_SET ns_noc_io_spio_soc_ip.csr 27446 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_SET ns_noc_io_spio_soc_ip.csr 27458 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 27469 BASE_ADDRESS_0_33 Base address 39 6 0x1f0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 27476 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 27569 spio_p00_dma_am_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 0x10468 R/W 0x000000fe00000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_SET ns_noc_io_spio_soc_ip.csr 27494 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 27505 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_SET ns_noc_io_spio_soc_ip.csr 27516 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_SET ns_noc_io_spio_soc_ip.csr 27527 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_SET ns_noc_io_spio_soc_ip.csr 27539 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_SET ns_noc_io_spio_soc_ip.csr 27550 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 27561 MASK_0_33 Mask 39 6 0x3f8000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 27568 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 27685 spio_p00_dma_am_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 0x10480 R/W 0x0000007e00000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_SET ns_noc_io_spio_soc_ip.csr 27609 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 27620 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_SET ns_noc_io_spio_soc_ip.csr 27631 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 27643 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_SET ns_noc_io_spio_soc_ip.csr 27654 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_SET ns_noc_io_spio_soc_ip.csr 27666 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 27677 BASE_ADDRESS_0_33 Base address 39 6 0x1f8000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 27684 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 27777 spio_p00_dma_am_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 0x10488 R/W 0x000000ff00000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_SET ns_noc_io_spio_soc_ip.csr 27702 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 27713 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_SET ns_noc_io_spio_soc_ip.csr 27724 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_SET ns_noc_io_spio_soc_ip.csr 27735 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_SET ns_noc_io_spio_soc_ip.csr 27747 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_SET ns_noc_io_spio_soc_ip.csr 27758 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 27769 MASK_0_33 Mask 39 6 0x3fc000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 27776 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 27893 spio_p00_dma_am_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 0x104A0 R/W 0x0000007f00000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_SET ns_noc_io_spio_soc_ip.csr 27817 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 27828 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_SET ns_noc_io_spio_soc_ip.csr 27839 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 27851 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_SET ns_noc_io_spio_soc_ip.csr 27862 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_SET ns_noc_io_spio_soc_ip.csr 27874 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 27885 BASE_ADDRESS_0_33 Base address 39 6 0x1fc000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 27892 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 27985 spio_p00_dma_am_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 0x104A8 R/W 0x000000ff80000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_SET ns_noc_io_spio_soc_ip.csr 27910 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 27921 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_SET ns_noc_io_spio_soc_ip.csr 27932 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_SET ns_noc_io_spio_soc_ip.csr 27943 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_SET ns_noc_io_spio_soc_ip.csr 27955 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_SET ns_noc_io_spio_soc_ip.csr 27966 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 27977 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 27984 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 28101 spio_p00_dma_am_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 0x104C0 R/W 0x0000007f80000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 28025 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 28036 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 28047 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 28059 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_SET ns_noc_io_spio_soc_ip.csr 28070 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_SET ns_noc_io_spio_soc_ip.csr 28082 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 28093 BASE_ADDRESS_0_33 Base address 39 6 0x1fe000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 28100 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 28193 spio_p00_dma_am_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 0x104C8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 28118 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 28129 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 28140 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_SET ns_noc_io_spio_soc_ip.csr 28151 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_SET ns_noc_io_spio_soc_ip.csr 28163 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_SET ns_noc_io_spio_soc_ip.csr 28174 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 28185 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 28192 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 28309 spio_p00_dma_am_m register am_adbase_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 0x104E0 R/W 0x0000000052100000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 28233 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 28244 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 28255 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 28267 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 28278 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 28290 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 28301 BASE_ADDRESS_0_33 Base address 39 6 0x001484000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 28308 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 28401 spio_p00_dma_am_m register am_admask_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 0x104E8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 28326 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 28337 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 28348 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 28359 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 28371 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 28382 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 28393 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 28400 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 28517 spio_p00_dma_am_m register am_adbase_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 0x10500 R/W 0x0000000042000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 28441 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 28452 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 28463 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 28475 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 28486 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 28498 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 28509 BASE_ADDRESS_0_33 Base address 39 6 0x001080000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 28516 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 28609 spio_p00_dma_am_m register am_admask_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 0x10508 R/W 0x000000fffe000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 28534 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 28545 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 28556 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 28567 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 28579 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 28590 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 28601 MASK_0_33 Mask 39 6 0x3fff80000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 28608 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 28725 spio_p00_dma_am_m register am_adbase_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 0x10520 R/W 0x0000000040200000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 28649 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 28660 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 28671 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 28683 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 28694 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 28706 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 28717 BASE_ADDRESS_0_33 Base address 39 6 0x001008000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 28724 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 28817 spio_p00_dma_am_m register am_admask_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 0x10528 R/W 0x000000fffff00000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 28742 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 28753 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 28764 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 28775 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 28787 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 28798 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 28809 MASK_0_33 Mask 39 6 0x3ffffc000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 28816 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 28933 spio_p00_dma_am_m register am_adbase_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 0x10540 R/W 0x0000000040400000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 28857 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 28868 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 28879 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 28891 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 28902 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 28914 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 28925 BASE_ADDRESS_0_33 Base address 39 6 0x001010000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 28932 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 29025 spio_p00_dma_am_m register am_admask_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 0x10548 R/W 0x000000fffff00000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 28950 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 28961 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 28972 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 28983 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 28995 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 29006 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 29017 MASK_0_33 Mask 39 6 0x3ffffc000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 29024 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 29141 spio_p00_dma_am_m register am_adbase_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 0x10560 R/W 0x0000000040000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 29065 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 29076 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 29087 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 29099 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 29110 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 29122 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 29133 BASE_ADDRESS_0_33 Base address 39 6 0x001000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 29140 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 29233 spio_p00_dma_am_m register am_admask_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 0x10568 R/W 0x000000ffffff0000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 29158 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 29169 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 29180 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 29191 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 29203 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 29214 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 29225 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 29232 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 29349 spio_p00_dma_am_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 0x10580 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 29273 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 29284 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 29295 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 29307 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 29318 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 29330 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 29341 BASE_ADDRESS_0_33 Base address 39 6 0x000000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 29348 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 29441 spio_p00_dma_am_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 0x10588 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 29366 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 29377 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 29388 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 29399 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 29411 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 29422 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 29433 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 29440 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 29557 spio_p00_dma_am_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 0x105A0 R/W 0x0000000000003000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_SET ns_noc_io_spio_soc_ip.csr 29481 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 29492 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_SET ns_noc_io_spio_soc_ip.csr 29503 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 29515 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_SET ns_noc_io_spio_soc_ip.csr 29526 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_SET ns_noc_io_spio_soc_ip.csr 29538 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 29549 BASE_ADDRESS_0_33 Base address 39 6 0x0000000c0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 29556 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 29649 spio_p00_dma_am_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 0x105A8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_SET ns_noc_io_spio_soc_ip.csr 29574 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 29585 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_SET ns_noc_io_spio_soc_ip.csr 29596 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_SET ns_noc_io_spio_soc_ip.csr 29607 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_SET ns_noc_io_spio_soc_ip.csr 29619 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_SET ns_noc_io_spio_soc_ip.csr 29630 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 29641 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 29648 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 29765 spio_p00_dma_am_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 0x105C0 R/W 0x0000000000010000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_SET ns_noc_io_spio_soc_ip.csr 29689 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 29700 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_SET ns_noc_io_spio_soc_ip.csr 29711 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 29723 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_SET ns_noc_io_spio_soc_ip.csr 29734 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_SET ns_noc_io_spio_soc_ip.csr 29746 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 29757 BASE_ADDRESS_0_33 Base address 39 6 0x000000400 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 29764 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 29857 spio_p00_dma_am_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 0x105C8 R/W 0x000000ffffffe000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_SET ns_noc_io_spio_soc_ip.csr 29782 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 29793 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_SET ns_noc_io_spio_soc_ip.csr 29804 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_SET ns_noc_io_spio_soc_ip.csr 29815 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_SET ns_noc_io_spio_soc_ip.csr 29827 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_SET ns_noc_io_spio_soc_ip.csr 29838 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 29849 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 29856 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 29973 spio_p00_dma_am_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 0x105E0 R/W 0x0000000000100000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_SET ns_noc_io_spio_soc_ip.csr 29897 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 29908 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_SET ns_noc_io_spio_soc_ip.csr 29919 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 29931 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_SET ns_noc_io_spio_soc_ip.csr 29942 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_SET ns_noc_io_spio_soc_ip.csr 29954 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 29965 BASE_ADDRESS_0_33 Base address 39 6 0x000004000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 29972 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 30065 spio_p00_dma_am_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 0x105E8 R/W 0x000000ffffff8000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_SET ns_noc_io_spio_soc_ip.csr 29990 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 30001 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_SET ns_noc_io_spio_soc_ip.csr 30012 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_SET ns_noc_io_spio_soc_ip.csr 30023 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_SET ns_noc_io_spio_soc_ip.csr 30035 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_SET ns_noc_io_spio_soc_ip.csr 30046 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 30057 MASK_0_33 Mask 39 6 0x3fffffe00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 30064 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 30181 spio_p00_dma_am_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 0x10600 R/W 0x0000000000200000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_SET ns_noc_io_spio_soc_ip.csr 30105 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 30116 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_SET ns_noc_io_spio_soc_ip.csr 30127 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 30139 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_SET ns_noc_io_spio_soc_ip.csr 30150 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_SET ns_noc_io_spio_soc_ip.csr 30162 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 30173 BASE_ADDRESS_0_33 Base address 39 6 0x000008000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 30180 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 30273 spio_p00_dma_am_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 0x10608 R/W 0x000000ffffffc000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_SET ns_noc_io_spio_soc_ip.csr 30198 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 30209 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_SET ns_noc_io_spio_soc_ip.csr 30220 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_SET ns_noc_io_spio_soc_ip.csr 30231 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_SET ns_noc_io_spio_soc_ip.csr 30243 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_SET ns_noc_io_spio_soc_ip.csr 30254 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 30265 MASK_0_33 Mask 39 6 0x3ffffff00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 30272 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 30389 spio_p00_dma_am_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 0x10620 R/W 0x0000000000300000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_SET ns_noc_io_spio_soc_ip.csr 30313 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 30324 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_SET ns_noc_io_spio_soc_ip.csr 30335 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 30347 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_SET ns_noc_io_spio_soc_ip.csr 30358 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_SET ns_noc_io_spio_soc_ip.csr 30370 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 30381 BASE_ADDRESS_0_33 Base address 39 6 0x00000c000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 30388 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 30481 spio_p00_dma_am_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 0x10628 R/W 0x000000ffffffc000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_SET ns_noc_io_spio_soc_ip.csr 30406 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 30417 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_SET ns_noc_io_spio_soc_ip.csr 30428 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_SET ns_noc_io_spio_soc_ip.csr 30439 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_SET ns_noc_io_spio_soc_ip.csr 30451 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_SET ns_noc_io_spio_soc_ip.csr 30462 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 30473 MASK_0_33 Mask 39 6 0x3ffffff00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 30480 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 30597 spio_p00_dma_am_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 0x10640 R/W 0x0000000002000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_SET ns_noc_io_spio_soc_ip.csr 30521 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 30532 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_SET ns_noc_io_spio_soc_ip.csr 30543 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 30555 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_SET ns_noc_io_spio_soc_ip.csr 30566 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_SET ns_noc_io_spio_soc_ip.csr 30578 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 30589 BASE_ADDRESS_0_33 Base address 39 6 0x000080000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 30596 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 30689 spio_p00_dma_am_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 0x10648 R/W 0x000000ffffff0000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_SET ns_noc_io_spio_soc_ip.csr 30614 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 30625 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_SET ns_noc_io_spio_soc_ip.csr 30636 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_SET ns_noc_io_spio_soc_ip.csr 30647 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_SET ns_noc_io_spio_soc_ip.csr 30659 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_SET ns_noc_io_spio_soc_ip.csr 30670 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 30681 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 30688 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 30805 spio_p00_dma_am_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 0x10660 R/W 0x0000000010000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_SET ns_noc_io_spio_soc_ip.csr 30729 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 30740 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_SET ns_noc_io_spio_soc_ip.csr 30751 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 30763 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_SET ns_noc_io_spio_soc_ip.csr 30774 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_SET ns_noc_io_spio_soc_ip.csr 30786 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 30797 BASE_ADDRESS_0_33 Base address 39 6 0x000400000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 30804 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 30897 spio_p00_dma_am_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 0x10668 R/W 0x000000fffe000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_SET ns_noc_io_spio_soc_ip.csr 30822 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 30833 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_SET ns_noc_io_spio_soc_ip.csr 30844 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_SET ns_noc_io_spio_soc_ip.csr 30855 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_SET ns_noc_io_spio_soc_ip.csr 30867 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_SET ns_noc_io_spio_soc_ip.csr 30878 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 30889 MASK_0_33 Mask 39 6 0x3fff80000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 30896 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 31013 spio_p00_dma_am_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 0x10680 R/W 0x0000000012000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_SET ns_noc_io_spio_soc_ip.csr 30937 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 30948 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_SET ns_noc_io_spio_soc_ip.csr 30959 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 30971 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_SET ns_noc_io_spio_soc_ip.csr 30982 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_SET ns_noc_io_spio_soc_ip.csr 30994 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 31005 BASE_ADDRESS_0_33 Base address 39 6 0x000480000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 31012 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 31105 spio_p00_dma_am_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 0x10688 R/W 0x000000ffffff8000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_SET ns_noc_io_spio_soc_ip.csr 31030 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 31041 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_SET ns_noc_io_spio_soc_ip.csr 31052 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_SET ns_noc_io_spio_soc_ip.csr 31063 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_SET ns_noc_io_spio_soc_ip.csr 31075 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_SET ns_noc_io_spio_soc_ip.csr 31086 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 31097 MASK_0_33 Mask 39 6 0x3fffffe00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 31104 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 31221 spio_p00_dma_am_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 0x106A0 R/W 0x0000000012008000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 31145 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 31156 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 31167 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 31179 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_SET ns_noc_io_spio_soc_ip.csr 31190 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_SET ns_noc_io_spio_soc_ip.csr 31202 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 31213 BASE_ADDRESS_0_33 Base address 39 6 0x000480200 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 31220 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 31313 spio_p00_dma_am_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 0x106A8 R/W 0x000000ffffffe000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 31238 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 31249 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 31260 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_SET ns_noc_io_spio_soc_ip.csr 31271 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_SET ns_noc_io_spio_soc_ip.csr 31283 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_SET ns_noc_io_spio_soc_ip.csr 31294 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 31305 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 31312 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 31429 spio_p00_dma_am_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 0x106C0 R/W 0x000000001200a000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_SET ns_noc_io_spio_soc_ip.csr 31353 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_SET ns_noc_io_spio_soc_ip.csr 31364 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_SET ns_noc_io_spio_soc_ip.csr 31375 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 31387 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_SET ns_noc_io_spio_soc_ip.csr 31398 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_SET ns_noc_io_spio_soc_ip.csr 31410 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 31421 BASE_ADDRESS_0_33 Base address 39 6 0x000480280 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 31428 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 31521 spio_p00_dma_am_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 0x106C8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_SET ns_noc_io_spio_soc_ip.csr 31446 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_SET ns_noc_io_spio_soc_ip.csr 31457 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_SET ns_noc_io_spio_soc_ip.csr 31468 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_SET ns_noc_io_spio_soc_ip.csr 31479 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_SET ns_noc_io_spio_soc_ip.csr 31491 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_SET ns_noc_io_spio_soc_ip.csr 31502 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 31513 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 31520 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 31637 spio_p00_dma_am_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 0x106E0 R/W 0x0000000014000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_SET ns_noc_io_spio_soc_ip.csr 31561 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_SET ns_noc_io_spio_soc_ip.csr 31572 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_SET ns_noc_io_spio_soc_ip.csr 31583 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 31595 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_SET ns_noc_io_spio_soc_ip.csr 31606 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_SET ns_noc_io_spio_soc_ip.csr 31618 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 31629 BASE_ADDRESS_0_33 Base address 39 6 0x000500000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 31636 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 31729 spio_p00_dma_am_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 0x106E8 R/W 0x000000fffffc0000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_SET ns_noc_io_spio_soc_ip.csr 31654 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_SET ns_noc_io_spio_soc_ip.csr 31665 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_SET ns_noc_io_spio_soc_ip.csr 31676 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_SET ns_noc_io_spio_soc_ip.csr 31687 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_SET ns_noc_io_spio_soc_ip.csr 31699 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_SET ns_noc_io_spio_soc_ip.csr 31710 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 31721 MASK_0_33 Mask 39 6 0x3fffff000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 31728 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 31845 spio_p00_dma_am_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 0x10700 R/W 0x0000000018000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_SET ns_noc_io_spio_soc_ip.csr 31769 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_SET ns_noc_io_spio_soc_ip.csr 31780 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_SET ns_noc_io_spio_soc_ip.csr 31791 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 31803 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_SET ns_noc_io_spio_soc_ip.csr 31814 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_SET ns_noc_io_spio_soc_ip.csr 31826 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 31837 BASE_ADDRESS_0_33 Base address 39 6 0x000600000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 31844 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 31937 spio_p00_dma_am_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 0x10708 R/W 0x000000fffff80000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_SET ns_noc_io_spio_soc_ip.csr 31862 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_SET ns_noc_io_spio_soc_ip.csr 31873 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_SET ns_noc_io_spio_soc_ip.csr 31884 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_SET ns_noc_io_spio_soc_ip.csr 31895 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_SET ns_noc_io_spio_soc_ip.csr 31907 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_SET ns_noc_io_spio_soc_ip.csr 31918 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 31929 MASK_0_33 Mask 39 6 0x3ffffe000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 31936 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 32053 spio_p00_dma_am_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 0x10720 R/W 0x0000000018080000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_SET ns_noc_io_spio_soc_ip.csr 31977 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_SET ns_noc_io_spio_soc_ip.csr 31988 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_SET ns_noc_io_spio_soc_ip.csr 31999 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 32011 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_SET ns_noc_io_spio_soc_ip.csr 32022 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_SET ns_noc_io_spio_soc_ip.csr 32034 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 32045 BASE_ADDRESS_0_33 Base address 39 6 0x000602000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 32052 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 32145 spio_p00_dma_am_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 0x10728 R/W 0x000000ffffffe000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_SET ns_noc_io_spio_soc_ip.csr 32070 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_SET ns_noc_io_spio_soc_ip.csr 32081 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_SET ns_noc_io_spio_soc_ip.csr 32092 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_SET ns_noc_io_spio_soc_ip.csr 32103 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_SET ns_noc_io_spio_soc_ip.csr 32115 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_SET ns_noc_io_spio_soc_ip.csr 32126 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 32137 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 32144 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 32261 spio_p00_dma_am_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 0x10740 R/W 0x0000000018082000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_SET ns_noc_io_spio_soc_ip.csr 32185 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_SET ns_noc_io_spio_soc_ip.csr 32196 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_SET ns_noc_io_spio_soc_ip.csr 32207 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 32219 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_SET ns_noc_io_spio_soc_ip.csr 32230 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_SET ns_noc_io_spio_soc_ip.csr 32242 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 32253 BASE_ADDRESS_0_33 Base address 39 6 0x000602080 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 32260 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 32353 spio_p00_dma_am_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 0x10748 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_SET ns_noc_io_spio_soc_ip.csr 32278 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_SET ns_noc_io_spio_soc_ip.csr 32289 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_SET ns_noc_io_spio_soc_ip.csr 32300 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_SET ns_noc_io_spio_soc_ip.csr 32311 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_SET ns_noc_io_spio_soc_ip.csr 32323 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_SET ns_noc_io_spio_soc_ip.csr 32334 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 32345 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 32352 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 32469 spio_p00_dma_am_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 0x10760 R/W 0x0000000020000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_SET ns_noc_io_spio_soc_ip.csr 32393 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_SET ns_noc_io_spio_soc_ip.csr 32404 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_SET ns_noc_io_spio_soc_ip.csr 32415 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 32427 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_SET ns_noc_io_spio_soc_ip.csr 32438 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_SET ns_noc_io_spio_soc_ip.csr 32450 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 32461 BASE_ADDRESS_0_33 Base address 39 6 0x000800000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 32468 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 32561 spio_p00_dma_am_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 0x10768 R/W 0x000000fffffc0000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_SET ns_noc_io_spio_soc_ip.csr 32486 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_SET ns_noc_io_spio_soc_ip.csr 32497 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_SET ns_noc_io_spio_soc_ip.csr 32508 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_SET ns_noc_io_spio_soc_ip.csr 32519 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_SET ns_noc_io_spio_soc_ip.csr 32531 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_SET ns_noc_io_spio_soc_ip.csr 32542 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 32553 MASK_0_33 Mask 39 6 0x3fffff000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 32560 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 32677 spio_p00_dma_am_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 0x10780 R/W 0x0000000030000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_SET ns_noc_io_spio_soc_ip.csr 32601 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_SET ns_noc_io_spio_soc_ip.csr 32612 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_SET ns_noc_io_spio_soc_ip.csr 32623 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 32635 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_SET ns_noc_io_spio_soc_ip.csr 32646 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_SET ns_noc_io_spio_soc_ip.csr 32658 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 32669 BASE_ADDRESS_0_33 Base address 39 6 0x000c00000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 32676 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 32769 spio_p00_dma_am_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 0x10788 R/W 0x000000ffffff8000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_SET ns_noc_io_spio_soc_ip.csr 32694 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_SET ns_noc_io_spio_soc_ip.csr 32705 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_SET ns_noc_io_spio_soc_ip.csr 32716 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_SET ns_noc_io_spio_soc_ip.csr 32727 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_SET ns_noc_io_spio_soc_ip.csr 32739 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_SET ns_noc_io_spio_soc_ip.csr 32750 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 32761 MASK_0_33 Mask 39 6 0x3fffffe00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 32768 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 32885 spio_p00_dma_am_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 0x107A0 R/W 0x0000000030008000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_SET ns_noc_io_spio_soc_ip.csr 32809 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_SET ns_noc_io_spio_soc_ip.csr 32820 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_SET ns_noc_io_spio_soc_ip.csr 32831 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 32843 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_SET ns_noc_io_spio_soc_ip.csr 32854 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_SET ns_noc_io_spio_soc_ip.csr 32866 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 32877 BASE_ADDRESS_0_33 Base address 39 6 0x000c00200 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 32884 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 32977 spio_p00_dma_am_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 0x107A8 R/W 0x000000ffffffc000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_SET ns_noc_io_spio_soc_ip.csr 32902 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_SET ns_noc_io_spio_soc_ip.csr 32913 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_SET ns_noc_io_spio_soc_ip.csr 32924 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_SET ns_noc_io_spio_soc_ip.csr 32935 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_SET ns_noc_io_spio_soc_ip.csr 32947 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_SET ns_noc_io_spio_soc_ip.csr 32958 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 32969 MASK_0_33 Mask 39 6 0x3ffffff00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 32976 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 33093 spio_p00_dma_am_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 0x107C0 R/W 0x0000000040080000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_SET ns_noc_io_spio_soc_ip.csr 33017 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_SET ns_noc_io_spio_soc_ip.csr 33028 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_SET ns_noc_io_spio_soc_ip.csr 33039 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 33051 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_SET ns_noc_io_spio_soc_ip.csr 33062 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_SET ns_noc_io_spio_soc_ip.csr 33074 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 33085 BASE_ADDRESS_0_33 Base address 39 6 0x001002000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 33092 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 33185 spio_p00_dma_am_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 0x107C8 R/W 0x000000ffffffe000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_SET ns_noc_io_spio_soc_ip.csr 33110 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_SET ns_noc_io_spio_soc_ip.csr 33121 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_SET ns_noc_io_spio_soc_ip.csr 33132 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_SET ns_noc_io_spio_soc_ip.csr 33143 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_SET ns_noc_io_spio_soc_ip.csr 33155 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_SET ns_noc_io_spio_soc_ip.csr 33166 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 33177 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 33184 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 33301 spio_p00_dma_am_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 0x107E0 R/W 0x0000000058000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_SET ns_noc_io_spio_soc_ip.csr 33225 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_SET ns_noc_io_spio_soc_ip.csr 33236 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_SET ns_noc_io_spio_soc_ip.csr 33247 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 33259 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_SET ns_noc_io_spio_soc_ip.csr 33270 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_SET ns_noc_io_spio_soc_ip.csr 33282 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 33293 BASE_ADDRESS_0_33 Base address 39 6 0x001600000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 33300 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 33393 spio_p00_dma_am_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 0x107E8 R/W 0x000000ffffffe000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_SET ns_noc_io_spio_soc_ip.csr 33318 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_SET ns_noc_io_spio_soc_ip.csr 33329 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_SET ns_noc_io_spio_soc_ip.csr 33340 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_SET ns_noc_io_spio_soc_ip.csr 33351 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_SET ns_noc_io_spio_soc_ip.csr 33363 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_SET ns_noc_io_spio_soc_ip.csr 33374 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 33385 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 33392 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 33509 spio_p00_dma_am_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 0x10800 R/W 0x0000000060000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_SET ns_noc_io_spio_soc_ip.csr 33433 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_SET ns_noc_io_spio_soc_ip.csr 33444 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_SET ns_noc_io_spio_soc_ip.csr 33455 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 33467 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_SET ns_noc_io_spio_soc_ip.csr 33478 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_SET ns_noc_io_spio_soc_ip.csr 33490 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 33501 BASE_ADDRESS_0_33 Base address 39 6 0x001800000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 33508 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 33601 spio_p00_dma_am_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 0x10808 R/W 0x000000ffe0000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_SET ns_noc_io_spio_soc_ip.csr 33526 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_SET ns_noc_io_spio_soc_ip.csr 33537 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_SET ns_noc_io_spio_soc_ip.csr 33548 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_SET ns_noc_io_spio_soc_ip.csr 33559 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_SET ns_noc_io_spio_soc_ip.csr 33571 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_SET ns_noc_io_spio_soc_ip.csr 33582 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 33593 MASK_0_33 Mask 39 6 0x3ff800000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 33600 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 33717 spio_p00_dma_am_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 0x10820 R/W 0x0000000080000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_SET ns_noc_io_spio_soc_ip.csr 33641 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_SET ns_noc_io_spio_soc_ip.csr 33652 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_SET ns_noc_io_spio_soc_ip.csr 33663 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 33675 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_SET ns_noc_io_spio_soc_ip.csr 33686 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_SET ns_noc_io_spio_soc_ip.csr 33698 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 33709 BASE_ADDRESS_0_33 Base address 39 6 0x002000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 33716 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 33809 spio_p00_dma_am_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 0x10828 R/W 0x000000ff80000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_SET ns_noc_io_spio_soc_ip.csr 33734 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_SET ns_noc_io_spio_soc_ip.csr 33745 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_SET ns_noc_io_spio_soc_ip.csr 33756 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_SET ns_noc_io_spio_soc_ip.csr 33767 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_SET ns_noc_io_spio_soc_ip.csr 33779 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_SET ns_noc_io_spio_soc_ip.csr 33790 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 33801 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 33808 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 33925 spio_p00_dma_am_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 0x10840 R/W 0x0000000100000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_SET ns_noc_io_spio_soc_ip.csr 33849 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_SET ns_noc_io_spio_soc_ip.csr 33860 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_SET ns_noc_io_spio_soc_ip.csr 33871 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 33883 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_SET ns_noc_io_spio_soc_ip.csr 33894 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_SET ns_noc_io_spio_soc_ip.csr 33906 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 33917 BASE_ADDRESS_0_33 Base address 39 6 0x004000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 33924 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 34017 spio_p00_dma_am_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 0x10848 R/W 0x000000ff00000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_SET ns_noc_io_spio_soc_ip.csr 33942 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_SET ns_noc_io_spio_soc_ip.csr 33953 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_SET ns_noc_io_spio_soc_ip.csr 33964 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_SET ns_noc_io_spio_soc_ip.csr 33975 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_SET ns_noc_io_spio_soc_ip.csr 33987 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_SET ns_noc_io_spio_soc_ip.csr 33998 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 34009 MASK_0_33 Mask 39 6 0x3fc000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 34016 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 34133 spio_p00_dma_am_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 0x10860 R/W 0x0000008000000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_SET ns_noc_io_spio_soc_ip.csr 34057 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_SET ns_noc_io_spio_soc_ip.csr 34068 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_SET ns_noc_io_spio_soc_ip.csr 34079 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 34091 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_SET ns_noc_io_spio_soc_ip.csr 34102 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_SET ns_noc_io_spio_soc_ip.csr 34114 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 34125 BASE_ADDRESS_0_33 Base address 39 6 0x200000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 34132 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 34225 spio_p00_dma_am_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 0x10868 R/W 0x000000f800000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_SET ns_noc_io_spio_soc_ip.csr 34150 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_SET ns_noc_io_spio_soc_ip.csr 34161 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_SET ns_noc_io_spio_soc_ip.csr 34172 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_SET ns_noc_io_spio_soc_ip.csr 34183 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_SET ns_noc_io_spio_soc_ip.csr 34195 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_SET ns_noc_io_spio_soc_ip.csr 34206 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 34217 MASK_0_33 Mask 39 6 0x3e0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 34224 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 34341 spio_p00_dma_am_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 0x10880 R/W 0x000000c000000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_SET ns_noc_io_spio_soc_ip.csr 34265 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_SET ns_noc_io_spio_soc_ip.csr 34276 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_SET ns_noc_io_spio_soc_ip.csr 34287 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 34299 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_SET ns_noc_io_spio_soc_ip.csr 34310 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_SET ns_noc_io_spio_soc_ip.csr 34322 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 34333 BASE_ADDRESS_0_33 Base address 39 6 0x300000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 34340 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 34433 spio_p00_dma_am_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 0x10888 R/W 0x000000f800000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_SET ns_noc_io_spio_soc_ip.csr 34358 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_SET ns_noc_io_spio_soc_ip.csr 34369 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_SET ns_noc_io_spio_soc_ip.csr 34380 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_SET ns_noc_io_spio_soc_ip.csr 34391 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_SET ns_noc_io_spio_soc_ip.csr 34403 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_SET ns_noc_io_spio_soc_ip.csr 34414 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 34425 MASK_0_33 Mask 39 6 0x3e0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 34432 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_p_0 bridge_spio_p00_dma_am_m_0_7_p_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 34498 spio_p00_dma_am_m register p_0 0x13000 R/W 0x00000003 Spio_noc_bridge_spio_p00_dma_am_m_0_7_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_0_SET ns_noc_io_spio_soc_ip.csr 34461 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_1_SET ns_noc_io_spio_soc_ip.csr 34473 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_2_SET ns_noc_io_spio_soc_ip.csr 34485 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_0_WT_QOS_3_SET ns_noc_io_spio_soc_ip.csr 34497 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_p_1 bridge_spio_p00_dma_am_m_0_7_p_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 34564 spio_p00_dma_am_m register p_1 0x13008 R 0x00000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_4_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_4_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_4_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_4_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_4_SET ns_noc_io_spio_soc_ip.csr 34527 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_5_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_5_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_5_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_5_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_5_SET ns_noc_io_spio_soc_ip.csr 34539 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_6_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_6_SET ns_noc_io_spio_soc_ip.csr 34551 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_7_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_7_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_7_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_7_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_1_WT_QOS_7_SET ns_noc_io_spio_soc_ip.csr 34563 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_p_2 bridge_spio_p00_dma_am_m_0_7_p_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 34630 spio_p00_dma_am_m register p_2 0x13010 R 0x00000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_8_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_8_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_8_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_8_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_8_SET ns_noc_io_spio_soc_ip.csr 34593 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_9_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_9_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_9_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_9_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_9_SET ns_noc_io_spio_soc_ip.csr 34605 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_10_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_10_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_10_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_10_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_10_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_10_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_10_SET ns_noc_io_spio_soc_ip.csr 34617 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_11_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_11_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_11_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_11_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_11_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_2_WT_QOS_11_SET ns_noc_io_spio_soc_ip.csr 34629 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_p_3 bridge_spio_p00_dma_am_m_0_7_p_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 34696 spio_p00_dma_am_m register p_3 0x13018 R 0x00000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_12_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_12_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_12_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_12_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_12_SET ns_noc_io_spio_soc_ip.csr 34659 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_13_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_13_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_13_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_13_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_13_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_13_SET ns_noc_io_spio_soc_ip.csr 34671 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_14_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_14_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_14_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_14_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_14_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_14_SET ns_noc_io_spio_soc_ip.csr 34683 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_15_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_15_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_15_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_15_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_15_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_P_3_WT_QOS_15_SET ns_noc_io_spio_soc_ip.csr 34695 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_txe bridge_spio_p00_dma_am_m_0_7_txe SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 34842 spio_p00_dma_am_m register txe 0x13040 R/W 0x00000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_TRANS_WITHOUT_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_TRANS_WITHOUT_SOP_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_TRANS_WITHOUT_SOP_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_TRANS_WITHOUT_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_TRANS_WITHOUT_SOP_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_TRANS_WITHOUT_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_TRANS_WITHOUT_SOP_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_spio_soc_ip.csr 34723 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_SOP_AFTER_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_SOP_AFTER_SOP_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_SOP_AFTER_SOP_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_SOP_AFTER_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_SOP_AFTER_SOP_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_SOP_AFTER_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_SOP_AFTER_SOP_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_SOP_AFTER_SOP_SET ns_noc_io_spio_soc_ip.csr 34735 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 34750 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 34763 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_spio_soc_ip.csr 34777 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_spio_soc_ip.csr 34791 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_spio_soc_ip.csr 34805 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_spio_soc_ip.csr 34819 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 34830 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXE_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 34841 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_txem bridge_spio_p00_dma_am_m_0_7_txem SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 34921 spio_p00_dma_am_m register txem 0x13048 R/W 0x00000008 Spio_noc_bridge_spio_p00_dma_am_m_0_7_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_UNSD_1_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_UNSD_1_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_UNSD_1_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_UNSD_1_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_UNSD_1_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_UNSD_1_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_UNSD_1_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_UNSD_1_0_SET ns_noc_io_spio_soc_ip.csr 34865 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 34876 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 34887 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_UNSD_7_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_UNSD_7_4_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_UNSD_7_4_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_UNSD_7_4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_UNSD_7_4_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_UNSD_7_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_UNSD_7_4_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_UNSD_7_4_SET ns_noc_io_spio_soc_ip.csr 34898 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 34909 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_TXEM_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 34920 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_btus_0 bridge_spio_p00_dma_am_m_0_7_btus_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 35289 spio_p00_dma_am_m register btus_0 0x13058 R 0x00000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_A_SET ns_noc_io_spio_soc_ip.csr 34947 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_B_SET ns_noc_io_spio_soc_ip.csr 34958 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_C_SET ns_noc_io_spio_soc_ip.csr 34969 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L0_D_SET ns_noc_io_spio_soc_ip.csr 34980 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_A_SET ns_noc_io_spio_soc_ip.csr 34991 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_B_SET ns_noc_io_spio_soc_ip.csr 35002 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_C_SET ns_noc_io_spio_soc_ip.csr 35013 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L1_D_SET ns_noc_io_spio_soc_ip.csr 35024 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_A_SET ns_noc_io_spio_soc_ip.csr 35035 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_B_SET ns_noc_io_spio_soc_ip.csr 35046 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_C_SET ns_noc_io_spio_soc_ip.csr 35057 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L2_D_SET ns_noc_io_spio_soc_ip.csr 35068 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_A_SET ns_noc_io_spio_soc_ip.csr 35079 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_B_SET ns_noc_io_spio_soc_ip.csr 35090 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_C_SET ns_noc_io_spio_soc_ip.csr 35101 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L3_D_SET ns_noc_io_spio_soc_ip.csr 35112 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_A_SET ns_noc_io_spio_soc_ip.csr 35123 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_B_SET ns_noc_io_spio_soc_ip.csr 35134 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_C_SET ns_noc_io_spio_soc_ip.csr 35145 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L4_D_SET ns_noc_io_spio_soc_ip.csr 35156 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_A_SET ns_noc_io_spio_soc_ip.csr 35167 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_B_SET ns_noc_io_spio_soc_ip.csr 35178 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_C_SET ns_noc_io_spio_soc_ip.csr 35189 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L5_D_SET ns_noc_io_spio_soc_ip.csr 35200 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_A_SET ns_noc_io_spio_soc_ip.csr 35211 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_B_SET ns_noc_io_spio_soc_ip.csr 35222 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_C_SET ns_noc_io_spio_soc_ip.csr 35233 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L6_D_SET ns_noc_io_spio_soc_ip.csr 35244 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_A_SET ns_noc_io_spio_soc_ip.csr 35255 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_B_SET ns_noc_io_spio_soc_ip.csr 35266 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_C_SET ns_noc_io_spio_soc_ip.csr 35277 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_0_L7_D_SET ns_noc_io_spio_soc_ip.csr 35288 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_btus_1 bridge_spio_p00_dma_am_m_0_7_btus_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 35657 spio_p00_dma_am_m register btus_1 0x13060 R 0x00000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_A_SET ns_noc_io_spio_soc_ip.csr 35315 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_B_SET ns_noc_io_spio_soc_ip.csr 35326 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_C_SET ns_noc_io_spio_soc_ip.csr 35337 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L8_D_SET ns_noc_io_spio_soc_ip.csr 35348 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_A_SET ns_noc_io_spio_soc_ip.csr 35359 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_B_SET ns_noc_io_spio_soc_ip.csr 35370 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_C_SET ns_noc_io_spio_soc_ip.csr 35381 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L9_D_SET ns_noc_io_spio_soc_ip.csr 35392 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_A_SET ns_noc_io_spio_soc_ip.csr 35403 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_B_SET ns_noc_io_spio_soc_ip.csr 35414 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_C_SET ns_noc_io_spio_soc_ip.csr 35425 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L10_D_SET ns_noc_io_spio_soc_ip.csr 35436 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_A_SET ns_noc_io_spio_soc_ip.csr 35447 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_B_SET ns_noc_io_spio_soc_ip.csr 35458 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_C_SET ns_noc_io_spio_soc_ip.csr 35469 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L11_D_SET ns_noc_io_spio_soc_ip.csr 35480 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_A_SET ns_noc_io_spio_soc_ip.csr 35491 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_B_SET ns_noc_io_spio_soc_ip.csr 35502 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_C_SET ns_noc_io_spio_soc_ip.csr 35513 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L12_D_SET ns_noc_io_spio_soc_ip.csr 35524 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_A_SET ns_noc_io_spio_soc_ip.csr 35535 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_B_SET ns_noc_io_spio_soc_ip.csr 35546 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_C_SET ns_noc_io_spio_soc_ip.csr 35557 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L13_D_SET ns_noc_io_spio_soc_ip.csr 35568 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_A_SET ns_noc_io_spio_soc_ip.csr 35579 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_B_SET ns_noc_io_spio_soc_ip.csr 35590 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_C_SET ns_noc_io_spio_soc_ip.csr 35601 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L14_D_SET ns_noc_io_spio_soc_ip.csr 35612 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_A_SET ns_noc_io_spio_soc_ip.csr 35623 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_B_SET ns_noc_io_spio_soc_ip.csr 35634 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_C_SET ns_noc_io_spio_soc_ip.csr 35645 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTUS_1_L15_D_SET ns_noc_io_spio_soc_ip.csr 35656 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_btrl_0 bridge_spio_p00_dma_am_m_0_7_btrl_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 35733 spio_p00_dma_am_m register btrl_0 0x13080 R 0x00000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_WT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_WT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_WT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_WT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_WT_SET ns_noc_io_spio_soc_ip.csr 35681 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 35692 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_CNT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_CNT_SET ns_noc_io_spio_soc_ip.csr 35707 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_EN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_EN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_EN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_EN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_EN_SET ns_noc_io_spio_soc_ip.csr 35721 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_0_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 35732 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_btrl_1 bridge_spio_p00_dma_am_m_0_7_btrl_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 35809 spio_p00_dma_am_m register btrl_1 0x13088 R 0x00000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_WT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_WT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_WT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_WT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_WT_SET ns_noc_io_spio_soc_ip.csr 35757 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 35768 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_CNT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_CNT_SET ns_noc_io_spio_soc_ip.csr 35783 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_EN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_EN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_EN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_EN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_EN_SET ns_noc_io_spio_soc_ip.csr 35797 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_1_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 35808 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_btrl_2 bridge_spio_p00_dma_am_m_0_7_btrl_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 35885 spio_p00_dma_am_m register btrl_2 0x13090 R 0x00000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_WT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_WT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_WT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_WT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_WT_SET ns_noc_io_spio_soc_ip.csr 35833 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 35844 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_CNT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_CNT_SET ns_noc_io_spio_soc_ip.csr 35859 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_EN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_EN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_EN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_EN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_EN_SET ns_noc_io_spio_soc_ip.csr 35873 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_2_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 35884 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_btrl_3 bridge_spio_p00_dma_am_m_0_7_btrl_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 35961 spio_p00_dma_am_m register btrl_3 0x13098 R 0x00000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_WT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_WT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_WT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_WT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_WT_SET ns_noc_io_spio_soc_ip.csr 35909 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 35920 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_CNT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_CNT_SET ns_noc_io_spio_soc_ip.csr 35935 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_EN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_EN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_EN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_EN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_EN_SET ns_noc_io_spio_soc_ip.csr 35949 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTRL_3_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 35960 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_btperr bridge_spio_p00_dma_am_m_0_7_btperr SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 36163 spio_p00_dma_am_m register btperr 0x130A8 R/W 0x00000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L0_SET ns_noc_io_spio_soc_ip.csr 35986 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L1_SET ns_noc_io_spio_soc_ip.csr 35997 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L2_SET ns_noc_io_spio_soc_ip.csr 36008 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L3_SET ns_noc_io_spio_soc_ip.csr 36019 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L4_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L4_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L4_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L4_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L4_SET ns_noc_io_spio_soc_ip.csr 36030 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L5_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L5_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L5_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L5_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L5_SET ns_noc_io_spio_soc_ip.csr 36041 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L6_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L6_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L6_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L6_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L6_SET ns_noc_io_spio_soc_ip.csr 36052 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L7_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L7_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L7_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L7_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L7_SET ns_noc_io_spio_soc_ip.csr 36063 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L8_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L8_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L8_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L8_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L8_SET ns_noc_io_spio_soc_ip.csr 36074 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L9_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L9_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L9_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L9_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L9_SET ns_noc_io_spio_soc_ip.csr 36085 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L10_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L10_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L10_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L10_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L10_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L10_SET ns_noc_io_spio_soc_ip.csr 36096 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L11_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L11_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L11_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L11_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L11_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L11_SET ns_noc_io_spio_soc_ip.csr 36107 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L12_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L12_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L12_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L12_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L12_SET ns_noc_io_spio_soc_ip.csr 36118 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L13_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L13_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L13_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L13_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L13_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L13_SET ns_noc_io_spio_soc_ip.csr 36129 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L14_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L14_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L14_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L14_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L14_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L14_SET ns_noc_io_spio_soc_ip.csr 36140 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L15_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L15_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L15_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L15_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L15_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_L15_SET ns_noc_io_spio_soc_ip.csr 36151 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_UNSD_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERR_UNSD_SET ns_noc_io_spio_soc_ip.csr 36162 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_btperrm bridge_spio_p00_dma_am_m_0_7_btperrm SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 36363 spio_p00_dma_am_m register btperrm 0x130B0 R/W 0x00000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L0_SET ns_noc_io_spio_soc_ip.csr 36186 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L1_SET ns_noc_io_spio_soc_ip.csr 36197 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L2_SET ns_noc_io_spio_soc_ip.csr 36208 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L3_SET ns_noc_io_spio_soc_ip.csr 36219 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L4_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L4_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L4_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L4_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L4_SET ns_noc_io_spio_soc_ip.csr 36230 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L5_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L5_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L5_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L5_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L5_SET ns_noc_io_spio_soc_ip.csr 36241 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L6_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L6_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L6_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L6_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L6_SET ns_noc_io_spio_soc_ip.csr 36252 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L7_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L7_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L7_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L7_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L7_SET ns_noc_io_spio_soc_ip.csr 36263 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L8_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L8_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L8_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L8_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L8_SET ns_noc_io_spio_soc_ip.csr 36274 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L9_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L9_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L9_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L9_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L9_SET ns_noc_io_spio_soc_ip.csr 36285 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L10_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L10_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L10_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L10_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L10_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L10_SET ns_noc_io_spio_soc_ip.csr 36296 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L11_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L11_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L11_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L11_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L11_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L11_SET ns_noc_io_spio_soc_ip.csr 36307 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L12_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L12_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L12_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L12_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L12_SET ns_noc_io_spio_soc_ip.csr 36318 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L13_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L13_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L13_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L13_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L13_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L13_SET ns_noc_io_spio_soc_ip.csr 36329 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L14_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L14_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L14_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L14_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L14_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L14_SET ns_noc_io_spio_soc_ip.csr 36340 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L15_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L15_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L15_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L15_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L15_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_L15_SET ns_noc_io_spio_soc_ip.csr 36351 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_UNSD_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BTPERRM_UNSD_SET ns_noc_io_spio_soc_ip.csr 36362 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_rxe bridge_spio_p00_dma_am_m_0_7_rxe SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 36471 spio_p00_dma_am_m register rxe 0x13120 R/W 0x00000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_A_SET ns_noc_io_spio_soc_ip.csr 36391 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_B_SET ns_noc_io_spio_soc_ip.csr 36402 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_C_SET ns_noc_io_spio_soc_ip.csr 36413 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_CRC_OFLW_D_SET ns_noc_io_spio_soc_ip.csr 36424 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_EVC_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_EVC_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_EVC_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_EVC_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_EVC_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_EVC_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_EVC_OFLW_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_EVC_OFLW_SET ns_noc_io_spio_soc_ip.csr 36436 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 36447 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_EVC1_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_EVC1_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_EVC1_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_EVC1_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_EVC1_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_EVC1_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_EVC1_OFLW_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_EVC1_OFLW_SET ns_noc_io_spio_soc_ip.csr 36459 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXE_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 36470 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_rxem bridge_spio_p00_dma_am_m_0_7_rxem SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 36543 spio_p00_dma_am_m register rxem 0x13128 R/W 0x00000050 Spio_noc_bridge_spio_p00_dma_am_m_0_7_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_UNSD_3_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_UNSD_3_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_UNSD_3_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_UNSD_3_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_UNSD_3_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_UNSD_3_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_UNSD_3_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_UNSD_3_0_SET ns_noc_io_spio_soc_ip.csr 36492 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_EVC_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_EVC_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_EVC_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_EVC_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_EVC_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_EVC_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_EVC_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_EVC_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 36506 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 36517 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_EVC1_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_EVC1_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_EVC1_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_EVC1_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_EVC1_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_EVC1_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_EVC1_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 36531 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_RXEM_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 36542 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_brs_0 bridge_spio_p00_dma_am_m_0_7_brs_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 36817 spio_p00_dma_am_m register brs_0 0x13130 R 0x00000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 36567 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_0_SET ns_noc_io_spio_soc_ip.csr 36578 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_0_SET ns_noc_io_spio_soc_ip.csr 36589 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_0_SET ns_noc_io_spio_soc_ip.csr 36600 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_0_SET ns_noc_io_spio_soc_ip.csr 36611 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 36621 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 36632 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_1_SET ns_noc_io_spio_soc_ip.csr 36643 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_1_SET ns_noc_io_spio_soc_ip.csr 36654 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_1_SET ns_noc_io_spio_soc_ip.csr 36665 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_1_SET ns_noc_io_spio_soc_ip.csr 36676 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 36686 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 36697 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_2_SET ns_noc_io_spio_soc_ip.csr 36708 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_2_SET ns_noc_io_spio_soc_ip.csr 36719 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_2_SET ns_noc_io_spio_soc_ip.csr 36730 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_2_SET ns_noc_io_spio_soc_ip.csr 36741 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 36751 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 36762 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_V_3_SET ns_noc_io_spio_soc_ip.csr 36773 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_S_3_SET ns_noc_io_spio_soc_ip.csr 36784 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_B_3_SET ns_noc_io_spio_soc_ip.csr 36795 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_F_3_SET ns_noc_io_spio_soc_ip.csr 36806 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_0_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 36816 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_brs_1 bridge_spio_p00_dma_am_m_0_7_brs_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 37091 spio_p00_dma_am_m register brs_1 0x13138 R 0x00000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 36841 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_0_SET ns_noc_io_spio_soc_ip.csr 36852 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_0_SET ns_noc_io_spio_soc_ip.csr 36863 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_0_SET ns_noc_io_spio_soc_ip.csr 36874 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_0_SET ns_noc_io_spio_soc_ip.csr 36885 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 36895 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 36906 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_1_SET ns_noc_io_spio_soc_ip.csr 36917 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_1_SET ns_noc_io_spio_soc_ip.csr 36928 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_1_SET ns_noc_io_spio_soc_ip.csr 36939 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_1_SET ns_noc_io_spio_soc_ip.csr 36950 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 36960 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 36971 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_2_SET ns_noc_io_spio_soc_ip.csr 36982 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_2_SET ns_noc_io_spio_soc_ip.csr 36993 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_2_SET ns_noc_io_spio_soc_ip.csr 37004 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_2_SET ns_noc_io_spio_soc_ip.csr 37015 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 37025 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 37036 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_V_3_SET ns_noc_io_spio_soc_ip.csr 37047 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_S_3_SET ns_noc_io_spio_soc_ip.csr 37058 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_B_3_SET ns_noc_io_spio_soc_ip.csr 37069 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_F_3_SET ns_noc_io_spio_soc_ip.csr 37080 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRS_1_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 37090 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_brus bridge_spio_p00_dma_am_m_0_7_brus SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 37160 spio_p00_dma_am_m register brus 0x131B0 R 0x00000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_A_SET ns_noc_io_spio_soc_ip.csr 37116 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_B_SET ns_noc_io_spio_soc_ip.csr 37127 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_C_SET ns_noc_io_spio_soc_ip.csr 37138 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_V_D_SET ns_noc_io_spio_soc_ip.csr 37149 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_UNSD_31_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_UNSD_31_4_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_UNSD_31_4_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_UNSD_31_4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_UNSD_31_4_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_UNSD_31_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_UNSD_31_4_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRUS_UNSD_31_4_SET ns_noc_io_spio_soc_ip.csr 37159 UNSD_31_4 31 4 0x0000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_brperr0 bridge_spio_p00_dma_am_m_0_7_brperr0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 37388 spio_p00_dma_am_m register brperr0 0x131D0 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_D0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_D0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_D0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_D0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_D0_SET ns_noc_io_spio_soc_ip.csr 37198 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_DC0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_DC0_SET ns_noc_io_spio_soc_ip.csr 37209 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SB0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SB0_SET ns_noc_io_spio_soc_ip.csr 37220 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SBC0_SET ns_noc_io_spio_soc_ip.csr 37232 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_PK0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_PK0_SET ns_noc_io_spio_soc_ip.csr 37243 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 37254 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_D1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_D1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_D1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_D1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_D1_SET ns_noc_io_spio_soc_ip.csr 37265 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_DC1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_DC1_SET ns_noc_io_spio_soc_ip.csr 37276 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SB1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SB1_SET ns_noc_io_spio_soc_ip.csr 37287 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_SBC1_SET ns_noc_io_spio_soc_ip.csr 37299 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_PK1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_PK1_SET ns_noc_io_spio_soc_ip.csr 37310 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 37321 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 37332 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 37343 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 37354 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 37365 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 37376 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 37387 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_brperr1 bridge_spio_p00_dma_am_m_0_7_brperr1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 37504 spio_p00_dma_am_m register brperr1 0x131D8 R 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 37426 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 37437 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 37448 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 37459 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 37470 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 37481 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 37492 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERR1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 37503 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_brperrm0 bridge_spio_p00_dma_am_m_0_7_brperrm0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 37725 spio_p00_dma_am_m register brperrm0 0x131E0 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_D0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_D0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_D0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_D0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_D0_SET ns_noc_io_spio_soc_ip.csr 37531 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_DC0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_DC0_SET ns_noc_io_spio_soc_ip.csr 37543 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SB0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SB0_SET ns_noc_io_spio_soc_ip.csr 37554 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SBC0_SET ns_noc_io_spio_soc_ip.csr 37566 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_PK0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_PK0_SET ns_noc_io_spio_soc_ip.csr 37578 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 37589 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_D1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_D1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_D1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_D1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_D1_SET ns_noc_io_spio_soc_ip.csr 37600 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_DC1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_DC1_SET ns_noc_io_spio_soc_ip.csr 37612 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SB1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SB1_SET ns_noc_io_spio_soc_ip.csr 37623 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_SBC1_SET ns_noc_io_spio_soc_ip.csr 37635 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_PK1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_PK1_SET ns_noc_io_spio_soc_ip.csr 37647 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 37658 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 37669 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 37680 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 37691 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 37702 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 37713 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 37724 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_brperrm1 bridge_spio_p00_dma_am_m_0_7_brperrm1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 37830 spio_p00_dma_am_m register brperrm1 0x131E8 R 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 37752 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 37763 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 37774 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 37785 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 37796 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 37807 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 37818 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_BRPERRM1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 37829 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_tocfg bridge_spio_p00_dma_am_m_0_7_am_tocfg SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 37904 spio_p00_dma_am_m register am_tocfg 0x13C00 R/W 0x000000000000001f Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_tocfg This register is used to configure response timeouts. AM_TOCFG[8] (En) needs to be set for timeout tracking to be enabled. When this bit is 1'b0, no timestamps are recorded to generate timeout interrupts. A 64-bit free running counter is used to time the response interval. AM_TOCFG[5:0] (TI) specifies the lower bit index into this counter, from where 2-bits are picked up and recorded as the arrival time stamp of every incoming AR and AW command. If response for a command does not return before the current time stamp rolls to arrival time stamp minus 1, the response is assumed to have timedout and an interrupt is raised along with the slave ID to which the timed out request was sent. When changing the TI field, first write to the register with the En field cleared, then write a second time with the TI field to its new value, then a 3rd write to restore the En field to Enabled. During this update while the En field is cleared, existing timers will cancelled, and new timer starts will be inhibited. false false false false TI SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_TI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_TI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_TI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_TI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_TI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_TI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_TI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_TI_SET ns_noc_io_spio_soc_ip.csr 37867 TI Timer index, index of a 64-bit counter from where timestamp is picked. The register value has to be 'd62 or smaller. 5 0 0x1f R/W UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 37878 UNSD_7_6 7 6 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_EN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_EN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_EN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_EN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_EN_SET ns_noc_io_spio_soc_ip.csr 37892 EN 1'b1: Enabled timeout tracking, a 64-bit free running counter is used to time the response interval. 1'b0: No timestamps are recorded to generate timeout interrupts 8 8 0x0 R/W UNSD_63_9 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_UNSD_63_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_UNSD_63_9_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_UNSD_63_9_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_UNSD_63_9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_UNSD_63_9_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_UNSD_63_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_UNSD_63_9_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOCFG_UNSD_63_9_SET ns_noc_io_spio_soc_ip.csr 37903 UNSD_63_9 63 9 0x00000000000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_osslv bridge_spio_p00_dma_am_m_0_7_am_osslv SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_OSSLV_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_OSSLV_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_OSSLV_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_OSSLV_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 37939 spio_p00_dma_am_m register am_osslv 0x13C08 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_osslv This register is used to check if there are any outstanding read/write commands to a slave specified by field slvid. NocStudio provides a table of slvids corresponding to the slave ports accessible from a master bridge. Outstanding status is reflected in AM_STS. false false false false SLVID SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_OSSLV_SLVID_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_OSSLV_SLVID_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_OSSLV_SLVID_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_OSSLV_SLVID_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_OSSLV_SLVID_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_OSSLV_SLVID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_OSSLV_SLVID_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_OSSLV_SLVID_SET ns_noc_io_spio_soc_ip.csr 37927 SLVID A slave ID associated with the current master for command outstanding status 15 0 0x0000 R/W UNSD_63_16 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_OSSLV_UNSD_63_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_OSSLV_UNSD_63_16_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_OSSLV_UNSD_63_16_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_OSSLV_UNSD_63_16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_OSSLV_UNSD_63_16_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_OSSLV_UNSD_63_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_OSSLV_UNSD_63_16_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_OSSLV_UNSD_63_16_SET ns_noc_io_spio_soc_ip.csr 37938 UNSD_63_16 63 16 0x000000000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_cgc bridge_spio_p00_dma_am_m_0_7_am_cgc SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGC_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGC_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGC_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 37976 spio_p00_dma_am_m register am_cgc 0x13C10 R/W 0x0000000000000064 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_cgc Programmable interval used by coarse clock gating logic in master bridge.This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGC_HYSTERESIS_COUNTER_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGC_HYSTERESIS_COUNTER_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGC_HYSTERESIS_COUNTER_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGC_HYSTERESIS_COUNTER_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGC_HYSTERESIS_COUNTER_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGC_HYSTERESIS_COUNTER_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGC_HYSTERESIS_COUNTER_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_spio_soc_ip.csr 37964 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGC_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGC_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGC_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGC_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGC_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGC_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGC_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGC_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 37975 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_cgo bridge_spio_p00_dma_am_m_0_7_am_cgo SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGO_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGO_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGO_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGO_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 38011 spio_p00_dma_am_m register am_cgo 0x13C18 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the master bridge. false false false false FPO SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGO_FPO_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGO_FPO_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGO_FPO_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGO_FPO_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGO_FPO_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGO_FPO_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGO_FPO_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGO_FPO_SET ns_noc_io_spio_soc_ip.csr 37999 FPO 1'b1: Clock gating override is enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGO_UNSD_63_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGO_UNSD_63_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGO_UNSD_63_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGO_UNSD_63_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGO_UNSD_63_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGO_UNSD_63_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGO_UNSD_63_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CGO_UNSD_63_1_SET ns_noc_io_spio_soc_ip.csr 38010 UNSD_63_1 63 1 0x0000000000000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_cfg bridge_spio_p00_dma_am_m_0_7_am_cfg SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CFG_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CFG_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CFG_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CFG_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 38048 spio_p00_dma_am_m register am_cfg 0x13C20 R/W 0x0000000000000001 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_cfg Configures the master bridge's support for autowake of power domains. When set, master bridge halts a request and issues wakeup requests for power domains that need to powered up to complete the transaction. The power domains should support auto wake. When reset, master bridge issues DECERR for any transaction which has dependent power domains in sleep state. false false false false AW SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CFG_AW_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CFG_AW_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CFG_AW_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CFG_AW_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CFG_AW_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CFG_AW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CFG_AW_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CFG_AW_SET ns_noc_io_spio_soc_ip.csr 38036 AW 1'b1: Autowake enabled 1'b0: Autowake disabled 0 0 0x1 R/W UNSD_63_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CFG_UNSD_63_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CFG_UNSD_63_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CFG_UNSD_63_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CFG_UNSD_63_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CFG_UNSD_63_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CFG_UNSD_63_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CFG_UNSD_63_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CFG_UNSD_63_1_SET ns_noc_io_spio_soc_ip.csr 38047 UNSD_63_1 63 1 0x0000000000000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_sts bridge_spio_p00_dma_am_m_0_7_am_sts SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 38176 spio_p00_dma_am_m register am_sts 0x13D00 R 0x000000000000000c Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_sts When reordering is disabled on the master bridge, hazard stall occurs if the master tries to access a new slave device while response from a different slave is outstanding on the same AID. This is because the responses can arrive out of order and the bridge is not equipped to correct the order. Without re-order buffers, hazard stalls also occur if a new large command needs to be split while there are older commands outstanding, or a large command just finished sending all its split segments but all responses have not returned yet. When reordering is enabled, stall due to hazard occurs if a new command arrives, whose NoC QoS is different from the NoC QoS of commands outstanding on that AID. false false false false ROF SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ROF_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ROF_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ROF_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ROF_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ROF_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ROF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ROF_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ROF_SET ns_noc_io_spio_soc_ip.csr 38081 ROF 1'b1: Maximum supported number of read commands are outstanding waiting for response and no more requests can be accepted 1'b0: Master bridge can accept more read requests 0 0 0x0 R WOF SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_WOF_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_WOF_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_WOF_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_WOF_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_WOF_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_WOF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_WOF_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_WOF_SET ns_noc_io_spio_soc_ip.csr 38095 WOF 1'b1: Maximum supported number of write commands are outstanding waiting for response and no more requests can be accepted 1'b0: Master bridge can accept more write requests 1 1 0x0 R ROE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ROE_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ROE_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ROE_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ROE_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ROE_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ROE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ROE_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ROE_SET ns_noc_io_spio_soc_ip.csr 38107 ROE 1'b1: There are no read commands outstanding from the attached master device 2 2 0x1 R WOE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_WOE_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_WOE_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_WOE_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_WOE_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_WOE_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_WOE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_WOE_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_WOE_SET ns_noc_io_spio_soc_ip.csr 38119 WOE 1'b1: There are no write commands outstanding from the attached master device 3 3 0x1 R ARS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ARS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ARS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ARS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ARS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ARS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ARS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ARS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ARS_SET ns_noc_io_spio_soc_ip.csr 38130 ARS 1'b1: AR channel is stalled on hazard 4 4 0x0 R AWS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_AWS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_AWS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_AWS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_AWS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_AWS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_AWS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_AWS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_AWS_SET ns_noc_io_spio_soc_ip.csr 38141 AWS 1'b1: AW channel is stalled on hazard 5 5 0x0 R ARO SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ARO_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ARO_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ARO_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ARO_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ARO_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ARO_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ARO_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_ARO_SET ns_noc_io_spio_soc_ip.csr 38153 ARO 1'b1: Read commands are outstanding to the slave specified in OSSLV register 6 6 0x0 R AWO SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_AWO_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_AWO_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_AWO_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_AWO_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_AWO_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_AWO_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_AWO_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_AWO_SET ns_noc_io_spio_soc_ip.csr 38165 AWO 1'b1: Write commands are outstanding to the slave specified in OSSLV register 7 7 0x0 R UNSD_63_8 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_UNSD_63_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_UNSD_63_8_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_UNSD_63_8_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_UNSD_63_8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_UNSD_63_8_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_UNSD_63_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_UNSD_63_8_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_STS_UNSD_63_8_SET ns_noc_io_spio_soc_ip.csr 38175 UNSD_63_8 63 8 0x00000000000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_bridge_id bridge_spio_p00_dma_am_m_0_7_am_bridge_id SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_BRIDGE_ID_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_BRIDGE_ID_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_BRIDGE_ID_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_BRIDGE_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 38206 spio_p00_dma_am_m register am_bridge_id 0x13D08 R 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_bridge_id Unique identifier assigned to the master bridge. false false false false ID SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_BRIDGE_ID_ID_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_BRIDGE_ID_ID_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_BRIDGE_ID_ID_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_BRIDGE_ID_ID_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_BRIDGE_ID_ID_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_BRIDGE_ID_ID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_BRIDGE_ID_ID_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_BRIDGE_ID_ID_SET ns_noc_io_spio_soc_ip.csr 38195 ID Unique bridge ID 15 0 0x0000 R UNSD_63_16 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_BRIDGE_ID_UNSD_63_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_BRIDGE_ID_UNSD_63_16_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_BRIDGE_ID_UNSD_63_16_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_BRIDGE_ID_UNSD_63_16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_BRIDGE_ID_UNSD_63_16_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_BRIDGE_ID_UNSD_63_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_BRIDGE_ID_UNSD_63_16_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_spio_soc_ip.csr 38205 UNSD_63_16 63 16 0x000000000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_err bridge_spio_p00_dma_am_m_0_7_am_err SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 38702 spio_p00_dma_am_m register am_err 0x13E00 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E0_SET ns_noc_io_spio_soc_ip.csr 38228 E0 1'b1: Local read address decode error: ARADDR did not find a match in the master bridges address table and a decode error was issued 0 0 0x0 R/W E1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E1_SET ns_noc_io_spio_soc_ip.csr 38240 E1 1'b1: Read address decode error from slave: A decode error response was received from a slave device 1 1 0x0 R/W E2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E2_SET ns_noc_io_spio_soc_ip.csr 38252 E2 1'b1: Read slave error: A slave error response was received from a slave device 2 2 0x0 R/W E3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E3_SET ns_noc_io_spio_soc_ip.csr 38264 E3 1'b1: Non modifiable WRAP: A WRAP command marked as non-modifiable (ARCACHE[0]=0) was detected 3 3 0x0 R/W E4 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E4_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E4_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E4_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E4_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E4_SET ns_noc_io_spio_soc_ip.csr 38276 E4 1'b1: [FATAL] Read exclusive split: An AR command of FIXED burst type was detected 4 4 0x0 R/W E5 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E5_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E5_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E5_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E5_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E5_SET ns_noc_io_spio_soc_ip.csr 38288 E5 1'b1: [FATAL] Read address multi-hit: An AR command matched against multiple entries in the address table 5 5 0x0 R/W E6 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E6_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E6_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E6_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E6_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E6_SET ns_noc_io_spio_soc_ip.csr 38301 E6 1'b1: Read response timeout: Read response timeout occurred. With timeout enabled, a response wasn't received within the expected interval 6 6 0x0 R/W E7 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E7_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E7_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E7_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E7_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E7_SET ns_noc_io_spio_soc_ip.csr 38314 E7 1'b1: [FATAL] Read WRAP not equal to supported cacheline size: A WRAP command of unupported cache line size was detected 7 7 0x0 R/W E8 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E8_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E8_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E8_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E8_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E8_SET ns_noc_io_spio_soc_ip.csr 38325 E8 1'b1: [FATAL] Unexpected narrow read detected 8 8 0x0 R/W UNSD_15_9 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_15_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_15_9_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_15_9_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_15_9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_15_9_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_15_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_15_9_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_15_9_SET ns_noc_io_spio_soc_ip.csr 38336 UNSD_15_9 15 9 0x00 R E16 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E16_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E16_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E16_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E16_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E16_SET ns_noc_io_spio_soc_ip.csr 38347 E16 1'b1: Local write address decode error 16 16 0x0 R/W E17 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E17_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E17_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E17_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E17_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E17_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E17_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E17_SET ns_noc_io_spio_soc_ip.csr 38358 E17 1'b1: Write address decode error from slave 17 17 0x0 R/W E18 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E18_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E18_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E18_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E18_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E18_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E18_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E18_SET ns_noc_io_spio_soc_ip.csr 38369 E18 1'b1: Write slave error 18 18 0x0 R/W E19 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E19_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E19_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E19_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E19_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E19_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E19_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E19_SET ns_noc_io_spio_soc_ip.csr 38380 E19 1'b1: Non modifiable WRAP 19 19 0x0 R/W E20 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E20_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E20_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E20_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E20_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E20_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E20_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E20_SET ns_noc_io_spio_soc_ip.csr 38391 E20 1'b1: [FATAL] Write exclusive split 20 20 0x0 R/W E21 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E21_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E21_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E21_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E21_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E21_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E21_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E21_SET ns_noc_io_spio_soc_ip.csr 38402 E21 1'b1: [FATAL] Write address multi-hit 21 21 0x0 R/W E22 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E22_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E22_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E22_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E22_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E22_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E22_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E22_SET ns_noc_io_spio_soc_ip.csr 38413 E22 1'b1: Write respone timeout 22 22 0x0 R/W E23 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E23_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E23_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E23_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E23_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E23_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E23_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E23_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E23_SET ns_noc_io_spio_soc_ip.csr 38425 E23 1'b1: [FATAL] Write WRAP not equal to supported cacheline size 23 23 0x0 R/W E24 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E24_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E24_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E24_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E24_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E24_SET ns_noc_io_spio_soc_ip.csr 38436 E24 1'b1: [FATAL] Unexpected narrow write detected 24 24 0x0 R/W UNSD_31_25 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_31_25_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_31_25_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_31_25_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_31_25_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_31_25_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_31_25_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_31_25_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_31_25_SET ns_noc_io_spio_soc_ip.csr 38447 UNSD_31_25 31 25 0x00 R E32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E32_SET ns_noc_io_spio_soc_ip.csr 38458 E32 1'b1: Capture counter0 overflow 32 32 0x0 R/W E33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E33_SET ns_noc_io_spio_soc_ip.csr 38469 E33 1'b1: Capture counter1 overflow 33 33 0x0 R/W E34 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E34_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E34_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E34_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E34_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E34_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E34_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E34_SET ns_noc_io_spio_soc_ip.csr 38481 E34 1'b1: [FATAL] Traffic sent to a noc layer which is power gate 34 34 0x0 R/W E35 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E35_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E35_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E35_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E35_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E35_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E35_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E35_SET ns_noc_io_spio_soc_ip.csr 38493 E35 1'b1: [FATAL] Parity error in configuration/status registers 35 35 0x0 R/W UNSD_39_36 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_39_36_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_39_36_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_39_36_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_39_36_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_39_36_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_39_36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_39_36_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_39_36_SET ns_noc_io_spio_soc_ip.csr 38504 UNSD_39_36 39 36 0x0 R E40 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E40_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E40_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E40_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E40_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E40_SET ns_noc_io_spio_soc_ip.csr 38516 E40 1'b1: [FATAL] Indicates that portcheck detected error (SIB mode only) 40 40 0x0 R/W E41 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E41_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E41_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E41_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E41_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E41_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E41_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E41_SET ns_noc_io_spio_soc_ip.csr 38527 E41 1'b1: [FATAL] AR Parity Err 41 41 0x0 R/W E42 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E42_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E42_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E42_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E42_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E42_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E42_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E42_SET ns_noc_io_spio_soc_ip.csr 38538 E42 1'b1: [FATAL] ARADDR Parity Err 42 42 0x0 R/W E43 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E43_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E43_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E43_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E43_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E43_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E43_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E43_SET ns_noc_io_spio_soc_ip.csr 38549 E43 1'b1: [FATAL] AW Parity Err 43 43 0x0 R/W E44 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E44_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E44_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E44_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E44_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E44_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E44_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E44_SET ns_noc_io_spio_soc_ip.csr 38560 E44 1'b1: [FATAL] AWADDR Parity Err 44 44 0x0 R/W E45 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E45_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E45_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E45_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E45_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E45_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E45_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E45_SET ns_noc_io_spio_soc_ip.csr 38571 E45 1'b1: [FATAL] WDATA Parity Err 45 45 0x0 R/W E46 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E46_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E46_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E46_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E46_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E46_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E46_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E46_SET ns_noc_io_spio_soc_ip.csr 38582 E46 1'b1: [FATAL] CDDATA Parity Err 46 46 0x0 R/W E47 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E47_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E47_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E47_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E47_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E47_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E47_SET ns_noc_io_spio_soc_ip.csr 38594 E47 1'b1: [FATAL] Ridtbl Entry Parity Err 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E48_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E48_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E48_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E48_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E48_SET ns_noc_io_spio_soc_ip.csr 38606 E48 1'b1: [FATAL] Widtbl Entry Parity Err 48 48 0x0 R E49 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E49_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E49_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E49_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E49_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E49_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E49_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E49_SET ns_noc_io_spio_soc_ip.csr 38618 E49 1'b1: [FATAL] Read Reorder Buffer Parity Err 49 49 0x0 R E50 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E50_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E50_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E50_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E50_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E50_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E50_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E50_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E50_SET ns_noc_io_spio_soc_ip.csr 38630 E50 1'b1: [FATAL] Write Reorder Buffer Parity Err 50 50 0x0 R E51 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E51_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E51_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E51_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E51_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E51_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E51_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E51_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E51_SET ns_noc_io_spio_soc_ip.csr 38642 E51 1'b1: [FATAL] Rx Fifo Parity Err 51 51 0x0 R E52 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E52_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E52_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E52_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E52_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E52_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E52_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E52_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E52_SET ns_noc_io_spio_soc_ip.csr 38654 E52 1'b1: [FATAL] Ack Channel Wack Fifo Parity Error 52 52 0x0 R E53 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E53_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E53_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E53_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E53_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E53_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E53_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E53_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E53_SET ns_noc_io_spio_soc_ip.csr 38666 E53 1'b1: [FATAL] Ack Channel Rack Fifo Parity Error 53 53 0x0 R E54 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E54_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E54_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E54_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E54_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E54_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E54_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E54_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E54_SET ns_noc_io_spio_soc_ip.csr 38678 E54 1'b1: [FATAL] CRCD Channel Crid Fifo Parity Error 54 54 0x0 R E55 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E55_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E55_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E55_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E55_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E55_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E55_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E55_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_E55_SET ns_noc_io_spio_soc_ip.csr 38690 E55 1'b1: [FATAL] R Channel Cpkt Fifo Parity Error 55 55 0x0 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERR_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 38701 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_toslvid bridge_spio_p00_dma_am_m_0_7_am_toslvid SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOSLVID_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOSLVID_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOSLVID_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOSLVID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 38747 spio_p00_dma_am_m register am_toslvid 0x13E08 R 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_toslvid AR slvid and AW slvid fields indicate slave IDs to which a read, write response timeout was detected. Note that slvid encoding is not same as the bridge ID of the slave. NocStudio provides a table mapping the slvids to the actual slave ports accessible from the master bridge. false false false false AR_SLVID SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOSLVID_AR_SLVID_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOSLVID_AR_SLVID_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOSLVID_AR_SLVID_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOSLVID_AR_SLVID_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOSLVID_AR_SLVID_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOSLVID_AR_SLVID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOSLVID_AR_SLVID_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOSLVID_AR_SLVID_SET ns_noc_io_spio_soc_ip.csr 38725 AR_SLVID Slave ID of timed out AR request 15 0 0x0000 R AW_SLVID SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOSLVID_AW_SLVID_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOSLVID_AW_SLVID_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOSLVID_AW_SLVID_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOSLVID_AW_SLVID_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOSLVID_AW_SLVID_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOSLVID_AW_SLVID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOSLVID_AW_SLVID_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOSLVID_AW_SLVID_SET ns_noc_io_spio_soc_ip.csr 38736 AW_SLVID Slave ID of timed out AW request 31 16 0x0000 R UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOSLVID_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOSLVID_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOSLVID_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOSLVID_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOSLVID_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOSLVID_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOSLVID_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_TOSLVID_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 38746 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_era bridge_spio_p00_dma_am_m_0_7_am_era SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERA_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERA_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERA_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERA_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 38769 spio_p00_dma_am_m register am_era 0x13E10 R 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_era This is the address on AR channel for which a decode error was detected. This corresponds to the status register bit e0 in AM_ERR. false false false false READ_DECERR_ADDRS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERA_READ_DECERR_ADDRS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERA_READ_DECERR_ADDRS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERA_READ_DECERR_ADDRS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERA_READ_DECERR_ADDRS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERA_READ_DECERR_ADDRS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERA_READ_DECERR_ADDRS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERA_READ_DECERR_ADDRS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_ERA_READ_DECERR_ADDRS_SET ns_noc_io_spio_soc_ip.csr 38768 READ_DECERR_ADDRS Read decerr address 63 0 0x0000000000000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_ewa bridge_spio_p00_dma_am_m_0_7_am_ewa SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_EWA_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_EWA_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_EWA_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_EWA_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 38791 spio_p00_dma_am_m register am_ewa 0x13E18 R 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_ewa This is the address on AW channel for which a decode error was detected. This corresponds to the status register bit e16 in AM_ERR. false false false false WRITE_DECERR_ADDRS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_EWA_WRITE_DECERR_ADDRS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_EWA_WRITE_DECERR_ADDRS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_EWA_WRITE_DECERR_ADDRS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_EWA_WRITE_DECERR_ADDRS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_EWA_WRITE_DECERR_ADDRS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_EWA_WRITE_DECERR_ADDRS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_EWA_WRITE_DECERR_ADDRS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_EWA_WRITE_DECERR_ADDRS_SET ns_noc_io_spio_soc_ip.csr 38790 WRITE_DECERR_ADDRS Write decerr address 63 0 0x0000000000000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_intm bridge_spio_p00_dma_am_m_0_7_am_intm SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 39275 spio_p00_dma_am_m register am_intm 0x13E40 R/W 0x00007e07004f004f Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_intm Interrupt mask register. Individual bit position matches the error bit positions in AM_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M0_SET ns_noc_io_spio_soc_ip.csr 38813 M0 1'b1: Mask interrupt for read channel 0 0 0x1 R/W M1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M1_SET ns_noc_io_spio_soc_ip.csr 38824 M1 1'b1: Mask interrupt for read channel 1 1 0x1 R/W M2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M2_SET ns_noc_io_spio_soc_ip.csr 38835 M2 1'b1: Mask interrupt for read channel 2 2 0x1 R/W M3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M3_SET ns_noc_io_spio_soc_ip.csr 38846 M3 1'b1: Mask interrupt for read channel 3 3 0x1 R/W M4 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M4_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M4_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M4_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M4_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M4_SET ns_noc_io_spio_soc_ip.csr 38857 M4 1'b1: Mask interrupt for read channel 4 4 0x0 R/W M5 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M5_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M5_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M5_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M5_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M5_SET ns_noc_io_spio_soc_ip.csr 38868 M5 1'b1: Mask interrupt for read channel 5 5 0x0 R/W M6 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M6_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M6_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M6_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M6_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M6_SET ns_noc_io_spio_soc_ip.csr 38879 M6 1'b1: Mask interrupt for read channel 6 6 0x1 R/W M7 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M7_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M7_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M7_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M7_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M7_SET ns_noc_io_spio_soc_ip.csr 38890 M7 1'b1: Mask interrupt for read channel 7 7 0x0 R/W M8 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M8_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M8_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M8_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M8_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M8_SET ns_noc_io_spio_soc_ip.csr 38901 M8 1'b1: Mask interrupt for read channel 8 8 0x0 R/W UNSD_15_9 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_15_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_15_9_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_15_9_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_15_9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_15_9_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_15_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_15_9_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_15_9_SET ns_noc_io_spio_soc_ip.csr 38912 UNSD_15_9 15 9 0x00 R M16 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M16_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M16_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M16_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M16_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M16_SET ns_noc_io_spio_soc_ip.csr 38923 M16 1'b1: Mask interrupt for write channel 16 16 0x1 R/W M17 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M17_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M17_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M17_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M17_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M17_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M17_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M17_SET ns_noc_io_spio_soc_ip.csr 38934 M17 1'b1: Mask interrupt for write channel 17 17 0x1 R/W M18 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M18_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M18_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M18_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M18_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M18_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M18_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M18_SET ns_noc_io_spio_soc_ip.csr 38945 M18 1'b1: Mask interrupt for write channel 18 18 0x1 R/W M19 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M19_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M19_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M19_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M19_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M19_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M19_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M19_SET ns_noc_io_spio_soc_ip.csr 38956 M19 1'b1: Mask interrupt for write channel 19 19 0x1 R/W M20 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M20_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M20_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M20_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M20_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M20_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M20_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M20_SET ns_noc_io_spio_soc_ip.csr 38967 M20 1'b1: Mask interrupt for write channel 20 20 0x0 R/W M21 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M21_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M21_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M21_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M21_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M21_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M21_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M21_SET ns_noc_io_spio_soc_ip.csr 38978 M21 1'b1: Mask interrupt for write channel 21 21 0x0 R/W M22 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M22_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M22_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M22_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M22_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M22_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M22_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M22_SET ns_noc_io_spio_soc_ip.csr 38989 M22 1'b1: Mask interrupt for write channel 22 22 0x1 R/W M23 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M23_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M23_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M23_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M23_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M23_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M23_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M23_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M23_SET ns_noc_io_spio_soc_ip.csr 39000 M23 1'b1: Mask interrupt for write channel 23 23 0x0 R/W M24 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M24_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M24_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M24_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M24_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M24_SET ns_noc_io_spio_soc_ip.csr 39011 M24 1'b1: Mask interrupt for write channel 24 24 0x0 R/W UNSD_31_25 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_31_25_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_31_25_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_31_25_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_31_25_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_31_25_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_31_25_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_31_25_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_31_25_SET ns_noc_io_spio_soc_ip.csr 39022 UNSD_31_25 31 25 0x00 R M32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M32_SET ns_noc_io_spio_soc_ip.csr 39033 M32 1'b1: Counter 0 overflow interrupt mask 32 32 0x1 R/W M33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M33_SET ns_noc_io_spio_soc_ip.csr 39044 M33 1'b1: Counter 1 overflow interrupt mask 33 33 0x1 R/W M34 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M34_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M34_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M34_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M34_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M34_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M34_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M34_SET ns_noc_io_spio_soc_ip.csr 39055 M34 1'b1: Mask interrupt on traffic to PG layer 34 34 0x1 R/W M35 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M35_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M35_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M35_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M35_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M35_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M35_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M35_SET ns_noc_io_spio_soc_ip.csr 39066 M35 1'b1: Mask interrupt on csr parity errors 35 35 0x0 R/W UNSD_39_36 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_39_36_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_39_36_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_39_36_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_39_36_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_39_36_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_39_36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_39_36_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_39_36_SET ns_noc_io_spio_soc_ip.csr 39077 UNSD_39_36 39 36 0x0 R M40 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M40_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M40_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M40_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M40_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M40_SET ns_noc_io_spio_soc_ip.csr 39089 M40 1'b1: Mask interrupt for SIB portcheck error (SIB mode only) 40 40 0x0 R/W M41 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M41_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M41_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M41_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M41_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M41_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M41_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M41_SET ns_noc_io_spio_soc_ip.csr 39100 M41 1'b1: AR Parity Intr Mask 41 41 0x1 R/W M42 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M42_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M42_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M42_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M42_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M42_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M42_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M42_SET ns_noc_io_spio_soc_ip.csr 39111 M42 1'b1: ARADDR Parity Intr Mask 42 42 0x1 R/W M43 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M43_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M43_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M43_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M43_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M43_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M43_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M43_SET ns_noc_io_spio_soc_ip.csr 39122 M43 1'b1: AW Parity Intr Mask 43 43 0x1 R/W M44 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M44_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M44_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M44_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M44_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M44_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M44_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M44_SET ns_noc_io_spio_soc_ip.csr 39133 M44 1'b1: AWADDR Parity Intr Mask 44 44 0x1 R/W M45 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M45_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M45_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M45_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M45_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M45_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M45_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M45_SET ns_noc_io_spio_soc_ip.csr 39144 M45 1'b1: WDATA Parity Intr Mask 45 45 0x1 R/W M46 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M46_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M46_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M46_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M46_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M46_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M46_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_M46_SET ns_noc_io_spio_soc_ip.csr 39155 M46 1'b1: CDDATA Parity Intr Mask 46 46 0x1 R/W E47 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E47_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E47_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E47_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E47_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E47_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E47_SET ns_noc_io_spio_soc_ip.csr 39167 E47 1'b1: Ridtbl Parity Intr Mask 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E48_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E48_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E48_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E48_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E48_SET ns_noc_io_spio_soc_ip.csr 39179 E48 1'b1: Widtbl Parity Intr Mask 48 48 0x0 R E49 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E49_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E49_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E49_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E49_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E49_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E49_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E49_SET ns_noc_io_spio_soc_ip.csr 39191 E49 1'b1: Read Reorder Buffer Parity Intr Mask 49 49 0x0 R E50 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E50_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E50_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E50_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E50_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E50_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E50_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E50_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E50_SET ns_noc_io_spio_soc_ip.csr 39203 E50 1'b1: Write Reorder Buffer Parity Intr Mask 50 50 0x0 R E51 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E51_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E51_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E51_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E51_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E51_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E51_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E51_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E51_SET ns_noc_io_spio_soc_ip.csr 39215 E51 1'b1: Rx Fifo Parity Intr Mask 51 51 0x0 R E52 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E52_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E52_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E52_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E52_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E52_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E52_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E52_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E52_SET ns_noc_io_spio_soc_ip.csr 39227 E52 1'b1: Ack Channel Wack Fifo Parity Intr Mask 52 52 0x0 R E53 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E53_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E53_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E53_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E53_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E53_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E53_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E53_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E53_SET ns_noc_io_spio_soc_ip.csr 39239 E53 1'b1: Ack Channel Rack Fifo Parity Intr Mask 53 53 0x0 R E54 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E54_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E54_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E54_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E54_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E54_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E54_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E54_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E54_SET ns_noc_io_spio_soc_ip.csr 39251 E54 1'b1: CRCD Channel Crid Fifo Parity Intr Mask 54 54 0x0 R E55 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E55_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E55_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E55_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E55_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E55_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E55_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E55_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_E55_SET ns_noc_io_spio_soc_ip.csr 39263 E55 1'b1: R Channel Cpkt Fifo Parity Intr Mask 55 55 0x0 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_INTM_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 39274 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_caddr bridge_spio_p00_dma_am_m_0_7_am_caddr SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CADDR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CADDR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CADDR_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CADDR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 39297 spio_p00_dma_am_m register am_caddr 0x13F00 R/W 0xffffffffffffffff Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_caddr This register is part of statistics gathering on the AR and AW command channels. This is the address value which is checked against AR, AW command channels in conjunction with the mask below to filter commands for statistics gathering. false false false false CAPTURE_ADDR SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CADDR_CAPTURE_ADDR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CADDR_CAPTURE_ADDR_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CADDR_CAPTURE_ADDR_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CADDR_CAPTURE_ADDR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CADDR_CAPTURE_ADDR_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CADDR_CAPTURE_ADDR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CADDR_CAPTURE_ADDR_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CADDR_CAPTURE_ADDR_SET ns_noc_io_spio_soc_ip.csr 39296 CAPTURE_ADDR Capture address 63 0 0xffffffffffffffff R/W register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_caddrmsk bridge_spio_p00_dma_am_m_0_7_am_caddrmsk SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CADDRMSK_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CADDRMSK_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CADDRMSK_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CADDRMSK_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 39320 spio_p00_dma_am_m register am_caddrmsk 0x13F08 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_caddrmsk If command address on the AR, AW channel logically ANDed with this mask is equal to the value specified in AM_CADDR, then an address match has occurred. Note that only lowest significant bits equal to the master's address width are used in the comparison. false false false false CAPTURE_ADDR_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_SET ns_noc_io_spio_soc_ip.csr 39319 CAPTURE_ADDR_MASK Capture address mask 63 0 0x0000000000000000 R/W register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_ccmd0 bridge_spio_p00_dma_am_m_0_7_am_ccmd0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 39510 spio_p00_dma_am_m register am_ccmd0 0x13F10 R/W 0x0000000003fff33f Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_ccmd0 Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands. false false false false SNOOP SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_SNOOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_SNOOP_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_SNOOP_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_SNOOP_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_SNOOP_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_SNOOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_SNOOP_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_SNOOP_SET ns_noc_io_spio_soc_ip.csr 39342 SNOOP Snoop 3 0 0xf R/W DOMAIN SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_DOMAIN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_DOMAIN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_DOMAIN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_DOMAIN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_DOMAIN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_DOMAIN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_DOMAIN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_DOMAIN_SET ns_noc_io_spio_soc_ip.csr 39353 DOMAIN Domain 5 4 0x3 R/W UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 39364 UNSD_7_6 7 6 0x0 R BAR SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_BAR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_BAR_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_BAR_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_BAR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_BAR_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_BAR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_BAR_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_BAR_SET ns_noc_io_spio_soc_ip.csr 39375 BAR Bar 9 8 0x3 R/W UNSD_11_10 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_11_10_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_11_10_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_11_10_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_11_10_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_11_10_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_11_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_11_10_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_11_10_SET ns_noc_io_spio_soc_ip.csr 39386 UNSD_11_10 11 10 0x0 R CACHE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_CACHE_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_CACHE_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_CACHE_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_CACHE_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_CACHE_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_CACHE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_CACHE_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_CACHE_SET ns_noc_io_spio_soc_ip.csr 39397 CACHE Cache 15 12 0xf R/W QOS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_QOS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_QOS_SET ns_noc_io_spio_soc_ip.csr 39408 QOS QoS 19 16 0xf R/W PROT SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_PROT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_PROT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_PROT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_PROT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_PROT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_PROT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_PROT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_PROT_SET ns_noc_io_spio_soc_ip.csr 39419 PROT Prot 22 20 0x7 R/W LOC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_LOC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_LOC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_LOC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_LOC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_LOC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_LOC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_LOC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_LOC_SET ns_noc_io_spio_soc_ip.csr 39430 LOC 1'b1: Lock 23 23 0x1 R/W RDY SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_RDY_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_RDY_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_RDY_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_RDY_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_RDY_SET ns_noc_io_spio_soc_ip.csr 39441 RDY 1'b1: Ready 24 24 0x1 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_VAL_SET ns_noc_io_spio_soc_ip.csr 39452 VAL 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_27_26_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_27_26_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_27_26_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_27_26_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_27_26_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_27_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_27_26_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_27_26_SET ns_noc_io_spio_soc_ip.csr 39463 UNSD_27_26 27 26 0x0 R INTFID SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_INTFID_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_INTFID_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_INTFID_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_INTFID_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_INTFID_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_INTFID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_INTFID_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_INTFID_SET ns_noc_io_spio_soc_ip.csr 39475 INTFID 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_31_31 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_31_31_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_31_31_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_31_31_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_31_31_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_31_31_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_31_31_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_31_31_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_31_31_SET ns_noc_io_spio_soc_ip.csr 39486 UNSD_31_31 31 31 0x0 R TYP SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_TYP_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_TYP_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_TYP_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_TYP_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_TYP_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_TYP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_TYP_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_TYP_SET ns_noc_io_spio_soc_ip.csr 39498 TYP 1'b1: Count response latency of captured command 1'b0: Count captured command 32 32 0x0 R/W UNSD_63_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_63_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_63_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_63_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_63_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_63_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_63_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_63_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD0_UNSD_63_33_SET ns_noc_io_spio_soc_ip.csr 39509 UNSD_63_33 63 33 0x00000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_ccmdmsk0 bridge_spio_p00_dma_am_m_0_7_am_ccmdmsk0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 39654 spio_p00_dma_am_m register am_ccmdmsk0 0x13F18 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_ccmdmsk0 If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters. false false false false SNOOP SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_SNOOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_SNOOP_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_SNOOP_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_SNOOP_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_SNOOP_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_SNOOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_SNOOP_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_SNOOP_SET ns_noc_io_spio_soc_ip.csr 39532 SNOOP Snoop 3 0 0x0 R/W DOMAIN SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_DOMAIN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_DOMAIN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_DOMAIN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_DOMAIN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_DOMAIN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_DOMAIN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_DOMAIN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_DOMAIN_SET ns_noc_io_spio_soc_ip.csr 39543 DOMAIN Domain 5 4 0x0 R/W UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 39554 UNSD_7_6 7 6 0x0 R BAR SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_BAR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_BAR_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_BAR_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_BAR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_BAR_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_BAR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_BAR_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_BAR_SET ns_noc_io_spio_soc_ip.csr 39565 BAR Bar 9 8 0x0 R/W UNSD_11_10 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_UNSD_11_10_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_UNSD_11_10_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_UNSD_11_10_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_UNSD_11_10_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_UNSD_11_10_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_UNSD_11_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_UNSD_11_10_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_UNSD_11_10_SET ns_noc_io_spio_soc_ip.csr 39576 UNSD_11_10 11 10 0x0 R CACHE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_CACHE_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_CACHE_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_CACHE_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_CACHE_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_CACHE_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_CACHE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_CACHE_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_CACHE_SET ns_noc_io_spio_soc_ip.csr 39587 CACHE Cache 15 12 0x0 R/W QOS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_QOS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_QOS_SET ns_noc_io_spio_soc_ip.csr 39598 QOS QoS 19 16 0x0 R/W PROT SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_PROT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_PROT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_PROT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_PROT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_PROT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_PROT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_PROT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_PROT_SET ns_noc_io_spio_soc_ip.csr 39609 PROT Prot 22 20 0x0 R/W LOC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_LOC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_LOC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_LOC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_LOC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_LOC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_LOC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_LOC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_LOC_SET ns_noc_io_spio_soc_ip.csr 39620 LOC 1'b1: Lock 23 23 0x0 R/W RDY SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_RDY_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_RDY_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_RDY_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_RDY_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_RDY_SET ns_noc_io_spio_soc_ip.csr 39631 RDY 1'b1: Ready 24 24 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_VAL_SET ns_noc_io_spio_soc_ip.csr 39642 VAL 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_UNSD_63_26_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_UNSD_63_26_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_UNSD_63_26_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_UNSD_63_26_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_UNSD_63_26_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_UNSD_63_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_UNSD_63_26_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK0_UNSD_63_26_SET ns_noc_io_spio_soc_ip.csr 39653 UNSD_63_26 63 26 0x0000000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_cntr0 bridge_spio_p00_dma_am_m_0_7_am_cntr0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 39689 spio_p00_dma_am_m register am_cntr0 0x13F20 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_cntr0 32-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured. false false false false CNTR SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR0_CNTR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR0_CNTR_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR0_CNTR_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR0_CNTR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR0_CNTR_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR0_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR0_CNTR_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR0_CNTR_SET ns_noc_io_spio_soc_ip.csr 39677 CNTR Counter 31 0 0x00000000 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR0_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR0_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR0_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR0_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR0_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR0_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR0_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR0_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 39688 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_latnum0 bridge_spio_p00_dma_am_m_0_7_am_latnum0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 39728 spio_p00_dma_am_m register am_latnum0 0x13F28 R/W 0x0000000000000007 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_latnum0 This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using: Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0 There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set. false false false false CNTR SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM0_CNTR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM0_CNTR_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM0_CNTR_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM0_CNTR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM0_CNTR_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM0_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM0_CNTR_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM0_CNTR_SET ns_noc_io_spio_soc_ip.csr 39716 CNTR Counter 31 0 0x00000007 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM0_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM0_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM0_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM0_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM0_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM0_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM0_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM0_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 39727 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_ccmd1 bridge_spio_p00_dma_am_m_0_7_am_ccmd1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 39918 spio_p00_dma_am_m register am_ccmd1 0x13F30 R/W 0x0000000003fff33f Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_ccmd1 Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands. false false false false SNOOP SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_SNOOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_SNOOP_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_SNOOP_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_SNOOP_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_SNOOP_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_SNOOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_SNOOP_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_SNOOP_SET ns_noc_io_spio_soc_ip.csr 39750 SNOOP Snoop 3 0 0xf R/W DOMAIN SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_DOMAIN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_DOMAIN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_DOMAIN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_DOMAIN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_DOMAIN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_DOMAIN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_DOMAIN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_DOMAIN_SET ns_noc_io_spio_soc_ip.csr 39761 DOMAIN Domain 5 4 0x3 R/W UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 39772 UNSD_7_6 7 6 0x0 R BAR SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_BAR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_BAR_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_BAR_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_BAR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_BAR_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_BAR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_BAR_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_BAR_SET ns_noc_io_spio_soc_ip.csr 39783 BAR Bar 9 8 0x3 R/W UNSD_11_10 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_11_10_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_11_10_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_11_10_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_11_10_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_11_10_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_11_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_11_10_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_11_10_SET ns_noc_io_spio_soc_ip.csr 39794 UNSD_11_10 11 10 0x0 R CACHE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_CACHE_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_CACHE_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_CACHE_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_CACHE_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_CACHE_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_CACHE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_CACHE_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_CACHE_SET ns_noc_io_spio_soc_ip.csr 39805 CACHE Cache 15 12 0xf R/W QOS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_QOS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_QOS_SET ns_noc_io_spio_soc_ip.csr 39816 QOS QoS 19 16 0xf R/W PROT SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_PROT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_PROT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_PROT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_PROT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_PROT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_PROT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_PROT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_PROT_SET ns_noc_io_spio_soc_ip.csr 39827 PROT Prot 22 20 0x7 R/W LOC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_LOC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_LOC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_LOC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_LOC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_LOC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_LOC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_LOC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_LOC_SET ns_noc_io_spio_soc_ip.csr 39838 LOC 1'b1: Lock 23 23 0x1 R/W RDY SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_RDY_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_RDY_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_RDY_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_RDY_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_RDY_SET ns_noc_io_spio_soc_ip.csr 39849 RDY 1'b1: Ready 24 24 0x1 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_VAL_SET ns_noc_io_spio_soc_ip.csr 39860 VAL 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_27_26_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_27_26_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_27_26_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_27_26_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_27_26_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_27_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_27_26_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_27_26_SET ns_noc_io_spio_soc_ip.csr 39871 UNSD_27_26 27 26 0x0 R INTFID SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_INTFID_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_INTFID_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_INTFID_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_INTFID_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_INTFID_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_INTFID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_INTFID_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_INTFID_SET ns_noc_io_spio_soc_ip.csr 39883 INTFID 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_31_31 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_31_31_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_31_31_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_31_31_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_31_31_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_31_31_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_31_31_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_31_31_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_31_31_SET ns_noc_io_spio_soc_ip.csr 39894 UNSD_31_31 31 31 0x0 R TYP SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_TYP_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_TYP_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_TYP_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_TYP_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_TYP_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_TYP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_TYP_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_TYP_SET ns_noc_io_spio_soc_ip.csr 39906 TYP 1'b1: Count response latency of captured command 1'b0: Count captured command 32 32 0x0 R/W UNSD_63_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_63_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_63_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_63_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_63_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_63_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_63_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_63_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMD1_UNSD_63_33_SET ns_noc_io_spio_soc_ip.csr 39917 UNSD_63_33 63 33 0x00000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_ccmdmsk1 bridge_spio_p00_dma_am_m_0_7_am_ccmdmsk1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 40062 spio_p00_dma_am_m register am_ccmdmsk1 0x13F38 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_ccmdmsk1 If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters. false false false false SNOOP SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_SNOOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_SNOOP_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_SNOOP_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_SNOOP_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_SNOOP_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_SNOOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_SNOOP_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_SNOOP_SET ns_noc_io_spio_soc_ip.csr 39940 SNOOP Snoop 3 0 0x0 R/W DOMAIN SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_DOMAIN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_DOMAIN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_DOMAIN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_DOMAIN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_DOMAIN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_DOMAIN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_DOMAIN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_DOMAIN_SET ns_noc_io_spio_soc_ip.csr 39951 DOMAIN Domain 5 4 0x0 R/W UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 39962 UNSD_7_6 7 6 0x0 R BAR SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_BAR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_BAR_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_BAR_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_BAR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_BAR_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_BAR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_BAR_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_BAR_SET ns_noc_io_spio_soc_ip.csr 39973 BAR Bar 9 8 0x0 R/W UNSD_11_10 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_UNSD_11_10_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_UNSD_11_10_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_UNSD_11_10_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_UNSD_11_10_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_UNSD_11_10_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_UNSD_11_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_UNSD_11_10_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_UNSD_11_10_SET ns_noc_io_spio_soc_ip.csr 39984 UNSD_11_10 11 10 0x0 R CACHE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_CACHE_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_CACHE_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_CACHE_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_CACHE_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_CACHE_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_CACHE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_CACHE_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_CACHE_SET ns_noc_io_spio_soc_ip.csr 39995 CACHE Cache 15 12 0x0 R/W QOS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_QOS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_QOS_SET ns_noc_io_spio_soc_ip.csr 40006 QOS QoS 19 16 0x0 R/W PROT SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_PROT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_PROT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_PROT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_PROT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_PROT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_PROT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_PROT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_PROT_SET ns_noc_io_spio_soc_ip.csr 40017 PROT Prot 22 20 0x0 R/W LOC SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_LOC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_LOC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_LOC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_LOC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_LOC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_LOC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_LOC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_LOC_SET ns_noc_io_spio_soc_ip.csr 40028 LOC 1'b1: Lock 23 23 0x0 R/W RDY SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_RDY_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_RDY_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_RDY_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_RDY_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_RDY_SET ns_noc_io_spio_soc_ip.csr 40039 RDY 1'b1: Ready 24 24 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_VAL_SET ns_noc_io_spio_soc_ip.csr 40050 VAL 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_UNSD_63_26_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_UNSD_63_26_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_UNSD_63_26_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_UNSD_63_26_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_UNSD_63_26_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_UNSD_63_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_UNSD_63_26_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CCMDMSK1_UNSD_63_26_SET ns_noc_io_spio_soc_ip.csr 40061 UNSD_63_26 63 26 0x0000000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_cntr1 bridge_spio_p00_dma_am_m_0_7_am_cntr1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 40097 spio_p00_dma_am_m register am_cntr1 0x13F40 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_cntr1 32-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured. false false false false CNTR SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR1_CNTR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR1_CNTR_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR1_CNTR_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR1_CNTR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR1_CNTR_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR1_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR1_CNTR_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR1_CNTR_SET ns_noc_io_spio_soc_ip.csr 40085 CNTR Counter 31 0 0x00000000 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR1_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR1_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR1_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR1_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR1_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR1_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR1_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_CNTR1_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 40096 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_latnum1 bridge_spio_p00_dma_am_m_0_7_am_latnum1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 40136 spio_p00_dma_am_m register am_latnum1 0x13F48 R/W 0x0000000000000007 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_latnum1 This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using: Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0 There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set. false false false false CNTR SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM1_CNTR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM1_CNTR_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM1_CNTR_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM1_CNTR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM1_CNTR_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM1_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM1_CNTR_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM1_CNTR_SET ns_noc_io_spio_soc_ip.csr 40124 CNTR Counter 31 0 0x00000007 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM1_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM1_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM1_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM1_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM1_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM1_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM1_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_LATNUM1_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 40135 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_arovrd bridge_spio_p00_dma_am_m_0_7_am_arovrd SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 40249 spio_p00_dma_am_m register am_arovrd 0x13F60 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_arovrd AR override. false false false false arcache_val SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 40154 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 40167 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 40178 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 40189 UNSD_11_11 11 11 0x0 R arprot_enb SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 40202 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 40213 UNSD_15_15 15 15 0x0 R arqos_val SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 40224 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_ARQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 40237 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AROVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 40248 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_p00_dma_am_m_0_7_am_awovrd bridge_spio_p00_dma_am_m_0_7_am_awovrd SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 40362 spio_p00_dma_am_m register am_awovrd 0x13F68 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_am_m_0_7_am_awovrd AW override. false false false false awcache_val SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 40267 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 40280 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 40291 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 40302 UNSD_11_11 11 11 0x0 R awprot_enb SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 40315 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 40326 UNSD_15_15 15 15 0x0 R awqos_val SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 40337 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_AWQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 40350 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_AM_M_0_7_AM_AWOVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 40361 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 40478 spio_p00_dma_m register am_adbase_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 0x14000 R/W 0x0000000040100000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 40402 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 40413 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 40424 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 40436 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 40447 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 40459 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 40470 BASE_ADDRESS_0_33 Base address 39 6 0x001004000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 40477 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 40570 spio_p00_dma_m register am_admask_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 0x14008 R/W 0x000000fffff00000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 40495 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 40506 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 40517 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 40528 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 40540 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 40551 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 40562 MASK_0_33 Mask 39 6 0x3ffffc000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 40569 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 40686 spio_p00_dma_m register am_adbase_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 0x14020 R/W 0x0000000056100000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 40610 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 40621 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 40632 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 40644 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 40655 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 40667 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 40678 BASE_ADDRESS_0_33 Base address 39 6 0x001584000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 40685 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 40778 spio_p00_dma_m register am_admask_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 0x14028 R/W 0x000000fffff00000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 40703 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 40714 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 40725 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 40736 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 40748 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 40759 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 40770 MASK_0_33 Mask 39 6 0x3ffffc000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 40777 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 40894 spio_p00_dma_m register am_adbase_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 0x14040 R/W 0x0000000056000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 40818 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 40829 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 40840 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 40852 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 40863 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 40875 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 40886 BASE_ADDRESS_0_33 Base address 39 6 0x001580000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 40893 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 40986 spio_p00_dma_m register am_admask_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 0x14048 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 40911 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 40922 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 40933 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 40944 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 40956 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 40967 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 40978 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 40985 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 41102 spio_p00_dma_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 0x14060 R/W 0x0000000054000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 41026 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 41037 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 41048 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 41060 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 41071 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 41083 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 41094 BASE_ADDRESS_0_33 Base address 39 6 0x001500000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 41101 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 41194 spio_p00_dma_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 0x14068 R/W 0x000000ffffff0000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 41119 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 41130 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 41141 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 41152 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 41164 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 41175 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 41186 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 41193 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 41310 spio_p00_dma_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 0x14080 R/W 0x0000000054010000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_SET ns_noc_io_spio_soc_ip.csr 41234 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 41245 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_SET ns_noc_io_spio_soc_ip.csr 41256 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 41268 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_SET ns_noc_io_spio_soc_ip.csr 41279 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_SET ns_noc_io_spio_soc_ip.csr 41291 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 41302 BASE_ADDRESS_0_33 Base address 39 6 0x001500400 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 41309 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 41402 spio_p00_dma_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 0x14088 R/W 0x000000ffffff0000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_SET ns_noc_io_spio_soc_ip.csr 41327 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 41338 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_SET ns_noc_io_spio_soc_ip.csr 41349 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_SET ns_noc_io_spio_soc_ip.csr 41360 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_SET ns_noc_io_spio_soc_ip.csr 41372 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_SET ns_noc_io_spio_soc_ip.csr 41383 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 41394 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 41401 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 41518 spio_p00_dma_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 0x140A0 R/W 0x0000000054020000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_SET ns_noc_io_spio_soc_ip.csr 41442 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 41453 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_SET ns_noc_io_spio_soc_ip.csr 41464 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 41476 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_SET ns_noc_io_spio_soc_ip.csr 41487 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_SET ns_noc_io_spio_soc_ip.csr 41499 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 41510 BASE_ADDRESS_0_33 Base address 39 6 0x001500800 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 41517 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 41610 spio_p00_dma_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 0x140A8 R/W 0x000000ffffff0000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_SET ns_noc_io_spio_soc_ip.csr 41535 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 41546 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_SET ns_noc_io_spio_soc_ip.csr 41557 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_SET ns_noc_io_spio_soc_ip.csr 41568 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_SET ns_noc_io_spio_soc_ip.csr 41580 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_SET ns_noc_io_spio_soc_ip.csr 41591 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 41602 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 41609 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 41726 spio_p00_dma_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 0x140C0 R/W 0x0000000054030000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_SET ns_noc_io_spio_soc_ip.csr 41650 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 41661 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_SET ns_noc_io_spio_soc_ip.csr 41672 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 41684 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_SET ns_noc_io_spio_soc_ip.csr 41695 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_SET ns_noc_io_spio_soc_ip.csr 41707 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 41718 BASE_ADDRESS_0_33 Base address 39 6 0x001500c00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 41725 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 41818 spio_p00_dma_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 0x140C8 R/W 0x000000ffffff0000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_SET ns_noc_io_spio_soc_ip.csr 41743 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 41754 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_SET ns_noc_io_spio_soc_ip.csr 41765 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_SET ns_noc_io_spio_soc_ip.csr 41776 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_SET ns_noc_io_spio_soc_ip.csr 41788 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_SET ns_noc_io_spio_soc_ip.csr 41799 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 41810 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 41817 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 41934 spio_p00_dma_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 0x140E0 R/W 0x0000000054040000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_SET ns_noc_io_spio_soc_ip.csr 41858 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 41869 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_SET ns_noc_io_spio_soc_ip.csr 41880 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 41892 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_SET ns_noc_io_spio_soc_ip.csr 41903 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_SET ns_noc_io_spio_soc_ip.csr 41915 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 41926 BASE_ADDRESS_0_33 Base address 39 6 0x001501000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 41933 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 42026 spio_p00_dma_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 0x140E8 R/W 0x000000ffffff0000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_SET ns_noc_io_spio_soc_ip.csr 41951 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 41962 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_SET ns_noc_io_spio_soc_ip.csr 41973 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_SET ns_noc_io_spio_soc_ip.csr 41984 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_SET ns_noc_io_spio_soc_ip.csr 41996 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_SET ns_noc_io_spio_soc_ip.csr 42007 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 42018 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 42025 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 42142 spio_p00_dma_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 0x14100 R/W 0x0000000054050000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_SET ns_noc_io_spio_soc_ip.csr 42066 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 42077 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_SET ns_noc_io_spio_soc_ip.csr 42088 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 42100 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_SET ns_noc_io_spio_soc_ip.csr 42111 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_SET ns_noc_io_spio_soc_ip.csr 42123 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 42134 BASE_ADDRESS_0_33 Base address 39 6 0x001501400 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 42141 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 42234 spio_p00_dma_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 0x14108 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_SET ns_noc_io_spio_soc_ip.csr 42159 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 42170 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_SET ns_noc_io_spio_soc_ip.csr 42181 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_SET ns_noc_io_spio_soc_ip.csr 42192 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_SET ns_noc_io_spio_soc_ip.csr 42204 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_SET ns_noc_io_spio_soc_ip.csr 42215 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 42226 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 42233 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 42350 spio_p00_dma_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 0x14120 R/W 0x0000000054051000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_SET ns_noc_io_spio_soc_ip.csr 42274 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 42285 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_SET ns_noc_io_spio_soc_ip.csr 42296 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 42308 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_SET ns_noc_io_spio_soc_ip.csr 42319 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_SET ns_noc_io_spio_soc_ip.csr 42331 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 42342 BASE_ADDRESS_0_33 Base address 39 6 0x001501440 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 42349 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 42442 spio_p00_dma_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 0x14128 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_SET ns_noc_io_spio_soc_ip.csr 42367 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 42378 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_SET ns_noc_io_spio_soc_ip.csr 42389 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_SET ns_noc_io_spio_soc_ip.csr 42400 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_SET ns_noc_io_spio_soc_ip.csr 42412 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_SET ns_noc_io_spio_soc_ip.csr 42423 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 42434 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 42441 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 42558 spio_p00_dma_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 0x14140 R/W 0x0000000054052000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_SET ns_noc_io_spio_soc_ip.csr 42482 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 42493 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_SET ns_noc_io_spio_soc_ip.csr 42504 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 42516 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_SET ns_noc_io_spio_soc_ip.csr 42527 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_SET ns_noc_io_spio_soc_ip.csr 42539 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 42550 BASE_ADDRESS_0_33 Base address 39 6 0x001501480 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 42557 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 42650 spio_p00_dma_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 0x14148 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_SET ns_noc_io_spio_soc_ip.csr 42575 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 42586 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_SET ns_noc_io_spio_soc_ip.csr 42597 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_SET ns_noc_io_spio_soc_ip.csr 42608 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_SET ns_noc_io_spio_soc_ip.csr 42620 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_SET ns_noc_io_spio_soc_ip.csr 42631 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 42642 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 42649 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 42766 spio_p00_dma_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 0x14160 R/W 0x0000000054053000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_SET ns_noc_io_spio_soc_ip.csr 42690 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 42701 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_SET ns_noc_io_spio_soc_ip.csr 42712 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 42724 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_SET ns_noc_io_spio_soc_ip.csr 42735 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_SET ns_noc_io_spio_soc_ip.csr 42747 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 42758 BASE_ADDRESS_0_33 Base address 39 6 0x0015014c0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 42765 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 42858 spio_p00_dma_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 0x14168 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_SET ns_noc_io_spio_soc_ip.csr 42783 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 42794 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_SET ns_noc_io_spio_soc_ip.csr 42805 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_SET ns_noc_io_spio_soc_ip.csr 42816 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_SET ns_noc_io_spio_soc_ip.csr 42828 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_SET ns_noc_io_spio_soc_ip.csr 42839 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 42850 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 42857 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 42974 spio_p00_dma_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 0x14180 R/W 0x0000000054054000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 42898 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 42909 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 42920 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 42932 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_SET ns_noc_io_spio_soc_ip.csr 42943 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_SET ns_noc_io_spio_soc_ip.csr 42955 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 42966 BASE_ADDRESS_0_33 Base address 39 6 0x001501500 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 42973 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 43066 spio_p00_dma_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 0x14188 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 42991 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 43002 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 43013 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_SET ns_noc_io_spio_soc_ip.csr 43024 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_SET ns_noc_io_spio_soc_ip.csr 43036 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_SET ns_noc_io_spio_soc_ip.csr 43047 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 43058 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 43065 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 43182 spio_p00_dma_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 0x141A0 R/W 0x0000000054055000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_SET ns_noc_io_spio_soc_ip.csr 43106 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_SET ns_noc_io_spio_soc_ip.csr 43117 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_SET ns_noc_io_spio_soc_ip.csr 43128 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 43140 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_SET ns_noc_io_spio_soc_ip.csr 43151 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_SET ns_noc_io_spio_soc_ip.csr 43163 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 43174 BASE_ADDRESS_0_33 Base address 39 6 0x001501540 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 43181 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 43274 spio_p00_dma_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 0x141A8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_SET ns_noc_io_spio_soc_ip.csr 43199 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_SET ns_noc_io_spio_soc_ip.csr 43210 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_SET ns_noc_io_spio_soc_ip.csr 43221 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_SET ns_noc_io_spio_soc_ip.csr 43232 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_SET ns_noc_io_spio_soc_ip.csr 43244 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_SET ns_noc_io_spio_soc_ip.csr 43255 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 43266 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 43273 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 43390 spio_p00_dma_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 0x141C0 R/W 0x0000000054056000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_SET ns_noc_io_spio_soc_ip.csr 43314 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_SET ns_noc_io_spio_soc_ip.csr 43325 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_SET ns_noc_io_spio_soc_ip.csr 43336 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 43348 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_SET ns_noc_io_spio_soc_ip.csr 43359 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_SET ns_noc_io_spio_soc_ip.csr 43371 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 43382 BASE_ADDRESS_0_33 Base address 39 6 0x001501580 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 43389 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 43482 spio_p00_dma_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 0x141C8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_SET ns_noc_io_spio_soc_ip.csr 43407 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_SET ns_noc_io_spio_soc_ip.csr 43418 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_SET ns_noc_io_spio_soc_ip.csr 43429 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_SET ns_noc_io_spio_soc_ip.csr 43440 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_SET ns_noc_io_spio_soc_ip.csr 43452 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_SET ns_noc_io_spio_soc_ip.csr 43463 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 43474 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 43481 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 43598 spio_p00_dma_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 0x141E0 R/W 0x0000000054057000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_SET ns_noc_io_spio_soc_ip.csr 43522 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_SET ns_noc_io_spio_soc_ip.csr 43533 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_SET ns_noc_io_spio_soc_ip.csr 43544 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 43556 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_SET ns_noc_io_spio_soc_ip.csr 43567 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_SET ns_noc_io_spio_soc_ip.csr 43579 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 43590 BASE_ADDRESS_0_33 Base address 39 6 0x0015015c0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 43597 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 43690 spio_p00_dma_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 0x141E8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_SET ns_noc_io_spio_soc_ip.csr 43615 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_SET ns_noc_io_spio_soc_ip.csr 43626 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_SET ns_noc_io_spio_soc_ip.csr 43637 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_SET ns_noc_io_spio_soc_ip.csr 43648 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_SET ns_noc_io_spio_soc_ip.csr 43660 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_SET ns_noc_io_spio_soc_ip.csr 43671 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 43682 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 43689 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 43806 spio_p00_dma_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 0x14200 R/W 0x0000000050000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_SET ns_noc_io_spio_soc_ip.csr 43730 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_SET ns_noc_io_spio_soc_ip.csr 43741 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_SET ns_noc_io_spio_soc_ip.csr 43752 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 43764 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_SET ns_noc_io_spio_soc_ip.csr 43775 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_SET ns_noc_io_spio_soc_ip.csr 43787 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 43798 BASE_ADDRESS_0_33 Base address 39 6 0x001400000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 43805 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 43898 spio_p00_dma_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 0x14208 R/W 0x000000fffe000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_SET ns_noc_io_spio_soc_ip.csr 43823 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_SET ns_noc_io_spio_soc_ip.csr 43834 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_SET ns_noc_io_spio_soc_ip.csr 43845 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_SET ns_noc_io_spio_soc_ip.csr 43856 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_SET ns_noc_io_spio_soc_ip.csr 43868 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_SET ns_noc_io_spio_soc_ip.csr 43879 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 43890 MASK_0_33 Mask 39 6 0x3fff80000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 43897 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 44014 spio_p00_dma_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 0x14220 R/W 0x0000000052000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 43938 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 43949 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 43960 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 43972 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_SET ns_noc_io_spio_soc_ip.csr 43983 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_SET ns_noc_io_spio_soc_ip.csr 43995 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 44006 BASE_ADDRESS_0_33 Base address 39 6 0x001480000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 44013 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 44106 spio_p00_dma_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 0x14228 R/W 0x000000fffffe0000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 44031 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 44042 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 44053 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_SET ns_noc_io_spio_soc_ip.csr 44064 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_SET ns_noc_io_spio_soc_ip.csr 44076 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_SET ns_noc_io_spio_soc_ip.csr 44087 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 44098 MASK_0_33 Mask 39 6 0x3fffff800 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 44105 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 44222 spio_p00_dma_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 0x14240 R/W 0x0000000052020000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_SET ns_noc_io_spio_soc_ip.csr 44146 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 44157 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_SET ns_noc_io_spio_soc_ip.csr 44168 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 44180 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_SET ns_noc_io_spio_soc_ip.csr 44191 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_SET ns_noc_io_spio_soc_ip.csr 44203 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 44214 BASE_ADDRESS_0_33 Base address 39 6 0x001480800 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 44221 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 44314 spio_p00_dma_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 0x14248 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_SET ns_noc_io_spio_soc_ip.csr 44239 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 44250 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_SET ns_noc_io_spio_soc_ip.csr 44261 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_SET ns_noc_io_spio_soc_ip.csr 44272 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_SET ns_noc_io_spio_soc_ip.csr 44284 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_SET ns_noc_io_spio_soc_ip.csr 44295 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 44306 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 44313 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 44430 spio_p00_dma_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 0x14260 R/W 0x0000000052021000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_SET ns_noc_io_spio_soc_ip.csr 44354 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 44365 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_SET ns_noc_io_spio_soc_ip.csr 44376 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 44388 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_SET ns_noc_io_spio_soc_ip.csr 44399 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_SET ns_noc_io_spio_soc_ip.csr 44411 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 44422 BASE_ADDRESS_0_33 Base address 39 6 0x001480840 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 44429 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 44522 spio_p00_dma_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 0x14268 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_SET ns_noc_io_spio_soc_ip.csr 44447 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 44458 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_SET ns_noc_io_spio_soc_ip.csr 44469 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_SET ns_noc_io_spio_soc_ip.csr 44480 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_SET ns_noc_io_spio_soc_ip.csr 44492 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_SET ns_noc_io_spio_soc_ip.csr 44503 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 44514 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 44521 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 44638 spio_p00_dma_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 0x14280 R/W 0x0000000052022000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_SET ns_noc_io_spio_soc_ip.csr 44562 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 44573 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_SET ns_noc_io_spio_soc_ip.csr 44584 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 44596 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_SET ns_noc_io_spio_soc_ip.csr 44607 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_SET ns_noc_io_spio_soc_ip.csr 44619 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 44630 BASE_ADDRESS_0_33 Base address 39 6 0x001480880 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 44637 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 44730 spio_p00_dma_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 0x14288 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_SET ns_noc_io_spio_soc_ip.csr 44655 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 44666 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_SET ns_noc_io_spio_soc_ip.csr 44677 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_SET ns_noc_io_spio_soc_ip.csr 44688 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_SET ns_noc_io_spio_soc_ip.csr 44700 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_SET ns_noc_io_spio_soc_ip.csr 44711 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 44722 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 44729 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 44846 spio_p00_dma_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 0x142A0 R/W 0x0000000052023000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 44770 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 44781 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 44792 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 44804 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 44815 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 44827 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 44838 BASE_ADDRESS_0_33 Base address 39 6 0x0014808c0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 44845 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 44938 spio_p00_dma_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 0x142A8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 44863 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 44874 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 44885 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 44896 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 44908 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 44919 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 44930 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 44937 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 45054 spio_p00_dma_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 0x142C0 R/W 0x0000000052024000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_SET ns_noc_io_spio_soc_ip.csr 44978 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 44989 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_SET ns_noc_io_spio_soc_ip.csr 45000 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 45012 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_SET ns_noc_io_spio_soc_ip.csr 45023 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_SET ns_noc_io_spio_soc_ip.csr 45035 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 45046 BASE_ADDRESS_0_33 Base address 39 6 0x001480900 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 45053 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 45146 spio_p00_dma_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 0x142C8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_SET ns_noc_io_spio_soc_ip.csr 45071 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 45082 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_SET ns_noc_io_spio_soc_ip.csr 45093 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_SET ns_noc_io_spio_soc_ip.csr 45104 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_SET ns_noc_io_spio_soc_ip.csr 45116 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_SET ns_noc_io_spio_soc_ip.csr 45127 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 45138 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 45145 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 45262 spio_p00_dma_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 0x142E0 R/W 0x0000000052025000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_SET ns_noc_io_spio_soc_ip.csr 45186 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 45197 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_SET ns_noc_io_spio_soc_ip.csr 45208 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 45220 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_SET ns_noc_io_spio_soc_ip.csr 45231 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_SET ns_noc_io_spio_soc_ip.csr 45243 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 45254 BASE_ADDRESS_0_33 Base address 39 6 0x001480940 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 45261 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 45354 spio_p00_dma_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 0x142E8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_SET ns_noc_io_spio_soc_ip.csr 45279 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 45290 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_SET ns_noc_io_spio_soc_ip.csr 45301 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_SET ns_noc_io_spio_soc_ip.csr 45312 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_SET ns_noc_io_spio_soc_ip.csr 45324 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_SET ns_noc_io_spio_soc_ip.csr 45335 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 45346 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 45353 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 45470 spio_p00_dma_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 0x14300 R/W 0x0000000052026000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_SET ns_noc_io_spio_soc_ip.csr 45394 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 45405 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_SET ns_noc_io_spio_soc_ip.csr 45416 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 45428 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_SET ns_noc_io_spio_soc_ip.csr 45439 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_SET ns_noc_io_spio_soc_ip.csr 45451 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 45462 BASE_ADDRESS_0_33 Base address 39 6 0x001480980 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 45469 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 45562 spio_p00_dma_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 0x14308 R/W 0x000000ffffffe000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_SET ns_noc_io_spio_soc_ip.csr 45487 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 45498 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_SET ns_noc_io_spio_soc_ip.csr 45509 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_SET ns_noc_io_spio_soc_ip.csr 45520 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_SET ns_noc_io_spio_soc_ip.csr 45532 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_SET ns_noc_io_spio_soc_ip.csr 45543 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 45554 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 45561 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 45678 spio_p00_dma_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 0x14320 R/W 0x0000000052028000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_SET ns_noc_io_spio_soc_ip.csr 45602 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 45613 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_SET ns_noc_io_spio_soc_ip.csr 45624 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 45636 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_SET ns_noc_io_spio_soc_ip.csr 45647 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_SET ns_noc_io_spio_soc_ip.csr 45659 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 45670 BASE_ADDRESS_0_33 Base address 39 6 0x001480a00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 45677 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 45770 spio_p00_dma_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 0x14328 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_SET ns_noc_io_spio_soc_ip.csr 45695 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 45706 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_SET ns_noc_io_spio_soc_ip.csr 45717 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_SET ns_noc_io_spio_soc_ip.csr 45728 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_SET ns_noc_io_spio_soc_ip.csr 45740 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_SET ns_noc_io_spio_soc_ip.csr 45751 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 45762 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 45769 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 45886 spio_p00_dma_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 0x14340 R/W 0x0000000052029000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_SET ns_noc_io_spio_soc_ip.csr 45810 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 45821 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_SET ns_noc_io_spio_soc_ip.csr 45832 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 45844 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_SET ns_noc_io_spio_soc_ip.csr 45855 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_SET ns_noc_io_spio_soc_ip.csr 45867 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 45878 BASE_ADDRESS_0_33 Base address 39 6 0x001480a40 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 45885 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 45978 spio_p00_dma_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 0x14348 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_SET ns_noc_io_spio_soc_ip.csr 45903 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 45914 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_SET ns_noc_io_spio_soc_ip.csr 45925 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_SET ns_noc_io_spio_soc_ip.csr 45936 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_SET ns_noc_io_spio_soc_ip.csr 45948 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_SET ns_noc_io_spio_soc_ip.csr 45959 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 45970 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 45977 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 46094 spio_p00_dma_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 0x14360 R/W 0x0000000054058000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_SET ns_noc_io_spio_soc_ip.csr 46018 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_SET ns_noc_io_spio_soc_ip.csr 46029 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_SET ns_noc_io_spio_soc_ip.csr 46040 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 46052 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_SET ns_noc_io_spio_soc_ip.csr 46063 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_SET ns_noc_io_spio_soc_ip.csr 46075 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 46086 BASE_ADDRESS_0_33 Base address 39 6 0x001501600 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 46093 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 46186 spio_p00_dma_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 0x14368 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_SET ns_noc_io_spio_soc_ip.csr 46111 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_SET ns_noc_io_spio_soc_ip.csr 46122 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_SET ns_noc_io_spio_soc_ip.csr 46133 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_SET ns_noc_io_spio_soc_ip.csr 46144 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_SET ns_noc_io_spio_soc_ip.csr 46156 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_SET ns_noc_io_spio_soc_ip.csr 46167 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 46178 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 46185 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 46302 spio_p00_dma_m register am_adbase_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 0x14380 R/W 0x0000000040300000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 46226 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 46237 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 46248 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 46260 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 46271 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 46283 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 46294 BASE_ADDRESS_0_33 Base address 39 6 0x00100c000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 46301 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 46394 spio_p00_dma_m register am_admask_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 0x14388 R/W 0x000000fffff00000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 46319 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 46330 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 46341 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 46352 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 46364 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 46375 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 46386 MASK_0_33 Mask 39 6 0x3ffffc000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 46393 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 46510 spio_p00_dma_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 0x143A0 R/W 0x0000000058200000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 46434 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 46445 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 46456 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 46468 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 46479 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 46491 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 46502 BASE_ADDRESS_0_33 Base address 39 6 0x001608000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 46509 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 46602 spio_p00_dma_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 0x143A8 R/W 0x000000ffffffe000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 46527 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 46538 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 46549 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 46560 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 46572 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 46583 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 46594 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 46601 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 46718 spio_p00_dma_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 0x143C0 R/W 0x0000000058400000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_SET ns_noc_io_spio_soc_ip.csr 46642 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 46653 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_SET ns_noc_io_spio_soc_ip.csr 46664 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 46676 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_SET ns_noc_io_spio_soc_ip.csr 46687 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_SET ns_noc_io_spio_soc_ip.csr 46699 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 46710 BASE_ADDRESS_0_33 Base address 39 6 0x001610000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 46717 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 46810 spio_p00_dma_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 0x143C8 R/W 0x000000ffffe00000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_SET ns_noc_io_spio_soc_ip.csr 46735 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 46746 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_SET ns_noc_io_spio_soc_ip.csr 46757 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_SET ns_noc_io_spio_soc_ip.csr 46768 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_SET ns_noc_io_spio_soc_ip.csr 46780 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_SET ns_noc_io_spio_soc_ip.csr 46791 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 46802 MASK_0_33 Mask 39 6 0x3ffff8000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 46809 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 46926 spio_p00_dma_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 0x143E0 R/W 0x0000004000000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_SET ns_noc_io_spio_soc_ip.csr 46850 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 46861 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_SET ns_noc_io_spio_soc_ip.csr 46872 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 46884 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_SET ns_noc_io_spio_soc_ip.csr 46895 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_SET ns_noc_io_spio_soc_ip.csr 46907 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 46918 BASE_ADDRESS_0_33 Base address 39 6 0x100000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 46925 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 47018 spio_p00_dma_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 0x143E8 R/W 0x000000e000000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_SET ns_noc_io_spio_soc_ip.csr 46943 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 46954 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_SET ns_noc_io_spio_soc_ip.csr 46965 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_SET ns_noc_io_spio_soc_ip.csr 46976 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_SET ns_noc_io_spio_soc_ip.csr 46988 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_SET ns_noc_io_spio_soc_ip.csr 46999 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 47010 MASK_0_33 Mask 39 6 0x380000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 47017 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 47134 spio_p00_dma_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 0x14400 R/W 0x0000006000000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_SET ns_noc_io_spio_soc_ip.csr 47058 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 47069 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_SET ns_noc_io_spio_soc_ip.csr 47080 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 47092 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_SET ns_noc_io_spio_soc_ip.csr 47103 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_SET ns_noc_io_spio_soc_ip.csr 47115 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 47126 BASE_ADDRESS_0_33 Base address 39 6 0x180000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 47133 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 47226 spio_p00_dma_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 0x14408 R/W 0x000000f000000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_SET ns_noc_io_spio_soc_ip.csr 47151 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 47162 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_SET ns_noc_io_spio_soc_ip.csr 47173 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_SET ns_noc_io_spio_soc_ip.csr 47184 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_SET ns_noc_io_spio_soc_ip.csr 47196 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_SET ns_noc_io_spio_soc_ip.csr 47207 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 47218 MASK_0_33 Mask 39 6 0x3c0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 47225 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 47342 spio_p00_dma_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 0x14420 R/W 0x0000007000000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_SET ns_noc_io_spio_soc_ip.csr 47266 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 47277 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_SET ns_noc_io_spio_soc_ip.csr 47288 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 47300 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_SET ns_noc_io_spio_soc_ip.csr 47311 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_SET ns_noc_io_spio_soc_ip.csr 47323 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 47334 BASE_ADDRESS_0_33 Base address 39 6 0x1c0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 47341 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 47434 spio_p00_dma_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 0x14428 R/W 0x000000f800000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_SET ns_noc_io_spio_soc_ip.csr 47359 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 47370 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_SET ns_noc_io_spio_soc_ip.csr 47381 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_SET ns_noc_io_spio_soc_ip.csr 47392 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_SET ns_noc_io_spio_soc_ip.csr 47404 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_SET ns_noc_io_spio_soc_ip.csr 47415 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 47426 MASK_0_33 Mask 39 6 0x3e0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 47433 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 47550 spio_p00_dma_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 0x14440 R/W 0x0000007800000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_SET ns_noc_io_spio_soc_ip.csr 47474 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 47485 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_SET ns_noc_io_spio_soc_ip.csr 47496 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 47508 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_SET ns_noc_io_spio_soc_ip.csr 47519 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_SET ns_noc_io_spio_soc_ip.csr 47531 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 47542 BASE_ADDRESS_0_33 Base address 39 6 0x1e0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 47549 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 47642 spio_p00_dma_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 0x14448 R/W 0x000000fc00000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_SET ns_noc_io_spio_soc_ip.csr 47567 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 47578 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_SET ns_noc_io_spio_soc_ip.csr 47589 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_SET ns_noc_io_spio_soc_ip.csr 47600 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_SET ns_noc_io_spio_soc_ip.csr 47612 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_SET ns_noc_io_spio_soc_ip.csr 47623 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 47634 MASK_0_33 Mask 39 6 0x3f0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 47641 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 47758 spio_p00_dma_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 0x14460 R/W 0x0000007c00000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_SET ns_noc_io_spio_soc_ip.csr 47682 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 47693 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_SET ns_noc_io_spio_soc_ip.csr 47704 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 47716 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_SET ns_noc_io_spio_soc_ip.csr 47727 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_SET ns_noc_io_spio_soc_ip.csr 47739 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 47750 BASE_ADDRESS_0_33 Base address 39 6 0x1f0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 47757 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 47850 spio_p00_dma_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 0x14468 R/W 0x000000fe00000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_SET ns_noc_io_spio_soc_ip.csr 47775 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 47786 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_SET ns_noc_io_spio_soc_ip.csr 47797 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_SET ns_noc_io_spio_soc_ip.csr 47808 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_SET ns_noc_io_spio_soc_ip.csr 47820 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_SET ns_noc_io_spio_soc_ip.csr 47831 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 47842 MASK_0_33 Mask 39 6 0x3f8000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 47849 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 47966 spio_p00_dma_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 0x14480 R/W 0x0000007e00000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_SET ns_noc_io_spio_soc_ip.csr 47890 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 47901 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_SET ns_noc_io_spio_soc_ip.csr 47912 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 47924 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_SET ns_noc_io_spio_soc_ip.csr 47935 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_SET ns_noc_io_spio_soc_ip.csr 47947 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 47958 BASE_ADDRESS_0_33 Base address 39 6 0x1f8000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 47965 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 48058 spio_p00_dma_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 0x14488 R/W 0x000000ff00000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_SET ns_noc_io_spio_soc_ip.csr 47983 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 47994 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_SET ns_noc_io_spio_soc_ip.csr 48005 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_SET ns_noc_io_spio_soc_ip.csr 48016 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_SET ns_noc_io_spio_soc_ip.csr 48028 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_SET ns_noc_io_spio_soc_ip.csr 48039 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 48050 MASK_0_33 Mask 39 6 0x3fc000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 48057 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 48174 spio_p00_dma_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 0x144A0 R/W 0x0000007f00000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_SET ns_noc_io_spio_soc_ip.csr 48098 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 48109 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_SET ns_noc_io_spio_soc_ip.csr 48120 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 48132 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_SET ns_noc_io_spio_soc_ip.csr 48143 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_SET ns_noc_io_spio_soc_ip.csr 48155 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 48166 BASE_ADDRESS_0_33 Base address 39 6 0x1fc000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 48173 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 48266 spio_p00_dma_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 0x144A8 R/W 0x000000ff80000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_SET ns_noc_io_spio_soc_ip.csr 48191 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 48202 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_SET ns_noc_io_spio_soc_ip.csr 48213 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_SET ns_noc_io_spio_soc_ip.csr 48224 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_SET ns_noc_io_spio_soc_ip.csr 48236 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_SET ns_noc_io_spio_soc_ip.csr 48247 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 48258 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 48265 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 48382 spio_p00_dma_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 0x144C0 R/W 0x0000007f80000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 48306 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 48317 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 48328 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 48340 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_SET ns_noc_io_spio_soc_ip.csr 48351 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_SET ns_noc_io_spio_soc_ip.csr 48363 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 48374 BASE_ADDRESS_0_33 Base address 39 6 0x1fe000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 48381 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 48474 spio_p00_dma_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 0x144C8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 48399 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 48410 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 48421 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_SET ns_noc_io_spio_soc_ip.csr 48432 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_SET ns_noc_io_spio_soc_ip.csr 48444 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_SET ns_noc_io_spio_soc_ip.csr 48455 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 48466 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 48473 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 48590 spio_p00_dma_m register am_adbase_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 0x144E0 R/W 0x0000000052100000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 48514 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 48525 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 48536 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 48548 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 48559 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 48571 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 48582 BASE_ADDRESS_0_33 Base address 39 6 0x001484000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 48589 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 48682 spio_p00_dma_m register am_admask_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 0x144E8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 48607 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 48618 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 48629 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 48640 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 48652 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 48663 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 48674 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 48681 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 48798 spio_p00_dma_m register am_adbase_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 0x14500 R/W 0x0000000042000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 48722 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 48733 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 48744 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 48756 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 48767 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 48779 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 48790 BASE_ADDRESS_0_33 Base address 39 6 0x001080000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 48797 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 48890 spio_p00_dma_m register am_admask_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 0x14508 R/W 0x000000fffe000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 48815 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 48826 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 48837 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 48848 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 48860 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 48871 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 48882 MASK_0_33 Mask 39 6 0x3fff80000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 48889 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 49006 spio_p00_dma_m register am_adbase_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 0x14520 R/W 0x0000000040200000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 48930 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 48941 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 48952 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 48964 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 48975 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 48987 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 48998 BASE_ADDRESS_0_33 Base address 39 6 0x001008000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 49005 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 49098 spio_p00_dma_m register am_admask_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 0x14528 R/W 0x000000fffff00000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 49023 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 49034 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 49045 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 49056 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 49068 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 49079 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 49090 MASK_0_33 Mask 39 6 0x3ffffc000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 49097 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 49214 spio_p00_dma_m register am_adbase_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 0x14540 R/W 0x0000000040400000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 49138 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 49149 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 49160 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 49172 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 49183 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 49195 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 49206 BASE_ADDRESS_0_33 Base address 39 6 0x001010000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 49213 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 49306 spio_p00_dma_m register am_admask_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 0x14548 R/W 0x000000fffff00000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 49231 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 49242 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 49253 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 49264 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 49276 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 49287 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 49298 MASK_0_33 Mask 39 6 0x3ffffc000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 49305 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 49422 spio_p00_dma_m register am_adbase_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 0x14560 R/W 0x0000000040000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 49346 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 49357 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 49368 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 49380 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 49391 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 49403 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 49414 BASE_ADDRESS_0_33 Base address 39 6 0x001000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 49421 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 49514 spio_p00_dma_m register am_admask_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 0x14568 R/W 0x000000ffffff0000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 49439 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 49450 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 49461 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 49472 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 49484 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 49495 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 49506 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 49513 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 49630 spio_p00_dma_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 0x14580 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 49554 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 49565 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 49576 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 49588 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 49599 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 49611 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 49622 BASE_ADDRESS_0_33 Base address 39 6 0x000000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 49629 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 49722 spio_p00_dma_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 0x14588 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 49647 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 49658 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 49669 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 49680 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 49692 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 49703 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 49714 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 49721 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 49838 spio_p00_dma_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 0x145A0 R/W 0x0000000000003000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_SET ns_noc_io_spio_soc_ip.csr 49762 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 49773 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_SET ns_noc_io_spio_soc_ip.csr 49784 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 49796 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_SET ns_noc_io_spio_soc_ip.csr 49807 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_SET ns_noc_io_spio_soc_ip.csr 49819 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 49830 BASE_ADDRESS_0_33 Base address 39 6 0x0000000c0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 49837 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 49930 spio_p00_dma_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 0x145A8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_SET ns_noc_io_spio_soc_ip.csr 49855 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 49866 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_SET ns_noc_io_spio_soc_ip.csr 49877 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_SET ns_noc_io_spio_soc_ip.csr 49888 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_SET ns_noc_io_spio_soc_ip.csr 49900 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_SET ns_noc_io_spio_soc_ip.csr 49911 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 49922 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 49929 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 50046 spio_p00_dma_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 0x145C0 R/W 0x0000000000010000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_SET ns_noc_io_spio_soc_ip.csr 49970 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 49981 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_SET ns_noc_io_spio_soc_ip.csr 49992 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 50004 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_SET ns_noc_io_spio_soc_ip.csr 50015 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_SET ns_noc_io_spio_soc_ip.csr 50027 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 50038 BASE_ADDRESS_0_33 Base address 39 6 0x000000400 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 50045 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 50138 spio_p00_dma_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 0x145C8 R/W 0x000000ffffffe000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_SET ns_noc_io_spio_soc_ip.csr 50063 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 50074 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_SET ns_noc_io_spio_soc_ip.csr 50085 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_SET ns_noc_io_spio_soc_ip.csr 50096 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_SET ns_noc_io_spio_soc_ip.csr 50108 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_SET ns_noc_io_spio_soc_ip.csr 50119 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 50130 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 50137 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 50254 spio_p00_dma_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 0x145E0 R/W 0x0000000000100000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_SET ns_noc_io_spio_soc_ip.csr 50178 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 50189 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_SET ns_noc_io_spio_soc_ip.csr 50200 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 50212 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_SET ns_noc_io_spio_soc_ip.csr 50223 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_SET ns_noc_io_spio_soc_ip.csr 50235 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 50246 BASE_ADDRESS_0_33 Base address 39 6 0x000004000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 50253 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 50346 spio_p00_dma_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 0x145E8 R/W 0x000000ffffff8000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_SET ns_noc_io_spio_soc_ip.csr 50271 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 50282 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_SET ns_noc_io_spio_soc_ip.csr 50293 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_SET ns_noc_io_spio_soc_ip.csr 50304 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_SET ns_noc_io_spio_soc_ip.csr 50316 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_SET ns_noc_io_spio_soc_ip.csr 50327 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 50338 MASK_0_33 Mask 39 6 0x3fffffe00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 50345 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 50462 spio_p00_dma_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 0x14600 R/W 0x0000000000200000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_SET ns_noc_io_spio_soc_ip.csr 50386 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 50397 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_SET ns_noc_io_spio_soc_ip.csr 50408 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 50420 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_SET ns_noc_io_spio_soc_ip.csr 50431 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_SET ns_noc_io_spio_soc_ip.csr 50443 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 50454 BASE_ADDRESS_0_33 Base address 39 6 0x000008000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 50461 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 50554 spio_p00_dma_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 0x14608 R/W 0x000000ffffffc000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_SET ns_noc_io_spio_soc_ip.csr 50479 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 50490 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_SET ns_noc_io_spio_soc_ip.csr 50501 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_SET ns_noc_io_spio_soc_ip.csr 50512 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_SET ns_noc_io_spio_soc_ip.csr 50524 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_SET ns_noc_io_spio_soc_ip.csr 50535 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 50546 MASK_0_33 Mask 39 6 0x3ffffff00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 50553 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 50670 spio_p00_dma_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 0x14620 R/W 0x0000000000300000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_SET ns_noc_io_spio_soc_ip.csr 50594 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 50605 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_SET ns_noc_io_spio_soc_ip.csr 50616 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 50628 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_SET ns_noc_io_spio_soc_ip.csr 50639 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_SET ns_noc_io_spio_soc_ip.csr 50651 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 50662 BASE_ADDRESS_0_33 Base address 39 6 0x00000c000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 50669 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 50762 spio_p00_dma_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 0x14628 R/W 0x000000ffffffc000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_SET ns_noc_io_spio_soc_ip.csr 50687 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 50698 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_SET ns_noc_io_spio_soc_ip.csr 50709 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_SET ns_noc_io_spio_soc_ip.csr 50720 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_SET ns_noc_io_spio_soc_ip.csr 50732 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_SET ns_noc_io_spio_soc_ip.csr 50743 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 50754 MASK_0_33 Mask 39 6 0x3ffffff00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 50761 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 50878 spio_p00_dma_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 0x14640 R/W 0x0000000002000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_SET ns_noc_io_spio_soc_ip.csr 50802 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 50813 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_SET ns_noc_io_spio_soc_ip.csr 50824 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 50836 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_SET ns_noc_io_spio_soc_ip.csr 50847 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_SET ns_noc_io_spio_soc_ip.csr 50859 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 50870 BASE_ADDRESS_0_33 Base address 39 6 0x000080000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 50877 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 50970 spio_p00_dma_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 0x14648 R/W 0x000000ffffff0000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_SET ns_noc_io_spio_soc_ip.csr 50895 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 50906 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_SET ns_noc_io_spio_soc_ip.csr 50917 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_SET ns_noc_io_spio_soc_ip.csr 50928 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_SET ns_noc_io_spio_soc_ip.csr 50940 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_SET ns_noc_io_spio_soc_ip.csr 50951 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 50962 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 50969 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 51086 spio_p00_dma_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 0x14660 R/W 0x0000000010000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_SET ns_noc_io_spio_soc_ip.csr 51010 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 51021 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_SET ns_noc_io_spio_soc_ip.csr 51032 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 51044 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_SET ns_noc_io_spio_soc_ip.csr 51055 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_SET ns_noc_io_spio_soc_ip.csr 51067 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 51078 BASE_ADDRESS_0_33 Base address 39 6 0x000400000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 51085 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 51178 spio_p00_dma_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 0x14668 R/W 0x000000fffe000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_SET ns_noc_io_spio_soc_ip.csr 51103 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 51114 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_SET ns_noc_io_spio_soc_ip.csr 51125 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_SET ns_noc_io_spio_soc_ip.csr 51136 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_SET ns_noc_io_spio_soc_ip.csr 51148 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_SET ns_noc_io_spio_soc_ip.csr 51159 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 51170 MASK_0_33 Mask 39 6 0x3fff80000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 51177 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 51294 spio_p00_dma_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 0x14680 R/W 0x0000000012000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_SET ns_noc_io_spio_soc_ip.csr 51218 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 51229 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_SET ns_noc_io_spio_soc_ip.csr 51240 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 51252 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_SET ns_noc_io_spio_soc_ip.csr 51263 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_SET ns_noc_io_spio_soc_ip.csr 51275 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 51286 BASE_ADDRESS_0_33 Base address 39 6 0x000480000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 51293 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 51386 spio_p00_dma_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 0x14688 R/W 0x000000ffffff8000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_SET ns_noc_io_spio_soc_ip.csr 51311 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 51322 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_SET ns_noc_io_spio_soc_ip.csr 51333 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_SET ns_noc_io_spio_soc_ip.csr 51344 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_SET ns_noc_io_spio_soc_ip.csr 51356 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_SET ns_noc_io_spio_soc_ip.csr 51367 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 51378 MASK_0_33 Mask 39 6 0x3fffffe00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 51385 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 51502 spio_p00_dma_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 0x146A0 R/W 0x0000000012008000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 51426 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 51437 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 51448 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 51460 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_SET ns_noc_io_spio_soc_ip.csr 51471 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_SET ns_noc_io_spio_soc_ip.csr 51483 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 51494 BASE_ADDRESS_0_33 Base address 39 6 0x000480200 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 51501 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 51594 spio_p00_dma_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 0x146A8 R/W 0x000000ffffffe000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 51519 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 51530 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 51541 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_SET ns_noc_io_spio_soc_ip.csr 51552 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_SET ns_noc_io_spio_soc_ip.csr 51564 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_SET ns_noc_io_spio_soc_ip.csr 51575 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 51586 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 51593 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 51710 spio_p00_dma_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 0x146C0 R/W 0x000000001200a000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_SET ns_noc_io_spio_soc_ip.csr 51634 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_SET ns_noc_io_spio_soc_ip.csr 51645 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_SET ns_noc_io_spio_soc_ip.csr 51656 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 51668 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_SET ns_noc_io_spio_soc_ip.csr 51679 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_SET ns_noc_io_spio_soc_ip.csr 51691 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 51702 BASE_ADDRESS_0_33 Base address 39 6 0x000480280 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 51709 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 51802 spio_p00_dma_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 0x146C8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_SET ns_noc_io_spio_soc_ip.csr 51727 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_SET ns_noc_io_spio_soc_ip.csr 51738 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_SET ns_noc_io_spio_soc_ip.csr 51749 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_SET ns_noc_io_spio_soc_ip.csr 51760 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_SET ns_noc_io_spio_soc_ip.csr 51772 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_SET ns_noc_io_spio_soc_ip.csr 51783 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 51794 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 51801 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 51918 spio_p00_dma_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 0x146E0 R/W 0x0000000014000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_SET ns_noc_io_spio_soc_ip.csr 51842 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_SET ns_noc_io_spio_soc_ip.csr 51853 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_SET ns_noc_io_spio_soc_ip.csr 51864 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 51876 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_SET ns_noc_io_spio_soc_ip.csr 51887 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_SET ns_noc_io_spio_soc_ip.csr 51899 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 51910 BASE_ADDRESS_0_33 Base address 39 6 0x000500000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 51917 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 52010 spio_p00_dma_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 0x146E8 R/W 0x000000fffffc0000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_SET ns_noc_io_spio_soc_ip.csr 51935 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_SET ns_noc_io_spio_soc_ip.csr 51946 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_SET ns_noc_io_spio_soc_ip.csr 51957 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_SET ns_noc_io_spio_soc_ip.csr 51968 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_SET ns_noc_io_spio_soc_ip.csr 51980 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_SET ns_noc_io_spio_soc_ip.csr 51991 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 52002 MASK_0_33 Mask 39 6 0x3fffff000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 52009 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 52126 spio_p00_dma_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 0x14700 R/W 0x0000000018000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_SET ns_noc_io_spio_soc_ip.csr 52050 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_SET ns_noc_io_spio_soc_ip.csr 52061 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_SET ns_noc_io_spio_soc_ip.csr 52072 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 52084 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_SET ns_noc_io_spio_soc_ip.csr 52095 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_SET ns_noc_io_spio_soc_ip.csr 52107 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 52118 BASE_ADDRESS_0_33 Base address 39 6 0x000600000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 52125 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 52218 spio_p00_dma_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 0x14708 R/W 0x000000fffff80000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_SET ns_noc_io_spio_soc_ip.csr 52143 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_SET ns_noc_io_spio_soc_ip.csr 52154 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_SET ns_noc_io_spio_soc_ip.csr 52165 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_SET ns_noc_io_spio_soc_ip.csr 52176 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_SET ns_noc_io_spio_soc_ip.csr 52188 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_SET ns_noc_io_spio_soc_ip.csr 52199 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 52210 MASK_0_33 Mask 39 6 0x3ffffe000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 52217 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 52334 spio_p00_dma_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 0x14720 R/W 0x0000000018080000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_SET ns_noc_io_spio_soc_ip.csr 52258 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_SET ns_noc_io_spio_soc_ip.csr 52269 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_SET ns_noc_io_spio_soc_ip.csr 52280 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 52292 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_SET ns_noc_io_spio_soc_ip.csr 52303 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_SET ns_noc_io_spio_soc_ip.csr 52315 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 52326 BASE_ADDRESS_0_33 Base address 39 6 0x000602000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 52333 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 52426 spio_p00_dma_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 0x14728 R/W 0x000000ffffffe000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_SET ns_noc_io_spio_soc_ip.csr 52351 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_SET ns_noc_io_spio_soc_ip.csr 52362 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_SET ns_noc_io_spio_soc_ip.csr 52373 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_SET ns_noc_io_spio_soc_ip.csr 52384 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_SET ns_noc_io_spio_soc_ip.csr 52396 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_SET ns_noc_io_spio_soc_ip.csr 52407 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 52418 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 52425 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 52542 spio_p00_dma_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 0x14740 R/W 0x0000000018082000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_SET ns_noc_io_spio_soc_ip.csr 52466 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_SET ns_noc_io_spio_soc_ip.csr 52477 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_SET ns_noc_io_spio_soc_ip.csr 52488 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 52500 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_SET ns_noc_io_spio_soc_ip.csr 52511 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_SET ns_noc_io_spio_soc_ip.csr 52523 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 52534 BASE_ADDRESS_0_33 Base address 39 6 0x000602080 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 52541 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 52634 spio_p00_dma_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 0x14748 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_SET ns_noc_io_spio_soc_ip.csr 52559 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_SET ns_noc_io_spio_soc_ip.csr 52570 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_SET ns_noc_io_spio_soc_ip.csr 52581 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_SET ns_noc_io_spio_soc_ip.csr 52592 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_SET ns_noc_io_spio_soc_ip.csr 52604 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_SET ns_noc_io_spio_soc_ip.csr 52615 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 52626 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 52633 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 52750 spio_p00_dma_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 0x14760 R/W 0x0000000020000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_SET ns_noc_io_spio_soc_ip.csr 52674 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_SET ns_noc_io_spio_soc_ip.csr 52685 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_SET ns_noc_io_spio_soc_ip.csr 52696 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 52708 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_SET ns_noc_io_spio_soc_ip.csr 52719 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_SET ns_noc_io_spio_soc_ip.csr 52731 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 52742 BASE_ADDRESS_0_33 Base address 39 6 0x000800000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 52749 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 52842 spio_p00_dma_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 0x14768 R/W 0x000000fffffc0000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_SET ns_noc_io_spio_soc_ip.csr 52767 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_SET ns_noc_io_spio_soc_ip.csr 52778 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_SET ns_noc_io_spio_soc_ip.csr 52789 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_SET ns_noc_io_spio_soc_ip.csr 52800 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_SET ns_noc_io_spio_soc_ip.csr 52812 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_SET ns_noc_io_spio_soc_ip.csr 52823 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 52834 MASK_0_33 Mask 39 6 0x3fffff000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 52841 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 52958 spio_p00_dma_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 0x14780 R/W 0x0000000030000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_SET ns_noc_io_spio_soc_ip.csr 52882 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_SET ns_noc_io_spio_soc_ip.csr 52893 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_SET ns_noc_io_spio_soc_ip.csr 52904 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 52916 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_SET ns_noc_io_spio_soc_ip.csr 52927 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_SET ns_noc_io_spio_soc_ip.csr 52939 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 52950 BASE_ADDRESS_0_33 Base address 39 6 0x000c00000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 52957 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 53050 spio_p00_dma_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 0x14788 R/W 0x000000ffffff8000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_SET ns_noc_io_spio_soc_ip.csr 52975 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_SET ns_noc_io_spio_soc_ip.csr 52986 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_SET ns_noc_io_spio_soc_ip.csr 52997 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_SET ns_noc_io_spio_soc_ip.csr 53008 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_SET ns_noc_io_spio_soc_ip.csr 53020 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_SET ns_noc_io_spio_soc_ip.csr 53031 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 53042 MASK_0_33 Mask 39 6 0x3fffffe00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 53049 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 53166 spio_p00_dma_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 0x147A0 R/W 0x0000000030008000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_SET ns_noc_io_spio_soc_ip.csr 53090 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_SET ns_noc_io_spio_soc_ip.csr 53101 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_SET ns_noc_io_spio_soc_ip.csr 53112 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 53124 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_SET ns_noc_io_spio_soc_ip.csr 53135 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_SET ns_noc_io_spio_soc_ip.csr 53147 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 53158 BASE_ADDRESS_0_33 Base address 39 6 0x000c00200 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 53165 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 53258 spio_p00_dma_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 0x147A8 R/W 0x000000ffffffc000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_SET ns_noc_io_spio_soc_ip.csr 53183 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_SET ns_noc_io_spio_soc_ip.csr 53194 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_SET ns_noc_io_spio_soc_ip.csr 53205 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_SET ns_noc_io_spio_soc_ip.csr 53216 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_SET ns_noc_io_spio_soc_ip.csr 53228 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_SET ns_noc_io_spio_soc_ip.csr 53239 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 53250 MASK_0_33 Mask 39 6 0x3ffffff00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 53257 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 53374 spio_p00_dma_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 0x147C0 R/W 0x0000000040080000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_SET ns_noc_io_spio_soc_ip.csr 53298 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_SET ns_noc_io_spio_soc_ip.csr 53309 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_SET ns_noc_io_spio_soc_ip.csr 53320 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 53332 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_SET ns_noc_io_spio_soc_ip.csr 53343 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_SET ns_noc_io_spio_soc_ip.csr 53355 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 53366 BASE_ADDRESS_0_33 Base address 39 6 0x001002000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 53373 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 53466 spio_p00_dma_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 0x147C8 R/W 0x000000ffffffe000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_SET ns_noc_io_spio_soc_ip.csr 53391 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_SET ns_noc_io_spio_soc_ip.csr 53402 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_SET ns_noc_io_spio_soc_ip.csr 53413 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_SET ns_noc_io_spio_soc_ip.csr 53424 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_SET ns_noc_io_spio_soc_ip.csr 53436 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_SET ns_noc_io_spio_soc_ip.csr 53447 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 53458 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 53465 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 53582 spio_p00_dma_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 0x147E0 R/W 0x0000000058000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_SET ns_noc_io_spio_soc_ip.csr 53506 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_SET ns_noc_io_spio_soc_ip.csr 53517 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_SET ns_noc_io_spio_soc_ip.csr 53528 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 53540 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_SET ns_noc_io_spio_soc_ip.csr 53551 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_SET ns_noc_io_spio_soc_ip.csr 53563 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 53574 BASE_ADDRESS_0_33 Base address 39 6 0x001600000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 53581 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 53674 spio_p00_dma_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 0x147E8 R/W 0x000000ffffffe000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_SET ns_noc_io_spio_soc_ip.csr 53599 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_SET ns_noc_io_spio_soc_ip.csr 53610 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_SET ns_noc_io_spio_soc_ip.csr 53621 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_SET ns_noc_io_spio_soc_ip.csr 53632 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_SET ns_noc_io_spio_soc_ip.csr 53644 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_SET ns_noc_io_spio_soc_ip.csr 53655 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 53666 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 53673 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 53790 spio_p00_dma_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 0x14800 R/W 0x0000000060000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_SET ns_noc_io_spio_soc_ip.csr 53714 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_SET ns_noc_io_spio_soc_ip.csr 53725 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_SET ns_noc_io_spio_soc_ip.csr 53736 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 53748 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_SET ns_noc_io_spio_soc_ip.csr 53759 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_SET ns_noc_io_spio_soc_ip.csr 53771 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 53782 BASE_ADDRESS_0_33 Base address 39 6 0x001800000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 53789 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 53882 spio_p00_dma_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 0x14808 R/W 0x000000ffe0000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_SET ns_noc_io_spio_soc_ip.csr 53807 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_SET ns_noc_io_spio_soc_ip.csr 53818 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_SET ns_noc_io_spio_soc_ip.csr 53829 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_SET ns_noc_io_spio_soc_ip.csr 53840 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_SET ns_noc_io_spio_soc_ip.csr 53852 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_SET ns_noc_io_spio_soc_ip.csr 53863 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 53874 MASK_0_33 Mask 39 6 0x3ff800000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 53881 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 53998 spio_p00_dma_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 0x14820 R/W 0x0000000080000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_SET ns_noc_io_spio_soc_ip.csr 53922 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_SET ns_noc_io_spio_soc_ip.csr 53933 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_SET ns_noc_io_spio_soc_ip.csr 53944 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 53956 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_SET ns_noc_io_spio_soc_ip.csr 53967 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_SET ns_noc_io_spio_soc_ip.csr 53979 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 53990 BASE_ADDRESS_0_33 Base address 39 6 0x002000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 53997 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 54090 spio_p00_dma_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 0x14828 R/W 0x000000ff80000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_SET ns_noc_io_spio_soc_ip.csr 54015 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_SET ns_noc_io_spio_soc_ip.csr 54026 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_SET ns_noc_io_spio_soc_ip.csr 54037 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_SET ns_noc_io_spio_soc_ip.csr 54048 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_SET ns_noc_io_spio_soc_ip.csr 54060 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_SET ns_noc_io_spio_soc_ip.csr 54071 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 54082 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 54089 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 54206 spio_p00_dma_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 0x14840 R/W 0x0000000100000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_SET ns_noc_io_spio_soc_ip.csr 54130 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_SET ns_noc_io_spio_soc_ip.csr 54141 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_SET ns_noc_io_spio_soc_ip.csr 54152 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 54164 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_SET ns_noc_io_spio_soc_ip.csr 54175 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_SET ns_noc_io_spio_soc_ip.csr 54187 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 54198 BASE_ADDRESS_0_33 Base address 39 6 0x004000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 54205 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 54298 spio_p00_dma_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 0x14848 R/W 0x000000ff00000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_SET ns_noc_io_spio_soc_ip.csr 54223 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_SET ns_noc_io_spio_soc_ip.csr 54234 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_SET ns_noc_io_spio_soc_ip.csr 54245 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_SET ns_noc_io_spio_soc_ip.csr 54256 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_SET ns_noc_io_spio_soc_ip.csr 54268 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_SET ns_noc_io_spio_soc_ip.csr 54279 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 54290 MASK_0_33 Mask 39 6 0x3fc000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 54297 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 54414 spio_p00_dma_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 0x14860 R/W 0x0000008000000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_SET ns_noc_io_spio_soc_ip.csr 54338 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_SET ns_noc_io_spio_soc_ip.csr 54349 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_SET ns_noc_io_spio_soc_ip.csr 54360 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 54372 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_SET ns_noc_io_spio_soc_ip.csr 54383 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_SET ns_noc_io_spio_soc_ip.csr 54395 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 54406 BASE_ADDRESS_0_33 Base address 39 6 0x200000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 54413 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 54506 spio_p00_dma_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 0x14868 R/W 0x000000f800000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_SET ns_noc_io_spio_soc_ip.csr 54431 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_SET ns_noc_io_spio_soc_ip.csr 54442 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_SET ns_noc_io_spio_soc_ip.csr 54453 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_SET ns_noc_io_spio_soc_ip.csr 54464 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_SET ns_noc_io_spio_soc_ip.csr 54476 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_SET ns_noc_io_spio_soc_ip.csr 54487 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 54498 MASK_0_33 Mask 39 6 0x3e0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 54505 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 54622 spio_p00_dma_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 0x14880 R/W 0x000000c000000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_SET ns_noc_io_spio_soc_ip.csr 54546 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_SET ns_noc_io_spio_soc_ip.csr 54557 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_SET ns_noc_io_spio_soc_ip.csr 54568 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 54580 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_SET ns_noc_io_spio_soc_ip.csr 54591 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_SET ns_noc_io_spio_soc_ip.csr 54603 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 54614 BASE_ADDRESS_0_33 Base address 39 6 0x300000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 54621 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 54714 spio_p00_dma_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 0x14888 R/W 0x000000f800000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_SET ns_noc_io_spio_soc_ip.csr 54639 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_SET ns_noc_io_spio_soc_ip.csr 54650 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_SET ns_noc_io_spio_soc_ip.csr 54661 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_SET ns_noc_io_spio_soc_ip.csr 54672 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_SET ns_noc_io_spio_soc_ip.csr 54684 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_SET ns_noc_io_spio_soc_ip.csr 54695 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 54706 MASK_0_33 Mask 39 6 0x3e0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 54713 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_p_0 bridge_spio_p00_dma_m_1_7_p_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 54779 spio_p00_dma_m register p_0 0x17000 R/W 0x00000003 Spio_noc_bridge_spio_p00_dma_m_1_7_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_0_SET ns_noc_io_spio_soc_ip.csr 54742 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_1_SET ns_noc_io_spio_soc_ip.csr 54754 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_2_SET ns_noc_io_spio_soc_ip.csr 54766 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_0_WT_QOS_3_SET ns_noc_io_spio_soc_ip.csr 54778 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register spio_noc.bridge_spio_p00_dma_m_1_7_p_1 bridge_spio_p00_dma_m_1_7_p_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 54845 spio_p00_dma_m register p_1 0x17008 R 0x00000000 Spio_noc_bridge_spio_p00_dma_m_1_7_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_4_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_4_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_4_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_4_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_4_SET ns_noc_io_spio_soc_ip.csr 54808 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_5_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_5_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_5_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_5_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_5_SET ns_noc_io_spio_soc_ip.csr 54820 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_6_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_6_SET ns_noc_io_spio_soc_ip.csr 54832 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_7_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_7_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_7_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_7_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_1_WT_QOS_7_SET ns_noc_io_spio_soc_ip.csr 54844 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register spio_noc.bridge_spio_p00_dma_m_1_7_p_2 bridge_spio_p00_dma_m_1_7_p_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 54911 spio_p00_dma_m register p_2 0x17010 R 0x00000000 Spio_noc_bridge_spio_p00_dma_m_1_7_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_8_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_8_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_8_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_8_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_8_SET ns_noc_io_spio_soc_ip.csr 54874 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_9_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_9_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_9_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_9_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_9_SET ns_noc_io_spio_soc_ip.csr 54886 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_10_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_10_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_10_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_10_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_10_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_10_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_10_SET ns_noc_io_spio_soc_ip.csr 54898 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_11_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_11_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_11_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_11_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_11_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_2_WT_QOS_11_SET ns_noc_io_spio_soc_ip.csr 54910 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register spio_noc.bridge_spio_p00_dma_m_1_7_p_3 bridge_spio_p00_dma_m_1_7_p_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 54977 spio_p00_dma_m register p_3 0x17018 R 0x00000000 Spio_noc_bridge_spio_p00_dma_m_1_7_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_12_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_12_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_12_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_12_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_12_SET ns_noc_io_spio_soc_ip.csr 54940 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_13_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_13_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_13_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_13_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_13_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_13_SET ns_noc_io_spio_soc_ip.csr 54952 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_14_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_14_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_14_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_14_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_14_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_14_SET ns_noc_io_spio_soc_ip.csr 54964 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_15_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_15_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_15_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_15_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_15_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_P_3_WT_QOS_15_SET ns_noc_io_spio_soc_ip.csr 54976 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register spio_noc.bridge_spio_p00_dma_m_1_7_txe bridge_spio_p00_dma_m_1_7_txe SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 55123 spio_p00_dma_m register txe 0x17040 R/W 0x00000000 Spio_noc_bridge_spio_p00_dma_m_1_7_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_TRANS_WITHOUT_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_TRANS_WITHOUT_SOP_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_TRANS_WITHOUT_SOP_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_TRANS_WITHOUT_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_TRANS_WITHOUT_SOP_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_TRANS_WITHOUT_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_TRANS_WITHOUT_SOP_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_spio_soc_ip.csr 55004 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_SOP_AFTER_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_SOP_AFTER_SOP_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_SOP_AFTER_SOP_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_SOP_AFTER_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_SOP_AFTER_SOP_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_SOP_AFTER_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_SOP_AFTER_SOP_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_SOP_AFTER_SOP_SET ns_noc_io_spio_soc_ip.csr 55016 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 55031 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 55044 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_spio_soc_ip.csr 55058 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_spio_soc_ip.csr 55072 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_spio_soc_ip.csr 55086 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_spio_soc_ip.csr 55100 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 55111 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXE_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 55122 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_txem bridge_spio_p00_dma_m_1_7_txem SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 55202 spio_p00_dma_m register txem 0x17048 R/W 0x00000008 Spio_noc_bridge_spio_p00_dma_m_1_7_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_UNSD_1_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_UNSD_1_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_UNSD_1_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_UNSD_1_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_UNSD_1_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_UNSD_1_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_UNSD_1_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_UNSD_1_0_SET ns_noc_io_spio_soc_ip.csr 55146 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 55157 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 55168 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_UNSD_7_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_UNSD_7_4_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_UNSD_7_4_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_UNSD_7_4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_UNSD_7_4_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_UNSD_7_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_UNSD_7_4_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_UNSD_7_4_SET ns_noc_io_spio_soc_ip.csr 55179 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 55190 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_TXEM_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 55201 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_btus_0 bridge_spio_p00_dma_m_1_7_btus_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 55570 spio_p00_dma_m register btus_0 0x17058 R 0x00000000 Spio_noc_bridge_spio_p00_dma_m_1_7_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_A_SET ns_noc_io_spio_soc_ip.csr 55228 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_B_SET ns_noc_io_spio_soc_ip.csr 55239 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_C_SET ns_noc_io_spio_soc_ip.csr 55250 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L0_D_SET ns_noc_io_spio_soc_ip.csr 55261 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_A_SET ns_noc_io_spio_soc_ip.csr 55272 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_B_SET ns_noc_io_spio_soc_ip.csr 55283 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_C_SET ns_noc_io_spio_soc_ip.csr 55294 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L1_D_SET ns_noc_io_spio_soc_ip.csr 55305 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_A_SET ns_noc_io_spio_soc_ip.csr 55316 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_B_SET ns_noc_io_spio_soc_ip.csr 55327 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_C_SET ns_noc_io_spio_soc_ip.csr 55338 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L2_D_SET ns_noc_io_spio_soc_ip.csr 55349 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_A_SET ns_noc_io_spio_soc_ip.csr 55360 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_B_SET ns_noc_io_spio_soc_ip.csr 55371 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_C_SET ns_noc_io_spio_soc_ip.csr 55382 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L3_D_SET ns_noc_io_spio_soc_ip.csr 55393 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_A_SET ns_noc_io_spio_soc_ip.csr 55404 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_B_SET ns_noc_io_spio_soc_ip.csr 55415 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_C_SET ns_noc_io_spio_soc_ip.csr 55426 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L4_D_SET ns_noc_io_spio_soc_ip.csr 55437 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_A_SET ns_noc_io_spio_soc_ip.csr 55448 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_B_SET ns_noc_io_spio_soc_ip.csr 55459 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_C_SET ns_noc_io_spio_soc_ip.csr 55470 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L5_D_SET ns_noc_io_spio_soc_ip.csr 55481 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_A_SET ns_noc_io_spio_soc_ip.csr 55492 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_B_SET ns_noc_io_spio_soc_ip.csr 55503 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_C_SET ns_noc_io_spio_soc_ip.csr 55514 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L6_D_SET ns_noc_io_spio_soc_ip.csr 55525 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_A_SET ns_noc_io_spio_soc_ip.csr 55536 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_B_SET ns_noc_io_spio_soc_ip.csr 55547 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_C_SET ns_noc_io_spio_soc_ip.csr 55558 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_0_L7_D_SET ns_noc_io_spio_soc_ip.csr 55569 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register spio_noc.bridge_spio_p00_dma_m_1_7_btus_1 bridge_spio_p00_dma_m_1_7_btus_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 55938 spio_p00_dma_m register btus_1 0x17060 R 0x00000000 Spio_noc_bridge_spio_p00_dma_m_1_7_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_A_SET ns_noc_io_spio_soc_ip.csr 55596 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_B_SET ns_noc_io_spio_soc_ip.csr 55607 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_C_SET ns_noc_io_spio_soc_ip.csr 55618 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L8_D_SET ns_noc_io_spio_soc_ip.csr 55629 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_A_SET ns_noc_io_spio_soc_ip.csr 55640 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_B_SET ns_noc_io_spio_soc_ip.csr 55651 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_C_SET ns_noc_io_spio_soc_ip.csr 55662 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L9_D_SET ns_noc_io_spio_soc_ip.csr 55673 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_A_SET ns_noc_io_spio_soc_ip.csr 55684 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_B_SET ns_noc_io_spio_soc_ip.csr 55695 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_C_SET ns_noc_io_spio_soc_ip.csr 55706 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L10_D_SET ns_noc_io_spio_soc_ip.csr 55717 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_A_SET ns_noc_io_spio_soc_ip.csr 55728 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_B_SET ns_noc_io_spio_soc_ip.csr 55739 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_C_SET ns_noc_io_spio_soc_ip.csr 55750 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L11_D_SET ns_noc_io_spio_soc_ip.csr 55761 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_A_SET ns_noc_io_spio_soc_ip.csr 55772 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_B_SET ns_noc_io_spio_soc_ip.csr 55783 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_C_SET ns_noc_io_spio_soc_ip.csr 55794 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L12_D_SET ns_noc_io_spio_soc_ip.csr 55805 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_A_SET ns_noc_io_spio_soc_ip.csr 55816 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_B_SET ns_noc_io_spio_soc_ip.csr 55827 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_C_SET ns_noc_io_spio_soc_ip.csr 55838 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L13_D_SET ns_noc_io_spio_soc_ip.csr 55849 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_A_SET ns_noc_io_spio_soc_ip.csr 55860 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_B_SET ns_noc_io_spio_soc_ip.csr 55871 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_C_SET ns_noc_io_spio_soc_ip.csr 55882 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L14_D_SET ns_noc_io_spio_soc_ip.csr 55893 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_A_SET ns_noc_io_spio_soc_ip.csr 55904 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_B_SET ns_noc_io_spio_soc_ip.csr 55915 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_C_SET ns_noc_io_spio_soc_ip.csr 55926 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTUS_1_L15_D_SET ns_noc_io_spio_soc_ip.csr 55937 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register spio_noc.bridge_spio_p00_dma_m_1_7_btrl_0 bridge_spio_p00_dma_m_1_7_btrl_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 56014 spio_p00_dma_m register btrl_0 0x17080 R 0x00000000 Spio_noc_bridge_spio_p00_dma_m_1_7_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_WT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_WT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_WT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_WT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_WT_SET ns_noc_io_spio_soc_ip.csr 55962 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 55973 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_CNT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_CNT_SET ns_noc_io_spio_soc_ip.csr 55988 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_EN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_EN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_EN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_EN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_EN_SET ns_noc_io_spio_soc_ip.csr 56002 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_0_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 56013 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p00_dma_m_1_7_btrl_1 bridge_spio_p00_dma_m_1_7_btrl_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 56090 spio_p00_dma_m register btrl_1 0x17088 R 0x00000000 Spio_noc_bridge_spio_p00_dma_m_1_7_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_WT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_WT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_WT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_WT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_WT_SET ns_noc_io_spio_soc_ip.csr 56038 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 56049 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_CNT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_CNT_SET ns_noc_io_spio_soc_ip.csr 56064 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_EN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_EN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_EN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_EN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_EN_SET ns_noc_io_spio_soc_ip.csr 56078 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_1_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 56089 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p00_dma_m_1_7_btrl_2 bridge_spio_p00_dma_m_1_7_btrl_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 56166 spio_p00_dma_m register btrl_2 0x17090 R 0x00000000 Spio_noc_bridge_spio_p00_dma_m_1_7_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_WT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_WT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_WT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_WT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_WT_SET ns_noc_io_spio_soc_ip.csr 56114 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 56125 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_CNT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_CNT_SET ns_noc_io_spio_soc_ip.csr 56140 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_EN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_EN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_EN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_EN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_EN_SET ns_noc_io_spio_soc_ip.csr 56154 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_2_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 56165 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p00_dma_m_1_7_btrl_3 bridge_spio_p00_dma_m_1_7_btrl_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 56242 spio_p00_dma_m register btrl_3 0x17098 R 0x00000000 Spio_noc_bridge_spio_p00_dma_m_1_7_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_WT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_WT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_WT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_WT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_WT_SET ns_noc_io_spio_soc_ip.csr 56190 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 56201 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_CNT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_CNT_SET ns_noc_io_spio_soc_ip.csr 56216 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_EN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_EN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_EN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_EN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_EN_SET ns_noc_io_spio_soc_ip.csr 56230 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTRL_3_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 56241 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p00_dma_m_1_7_btperr bridge_spio_p00_dma_m_1_7_btperr SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 56444 spio_p00_dma_m register btperr 0x170A8 R/W 0x00000000 Spio_noc_bridge_spio_p00_dma_m_1_7_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L0_SET ns_noc_io_spio_soc_ip.csr 56267 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L1_SET ns_noc_io_spio_soc_ip.csr 56278 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L2_SET ns_noc_io_spio_soc_ip.csr 56289 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L3_SET ns_noc_io_spio_soc_ip.csr 56300 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L4_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L4_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L4_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L4_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L4_SET ns_noc_io_spio_soc_ip.csr 56311 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L5_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L5_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L5_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L5_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L5_SET ns_noc_io_spio_soc_ip.csr 56322 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L6_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L6_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L6_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L6_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L6_SET ns_noc_io_spio_soc_ip.csr 56333 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L7_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L7_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L7_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L7_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L7_SET ns_noc_io_spio_soc_ip.csr 56344 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L8_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L8_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L8_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L8_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L8_SET ns_noc_io_spio_soc_ip.csr 56355 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L9_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L9_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L9_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L9_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L9_SET ns_noc_io_spio_soc_ip.csr 56366 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L10_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L10_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L10_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L10_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L10_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L10_SET ns_noc_io_spio_soc_ip.csr 56377 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L11_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L11_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L11_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L11_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L11_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L11_SET ns_noc_io_spio_soc_ip.csr 56388 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L12_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L12_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L12_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L12_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L12_SET ns_noc_io_spio_soc_ip.csr 56399 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L13_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L13_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L13_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L13_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L13_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L13_SET ns_noc_io_spio_soc_ip.csr 56410 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L14_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L14_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L14_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L14_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L14_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L14_SET ns_noc_io_spio_soc_ip.csr 56421 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L15_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L15_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L15_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L15_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L15_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_L15_SET ns_noc_io_spio_soc_ip.csr 56432 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_UNSD_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERR_UNSD_SET ns_noc_io_spio_soc_ip.csr 56443 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_p00_dma_m_1_7_btperrm bridge_spio_p00_dma_m_1_7_btperrm SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 56644 spio_p00_dma_m register btperrm 0x170B0 R/W 0x00000000 Spio_noc_bridge_spio_p00_dma_m_1_7_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L0_SET ns_noc_io_spio_soc_ip.csr 56467 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L1_SET ns_noc_io_spio_soc_ip.csr 56478 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L2_SET ns_noc_io_spio_soc_ip.csr 56489 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L3_SET ns_noc_io_spio_soc_ip.csr 56500 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L4_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L4_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L4_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L4_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L4_SET ns_noc_io_spio_soc_ip.csr 56511 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L5_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L5_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L5_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L5_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L5_SET ns_noc_io_spio_soc_ip.csr 56522 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L6_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L6_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L6_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L6_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L6_SET ns_noc_io_spio_soc_ip.csr 56533 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L7_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L7_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L7_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L7_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L7_SET ns_noc_io_spio_soc_ip.csr 56544 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L8_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L8_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L8_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L8_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L8_SET ns_noc_io_spio_soc_ip.csr 56555 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L9_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L9_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L9_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L9_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L9_SET ns_noc_io_spio_soc_ip.csr 56566 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L10_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L10_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L10_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L10_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L10_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L10_SET ns_noc_io_spio_soc_ip.csr 56577 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L11_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L11_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L11_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L11_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L11_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L11_SET ns_noc_io_spio_soc_ip.csr 56588 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L12_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L12_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L12_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L12_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L12_SET ns_noc_io_spio_soc_ip.csr 56599 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L13_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L13_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L13_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L13_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L13_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L13_SET ns_noc_io_spio_soc_ip.csr 56610 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L14_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L14_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L14_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L14_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L14_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L14_SET ns_noc_io_spio_soc_ip.csr 56621 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L15_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L15_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L15_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L15_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L15_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_L15_SET ns_noc_io_spio_soc_ip.csr 56632 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_UNSD_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BTPERRM_UNSD_SET ns_noc_io_spio_soc_ip.csr 56643 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_p00_dma_m_1_7_rxe bridge_spio_p00_dma_m_1_7_rxe SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 56752 spio_p00_dma_m register rxe 0x17120 R/W 0x00000000 Spio_noc_bridge_spio_p00_dma_m_1_7_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_A_SET ns_noc_io_spio_soc_ip.csr 56672 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_B_SET ns_noc_io_spio_soc_ip.csr 56683 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_C_SET ns_noc_io_spio_soc_ip.csr 56694 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_CRC_OFLW_D_SET ns_noc_io_spio_soc_ip.csr 56705 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_EVC_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_EVC_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_EVC_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_EVC_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_EVC_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_EVC_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_EVC_OFLW_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_EVC_OFLW_SET ns_noc_io_spio_soc_ip.csr 56717 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 56728 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_EVC1_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_EVC1_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_EVC1_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_EVC1_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_EVC1_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_EVC1_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_EVC1_OFLW_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_EVC1_OFLW_SET ns_noc_io_spio_soc_ip.csr 56740 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXE_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 56751 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_rxem bridge_spio_p00_dma_m_1_7_rxem SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 56824 spio_p00_dma_m register rxem 0x17128 R/W 0x00000050 Spio_noc_bridge_spio_p00_dma_m_1_7_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_UNSD_3_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_UNSD_3_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_UNSD_3_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_UNSD_3_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_UNSD_3_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_UNSD_3_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_UNSD_3_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_UNSD_3_0_SET ns_noc_io_spio_soc_ip.csr 56773 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_EVC_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_EVC_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_EVC_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_EVC_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_EVC_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_EVC_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_EVC_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_EVC_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 56787 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 56798 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_EVC1_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_EVC1_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_EVC1_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_EVC1_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_EVC1_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_EVC1_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_EVC1_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 56812 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_RXEM_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 56823 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_brs_0 bridge_spio_p00_dma_m_1_7_brs_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 57098 spio_p00_dma_m register brs_0 0x17130 R 0x00000000 Spio_noc_bridge_spio_p00_dma_m_1_7_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 56848 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_0_SET ns_noc_io_spio_soc_ip.csr 56859 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_0_SET ns_noc_io_spio_soc_ip.csr 56870 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_0_SET ns_noc_io_spio_soc_ip.csr 56881 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_0_SET ns_noc_io_spio_soc_ip.csr 56892 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 56902 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 56913 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_1_SET ns_noc_io_spio_soc_ip.csr 56924 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_1_SET ns_noc_io_spio_soc_ip.csr 56935 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_1_SET ns_noc_io_spio_soc_ip.csr 56946 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_1_SET ns_noc_io_spio_soc_ip.csr 56957 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 56967 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 56978 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_2_SET ns_noc_io_spio_soc_ip.csr 56989 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_2_SET ns_noc_io_spio_soc_ip.csr 57000 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_2_SET ns_noc_io_spio_soc_ip.csr 57011 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_2_SET ns_noc_io_spio_soc_ip.csr 57022 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 57032 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 57043 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_V_3_SET ns_noc_io_spio_soc_ip.csr 57054 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_S_3_SET ns_noc_io_spio_soc_ip.csr 57065 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_B_3_SET ns_noc_io_spio_soc_ip.csr 57076 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_F_3_SET ns_noc_io_spio_soc_ip.csr 57087 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_0_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 57097 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_p00_dma_m_1_7_brs_1 bridge_spio_p00_dma_m_1_7_brs_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 57372 spio_p00_dma_m register brs_1 0x17138 R 0x00000000 Spio_noc_bridge_spio_p00_dma_m_1_7_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 57122 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_0_SET ns_noc_io_spio_soc_ip.csr 57133 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_0_SET ns_noc_io_spio_soc_ip.csr 57144 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_0_SET ns_noc_io_spio_soc_ip.csr 57155 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_0_SET ns_noc_io_spio_soc_ip.csr 57166 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 57176 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 57187 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_1_SET ns_noc_io_spio_soc_ip.csr 57198 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_1_SET ns_noc_io_spio_soc_ip.csr 57209 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_1_SET ns_noc_io_spio_soc_ip.csr 57220 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_1_SET ns_noc_io_spio_soc_ip.csr 57231 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 57241 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 57252 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_2_SET ns_noc_io_spio_soc_ip.csr 57263 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_2_SET ns_noc_io_spio_soc_ip.csr 57274 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_2_SET ns_noc_io_spio_soc_ip.csr 57285 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_2_SET ns_noc_io_spio_soc_ip.csr 57296 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 57306 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 57317 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_V_3_SET ns_noc_io_spio_soc_ip.csr 57328 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_S_3_SET ns_noc_io_spio_soc_ip.csr 57339 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_B_3_SET ns_noc_io_spio_soc_ip.csr 57350 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_F_3_SET ns_noc_io_spio_soc_ip.csr 57361 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRS_1_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 57371 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_p00_dma_m_1_7_brus bridge_spio_p00_dma_m_1_7_brus SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 57441 spio_p00_dma_m register brus 0x171B0 R 0x00000000 Spio_noc_bridge_spio_p00_dma_m_1_7_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_A_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_A_SET ns_noc_io_spio_soc_ip.csr 57397 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_B_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_B_SET ns_noc_io_spio_soc_ip.csr 57408 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_C_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_C_SET ns_noc_io_spio_soc_ip.csr 57419 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_D_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_V_D_SET ns_noc_io_spio_soc_ip.csr 57430 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_UNSD_31_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_UNSD_31_4_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_UNSD_31_4_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_UNSD_31_4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_UNSD_31_4_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_UNSD_31_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_UNSD_31_4_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRUS_UNSD_31_4_SET ns_noc_io_spio_soc_ip.csr 57440 UNSD_31_4 31 4 0x0000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_brperr0 bridge_spio_p00_dma_m_1_7_brperr0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 57669 spio_p00_dma_m register brperr0 0x171D0 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_m_1_7_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_D0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_D0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_D0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_D0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_D0_SET ns_noc_io_spio_soc_ip.csr 57479 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_DC0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_DC0_SET ns_noc_io_spio_soc_ip.csr 57490 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SB0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SB0_SET ns_noc_io_spio_soc_ip.csr 57501 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SBC0_SET ns_noc_io_spio_soc_ip.csr 57513 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_PK0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_PK0_SET ns_noc_io_spio_soc_ip.csr 57524 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 57535 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_D1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_D1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_D1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_D1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_D1_SET ns_noc_io_spio_soc_ip.csr 57546 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_DC1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_DC1_SET ns_noc_io_spio_soc_ip.csr 57557 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SB1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SB1_SET ns_noc_io_spio_soc_ip.csr 57568 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_SBC1_SET ns_noc_io_spio_soc_ip.csr 57580 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_PK1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_PK1_SET ns_noc_io_spio_soc_ip.csr 57591 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 57602 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 57613 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 57624 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 57635 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 57646 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 57657 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 57668 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p00_dma_m_1_7_brperr1 bridge_spio_p00_dma_m_1_7_brperr1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 57785 spio_p00_dma_m register brperr1 0x171D8 R 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_m_1_7_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 57707 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 57718 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 57729 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 57740 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 57751 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 57762 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 57773 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERR1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 57784 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p00_dma_m_1_7_brperrm0 bridge_spio_p00_dma_m_1_7_brperrm0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 58006 spio_p00_dma_m register brperrm0 0x171E0 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_m_1_7_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_D0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_D0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_D0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_D0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_D0_SET ns_noc_io_spio_soc_ip.csr 57812 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_DC0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_DC0_SET ns_noc_io_spio_soc_ip.csr 57824 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SB0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SB0_SET ns_noc_io_spio_soc_ip.csr 57835 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SBC0_SET ns_noc_io_spio_soc_ip.csr 57847 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_PK0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_PK0_SET ns_noc_io_spio_soc_ip.csr 57859 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 57870 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_D1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_D1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_D1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_D1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_D1_SET ns_noc_io_spio_soc_ip.csr 57881 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_DC1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_DC1_SET ns_noc_io_spio_soc_ip.csr 57893 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SB1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SB1_SET ns_noc_io_spio_soc_ip.csr 57904 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_SBC1_SET ns_noc_io_spio_soc_ip.csr 57916 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_PK1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_PK1_SET ns_noc_io_spio_soc_ip.csr 57928 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 57939 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 57950 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 57961 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 57972 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 57983 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 57994 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 58005 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p00_dma_m_1_7_brperrm1 bridge_spio_p00_dma_m_1_7_brperrm1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 58111 spio_p00_dma_m register brperrm1 0x171E8 R 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_m_1_7_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 58033 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 58044 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 58055 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 58066 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 58077 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 58088 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 58099 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_BRPERRM1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 58110 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_tocfg bridge_spio_p00_dma_m_1_7_am_tocfg SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 58185 spio_p00_dma_m register am_tocfg 0x17C00 R/W 0x000000000000001f Spio_noc_bridge_spio_p00_dma_m_1_7_am_tocfg This register is used to configure response timeouts. AM_TOCFG[8] (En) needs to be set for timeout tracking to be enabled. When this bit is 1'b0, no timestamps are recorded to generate timeout interrupts. A 64-bit free running counter is used to time the response interval. AM_TOCFG[5:0] (TI) specifies the lower bit index into this counter, from where 2-bits are picked up and recorded as the arrival time stamp of every incoming AR and AW command. If response for a command does not return before the current time stamp rolls to arrival time stamp minus 1, the response is assumed to have timedout and an interrupt is raised along with the slave ID to which the timed out request was sent. When changing the TI field, first write to the register with the En field cleared, then write a second time with the TI field to its new value, then a 3rd write to restore the En field to Enabled. During this update while the En field is cleared, existing timers will cancelled, and new timer starts will be inhibited. false false false false TI SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_TI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_TI_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_TI_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_TI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_TI_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_TI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_TI_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_TI_SET ns_noc_io_spio_soc_ip.csr 58148 TI Timer index, index of a 64-bit counter from where timestamp is picked. The register value has to be 'd62 or smaller. 5 0 0x1f R/W UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 58159 UNSD_7_6 7 6 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_EN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_EN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_EN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_EN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_EN_SET ns_noc_io_spio_soc_ip.csr 58173 EN 1'b1: Enabled timeout tracking, a 64-bit free running counter is used to time the response interval. 1'b0: No timestamps are recorded to generate timeout interrupts 8 8 0x0 R/W UNSD_63_9 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_UNSD_63_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_UNSD_63_9_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_UNSD_63_9_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_UNSD_63_9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_UNSD_63_9_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_UNSD_63_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_UNSD_63_9_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOCFG_UNSD_63_9_SET ns_noc_io_spio_soc_ip.csr 58184 UNSD_63_9 63 9 0x00000000000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_osslv bridge_spio_p00_dma_m_1_7_am_osslv SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_OSSLV_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_OSSLV_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_OSSLV_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_OSSLV_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 58220 spio_p00_dma_m register am_osslv 0x17C08 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_osslv This register is used to check if there are any outstanding read/write commands to a slave specified by field slvid. NocStudio provides a table of slvids corresponding to the slave ports accessible from a master bridge. Outstanding status is reflected in AM_STS. false false false false SLVID SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_OSSLV_SLVID_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_OSSLV_SLVID_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_OSSLV_SLVID_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_OSSLV_SLVID_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_OSSLV_SLVID_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_OSSLV_SLVID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_OSSLV_SLVID_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_OSSLV_SLVID_SET ns_noc_io_spio_soc_ip.csr 58208 SLVID A slave ID associated with the current master for command outstanding status 15 0 0x0000 R/W UNSD_63_16 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_OSSLV_UNSD_63_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_OSSLV_UNSD_63_16_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_OSSLV_UNSD_63_16_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_OSSLV_UNSD_63_16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_OSSLV_UNSD_63_16_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_OSSLV_UNSD_63_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_OSSLV_UNSD_63_16_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_OSSLV_UNSD_63_16_SET ns_noc_io_spio_soc_ip.csr 58219 UNSD_63_16 63 16 0x000000000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_cgc bridge_spio_p00_dma_m_1_7_am_cgc SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGC_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGC_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGC_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 58257 spio_p00_dma_m register am_cgc 0x17C10 R/W 0x0000000000000064 Spio_noc_bridge_spio_p00_dma_m_1_7_am_cgc Programmable interval used by coarse clock gating logic in master bridge.This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGC_HYSTERESIS_COUNTER_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGC_HYSTERESIS_COUNTER_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGC_HYSTERESIS_COUNTER_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGC_HYSTERESIS_COUNTER_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGC_HYSTERESIS_COUNTER_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGC_HYSTERESIS_COUNTER_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGC_HYSTERESIS_COUNTER_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_spio_soc_ip.csr 58245 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGC_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGC_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGC_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGC_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGC_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGC_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGC_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGC_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 58256 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_cgo bridge_spio_p00_dma_m_1_7_am_cgo SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGO_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGO_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGO_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGO_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 58292 spio_p00_dma_m register am_cgo 0x17C18 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the master bridge. false false false false FPO SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGO_FPO_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGO_FPO_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGO_FPO_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGO_FPO_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGO_FPO_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGO_FPO_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGO_FPO_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGO_FPO_SET ns_noc_io_spio_soc_ip.csr 58280 FPO 1'b1: Clock gating override is enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGO_UNSD_63_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGO_UNSD_63_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGO_UNSD_63_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGO_UNSD_63_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGO_UNSD_63_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGO_UNSD_63_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGO_UNSD_63_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CGO_UNSD_63_1_SET ns_noc_io_spio_soc_ip.csr 58291 UNSD_63_1 63 1 0x0000000000000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_cfg bridge_spio_p00_dma_m_1_7_am_cfg SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CFG_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CFG_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CFG_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CFG_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 58329 spio_p00_dma_m register am_cfg 0x17C20 R/W 0x0000000000000001 Spio_noc_bridge_spio_p00_dma_m_1_7_am_cfg Configures the master bridge's support for autowake of power domains. When set, master bridge halts a request and issues wakeup requests for power domains that need to powered up to complete the transaction. The power domains should support auto wake. When reset, master bridge issues DECERR for any transaction which has dependent power domains in sleep state. false false false false AW SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CFG_AW_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CFG_AW_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CFG_AW_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CFG_AW_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CFG_AW_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CFG_AW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CFG_AW_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CFG_AW_SET ns_noc_io_spio_soc_ip.csr 58317 AW 1'b1: Autowake enabled 1'b0: Autowake disabled 0 0 0x1 R/W UNSD_63_1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CFG_UNSD_63_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CFG_UNSD_63_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CFG_UNSD_63_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CFG_UNSD_63_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CFG_UNSD_63_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CFG_UNSD_63_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CFG_UNSD_63_1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CFG_UNSD_63_1_SET ns_noc_io_spio_soc_ip.csr 58328 UNSD_63_1 63 1 0x0000000000000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_sts bridge_spio_p00_dma_m_1_7_am_sts SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 58457 spio_p00_dma_m register am_sts 0x17D00 R 0x000000000000000c Spio_noc_bridge_spio_p00_dma_m_1_7_am_sts When reordering is disabled on the master bridge, hazard stall occurs if the master tries to access a new slave device while response from a different slave is outstanding on the same AID. This is because the responses can arrive out of order and the bridge is not equipped to correct the order. Without re-order buffers, hazard stalls also occur if a new large command needs to be split while there are older commands outstanding, or a large command just finished sending all its split segments but all responses have not returned yet. When reordering is enabled, stall due to hazard occurs if a new command arrives, whose NoC QoS is different from the NoC QoS of commands outstanding on that AID. false false false false ROF SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ROF_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ROF_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ROF_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ROF_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ROF_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ROF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ROF_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ROF_SET ns_noc_io_spio_soc_ip.csr 58362 ROF 1'b1: Maximum supported number of read commands are outstanding waiting for response and no more requests can be accepted 1'b0: Master bridge can accept more read requests 0 0 0x0 R WOF SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_WOF_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_WOF_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_WOF_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_WOF_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_WOF_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_WOF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_WOF_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_WOF_SET ns_noc_io_spio_soc_ip.csr 58376 WOF 1'b1: Maximum supported number of write commands are outstanding waiting for response and no more requests can be accepted 1'b0: Master bridge can accept more write requests 1 1 0x0 R ROE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ROE_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ROE_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ROE_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ROE_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ROE_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ROE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ROE_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ROE_SET ns_noc_io_spio_soc_ip.csr 58388 ROE 1'b1: There are no read commands outstanding from the attached master device 2 2 0x1 R WOE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_WOE_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_WOE_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_WOE_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_WOE_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_WOE_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_WOE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_WOE_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_WOE_SET ns_noc_io_spio_soc_ip.csr 58400 WOE 1'b1: There are no write commands outstanding from the attached master device 3 3 0x1 R ARS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ARS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ARS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ARS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ARS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ARS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ARS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ARS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ARS_SET ns_noc_io_spio_soc_ip.csr 58411 ARS 1'b1: AR channel is stalled on hazard 4 4 0x0 R AWS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_AWS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_AWS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_AWS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_AWS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_AWS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_AWS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_AWS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_AWS_SET ns_noc_io_spio_soc_ip.csr 58422 AWS 1'b1: AW channel is stalled on hazard 5 5 0x0 R ARO SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ARO_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ARO_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ARO_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ARO_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ARO_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ARO_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ARO_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_ARO_SET ns_noc_io_spio_soc_ip.csr 58434 ARO 1'b1: Read commands are outstanding to the slave specified in OSSLV register 6 6 0x0 R AWO SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_AWO_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_AWO_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_AWO_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_AWO_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_AWO_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_AWO_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_AWO_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_AWO_SET ns_noc_io_spio_soc_ip.csr 58446 AWO 1'b1: Write commands are outstanding to the slave specified in OSSLV register 7 7 0x0 R UNSD_63_8 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_UNSD_63_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_UNSD_63_8_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_UNSD_63_8_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_UNSD_63_8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_UNSD_63_8_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_UNSD_63_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_UNSD_63_8_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_STS_UNSD_63_8_SET ns_noc_io_spio_soc_ip.csr 58456 UNSD_63_8 63 8 0x00000000000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_bridge_id bridge_spio_p00_dma_m_1_7_am_bridge_id SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_BRIDGE_ID_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_BRIDGE_ID_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_BRIDGE_ID_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_BRIDGE_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 58487 spio_p00_dma_m register am_bridge_id 0x17D08 R 0x0000000000000001 Spio_noc_bridge_spio_p00_dma_m_1_7_am_bridge_id Unique identifier assigned to the master bridge. false false false false ID SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_BRIDGE_ID_ID_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_BRIDGE_ID_ID_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_BRIDGE_ID_ID_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_BRIDGE_ID_ID_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_BRIDGE_ID_ID_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_BRIDGE_ID_ID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_BRIDGE_ID_ID_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_BRIDGE_ID_ID_SET ns_noc_io_spio_soc_ip.csr 58476 ID Unique bridge ID 15 0 0x0001 R UNSD_63_16 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_BRIDGE_ID_UNSD_63_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_BRIDGE_ID_UNSD_63_16_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_BRIDGE_ID_UNSD_63_16_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_BRIDGE_ID_UNSD_63_16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_BRIDGE_ID_UNSD_63_16_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_BRIDGE_ID_UNSD_63_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_BRIDGE_ID_UNSD_63_16_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_spio_soc_ip.csr 58486 UNSD_63_16 63 16 0x000000000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_err bridge_spio_p00_dma_m_1_7_am_err SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 58983 spio_p00_dma_m register am_err 0x17E00 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E0_SET ns_noc_io_spio_soc_ip.csr 58509 E0 1'b1: Local read address decode error: ARADDR did not find a match in the master bridges address table and a decode error was issued 0 0 0x0 R/W E1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E1_SET ns_noc_io_spio_soc_ip.csr 58521 E1 1'b1: Read address decode error from slave: A decode error response was received from a slave device 1 1 0x0 R/W E2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E2_SET ns_noc_io_spio_soc_ip.csr 58533 E2 1'b1: Read slave error: A slave error response was received from a slave device 2 2 0x0 R/W E3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E3_SET ns_noc_io_spio_soc_ip.csr 58545 E3 1'b1: Non modifiable WRAP: A WRAP command marked as non-modifiable (ARCACHE[0]=0) was detected 3 3 0x0 R/W E4 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E4_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E4_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E4_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E4_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E4_SET ns_noc_io_spio_soc_ip.csr 58557 E4 1'b1: [FATAL] Read exclusive split: An AR command of FIXED burst type was detected 4 4 0x0 R/W E5 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E5_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E5_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E5_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E5_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E5_SET ns_noc_io_spio_soc_ip.csr 58569 E5 1'b1: [FATAL] Read address multi-hit: An AR command matched against multiple entries in the address table 5 5 0x0 R/W E6 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E6_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E6_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E6_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E6_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E6_SET ns_noc_io_spio_soc_ip.csr 58582 E6 1'b1: Read response timeout: Read response timeout occurred. With timeout enabled, a response wasn't received within the expected interval 6 6 0x0 R/W E7 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E7_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E7_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E7_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E7_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E7_SET ns_noc_io_spio_soc_ip.csr 58595 E7 1'b1: [FATAL] Read WRAP not equal to supported cacheline size: A WRAP command of unupported cache line size was detected 7 7 0x0 R/W E8 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E8_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E8_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E8_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E8_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E8_SET ns_noc_io_spio_soc_ip.csr 58606 E8 1'b1: [FATAL] Unexpected narrow read detected 8 8 0x0 R/W UNSD_15_9 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_15_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_15_9_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_15_9_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_15_9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_15_9_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_15_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_15_9_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_15_9_SET ns_noc_io_spio_soc_ip.csr 58617 UNSD_15_9 15 9 0x00 R E16 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E16_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E16_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E16_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E16_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E16_SET ns_noc_io_spio_soc_ip.csr 58628 E16 1'b1: Local write address decode error 16 16 0x0 R/W E17 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E17_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E17_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E17_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E17_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E17_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E17_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E17_SET ns_noc_io_spio_soc_ip.csr 58639 E17 1'b1: Write address decode error from slave 17 17 0x0 R/W E18 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E18_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E18_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E18_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E18_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E18_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E18_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E18_SET ns_noc_io_spio_soc_ip.csr 58650 E18 1'b1: Write slave error 18 18 0x0 R/W E19 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E19_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E19_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E19_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E19_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E19_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E19_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E19_SET ns_noc_io_spio_soc_ip.csr 58661 E19 1'b1: Non modifiable WRAP 19 19 0x0 R/W E20 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E20_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E20_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E20_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E20_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E20_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E20_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E20_SET ns_noc_io_spio_soc_ip.csr 58672 E20 1'b1: [FATAL] Write exclusive split 20 20 0x0 R/W E21 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E21_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E21_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E21_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E21_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E21_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E21_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E21_SET ns_noc_io_spio_soc_ip.csr 58683 E21 1'b1: [FATAL] Write address multi-hit 21 21 0x0 R/W E22 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E22_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E22_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E22_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E22_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E22_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E22_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E22_SET ns_noc_io_spio_soc_ip.csr 58694 E22 1'b1: Write respone timeout 22 22 0x0 R/W E23 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E23_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E23_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E23_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E23_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E23_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E23_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E23_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E23_SET ns_noc_io_spio_soc_ip.csr 58706 E23 1'b1: [FATAL] Write WRAP not equal to supported cacheline size 23 23 0x0 R/W E24 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E24_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E24_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E24_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E24_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E24_SET ns_noc_io_spio_soc_ip.csr 58717 E24 1'b1: [FATAL] Unexpected narrow write detected 24 24 0x0 R/W UNSD_31_25 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_31_25_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_31_25_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_31_25_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_31_25_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_31_25_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_31_25_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_31_25_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_31_25_SET ns_noc_io_spio_soc_ip.csr 58728 UNSD_31_25 31 25 0x00 R E32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E32_SET ns_noc_io_spio_soc_ip.csr 58739 E32 1'b1: Capture counter0 overflow 32 32 0x0 R/W E33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E33_SET ns_noc_io_spio_soc_ip.csr 58750 E33 1'b1: Capture counter1 overflow 33 33 0x0 R/W E34 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E34_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E34_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E34_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E34_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E34_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E34_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E34_SET ns_noc_io_spio_soc_ip.csr 58762 E34 1'b1: [FATAL] Traffic sent to a noc layer which is power gate 34 34 0x0 R/W E35 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E35_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E35_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E35_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E35_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E35_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E35_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E35_SET ns_noc_io_spio_soc_ip.csr 58774 E35 1'b1: [FATAL] Parity error in configuration/status registers 35 35 0x0 R/W UNSD_39_36 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_39_36_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_39_36_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_39_36_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_39_36_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_39_36_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_39_36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_39_36_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_39_36_SET ns_noc_io_spio_soc_ip.csr 58785 UNSD_39_36 39 36 0x0 R E40 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E40_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E40_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E40_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E40_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E40_SET ns_noc_io_spio_soc_ip.csr 58797 E40 1'b1: [FATAL] Indicates that portcheck detected error (SIB mode only) 40 40 0x0 R/W E41 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E41_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E41_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E41_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E41_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E41_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E41_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E41_SET ns_noc_io_spio_soc_ip.csr 58808 E41 1'b1: [FATAL] AR Parity Err 41 41 0x0 R/W E42 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E42_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E42_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E42_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E42_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E42_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E42_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E42_SET ns_noc_io_spio_soc_ip.csr 58819 E42 1'b1: [FATAL] ARADDR Parity Err 42 42 0x0 R/W E43 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E43_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E43_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E43_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E43_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E43_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E43_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E43_SET ns_noc_io_spio_soc_ip.csr 58830 E43 1'b1: [FATAL] AW Parity Err 43 43 0x0 R/W E44 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E44_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E44_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E44_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E44_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E44_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E44_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E44_SET ns_noc_io_spio_soc_ip.csr 58841 E44 1'b1: [FATAL] AWADDR Parity Err 44 44 0x0 R/W E45 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E45_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E45_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E45_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E45_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E45_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E45_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E45_SET ns_noc_io_spio_soc_ip.csr 58852 E45 1'b1: [FATAL] WDATA Parity Err 45 45 0x0 R/W E46 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E46_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E46_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E46_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E46_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E46_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E46_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E46_SET ns_noc_io_spio_soc_ip.csr 58863 E46 1'b1: [FATAL] CDDATA Parity Err 46 46 0x0 R/W E47 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E47_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E47_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E47_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E47_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E47_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E47_SET ns_noc_io_spio_soc_ip.csr 58875 E47 1'b1: [FATAL] Ridtbl Entry Parity Err 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E48_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E48_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E48_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E48_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E48_SET ns_noc_io_spio_soc_ip.csr 58887 E48 1'b1: [FATAL] Widtbl Entry Parity Err 48 48 0x0 R E49 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E49_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E49_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E49_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E49_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E49_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E49_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E49_SET ns_noc_io_spio_soc_ip.csr 58899 E49 1'b1: [FATAL] Read Reorder Buffer Parity Err 49 49 0x0 R E50 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E50_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E50_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E50_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E50_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E50_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E50_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E50_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E50_SET ns_noc_io_spio_soc_ip.csr 58911 E50 1'b1: [FATAL] Write Reorder Buffer Parity Err 50 50 0x0 R E51 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E51_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E51_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E51_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E51_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E51_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E51_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E51_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E51_SET ns_noc_io_spio_soc_ip.csr 58923 E51 1'b1: [FATAL] Rx Fifo Parity Err 51 51 0x0 R E52 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E52_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E52_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E52_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E52_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E52_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E52_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E52_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E52_SET ns_noc_io_spio_soc_ip.csr 58935 E52 1'b1: [FATAL] Ack Channel Wack Fifo Parity Error 52 52 0x0 R E53 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E53_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E53_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E53_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E53_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E53_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E53_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E53_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E53_SET ns_noc_io_spio_soc_ip.csr 58947 E53 1'b1: [FATAL] Ack Channel Rack Fifo Parity Error 53 53 0x0 R E54 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E54_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E54_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E54_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E54_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E54_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E54_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E54_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E54_SET ns_noc_io_spio_soc_ip.csr 58959 E54 1'b1: [FATAL] CRCD Channel Crid Fifo Parity Error 54 54 0x0 R E55 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E55_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E55_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E55_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E55_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E55_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E55_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E55_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_E55_SET ns_noc_io_spio_soc_ip.csr 58971 E55 1'b1: [FATAL] R Channel Cpkt Fifo Parity Error 55 55 0x0 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERR_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 58982 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_toslvid bridge_spio_p00_dma_m_1_7_am_toslvid SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOSLVID_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOSLVID_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOSLVID_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOSLVID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 59028 spio_p00_dma_m register am_toslvid 0x17E08 R 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_toslvid AR slvid and AW slvid fields indicate slave IDs to which a read, write response timeout was detected. Note that slvid encoding is not same as the bridge ID of the slave. NocStudio provides a table mapping the slvids to the actual slave ports accessible from the master bridge. false false false false AR_SLVID SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOSLVID_AR_SLVID_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOSLVID_AR_SLVID_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOSLVID_AR_SLVID_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOSLVID_AR_SLVID_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOSLVID_AR_SLVID_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOSLVID_AR_SLVID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOSLVID_AR_SLVID_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOSLVID_AR_SLVID_SET ns_noc_io_spio_soc_ip.csr 59006 AR_SLVID Slave ID of timed out AR request 15 0 0x0000 R AW_SLVID SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOSLVID_AW_SLVID_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOSLVID_AW_SLVID_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOSLVID_AW_SLVID_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOSLVID_AW_SLVID_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOSLVID_AW_SLVID_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOSLVID_AW_SLVID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOSLVID_AW_SLVID_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOSLVID_AW_SLVID_SET ns_noc_io_spio_soc_ip.csr 59017 AW_SLVID Slave ID of timed out AW request 31 16 0x0000 R UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOSLVID_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOSLVID_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOSLVID_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOSLVID_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOSLVID_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOSLVID_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOSLVID_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_TOSLVID_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 59027 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_era bridge_spio_p00_dma_m_1_7_am_era SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERA_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERA_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERA_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERA_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 59050 spio_p00_dma_m register am_era 0x17E10 R 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_era This is the address on AR channel for which a decode error was detected. This corresponds to the status register bit e0 in AM_ERR. false false false false READ_DECERR_ADDRS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERA_READ_DECERR_ADDRS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERA_READ_DECERR_ADDRS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERA_READ_DECERR_ADDRS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERA_READ_DECERR_ADDRS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERA_READ_DECERR_ADDRS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERA_READ_DECERR_ADDRS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERA_READ_DECERR_ADDRS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_ERA_READ_DECERR_ADDRS_SET ns_noc_io_spio_soc_ip.csr 59049 READ_DECERR_ADDRS Read decerr address 63 0 0x0000000000000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_ewa bridge_spio_p00_dma_m_1_7_am_ewa SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_EWA_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_EWA_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_EWA_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_EWA_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 59072 spio_p00_dma_m register am_ewa 0x17E18 R 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_ewa This is the address on AW channel for which a decode error was detected. This corresponds to the status register bit e16 in AM_ERR. false false false false WRITE_DECERR_ADDRS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_EWA_WRITE_DECERR_ADDRS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_EWA_WRITE_DECERR_ADDRS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_EWA_WRITE_DECERR_ADDRS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_EWA_WRITE_DECERR_ADDRS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_EWA_WRITE_DECERR_ADDRS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_EWA_WRITE_DECERR_ADDRS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_EWA_WRITE_DECERR_ADDRS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_EWA_WRITE_DECERR_ADDRS_SET ns_noc_io_spio_soc_ip.csr 59071 WRITE_DECERR_ADDRS Write decerr address 63 0 0x0000000000000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_intm bridge_spio_p00_dma_m_1_7_am_intm SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 59556 spio_p00_dma_m register am_intm 0x17E40 R/W 0x00007e07004f004f Spio_noc_bridge_spio_p00_dma_m_1_7_am_intm Interrupt mask register. Individual bit position matches the error bit positions in AM_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M0_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M0_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M0_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M0_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M0_SET ns_noc_io_spio_soc_ip.csr 59094 M0 1'b1: Mask interrupt for read channel 0 0 0x1 R/W M1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M1_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M1_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M1_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M1_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M1_SET ns_noc_io_spio_soc_ip.csr 59105 M1 1'b1: Mask interrupt for read channel 1 1 0x1 R/W M2 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M2_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M2_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M2_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M2_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M2_SET ns_noc_io_spio_soc_ip.csr 59116 M2 1'b1: Mask interrupt for read channel 2 2 0x1 R/W M3 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M3_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M3_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M3_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M3_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M3_SET ns_noc_io_spio_soc_ip.csr 59127 M3 1'b1: Mask interrupt for read channel 3 3 0x1 R/W M4 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M4_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M4_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M4_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M4_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M4_SET ns_noc_io_spio_soc_ip.csr 59138 M4 1'b1: Mask interrupt for read channel 4 4 0x0 R/W M5 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M5_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M5_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M5_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M5_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M5_SET ns_noc_io_spio_soc_ip.csr 59149 M5 1'b1: Mask interrupt for read channel 5 5 0x0 R/W M6 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M6_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M6_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M6_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M6_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M6_SET ns_noc_io_spio_soc_ip.csr 59160 M6 1'b1: Mask interrupt for read channel 6 6 0x1 R/W M7 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M7_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M7_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M7_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M7_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M7_SET ns_noc_io_spio_soc_ip.csr 59171 M7 1'b1: Mask interrupt for read channel 7 7 0x0 R/W M8 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M8_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M8_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M8_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M8_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M8_SET ns_noc_io_spio_soc_ip.csr 59182 M8 1'b1: Mask interrupt for read channel 8 8 0x0 R/W UNSD_15_9 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_15_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_15_9_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_15_9_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_15_9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_15_9_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_15_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_15_9_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_15_9_SET ns_noc_io_spio_soc_ip.csr 59193 UNSD_15_9 15 9 0x00 R M16 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M16_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M16_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M16_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M16_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M16_SET ns_noc_io_spio_soc_ip.csr 59204 M16 1'b1: Mask interrupt for write channel 16 16 0x1 R/W M17 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M17_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M17_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M17_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M17_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M17_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M17_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M17_SET ns_noc_io_spio_soc_ip.csr 59215 M17 1'b1: Mask interrupt for write channel 17 17 0x1 R/W M18 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M18_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M18_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M18_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M18_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M18_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M18_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M18_SET ns_noc_io_spio_soc_ip.csr 59226 M18 1'b1: Mask interrupt for write channel 18 18 0x1 R/W M19 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M19_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M19_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M19_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M19_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M19_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M19_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M19_SET ns_noc_io_spio_soc_ip.csr 59237 M19 1'b1: Mask interrupt for write channel 19 19 0x1 R/W M20 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M20_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M20_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M20_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M20_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M20_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M20_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M20_SET ns_noc_io_spio_soc_ip.csr 59248 M20 1'b1: Mask interrupt for write channel 20 20 0x0 R/W M21 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M21_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M21_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M21_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M21_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M21_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M21_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M21_SET ns_noc_io_spio_soc_ip.csr 59259 M21 1'b1: Mask interrupt for write channel 21 21 0x0 R/W M22 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M22_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M22_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M22_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M22_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M22_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M22_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M22_SET ns_noc_io_spio_soc_ip.csr 59270 M22 1'b1: Mask interrupt for write channel 22 22 0x1 R/W M23 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M23_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M23_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M23_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M23_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M23_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M23_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M23_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M23_SET ns_noc_io_spio_soc_ip.csr 59281 M23 1'b1: Mask interrupt for write channel 23 23 0x0 R/W M24 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M24_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M24_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M24_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M24_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M24_SET ns_noc_io_spio_soc_ip.csr 59292 M24 1'b1: Mask interrupt for write channel 24 24 0x0 R/W UNSD_31_25 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_31_25_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_31_25_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_31_25_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_31_25_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_31_25_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_31_25_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_31_25_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_31_25_SET ns_noc_io_spio_soc_ip.csr 59303 UNSD_31_25 31 25 0x00 R M32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M32_SET ns_noc_io_spio_soc_ip.csr 59314 M32 1'b1: Counter 0 overflow interrupt mask 32 32 0x1 R/W M33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M33_SET ns_noc_io_spio_soc_ip.csr 59325 M33 1'b1: Counter 1 overflow interrupt mask 33 33 0x1 R/W M34 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M34_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M34_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M34_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M34_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M34_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M34_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M34_SET ns_noc_io_spio_soc_ip.csr 59336 M34 1'b1: Mask interrupt on traffic to PG layer 34 34 0x1 R/W M35 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M35_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M35_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M35_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M35_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M35_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M35_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M35_SET ns_noc_io_spio_soc_ip.csr 59347 M35 1'b1: Mask interrupt on csr parity errors 35 35 0x0 R/W UNSD_39_36 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_39_36_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_39_36_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_39_36_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_39_36_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_39_36_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_39_36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_39_36_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_39_36_SET ns_noc_io_spio_soc_ip.csr 59358 UNSD_39_36 39 36 0x0 R M40 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M40_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M40_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M40_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M40_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M40_SET ns_noc_io_spio_soc_ip.csr 59370 M40 1'b1: Mask interrupt for SIB portcheck error (SIB mode only) 40 40 0x0 R/W M41 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M41_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M41_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M41_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M41_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M41_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M41_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M41_SET ns_noc_io_spio_soc_ip.csr 59381 M41 1'b1: AR Parity Intr Mask 41 41 0x1 R/W M42 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M42_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M42_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M42_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M42_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M42_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M42_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M42_SET ns_noc_io_spio_soc_ip.csr 59392 M42 1'b1: ARADDR Parity Intr Mask 42 42 0x1 R/W M43 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M43_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M43_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M43_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M43_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M43_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M43_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M43_SET ns_noc_io_spio_soc_ip.csr 59403 M43 1'b1: AW Parity Intr Mask 43 43 0x1 R/W M44 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M44_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M44_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M44_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M44_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M44_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M44_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M44_SET ns_noc_io_spio_soc_ip.csr 59414 M44 1'b1: AWADDR Parity Intr Mask 44 44 0x1 R/W M45 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M45_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M45_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M45_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M45_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M45_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M45_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M45_SET ns_noc_io_spio_soc_ip.csr 59425 M45 1'b1: WDATA Parity Intr Mask 45 45 0x1 R/W M46 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M46_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M46_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M46_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M46_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M46_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M46_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_M46_SET ns_noc_io_spio_soc_ip.csr 59436 M46 1'b1: CDDATA Parity Intr Mask 46 46 0x1 R/W E47 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E47_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E47_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E47_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E47_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E47_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E47_SET ns_noc_io_spio_soc_ip.csr 59448 E47 1'b1: Ridtbl Parity Intr Mask 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E48_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E48_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E48_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E48_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E48_SET ns_noc_io_spio_soc_ip.csr 59460 E48 1'b1: Widtbl Parity Intr Mask 48 48 0x0 R E49 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E49_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E49_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E49_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E49_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E49_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E49_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E49_SET ns_noc_io_spio_soc_ip.csr 59472 E49 1'b1: Read Reorder Buffer Parity Intr Mask 49 49 0x0 R E50 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E50_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E50_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E50_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E50_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E50_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E50_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E50_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E50_SET ns_noc_io_spio_soc_ip.csr 59484 E50 1'b1: Write Reorder Buffer Parity Intr Mask 50 50 0x0 R E51 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E51_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E51_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E51_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E51_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E51_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E51_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E51_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E51_SET ns_noc_io_spio_soc_ip.csr 59496 E51 1'b1: Rx Fifo Parity Intr Mask 51 51 0x0 R E52 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E52_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E52_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E52_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E52_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E52_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E52_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E52_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E52_SET ns_noc_io_spio_soc_ip.csr 59508 E52 1'b1: Ack Channel Wack Fifo Parity Intr Mask 52 52 0x0 R E53 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E53_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E53_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E53_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E53_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E53_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E53_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E53_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E53_SET ns_noc_io_spio_soc_ip.csr 59520 E53 1'b1: Ack Channel Rack Fifo Parity Intr Mask 53 53 0x0 R E54 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E54_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E54_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E54_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E54_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E54_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E54_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E54_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E54_SET ns_noc_io_spio_soc_ip.csr 59532 E54 1'b1: CRCD Channel Crid Fifo Parity Intr Mask 54 54 0x0 R E55 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E55_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E55_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E55_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E55_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E55_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E55_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E55_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_E55_SET ns_noc_io_spio_soc_ip.csr 59544 E55 1'b1: R Channel Cpkt Fifo Parity Intr Mask 55 55 0x0 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_INTM_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 59555 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_caddr bridge_spio_p00_dma_m_1_7_am_caddr SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CADDR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CADDR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CADDR_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CADDR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 59578 spio_p00_dma_m register am_caddr 0x17F00 R/W 0xffffffffffffffff Spio_noc_bridge_spio_p00_dma_m_1_7_am_caddr This register is part of statistics gathering on the AR and AW command channels. This is the address value which is checked against AR, AW command channels in conjunction with the mask below to filter commands for statistics gathering. false false false false CAPTURE_ADDR SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CADDR_CAPTURE_ADDR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CADDR_CAPTURE_ADDR_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CADDR_CAPTURE_ADDR_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CADDR_CAPTURE_ADDR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CADDR_CAPTURE_ADDR_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CADDR_CAPTURE_ADDR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CADDR_CAPTURE_ADDR_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CADDR_CAPTURE_ADDR_SET ns_noc_io_spio_soc_ip.csr 59577 CAPTURE_ADDR Capture address 63 0 0xffffffffffffffff R/W register spio_noc.bridge_spio_p00_dma_m_1_7_am_caddrmsk bridge_spio_p00_dma_m_1_7_am_caddrmsk SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CADDRMSK_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CADDRMSK_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CADDRMSK_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CADDRMSK_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 59601 spio_p00_dma_m register am_caddrmsk 0x17F08 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_caddrmsk If command address on the AR, AW channel logically ANDed with this mask is equal to the value specified in AM_CADDR, then an address match has occurred. Note that only lowest significant bits equal to the master's address width are used in the comparison. false false false false CAPTURE_ADDR_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_SET ns_noc_io_spio_soc_ip.csr 59600 CAPTURE_ADDR_MASK Capture address mask 63 0 0x0000000000000000 R/W register spio_noc.bridge_spio_p00_dma_m_1_7_am_ccmd0 bridge_spio_p00_dma_m_1_7_am_ccmd0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 59791 spio_p00_dma_m register am_ccmd0 0x17F10 R/W 0x0000000003fff33f Spio_noc_bridge_spio_p00_dma_m_1_7_am_ccmd0 Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands. false false false false SNOOP SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_SNOOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_SNOOP_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_SNOOP_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_SNOOP_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_SNOOP_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_SNOOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_SNOOP_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_SNOOP_SET ns_noc_io_spio_soc_ip.csr 59623 SNOOP Snoop 3 0 0xf R/W DOMAIN SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_DOMAIN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_DOMAIN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_DOMAIN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_DOMAIN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_DOMAIN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_DOMAIN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_DOMAIN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_DOMAIN_SET ns_noc_io_spio_soc_ip.csr 59634 DOMAIN Domain 5 4 0x3 R/W UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 59645 UNSD_7_6 7 6 0x0 R BAR SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_BAR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_BAR_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_BAR_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_BAR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_BAR_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_BAR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_BAR_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_BAR_SET ns_noc_io_spio_soc_ip.csr 59656 BAR Bar 9 8 0x3 R/W UNSD_11_10 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_11_10_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_11_10_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_11_10_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_11_10_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_11_10_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_11_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_11_10_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_11_10_SET ns_noc_io_spio_soc_ip.csr 59667 UNSD_11_10 11 10 0x0 R CACHE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_CACHE_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_CACHE_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_CACHE_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_CACHE_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_CACHE_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_CACHE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_CACHE_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_CACHE_SET ns_noc_io_spio_soc_ip.csr 59678 CACHE Cache 15 12 0xf R/W QOS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_QOS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_QOS_SET ns_noc_io_spio_soc_ip.csr 59689 QOS QoS 19 16 0xf R/W PROT SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_PROT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_PROT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_PROT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_PROT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_PROT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_PROT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_PROT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_PROT_SET ns_noc_io_spio_soc_ip.csr 59700 PROT Prot 22 20 0x7 R/W LOC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_LOC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_LOC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_LOC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_LOC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_LOC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_LOC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_LOC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_LOC_SET ns_noc_io_spio_soc_ip.csr 59711 LOC 1'b1: Lock 23 23 0x1 R/W RDY SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_RDY_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_RDY_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_RDY_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_RDY_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_RDY_SET ns_noc_io_spio_soc_ip.csr 59722 RDY 1'b1: Ready 24 24 0x1 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_VAL_SET ns_noc_io_spio_soc_ip.csr 59733 VAL 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_27_26_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_27_26_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_27_26_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_27_26_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_27_26_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_27_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_27_26_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_27_26_SET ns_noc_io_spio_soc_ip.csr 59744 UNSD_27_26 27 26 0x0 R INTFID SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_INTFID_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_INTFID_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_INTFID_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_INTFID_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_INTFID_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_INTFID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_INTFID_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_INTFID_SET ns_noc_io_spio_soc_ip.csr 59756 INTFID 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_31_31 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_31_31_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_31_31_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_31_31_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_31_31_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_31_31_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_31_31_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_31_31_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_31_31_SET ns_noc_io_spio_soc_ip.csr 59767 UNSD_31_31 31 31 0x0 R TYP SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_TYP_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_TYP_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_TYP_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_TYP_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_TYP_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_TYP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_TYP_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_TYP_SET ns_noc_io_spio_soc_ip.csr 59779 TYP 1'b1: Count response latency of captured command 1'b0: Count captured command 32 32 0x0 R/W UNSD_63_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_63_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_63_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_63_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_63_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_63_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_63_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_63_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD0_UNSD_63_33_SET ns_noc_io_spio_soc_ip.csr 59790 UNSD_63_33 63 33 0x00000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_ccmdmsk0 bridge_spio_p00_dma_m_1_7_am_ccmdmsk0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 59935 spio_p00_dma_m register am_ccmdmsk0 0x17F18 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_ccmdmsk0 If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters. false false false false SNOOP SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_SNOOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_SNOOP_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_SNOOP_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_SNOOP_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_SNOOP_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_SNOOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_SNOOP_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_SNOOP_SET ns_noc_io_spio_soc_ip.csr 59813 SNOOP Snoop 3 0 0x0 R/W DOMAIN SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_DOMAIN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_DOMAIN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_DOMAIN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_DOMAIN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_DOMAIN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_DOMAIN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_DOMAIN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_DOMAIN_SET ns_noc_io_spio_soc_ip.csr 59824 DOMAIN Domain 5 4 0x0 R/W UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 59835 UNSD_7_6 7 6 0x0 R BAR SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_BAR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_BAR_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_BAR_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_BAR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_BAR_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_BAR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_BAR_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_BAR_SET ns_noc_io_spio_soc_ip.csr 59846 BAR Bar 9 8 0x0 R/W UNSD_11_10 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_UNSD_11_10_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_UNSD_11_10_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_UNSD_11_10_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_UNSD_11_10_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_UNSD_11_10_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_UNSD_11_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_UNSD_11_10_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_UNSD_11_10_SET ns_noc_io_spio_soc_ip.csr 59857 UNSD_11_10 11 10 0x0 R CACHE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_CACHE_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_CACHE_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_CACHE_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_CACHE_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_CACHE_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_CACHE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_CACHE_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_CACHE_SET ns_noc_io_spio_soc_ip.csr 59868 CACHE Cache 15 12 0x0 R/W QOS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_QOS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_QOS_SET ns_noc_io_spio_soc_ip.csr 59879 QOS QoS 19 16 0x0 R/W PROT SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_PROT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_PROT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_PROT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_PROT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_PROT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_PROT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_PROT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_PROT_SET ns_noc_io_spio_soc_ip.csr 59890 PROT Prot 22 20 0x0 R/W LOC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_LOC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_LOC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_LOC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_LOC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_LOC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_LOC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_LOC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_LOC_SET ns_noc_io_spio_soc_ip.csr 59901 LOC 1'b1: Lock 23 23 0x0 R/W RDY SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_RDY_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_RDY_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_RDY_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_RDY_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_RDY_SET ns_noc_io_spio_soc_ip.csr 59912 RDY 1'b1: Ready 24 24 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_VAL_SET ns_noc_io_spio_soc_ip.csr 59923 VAL 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_UNSD_63_26_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_UNSD_63_26_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_UNSD_63_26_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_UNSD_63_26_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_UNSD_63_26_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_UNSD_63_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_UNSD_63_26_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK0_UNSD_63_26_SET ns_noc_io_spio_soc_ip.csr 59934 UNSD_63_26 63 26 0x0000000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_cntr0 bridge_spio_p00_dma_m_1_7_am_cntr0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 59970 spio_p00_dma_m register am_cntr0 0x17F20 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_cntr0 32-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured. false false false false CNTR SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR0_CNTR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR0_CNTR_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR0_CNTR_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR0_CNTR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR0_CNTR_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR0_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR0_CNTR_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR0_CNTR_SET ns_noc_io_spio_soc_ip.csr 59958 CNTR Counter 31 0 0x00000000 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR0_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR0_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR0_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR0_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR0_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR0_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR0_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR0_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 59969 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_latnum0 bridge_spio_p00_dma_m_1_7_am_latnum0 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 60009 spio_p00_dma_m register am_latnum0 0x17F28 R/W 0x0000000000000007 Spio_noc_bridge_spio_p00_dma_m_1_7_am_latnum0 This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using: Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0 There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set. false false false false CNTR SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM0_CNTR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM0_CNTR_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM0_CNTR_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM0_CNTR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM0_CNTR_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM0_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM0_CNTR_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM0_CNTR_SET ns_noc_io_spio_soc_ip.csr 59997 CNTR Counter 31 0 0x00000007 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM0_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM0_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM0_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM0_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM0_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM0_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM0_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM0_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 60008 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_ccmd1 bridge_spio_p00_dma_m_1_7_am_ccmd1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 60199 spio_p00_dma_m register am_ccmd1 0x17F30 R/W 0x0000000003fff33f Spio_noc_bridge_spio_p00_dma_m_1_7_am_ccmd1 Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands. false false false false SNOOP SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_SNOOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_SNOOP_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_SNOOP_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_SNOOP_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_SNOOP_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_SNOOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_SNOOP_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_SNOOP_SET ns_noc_io_spio_soc_ip.csr 60031 SNOOP Snoop 3 0 0xf R/W DOMAIN SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_DOMAIN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_DOMAIN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_DOMAIN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_DOMAIN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_DOMAIN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_DOMAIN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_DOMAIN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_DOMAIN_SET ns_noc_io_spio_soc_ip.csr 60042 DOMAIN Domain 5 4 0x3 R/W UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 60053 UNSD_7_6 7 6 0x0 R BAR SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_BAR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_BAR_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_BAR_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_BAR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_BAR_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_BAR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_BAR_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_BAR_SET ns_noc_io_spio_soc_ip.csr 60064 BAR Bar 9 8 0x3 R/W UNSD_11_10 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_11_10_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_11_10_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_11_10_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_11_10_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_11_10_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_11_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_11_10_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_11_10_SET ns_noc_io_spio_soc_ip.csr 60075 UNSD_11_10 11 10 0x0 R CACHE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_CACHE_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_CACHE_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_CACHE_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_CACHE_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_CACHE_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_CACHE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_CACHE_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_CACHE_SET ns_noc_io_spio_soc_ip.csr 60086 CACHE Cache 15 12 0xf R/W QOS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_QOS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_QOS_SET ns_noc_io_spio_soc_ip.csr 60097 QOS QoS 19 16 0xf R/W PROT SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_PROT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_PROT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_PROT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_PROT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_PROT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_PROT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_PROT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_PROT_SET ns_noc_io_spio_soc_ip.csr 60108 PROT Prot 22 20 0x7 R/W LOC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_LOC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_LOC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_LOC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_LOC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_LOC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_LOC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_LOC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_LOC_SET ns_noc_io_spio_soc_ip.csr 60119 LOC 1'b1: Lock 23 23 0x1 R/W RDY SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_RDY_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_RDY_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_RDY_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_RDY_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_RDY_SET ns_noc_io_spio_soc_ip.csr 60130 RDY 1'b1: Ready 24 24 0x1 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_VAL_SET ns_noc_io_spio_soc_ip.csr 60141 VAL 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_27_26_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_27_26_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_27_26_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_27_26_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_27_26_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_27_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_27_26_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_27_26_SET ns_noc_io_spio_soc_ip.csr 60152 UNSD_27_26 27 26 0x0 R INTFID SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_INTFID_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_INTFID_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_INTFID_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_INTFID_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_INTFID_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_INTFID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_INTFID_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_INTFID_SET ns_noc_io_spio_soc_ip.csr 60164 INTFID 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_31_31 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_31_31_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_31_31_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_31_31_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_31_31_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_31_31_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_31_31_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_31_31_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_31_31_SET ns_noc_io_spio_soc_ip.csr 60175 UNSD_31_31 31 31 0x0 R TYP SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_TYP_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_TYP_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_TYP_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_TYP_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_TYP_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_TYP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_TYP_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_TYP_SET ns_noc_io_spio_soc_ip.csr 60187 TYP 1'b1: Count response latency of captured command 1'b0: Count captured command 32 32 0x0 R/W UNSD_63_33 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_63_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_63_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_63_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_63_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_63_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_63_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_63_33_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMD1_UNSD_63_33_SET ns_noc_io_spio_soc_ip.csr 60198 UNSD_63_33 63 33 0x00000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_ccmdmsk1 bridge_spio_p00_dma_m_1_7_am_ccmdmsk1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 60343 spio_p00_dma_m register am_ccmdmsk1 0x17F38 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_ccmdmsk1 If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters. false false false false SNOOP SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_SNOOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_SNOOP_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_SNOOP_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_SNOOP_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_SNOOP_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_SNOOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_SNOOP_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_SNOOP_SET ns_noc_io_spio_soc_ip.csr 60221 SNOOP Snoop 3 0 0x0 R/W DOMAIN SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_DOMAIN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_DOMAIN_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_DOMAIN_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_DOMAIN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_DOMAIN_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_DOMAIN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_DOMAIN_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_DOMAIN_SET ns_noc_io_spio_soc_ip.csr 60232 DOMAIN Domain 5 4 0x0 R/W UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 60243 UNSD_7_6 7 6 0x0 R BAR SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_BAR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_BAR_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_BAR_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_BAR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_BAR_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_BAR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_BAR_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_BAR_SET ns_noc_io_spio_soc_ip.csr 60254 BAR Bar 9 8 0x0 R/W UNSD_11_10 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_UNSD_11_10_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_UNSD_11_10_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_UNSD_11_10_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_UNSD_11_10_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_UNSD_11_10_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_UNSD_11_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_UNSD_11_10_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_UNSD_11_10_SET ns_noc_io_spio_soc_ip.csr 60265 UNSD_11_10 11 10 0x0 R CACHE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_CACHE_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_CACHE_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_CACHE_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_CACHE_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_CACHE_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_CACHE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_CACHE_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_CACHE_SET ns_noc_io_spio_soc_ip.csr 60276 CACHE Cache 15 12 0x0 R/W QOS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_QOS_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_QOS_SET ns_noc_io_spio_soc_ip.csr 60287 QOS QoS 19 16 0x0 R/W PROT SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_PROT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_PROT_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_PROT_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_PROT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_PROT_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_PROT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_PROT_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_PROT_SET ns_noc_io_spio_soc_ip.csr 60298 PROT Prot 22 20 0x0 R/W LOC SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_LOC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_LOC_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_LOC_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_LOC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_LOC_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_LOC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_LOC_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_LOC_SET ns_noc_io_spio_soc_ip.csr 60309 LOC 1'b1: Lock 23 23 0x0 R/W RDY SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_RDY_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_RDY_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_RDY_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_RDY_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_RDY_SET ns_noc_io_spio_soc_ip.csr 60320 RDY 1'b1: Ready 24 24 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_VAL_SET ns_noc_io_spio_soc_ip.csr 60331 VAL 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_UNSD_63_26_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_UNSD_63_26_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_UNSD_63_26_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_UNSD_63_26_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_UNSD_63_26_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_UNSD_63_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_UNSD_63_26_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CCMDMSK1_UNSD_63_26_SET ns_noc_io_spio_soc_ip.csr 60342 UNSD_63_26 63 26 0x0000000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_cntr1 bridge_spio_p00_dma_m_1_7_am_cntr1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 60378 spio_p00_dma_m register am_cntr1 0x17F40 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_cntr1 32-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured. false false false false CNTR SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR1_CNTR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR1_CNTR_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR1_CNTR_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR1_CNTR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR1_CNTR_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR1_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR1_CNTR_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR1_CNTR_SET ns_noc_io_spio_soc_ip.csr 60366 CNTR Counter 31 0 0x00000000 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR1_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR1_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR1_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR1_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR1_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR1_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR1_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_CNTR1_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 60377 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_latnum1 bridge_spio_p00_dma_m_1_7_am_latnum1 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 60417 spio_p00_dma_m register am_latnum1 0x17F48 R/W 0x0000000000000007 Spio_noc_bridge_spio_p00_dma_m_1_7_am_latnum1 This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using: Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0 There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set. false false false false CNTR SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM1_CNTR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM1_CNTR_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM1_CNTR_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM1_CNTR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM1_CNTR_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM1_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM1_CNTR_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM1_CNTR_SET ns_noc_io_spio_soc_ip.csr 60405 CNTR Counter 31 0 0x00000007 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM1_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM1_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM1_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM1_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM1_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM1_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM1_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_LATNUM1_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 60416 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_arovrd bridge_spio_p00_dma_m_1_7_am_arovrd SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 60530 spio_p00_dma_m register am_arovrd 0x17F60 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_arovrd AR override. false false false false arcache_val SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 60435 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 60448 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 60459 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 60470 UNSD_11_11 11 11 0x0 R arprot_enb SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 60483 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 60494 UNSD_15_15 15 15 0x0 R arqos_val SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 60505 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_ARQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 60518 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AROVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 60529 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_p00_dma_m_1_7_am_awovrd bridge_spio_p00_dma_m_1_7_am_awovrd SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 60643 spio_p00_dma_m register am_awovrd 0x17F68 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_dma_m_1_7_am_awovrd AW override. false false false false awcache_val SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 60548 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 60561 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 60572 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 60583 UNSD_11_11 11 11 0x0 R awprot_enb SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 60596 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 60607 UNSD_15_15 15 15 0x0 R awqos_val SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 60618 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_AWQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 60631 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_P00_DMA_M_1_7_AM_AWOVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 60642 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 60759 spio_p00_rot_m register am_adbase_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 0x18000 R/W 0x0000000040100000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 60683 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 60694 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 60705 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 60717 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 60728 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 60740 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 60751 BASE_ADDRESS_0_33 Base address 39 6 0x001004000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 60758 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 60851 spio_p00_rot_m register am_admask_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 0x18008 R/W 0x000000fffff00000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 60776 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 60787 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 60798 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 60809 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 60821 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 60832 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 60843 MASK_0_33 Mask 39 6 0x3ffffc000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 60850 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 60967 spio_p00_rot_m register am_adbase_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 0x18020 R/W 0x0000000056100000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 60891 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 60902 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 60913 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 60925 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 60936 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 60948 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 60959 BASE_ADDRESS_0_33 Base address 39 6 0x001584000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 60966 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 61059 spio_p00_rot_m register am_admask_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 0x18028 R/W 0x000000fffff00000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 60984 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 60995 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 61006 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 61017 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 61029 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 61040 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 61051 MASK_0_33 Mask 39 6 0x3ffffc000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 61058 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 61175 spio_p00_rot_m register am_adbase_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 0x18040 R/W 0x0000000056000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 61099 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 61110 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 61121 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 61133 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 61144 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 61156 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 61167 BASE_ADDRESS_0_33 Base address 39 6 0x001580000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 61174 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 61267 spio_p00_rot_m register am_admask_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 0x18048 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 61192 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 61203 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 61214 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 61225 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 61237 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 61248 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 61259 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 61266 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 61383 spio_p00_rot_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 0x18060 R/W 0x0000000054000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 61307 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 61318 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 61329 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 61341 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 61352 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 61364 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 61375 BASE_ADDRESS_0_33 Base address 39 6 0x001500000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 61382 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 61475 spio_p00_rot_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 0x18068 R/W 0x000000ffffff0000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 61400 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 61411 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 61422 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 61433 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 61445 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 61456 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 61467 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 61474 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 61591 spio_p00_rot_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 0x18080 R/W 0x0000000054010000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_SET ns_noc_io_spio_soc_ip.csr 61515 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 61526 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_SET ns_noc_io_spio_soc_ip.csr 61537 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 61549 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_SET ns_noc_io_spio_soc_ip.csr 61560 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_SET ns_noc_io_spio_soc_ip.csr 61572 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 61583 BASE_ADDRESS_0_33 Base address 39 6 0x001500400 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 61590 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 61683 spio_p00_rot_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 0x18088 R/W 0x000000ffffff0000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_SET ns_noc_io_spio_soc_ip.csr 61608 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 61619 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_SET ns_noc_io_spio_soc_ip.csr 61630 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_SET ns_noc_io_spio_soc_ip.csr 61641 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_SET ns_noc_io_spio_soc_ip.csr 61653 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_SET ns_noc_io_spio_soc_ip.csr 61664 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 61675 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 61682 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 61799 spio_p00_rot_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 0x180A0 R/W 0x0000000054020000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_SET ns_noc_io_spio_soc_ip.csr 61723 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 61734 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_SET ns_noc_io_spio_soc_ip.csr 61745 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 61757 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_SET ns_noc_io_spio_soc_ip.csr 61768 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_SET ns_noc_io_spio_soc_ip.csr 61780 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 61791 BASE_ADDRESS_0_33 Base address 39 6 0x001500800 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 61798 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 61891 spio_p00_rot_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 0x180A8 R/W 0x000000ffffff0000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_SET ns_noc_io_spio_soc_ip.csr 61816 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 61827 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_SET ns_noc_io_spio_soc_ip.csr 61838 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_SET ns_noc_io_spio_soc_ip.csr 61849 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_SET ns_noc_io_spio_soc_ip.csr 61861 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_SET ns_noc_io_spio_soc_ip.csr 61872 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 61883 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 61890 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 62007 spio_p00_rot_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 0x180C0 R/W 0x0000000054030000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_SET ns_noc_io_spio_soc_ip.csr 61931 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 61942 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_SET ns_noc_io_spio_soc_ip.csr 61953 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 61965 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_SET ns_noc_io_spio_soc_ip.csr 61976 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_SET ns_noc_io_spio_soc_ip.csr 61988 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 61999 BASE_ADDRESS_0_33 Base address 39 6 0x001500c00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 62006 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 62099 spio_p00_rot_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 0x180C8 R/W 0x000000ffffff0000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_SET ns_noc_io_spio_soc_ip.csr 62024 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 62035 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_SET ns_noc_io_spio_soc_ip.csr 62046 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_SET ns_noc_io_spio_soc_ip.csr 62057 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_SET ns_noc_io_spio_soc_ip.csr 62069 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_SET ns_noc_io_spio_soc_ip.csr 62080 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 62091 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 62098 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 62215 spio_p00_rot_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 0x180E0 R/W 0x0000000054040000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_SET ns_noc_io_spio_soc_ip.csr 62139 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 62150 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_SET ns_noc_io_spio_soc_ip.csr 62161 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 62173 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_SET ns_noc_io_spio_soc_ip.csr 62184 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_SET ns_noc_io_spio_soc_ip.csr 62196 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 62207 BASE_ADDRESS_0_33 Base address 39 6 0x001501000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 62214 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 62307 spio_p00_rot_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 0x180E8 R/W 0x000000ffffff0000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_SET ns_noc_io_spio_soc_ip.csr 62232 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 62243 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_SET ns_noc_io_spio_soc_ip.csr 62254 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_SET ns_noc_io_spio_soc_ip.csr 62265 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_SET ns_noc_io_spio_soc_ip.csr 62277 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_SET ns_noc_io_spio_soc_ip.csr 62288 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 62299 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 62306 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 62423 spio_p00_rot_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 0x18100 R/W 0x0000000054050000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_SET ns_noc_io_spio_soc_ip.csr 62347 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 62358 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_SET ns_noc_io_spio_soc_ip.csr 62369 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 62381 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_SET ns_noc_io_spio_soc_ip.csr 62392 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_SET ns_noc_io_spio_soc_ip.csr 62404 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 62415 BASE_ADDRESS_0_33 Base address 39 6 0x001501400 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 62422 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 62515 spio_p00_rot_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 0x18108 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_SET ns_noc_io_spio_soc_ip.csr 62440 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 62451 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_SET ns_noc_io_spio_soc_ip.csr 62462 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_SET ns_noc_io_spio_soc_ip.csr 62473 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_SET ns_noc_io_spio_soc_ip.csr 62485 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_SET ns_noc_io_spio_soc_ip.csr 62496 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 62507 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 62514 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 62631 spio_p00_rot_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 0x18120 R/W 0x0000000054051000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_SET ns_noc_io_spio_soc_ip.csr 62555 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 62566 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_SET ns_noc_io_spio_soc_ip.csr 62577 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 62589 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_SET ns_noc_io_spio_soc_ip.csr 62600 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_SET ns_noc_io_spio_soc_ip.csr 62612 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 62623 BASE_ADDRESS_0_33 Base address 39 6 0x001501440 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 62630 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 62723 spio_p00_rot_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 0x18128 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_SET ns_noc_io_spio_soc_ip.csr 62648 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 62659 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_SET ns_noc_io_spio_soc_ip.csr 62670 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_SET ns_noc_io_spio_soc_ip.csr 62681 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_SET ns_noc_io_spio_soc_ip.csr 62693 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_SET ns_noc_io_spio_soc_ip.csr 62704 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 62715 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 62722 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 62839 spio_p00_rot_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 0x18140 R/W 0x0000000054052000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_SET ns_noc_io_spio_soc_ip.csr 62763 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 62774 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_SET ns_noc_io_spio_soc_ip.csr 62785 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 62797 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_SET ns_noc_io_spio_soc_ip.csr 62808 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_SET ns_noc_io_spio_soc_ip.csr 62820 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 62831 BASE_ADDRESS_0_33 Base address 39 6 0x001501480 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 62838 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 62931 spio_p00_rot_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 0x18148 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_SET ns_noc_io_spio_soc_ip.csr 62856 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 62867 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_SET ns_noc_io_spio_soc_ip.csr 62878 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_SET ns_noc_io_spio_soc_ip.csr 62889 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_SET ns_noc_io_spio_soc_ip.csr 62901 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_SET ns_noc_io_spio_soc_ip.csr 62912 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 62923 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 62930 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 63047 spio_p00_rot_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 0x18160 R/W 0x0000000054053000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_SET ns_noc_io_spio_soc_ip.csr 62971 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 62982 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_SET ns_noc_io_spio_soc_ip.csr 62993 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 63005 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_SET ns_noc_io_spio_soc_ip.csr 63016 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_SET ns_noc_io_spio_soc_ip.csr 63028 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 63039 BASE_ADDRESS_0_33 Base address 39 6 0x0015014c0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 63046 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 63139 spio_p00_rot_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 0x18168 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_SET ns_noc_io_spio_soc_ip.csr 63064 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 63075 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_SET ns_noc_io_spio_soc_ip.csr 63086 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_SET ns_noc_io_spio_soc_ip.csr 63097 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_SET ns_noc_io_spio_soc_ip.csr 63109 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_SET ns_noc_io_spio_soc_ip.csr 63120 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 63131 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 63138 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 63255 spio_p00_rot_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 0x18180 R/W 0x0000000054054000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 63179 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 63190 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 63201 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 63213 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_SET ns_noc_io_spio_soc_ip.csr 63224 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_SET ns_noc_io_spio_soc_ip.csr 63236 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 63247 BASE_ADDRESS_0_33 Base address 39 6 0x001501500 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 63254 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 63347 spio_p00_rot_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 0x18188 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 63272 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 63283 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 63294 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_SET ns_noc_io_spio_soc_ip.csr 63305 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_SET ns_noc_io_spio_soc_ip.csr 63317 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_SET ns_noc_io_spio_soc_ip.csr 63328 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 63339 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 63346 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 63463 spio_p00_rot_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 0x181A0 R/W 0x0000000054055000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_SET ns_noc_io_spio_soc_ip.csr 63387 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_SET ns_noc_io_spio_soc_ip.csr 63398 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_SET ns_noc_io_spio_soc_ip.csr 63409 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 63421 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_SET ns_noc_io_spio_soc_ip.csr 63432 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_SET ns_noc_io_spio_soc_ip.csr 63444 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 63455 BASE_ADDRESS_0_33 Base address 39 6 0x001501540 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 63462 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 63555 spio_p00_rot_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 0x181A8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_SET ns_noc_io_spio_soc_ip.csr 63480 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_SET ns_noc_io_spio_soc_ip.csr 63491 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_SET ns_noc_io_spio_soc_ip.csr 63502 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_SET ns_noc_io_spio_soc_ip.csr 63513 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_SET ns_noc_io_spio_soc_ip.csr 63525 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_SET ns_noc_io_spio_soc_ip.csr 63536 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 63547 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 63554 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 63671 spio_p00_rot_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 0x181C0 R/W 0x0000000054056000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_SET ns_noc_io_spio_soc_ip.csr 63595 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_SET ns_noc_io_spio_soc_ip.csr 63606 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_SET ns_noc_io_spio_soc_ip.csr 63617 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 63629 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_SET ns_noc_io_spio_soc_ip.csr 63640 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_SET ns_noc_io_spio_soc_ip.csr 63652 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 63663 BASE_ADDRESS_0_33 Base address 39 6 0x001501580 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 63670 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 63763 spio_p00_rot_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 0x181C8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_SET ns_noc_io_spio_soc_ip.csr 63688 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_SET ns_noc_io_spio_soc_ip.csr 63699 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_SET ns_noc_io_spio_soc_ip.csr 63710 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_SET ns_noc_io_spio_soc_ip.csr 63721 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_SET ns_noc_io_spio_soc_ip.csr 63733 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_SET ns_noc_io_spio_soc_ip.csr 63744 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 63755 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 63762 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 63879 spio_p00_rot_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 0x181E0 R/W 0x0000000054057000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_SET ns_noc_io_spio_soc_ip.csr 63803 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_SET ns_noc_io_spio_soc_ip.csr 63814 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_SET ns_noc_io_spio_soc_ip.csr 63825 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 63837 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_SET ns_noc_io_spio_soc_ip.csr 63848 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_SET ns_noc_io_spio_soc_ip.csr 63860 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 63871 BASE_ADDRESS_0_33 Base address 39 6 0x0015015c0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 63878 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 63971 spio_p00_rot_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 0x181E8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_SET ns_noc_io_spio_soc_ip.csr 63896 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_SET ns_noc_io_spio_soc_ip.csr 63907 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_SET ns_noc_io_spio_soc_ip.csr 63918 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_SET ns_noc_io_spio_soc_ip.csr 63929 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_SET ns_noc_io_spio_soc_ip.csr 63941 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_SET ns_noc_io_spio_soc_ip.csr 63952 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 63963 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 63970 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 64087 spio_p00_rot_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 0x18200 R/W 0x0000000050000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_SET ns_noc_io_spio_soc_ip.csr 64011 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_SET ns_noc_io_spio_soc_ip.csr 64022 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_SET ns_noc_io_spio_soc_ip.csr 64033 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 64045 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_SET ns_noc_io_spio_soc_ip.csr 64056 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_SET ns_noc_io_spio_soc_ip.csr 64068 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 64079 BASE_ADDRESS_0_33 Base address 39 6 0x001400000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 64086 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 64179 spio_p00_rot_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 0x18208 R/W 0x000000fffe000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_SET ns_noc_io_spio_soc_ip.csr 64104 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_SET ns_noc_io_spio_soc_ip.csr 64115 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_SET ns_noc_io_spio_soc_ip.csr 64126 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_SET ns_noc_io_spio_soc_ip.csr 64137 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_SET ns_noc_io_spio_soc_ip.csr 64149 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_SET ns_noc_io_spio_soc_ip.csr 64160 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 64171 MASK_0_33 Mask 39 6 0x3fff80000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 64178 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 64295 spio_p00_rot_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 0x18220 R/W 0x0000000052000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 64219 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 64230 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 64241 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 64253 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_SET ns_noc_io_spio_soc_ip.csr 64264 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_SET ns_noc_io_spio_soc_ip.csr 64276 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 64287 BASE_ADDRESS_0_33 Base address 39 6 0x001480000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 64294 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 64387 spio_p00_rot_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 0x18228 R/W 0x000000fffffe0000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 64312 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 64323 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 64334 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_SET ns_noc_io_spio_soc_ip.csr 64345 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_SET ns_noc_io_spio_soc_ip.csr 64357 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_SET ns_noc_io_spio_soc_ip.csr 64368 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 64379 MASK_0_33 Mask 39 6 0x3fffff800 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 64386 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 64503 spio_p00_rot_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 0x18240 R/W 0x0000000052020000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_SET ns_noc_io_spio_soc_ip.csr 64427 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 64438 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_SET ns_noc_io_spio_soc_ip.csr 64449 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 64461 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_SET ns_noc_io_spio_soc_ip.csr 64472 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_SET ns_noc_io_spio_soc_ip.csr 64484 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 64495 BASE_ADDRESS_0_33 Base address 39 6 0x001480800 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 64502 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 64595 spio_p00_rot_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 0x18248 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_SET ns_noc_io_spio_soc_ip.csr 64520 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 64531 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_SET ns_noc_io_spio_soc_ip.csr 64542 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_SET ns_noc_io_spio_soc_ip.csr 64553 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_SET ns_noc_io_spio_soc_ip.csr 64565 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_SET ns_noc_io_spio_soc_ip.csr 64576 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 64587 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 64594 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 64711 spio_p00_rot_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 0x18260 R/W 0x0000000052021000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_SET ns_noc_io_spio_soc_ip.csr 64635 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 64646 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_SET ns_noc_io_spio_soc_ip.csr 64657 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 64669 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_SET ns_noc_io_spio_soc_ip.csr 64680 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_SET ns_noc_io_spio_soc_ip.csr 64692 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 64703 BASE_ADDRESS_0_33 Base address 39 6 0x001480840 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 64710 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 64803 spio_p00_rot_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 0x18268 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_SET ns_noc_io_spio_soc_ip.csr 64728 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 64739 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_SET ns_noc_io_spio_soc_ip.csr 64750 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_SET ns_noc_io_spio_soc_ip.csr 64761 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_SET ns_noc_io_spio_soc_ip.csr 64773 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_SET ns_noc_io_spio_soc_ip.csr 64784 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 64795 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 64802 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 64919 spio_p00_rot_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 0x18280 R/W 0x0000000052022000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_SET ns_noc_io_spio_soc_ip.csr 64843 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 64854 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_SET ns_noc_io_spio_soc_ip.csr 64865 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 64877 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_SET ns_noc_io_spio_soc_ip.csr 64888 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_SET ns_noc_io_spio_soc_ip.csr 64900 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 64911 BASE_ADDRESS_0_33 Base address 39 6 0x001480880 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 64918 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 65011 spio_p00_rot_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 0x18288 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_SET ns_noc_io_spio_soc_ip.csr 64936 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 64947 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_SET ns_noc_io_spio_soc_ip.csr 64958 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_SET ns_noc_io_spio_soc_ip.csr 64969 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_SET ns_noc_io_spio_soc_ip.csr 64981 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_SET ns_noc_io_spio_soc_ip.csr 64992 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 65003 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 65010 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 65127 spio_p00_rot_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 0x182A0 R/W 0x0000000052023000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 65051 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 65062 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 65073 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 65085 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 65096 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 65108 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 65119 BASE_ADDRESS_0_33 Base address 39 6 0x0014808c0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 65126 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 65219 spio_p00_rot_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 0x182A8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 65144 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 65155 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 65166 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 65177 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 65189 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 65200 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 65211 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 65218 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 65335 spio_p00_rot_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 0x182C0 R/W 0x0000000052024000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_SET ns_noc_io_spio_soc_ip.csr 65259 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 65270 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_SET ns_noc_io_spio_soc_ip.csr 65281 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 65293 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_SET ns_noc_io_spio_soc_ip.csr 65304 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_SET ns_noc_io_spio_soc_ip.csr 65316 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 65327 BASE_ADDRESS_0_33 Base address 39 6 0x001480900 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 65334 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 65427 spio_p00_rot_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 0x182C8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_SET ns_noc_io_spio_soc_ip.csr 65352 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 65363 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_SET ns_noc_io_spio_soc_ip.csr 65374 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_SET ns_noc_io_spio_soc_ip.csr 65385 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_SET ns_noc_io_spio_soc_ip.csr 65397 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_SET ns_noc_io_spio_soc_ip.csr 65408 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 65419 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 65426 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 65543 spio_p00_rot_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 0x182E0 R/W 0x0000000052025000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_SET ns_noc_io_spio_soc_ip.csr 65467 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 65478 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_SET ns_noc_io_spio_soc_ip.csr 65489 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 65501 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_SET ns_noc_io_spio_soc_ip.csr 65512 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_SET ns_noc_io_spio_soc_ip.csr 65524 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 65535 BASE_ADDRESS_0_33 Base address 39 6 0x001480940 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 65542 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 65635 spio_p00_rot_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 0x182E8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_SET ns_noc_io_spio_soc_ip.csr 65560 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 65571 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_SET ns_noc_io_spio_soc_ip.csr 65582 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_SET ns_noc_io_spio_soc_ip.csr 65593 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_SET ns_noc_io_spio_soc_ip.csr 65605 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_SET ns_noc_io_spio_soc_ip.csr 65616 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 65627 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 65634 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 65751 spio_p00_rot_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 0x18300 R/W 0x0000000052026000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_SET ns_noc_io_spio_soc_ip.csr 65675 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 65686 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_SET ns_noc_io_spio_soc_ip.csr 65697 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 65709 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_SET ns_noc_io_spio_soc_ip.csr 65720 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_SET ns_noc_io_spio_soc_ip.csr 65732 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 65743 BASE_ADDRESS_0_33 Base address 39 6 0x001480980 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 65750 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 65843 spio_p00_rot_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 0x18308 R/W 0x000000ffffffe000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_SET ns_noc_io_spio_soc_ip.csr 65768 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 65779 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_SET ns_noc_io_spio_soc_ip.csr 65790 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_SET ns_noc_io_spio_soc_ip.csr 65801 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_SET ns_noc_io_spio_soc_ip.csr 65813 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_SET ns_noc_io_spio_soc_ip.csr 65824 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 65835 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 65842 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 65959 spio_p00_rot_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 0x18320 R/W 0x0000000052028000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_SET ns_noc_io_spio_soc_ip.csr 65883 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 65894 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_SET ns_noc_io_spio_soc_ip.csr 65905 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 65917 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_SET ns_noc_io_spio_soc_ip.csr 65928 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_SET ns_noc_io_spio_soc_ip.csr 65940 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 65951 BASE_ADDRESS_0_33 Base address 39 6 0x001480a00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 65958 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 66051 spio_p00_rot_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 0x18328 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_SET ns_noc_io_spio_soc_ip.csr 65976 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 65987 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_SET ns_noc_io_spio_soc_ip.csr 65998 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_SET ns_noc_io_spio_soc_ip.csr 66009 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_SET ns_noc_io_spio_soc_ip.csr 66021 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_SET ns_noc_io_spio_soc_ip.csr 66032 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 66043 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 66050 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 66167 spio_p00_rot_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 0x18340 R/W 0x0000000052029000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_SET ns_noc_io_spio_soc_ip.csr 66091 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 66102 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_SET ns_noc_io_spio_soc_ip.csr 66113 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 66125 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_SET ns_noc_io_spio_soc_ip.csr 66136 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_SET ns_noc_io_spio_soc_ip.csr 66148 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 66159 BASE_ADDRESS_0_33 Base address 39 6 0x001480a40 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 66166 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 66259 spio_p00_rot_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 0x18348 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_SET ns_noc_io_spio_soc_ip.csr 66184 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 66195 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_SET ns_noc_io_spio_soc_ip.csr 66206 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_SET ns_noc_io_spio_soc_ip.csr 66217 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_SET ns_noc_io_spio_soc_ip.csr 66229 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_SET ns_noc_io_spio_soc_ip.csr 66240 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 66251 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 66258 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 66375 spio_p00_rot_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 0x18360 R/W 0x0000000054058000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_SET ns_noc_io_spio_soc_ip.csr 66299 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_SET ns_noc_io_spio_soc_ip.csr 66310 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_SET ns_noc_io_spio_soc_ip.csr 66321 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 66333 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_SET ns_noc_io_spio_soc_ip.csr 66344 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_SET ns_noc_io_spio_soc_ip.csr 66356 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 66367 BASE_ADDRESS_0_33 Base address 39 6 0x001501600 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 66374 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 66467 spio_p00_rot_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 0x18368 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_SET ns_noc_io_spio_soc_ip.csr 66392 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_SET ns_noc_io_spio_soc_ip.csr 66403 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_SET ns_noc_io_spio_soc_ip.csr 66414 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_SET ns_noc_io_spio_soc_ip.csr 66425 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_SET ns_noc_io_spio_soc_ip.csr 66437 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_SET ns_noc_io_spio_soc_ip.csr 66448 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 66459 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 66466 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 66583 spio_p00_rot_m register am_adbase_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 0x18380 R/W 0x0000000040300000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 66507 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 66518 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 66529 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 66541 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 66552 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 66564 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 66575 BASE_ADDRESS_0_33 Base address 39 6 0x00100c000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 66582 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 66675 spio_p00_rot_m register am_admask_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 0x18388 R/W 0x000000fffff00000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 66600 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 66611 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 66622 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 66633 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 66645 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 66656 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 66667 MASK_0_33 Mask 39 6 0x3ffffc000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 66674 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 66791 spio_p00_rot_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 0x183A0 R/W 0x0000000058200000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 66715 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 66726 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 66737 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 66749 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 66760 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 66772 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 66783 BASE_ADDRESS_0_33 Base address 39 6 0x001608000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 66790 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 66883 spio_p00_rot_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 0x183A8 R/W 0x000000ffffffe000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 66808 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 66819 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 66830 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 66841 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 66853 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 66864 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 66875 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 66882 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 66999 spio_p00_rot_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 0x183C0 R/W 0x0000000058400000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_SET ns_noc_io_spio_soc_ip.csr 66923 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 66934 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_SET ns_noc_io_spio_soc_ip.csr 66945 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 66957 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_SET ns_noc_io_spio_soc_ip.csr 66968 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_SET ns_noc_io_spio_soc_ip.csr 66980 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 66991 BASE_ADDRESS_0_33 Base address 39 6 0x001610000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 66998 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 67091 spio_p00_rot_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 0x183C8 R/W 0x000000ffffe00000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_SET ns_noc_io_spio_soc_ip.csr 67016 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 67027 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_SET ns_noc_io_spio_soc_ip.csr 67038 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_SET ns_noc_io_spio_soc_ip.csr 67049 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_SET ns_noc_io_spio_soc_ip.csr 67061 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_SET ns_noc_io_spio_soc_ip.csr 67072 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 67083 MASK_0_33 Mask 39 6 0x3ffff8000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 67090 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 67207 spio_p00_rot_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 0x183E0 R/W 0x0000004000000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_SET ns_noc_io_spio_soc_ip.csr 67131 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 67142 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_SET ns_noc_io_spio_soc_ip.csr 67153 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 67165 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_SET ns_noc_io_spio_soc_ip.csr 67176 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_SET ns_noc_io_spio_soc_ip.csr 67188 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 67199 BASE_ADDRESS_0_33 Base address 39 6 0x100000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 67206 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 67299 spio_p00_rot_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 0x183E8 R/W 0x000000e000000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_SET ns_noc_io_spio_soc_ip.csr 67224 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 67235 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_SET ns_noc_io_spio_soc_ip.csr 67246 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_SET ns_noc_io_spio_soc_ip.csr 67257 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_SET ns_noc_io_spio_soc_ip.csr 67269 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_SET ns_noc_io_spio_soc_ip.csr 67280 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 67291 MASK_0_33 Mask 39 6 0x380000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 67298 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 67415 spio_p00_rot_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 0x18400 R/W 0x0000006000000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_SET ns_noc_io_spio_soc_ip.csr 67339 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 67350 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_SET ns_noc_io_spio_soc_ip.csr 67361 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 67373 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_SET ns_noc_io_spio_soc_ip.csr 67384 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_SET ns_noc_io_spio_soc_ip.csr 67396 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 67407 BASE_ADDRESS_0_33 Base address 39 6 0x180000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 67414 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 67507 spio_p00_rot_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 0x18408 R/W 0x000000f000000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_SET ns_noc_io_spio_soc_ip.csr 67432 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 67443 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_SET ns_noc_io_spio_soc_ip.csr 67454 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_SET ns_noc_io_spio_soc_ip.csr 67465 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_SET ns_noc_io_spio_soc_ip.csr 67477 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_SET ns_noc_io_spio_soc_ip.csr 67488 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 67499 MASK_0_33 Mask 39 6 0x3c0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 67506 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 67623 spio_p00_rot_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 0x18420 R/W 0x0000007000000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_SET ns_noc_io_spio_soc_ip.csr 67547 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 67558 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_SET ns_noc_io_spio_soc_ip.csr 67569 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 67581 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_SET ns_noc_io_spio_soc_ip.csr 67592 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_SET ns_noc_io_spio_soc_ip.csr 67604 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 67615 BASE_ADDRESS_0_33 Base address 39 6 0x1c0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 67622 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 67715 spio_p00_rot_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 0x18428 R/W 0x000000f800000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_SET ns_noc_io_spio_soc_ip.csr 67640 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 67651 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_SET ns_noc_io_spio_soc_ip.csr 67662 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_SET ns_noc_io_spio_soc_ip.csr 67673 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_SET ns_noc_io_spio_soc_ip.csr 67685 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_SET ns_noc_io_spio_soc_ip.csr 67696 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 67707 MASK_0_33 Mask 39 6 0x3e0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 67714 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 67831 spio_p00_rot_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 0x18440 R/W 0x0000007800000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_SET ns_noc_io_spio_soc_ip.csr 67755 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 67766 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_SET ns_noc_io_spio_soc_ip.csr 67777 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 67789 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_SET ns_noc_io_spio_soc_ip.csr 67800 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_SET ns_noc_io_spio_soc_ip.csr 67812 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 67823 BASE_ADDRESS_0_33 Base address 39 6 0x1e0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 67830 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 67923 spio_p00_rot_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 0x18448 R/W 0x000000fc00000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_SET ns_noc_io_spio_soc_ip.csr 67848 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 67859 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_SET ns_noc_io_spio_soc_ip.csr 67870 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_SET ns_noc_io_spio_soc_ip.csr 67881 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_SET ns_noc_io_spio_soc_ip.csr 67893 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_SET ns_noc_io_spio_soc_ip.csr 67904 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 67915 MASK_0_33 Mask 39 6 0x3f0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 67922 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 68039 spio_p00_rot_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 0x18460 R/W 0x0000007c00000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_SET ns_noc_io_spio_soc_ip.csr 67963 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 67974 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_SET ns_noc_io_spio_soc_ip.csr 67985 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 67997 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_SET ns_noc_io_spio_soc_ip.csr 68008 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_SET ns_noc_io_spio_soc_ip.csr 68020 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 68031 BASE_ADDRESS_0_33 Base address 39 6 0x1f0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 68038 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 68131 spio_p00_rot_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 0x18468 R/W 0x000000fe00000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_SET ns_noc_io_spio_soc_ip.csr 68056 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 68067 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_SET ns_noc_io_spio_soc_ip.csr 68078 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_SET ns_noc_io_spio_soc_ip.csr 68089 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_SET ns_noc_io_spio_soc_ip.csr 68101 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_SET ns_noc_io_spio_soc_ip.csr 68112 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 68123 MASK_0_33 Mask 39 6 0x3f8000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 68130 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 68247 spio_p00_rot_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 0x18480 R/W 0x0000007e00000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_SET ns_noc_io_spio_soc_ip.csr 68171 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 68182 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_SET ns_noc_io_spio_soc_ip.csr 68193 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 68205 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_SET ns_noc_io_spio_soc_ip.csr 68216 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_SET ns_noc_io_spio_soc_ip.csr 68228 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 68239 BASE_ADDRESS_0_33 Base address 39 6 0x1f8000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 68246 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 68339 spio_p00_rot_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 0x18488 R/W 0x000000ff00000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_SET ns_noc_io_spio_soc_ip.csr 68264 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 68275 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_SET ns_noc_io_spio_soc_ip.csr 68286 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_SET ns_noc_io_spio_soc_ip.csr 68297 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_SET ns_noc_io_spio_soc_ip.csr 68309 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_SET ns_noc_io_spio_soc_ip.csr 68320 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 68331 MASK_0_33 Mask 39 6 0x3fc000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 68338 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 68455 spio_p00_rot_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 0x184A0 R/W 0x0000007f00000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_SET ns_noc_io_spio_soc_ip.csr 68379 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 68390 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_SET ns_noc_io_spio_soc_ip.csr 68401 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 68413 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_SET ns_noc_io_spio_soc_ip.csr 68424 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_SET ns_noc_io_spio_soc_ip.csr 68436 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 68447 BASE_ADDRESS_0_33 Base address 39 6 0x1fc000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 68454 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 68547 spio_p00_rot_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 0x184A8 R/W 0x000000ff80000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_SET ns_noc_io_spio_soc_ip.csr 68472 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 68483 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_SET ns_noc_io_spio_soc_ip.csr 68494 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_SET ns_noc_io_spio_soc_ip.csr 68505 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_SET ns_noc_io_spio_soc_ip.csr 68517 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_SET ns_noc_io_spio_soc_ip.csr 68528 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 68539 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 68546 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 68663 spio_p00_rot_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 0x184C0 R/W 0x0000007f80000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 68587 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 68598 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 68609 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 68621 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_SET ns_noc_io_spio_soc_ip.csr 68632 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_SET ns_noc_io_spio_soc_ip.csr 68644 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 68655 BASE_ADDRESS_0_33 Base address 39 6 0x1fe000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 68662 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 68755 spio_p00_rot_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 0x184C8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 68680 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 68691 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 68702 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_SET ns_noc_io_spio_soc_ip.csr 68713 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_SET ns_noc_io_spio_soc_ip.csr 68725 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_SET ns_noc_io_spio_soc_ip.csr 68736 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 68747 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 68754 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 68871 spio_p00_rot_m register am_adbase_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 0x184E0 R/W 0x0000000052100000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 68795 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 68806 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 68817 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 68829 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 68840 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 68852 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 68863 BASE_ADDRESS_0_33 Base address 39 6 0x001484000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 68870 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 68963 spio_p00_rot_m register am_admask_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 0x184E8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 68888 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 68899 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 68910 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 68921 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 68933 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 68944 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 68955 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 68962 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 69079 spio_p00_rot_m register am_adbase_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 0x18500 R/W 0x0000000042000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 69003 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 69014 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 69025 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 69037 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 69048 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 69060 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 69071 BASE_ADDRESS_0_33 Base address 39 6 0x001080000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 69078 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 69171 spio_p00_rot_m register am_admask_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 0x18508 R/W 0x000000fffe000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 69096 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 69107 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 69118 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 69129 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 69141 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 69152 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 69163 MASK_0_33 Mask 39 6 0x3fff80000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 69170 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 69287 spio_p00_rot_m register am_adbase_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 0x18520 R/W 0x0000000040200000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 69211 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 69222 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 69233 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 69245 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 69256 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 69268 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 69279 BASE_ADDRESS_0_33 Base address 39 6 0x001008000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 69286 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 69379 spio_p00_rot_m register am_admask_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 0x18528 R/W 0x000000fffff00000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 69304 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 69315 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 69326 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 69337 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 69349 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 69360 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 69371 MASK_0_33 Mask 39 6 0x3ffffc000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 69378 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 69495 spio_p00_rot_m register am_adbase_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 0x18540 R/W 0x0000000040400000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 69419 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 69430 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 69441 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 69453 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 69464 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 69476 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 69487 BASE_ADDRESS_0_33 Base address 39 6 0x001010000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 69494 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 69587 spio_p00_rot_m register am_admask_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 0x18548 R/W 0x000000fffff00000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 69512 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 69523 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 69534 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 69545 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 69557 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 69568 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 69579 MASK_0_33 Mask 39 6 0x3ffffc000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 69586 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 69703 spio_p00_rot_m register am_adbase_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 0x18560 R/W 0x0000000040000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 69627 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 69638 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 69649 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 69661 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 69672 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 69684 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 69695 BASE_ADDRESS_0_33 Base address 39 6 0x001000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 69702 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 69795 spio_p00_rot_m register am_admask_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 0x18568 R/W 0x000000ffffff0000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 69720 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 69731 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 69742 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 69753 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 69765 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 69776 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 69787 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 69794 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 69911 spio_p00_rot_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 0x18580 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 69835 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 69846 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 69857 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 69869 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 69880 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 69892 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 69903 BASE_ADDRESS_0_33 Base address 39 6 0x000000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 69910 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 70003 spio_p00_rot_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 0x18588 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 69928 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 69939 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 69950 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 69961 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 69973 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 69984 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 69995 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 70002 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 70119 spio_p00_rot_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 0x185A0 R/W 0x0000000000003000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_SET ns_noc_io_spio_soc_ip.csr 70043 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 70054 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_SET ns_noc_io_spio_soc_ip.csr 70065 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 70077 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_SET ns_noc_io_spio_soc_ip.csr 70088 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_SET ns_noc_io_spio_soc_ip.csr 70100 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 70111 BASE_ADDRESS_0_33 Base address 39 6 0x0000000c0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 70118 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 70211 spio_p00_rot_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 0x185A8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_SET ns_noc_io_spio_soc_ip.csr 70136 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 70147 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_SET ns_noc_io_spio_soc_ip.csr 70158 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_SET ns_noc_io_spio_soc_ip.csr 70169 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_SET ns_noc_io_spio_soc_ip.csr 70181 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_SET ns_noc_io_spio_soc_ip.csr 70192 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 70203 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 70210 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 70327 spio_p00_rot_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 0x185C0 R/W 0x0000000000010000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_SET ns_noc_io_spio_soc_ip.csr 70251 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 70262 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_SET ns_noc_io_spio_soc_ip.csr 70273 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 70285 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_SET ns_noc_io_spio_soc_ip.csr 70296 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_SET ns_noc_io_spio_soc_ip.csr 70308 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 70319 BASE_ADDRESS_0_33 Base address 39 6 0x000000400 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 70326 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 70419 spio_p00_rot_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 0x185C8 R/W 0x000000ffffffe000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_SET ns_noc_io_spio_soc_ip.csr 70344 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 70355 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_SET ns_noc_io_spio_soc_ip.csr 70366 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_SET ns_noc_io_spio_soc_ip.csr 70377 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_SET ns_noc_io_spio_soc_ip.csr 70389 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_SET ns_noc_io_spio_soc_ip.csr 70400 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 70411 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 70418 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 70535 spio_p00_rot_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 0x185E0 R/W 0x0000000000100000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_SET ns_noc_io_spio_soc_ip.csr 70459 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 70470 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_SET ns_noc_io_spio_soc_ip.csr 70481 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 70493 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_SET ns_noc_io_spio_soc_ip.csr 70504 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_SET ns_noc_io_spio_soc_ip.csr 70516 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 70527 BASE_ADDRESS_0_33 Base address 39 6 0x000004000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 70534 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 70627 spio_p00_rot_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 0x185E8 R/W 0x000000ffffff8000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_SET ns_noc_io_spio_soc_ip.csr 70552 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 70563 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_SET ns_noc_io_spio_soc_ip.csr 70574 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_SET ns_noc_io_spio_soc_ip.csr 70585 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_SET ns_noc_io_spio_soc_ip.csr 70597 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_SET ns_noc_io_spio_soc_ip.csr 70608 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 70619 MASK_0_33 Mask 39 6 0x3fffffe00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 70626 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 70743 spio_p00_rot_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 0x18600 R/W 0x0000000000200000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_SET ns_noc_io_spio_soc_ip.csr 70667 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 70678 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_SET ns_noc_io_spio_soc_ip.csr 70689 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 70701 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_SET ns_noc_io_spio_soc_ip.csr 70712 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_SET ns_noc_io_spio_soc_ip.csr 70724 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 70735 BASE_ADDRESS_0_33 Base address 39 6 0x000008000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 70742 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 70835 spio_p00_rot_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 0x18608 R/W 0x000000ffffffc000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_SET ns_noc_io_spio_soc_ip.csr 70760 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 70771 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_SET ns_noc_io_spio_soc_ip.csr 70782 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_SET ns_noc_io_spio_soc_ip.csr 70793 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_SET ns_noc_io_spio_soc_ip.csr 70805 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_SET ns_noc_io_spio_soc_ip.csr 70816 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 70827 MASK_0_33 Mask 39 6 0x3ffffff00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 70834 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 70951 spio_p00_rot_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 0x18620 R/W 0x0000000000300000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_SET ns_noc_io_spio_soc_ip.csr 70875 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 70886 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_SET ns_noc_io_spio_soc_ip.csr 70897 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 70909 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_SET ns_noc_io_spio_soc_ip.csr 70920 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_SET ns_noc_io_spio_soc_ip.csr 70932 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 70943 BASE_ADDRESS_0_33 Base address 39 6 0x00000c000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 70950 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 71043 spio_p00_rot_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 0x18628 R/W 0x000000ffffffc000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_SET ns_noc_io_spio_soc_ip.csr 70968 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 70979 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_SET ns_noc_io_spio_soc_ip.csr 70990 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_SET ns_noc_io_spio_soc_ip.csr 71001 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_SET ns_noc_io_spio_soc_ip.csr 71013 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_SET ns_noc_io_spio_soc_ip.csr 71024 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 71035 MASK_0_33 Mask 39 6 0x3ffffff00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 71042 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 71159 spio_p00_rot_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 0x18640 R/W 0x0000000002000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_SET ns_noc_io_spio_soc_ip.csr 71083 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 71094 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_SET ns_noc_io_spio_soc_ip.csr 71105 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 71117 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_SET ns_noc_io_spio_soc_ip.csr 71128 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_SET ns_noc_io_spio_soc_ip.csr 71140 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 71151 BASE_ADDRESS_0_33 Base address 39 6 0x000080000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 71158 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 71251 spio_p00_rot_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 0x18648 R/W 0x000000ffffff0000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_SET ns_noc_io_spio_soc_ip.csr 71176 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 71187 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_SET ns_noc_io_spio_soc_ip.csr 71198 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_SET ns_noc_io_spio_soc_ip.csr 71209 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_SET ns_noc_io_spio_soc_ip.csr 71221 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_SET ns_noc_io_spio_soc_ip.csr 71232 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 71243 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 71250 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 71367 spio_p00_rot_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 0x18660 R/W 0x0000000010000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_SET ns_noc_io_spio_soc_ip.csr 71291 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 71302 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_SET ns_noc_io_spio_soc_ip.csr 71313 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 71325 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_SET ns_noc_io_spio_soc_ip.csr 71336 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_SET ns_noc_io_spio_soc_ip.csr 71348 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 71359 BASE_ADDRESS_0_33 Base address 39 6 0x000400000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 71366 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 71459 spio_p00_rot_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 0x18668 R/W 0x000000fffe000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_SET ns_noc_io_spio_soc_ip.csr 71384 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 71395 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_SET ns_noc_io_spio_soc_ip.csr 71406 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_SET ns_noc_io_spio_soc_ip.csr 71417 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_SET ns_noc_io_spio_soc_ip.csr 71429 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_SET ns_noc_io_spio_soc_ip.csr 71440 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 71451 MASK_0_33 Mask 39 6 0x3fff80000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 71458 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 71575 spio_p00_rot_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 0x18680 R/W 0x0000000012000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_SET ns_noc_io_spio_soc_ip.csr 71499 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 71510 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_SET ns_noc_io_spio_soc_ip.csr 71521 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 71533 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_SET ns_noc_io_spio_soc_ip.csr 71544 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_SET ns_noc_io_spio_soc_ip.csr 71556 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 71567 BASE_ADDRESS_0_33 Base address 39 6 0x000480000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 71574 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 71667 spio_p00_rot_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 0x18688 R/W 0x000000ffffff8000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_SET ns_noc_io_spio_soc_ip.csr 71592 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 71603 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_SET ns_noc_io_spio_soc_ip.csr 71614 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_SET ns_noc_io_spio_soc_ip.csr 71625 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_SET ns_noc_io_spio_soc_ip.csr 71637 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_SET ns_noc_io_spio_soc_ip.csr 71648 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 71659 MASK_0_33 Mask 39 6 0x3fffffe00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 71666 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 71783 spio_p00_rot_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 0x186A0 R/W 0x0000000012008000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 71707 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 71718 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 71729 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 71741 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_SET ns_noc_io_spio_soc_ip.csr 71752 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_SET ns_noc_io_spio_soc_ip.csr 71764 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 71775 BASE_ADDRESS_0_33 Base address 39 6 0x000480200 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 71782 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 71875 spio_p00_rot_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 0x186A8 R/W 0x000000ffffffe000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 71800 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 71811 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 71822 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_SET ns_noc_io_spio_soc_ip.csr 71833 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_SET ns_noc_io_spio_soc_ip.csr 71845 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_SET ns_noc_io_spio_soc_ip.csr 71856 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 71867 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 71874 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 71991 spio_p00_rot_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 0x186C0 R/W 0x000000001200a000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_SET ns_noc_io_spio_soc_ip.csr 71915 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_SET ns_noc_io_spio_soc_ip.csr 71926 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_SET ns_noc_io_spio_soc_ip.csr 71937 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 71949 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_SET ns_noc_io_spio_soc_ip.csr 71960 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_SET ns_noc_io_spio_soc_ip.csr 71972 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 71983 BASE_ADDRESS_0_33 Base address 39 6 0x000480280 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 71990 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 72083 spio_p00_rot_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 0x186C8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_SET ns_noc_io_spio_soc_ip.csr 72008 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_SET ns_noc_io_spio_soc_ip.csr 72019 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_SET ns_noc_io_spio_soc_ip.csr 72030 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_SET ns_noc_io_spio_soc_ip.csr 72041 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_SET ns_noc_io_spio_soc_ip.csr 72053 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_SET ns_noc_io_spio_soc_ip.csr 72064 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 72075 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 72082 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 72199 spio_p00_rot_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 0x186E0 R/W 0x0000000014000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_SET ns_noc_io_spio_soc_ip.csr 72123 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_SET ns_noc_io_spio_soc_ip.csr 72134 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_SET ns_noc_io_spio_soc_ip.csr 72145 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 72157 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_SET ns_noc_io_spio_soc_ip.csr 72168 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_SET ns_noc_io_spio_soc_ip.csr 72180 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 72191 BASE_ADDRESS_0_33 Base address 39 6 0x000500000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 72198 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 72291 spio_p00_rot_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 0x186E8 R/W 0x000000fffffc0000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_SET ns_noc_io_spio_soc_ip.csr 72216 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_SET ns_noc_io_spio_soc_ip.csr 72227 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_SET ns_noc_io_spio_soc_ip.csr 72238 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_SET ns_noc_io_spio_soc_ip.csr 72249 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_SET ns_noc_io_spio_soc_ip.csr 72261 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_SET ns_noc_io_spio_soc_ip.csr 72272 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 72283 MASK_0_33 Mask 39 6 0x3fffff000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 72290 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 72407 spio_p00_rot_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 0x18700 R/W 0x0000000018000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_SET ns_noc_io_spio_soc_ip.csr 72331 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_SET ns_noc_io_spio_soc_ip.csr 72342 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_SET ns_noc_io_spio_soc_ip.csr 72353 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 72365 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_SET ns_noc_io_spio_soc_ip.csr 72376 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_SET ns_noc_io_spio_soc_ip.csr 72388 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 72399 BASE_ADDRESS_0_33 Base address 39 6 0x000600000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 72406 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 72499 spio_p00_rot_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 0x18708 R/W 0x000000fffff80000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_SET ns_noc_io_spio_soc_ip.csr 72424 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_SET ns_noc_io_spio_soc_ip.csr 72435 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_SET ns_noc_io_spio_soc_ip.csr 72446 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_SET ns_noc_io_spio_soc_ip.csr 72457 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_SET ns_noc_io_spio_soc_ip.csr 72469 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_SET ns_noc_io_spio_soc_ip.csr 72480 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 72491 MASK_0_33 Mask 39 6 0x3ffffe000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 72498 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 72615 spio_p00_rot_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 0x18720 R/W 0x0000000018080000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_SET ns_noc_io_spio_soc_ip.csr 72539 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_SET ns_noc_io_spio_soc_ip.csr 72550 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_SET ns_noc_io_spio_soc_ip.csr 72561 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 72573 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_SET ns_noc_io_spio_soc_ip.csr 72584 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_SET ns_noc_io_spio_soc_ip.csr 72596 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 72607 BASE_ADDRESS_0_33 Base address 39 6 0x000602000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 72614 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 72707 spio_p00_rot_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 0x18728 R/W 0x000000ffffffe000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_SET ns_noc_io_spio_soc_ip.csr 72632 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_SET ns_noc_io_spio_soc_ip.csr 72643 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_SET ns_noc_io_spio_soc_ip.csr 72654 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_SET ns_noc_io_spio_soc_ip.csr 72665 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_SET ns_noc_io_spio_soc_ip.csr 72677 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_SET ns_noc_io_spio_soc_ip.csr 72688 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 72699 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 72706 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 72823 spio_p00_rot_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 0x18740 R/W 0x0000000018082000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_SET ns_noc_io_spio_soc_ip.csr 72747 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_SET ns_noc_io_spio_soc_ip.csr 72758 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_SET ns_noc_io_spio_soc_ip.csr 72769 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 72781 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_SET ns_noc_io_spio_soc_ip.csr 72792 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_SET ns_noc_io_spio_soc_ip.csr 72804 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 72815 BASE_ADDRESS_0_33 Base address 39 6 0x000602080 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 72822 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 72915 spio_p00_rot_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 0x18748 R/W 0x000000fffffff000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_SET ns_noc_io_spio_soc_ip.csr 72840 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_SET ns_noc_io_spio_soc_ip.csr 72851 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_SET ns_noc_io_spio_soc_ip.csr 72862 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_SET ns_noc_io_spio_soc_ip.csr 72873 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_SET ns_noc_io_spio_soc_ip.csr 72885 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_SET ns_noc_io_spio_soc_ip.csr 72896 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 72907 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 72914 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 73031 spio_p00_rot_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 0x18760 R/W 0x0000000020000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_SET ns_noc_io_spio_soc_ip.csr 72955 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_SET ns_noc_io_spio_soc_ip.csr 72966 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_SET ns_noc_io_spio_soc_ip.csr 72977 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 72989 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_SET ns_noc_io_spio_soc_ip.csr 73000 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_SET ns_noc_io_spio_soc_ip.csr 73012 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 73023 BASE_ADDRESS_0_33 Base address 39 6 0x000800000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 73030 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 73123 spio_p00_rot_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 0x18768 R/W 0x000000fffffc0000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_SET ns_noc_io_spio_soc_ip.csr 73048 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_SET ns_noc_io_spio_soc_ip.csr 73059 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_SET ns_noc_io_spio_soc_ip.csr 73070 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_SET ns_noc_io_spio_soc_ip.csr 73081 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_SET ns_noc_io_spio_soc_ip.csr 73093 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_SET ns_noc_io_spio_soc_ip.csr 73104 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 73115 MASK_0_33 Mask 39 6 0x3fffff000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 73122 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 73239 spio_p00_rot_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 0x18780 R/W 0x0000000030000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_SET ns_noc_io_spio_soc_ip.csr 73163 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_SET ns_noc_io_spio_soc_ip.csr 73174 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_SET ns_noc_io_spio_soc_ip.csr 73185 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 73197 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_SET ns_noc_io_spio_soc_ip.csr 73208 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_SET ns_noc_io_spio_soc_ip.csr 73220 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 73231 BASE_ADDRESS_0_33 Base address 39 6 0x000c00000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 73238 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 73331 spio_p00_rot_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 0x18788 R/W 0x000000ffffff8000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_SET ns_noc_io_spio_soc_ip.csr 73256 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_SET ns_noc_io_spio_soc_ip.csr 73267 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_SET ns_noc_io_spio_soc_ip.csr 73278 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_SET ns_noc_io_spio_soc_ip.csr 73289 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_SET ns_noc_io_spio_soc_ip.csr 73301 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_SET ns_noc_io_spio_soc_ip.csr 73312 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 73323 MASK_0_33 Mask 39 6 0x3fffffe00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 73330 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 73447 spio_p00_rot_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 0x187A0 R/W 0x0000000030008000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_SET ns_noc_io_spio_soc_ip.csr 73371 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_SET ns_noc_io_spio_soc_ip.csr 73382 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_SET ns_noc_io_spio_soc_ip.csr 73393 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 73405 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_SET ns_noc_io_spio_soc_ip.csr 73416 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_SET ns_noc_io_spio_soc_ip.csr 73428 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 73439 BASE_ADDRESS_0_33 Base address 39 6 0x000c00200 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 73446 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 73539 spio_p00_rot_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 0x187A8 R/W 0x000000ffffffc000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_SET ns_noc_io_spio_soc_ip.csr 73464 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_SET ns_noc_io_spio_soc_ip.csr 73475 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_SET ns_noc_io_spio_soc_ip.csr 73486 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_SET ns_noc_io_spio_soc_ip.csr 73497 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_SET ns_noc_io_spio_soc_ip.csr 73509 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_SET ns_noc_io_spio_soc_ip.csr 73520 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 73531 MASK_0_33 Mask 39 6 0x3ffffff00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 73538 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 73655 spio_p00_rot_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 0x187C0 R/W 0x0000000040080000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_SET ns_noc_io_spio_soc_ip.csr 73579 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_SET ns_noc_io_spio_soc_ip.csr 73590 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_SET ns_noc_io_spio_soc_ip.csr 73601 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 73613 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_SET ns_noc_io_spio_soc_ip.csr 73624 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_SET ns_noc_io_spio_soc_ip.csr 73636 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 73647 BASE_ADDRESS_0_33 Base address 39 6 0x001002000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 73654 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 73747 spio_p00_rot_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 0x187C8 R/W 0x000000ffffffe000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_SET ns_noc_io_spio_soc_ip.csr 73672 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_SET ns_noc_io_spio_soc_ip.csr 73683 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_SET ns_noc_io_spio_soc_ip.csr 73694 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_SET ns_noc_io_spio_soc_ip.csr 73705 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_SET ns_noc_io_spio_soc_ip.csr 73717 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_SET ns_noc_io_spio_soc_ip.csr 73728 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 73739 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 73746 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 73863 spio_p00_rot_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 0x187E0 R/W 0x0000000058000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_SET ns_noc_io_spio_soc_ip.csr 73787 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_SET ns_noc_io_spio_soc_ip.csr 73798 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_SET ns_noc_io_spio_soc_ip.csr 73809 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 73821 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_SET ns_noc_io_spio_soc_ip.csr 73832 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_SET ns_noc_io_spio_soc_ip.csr 73844 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 73855 BASE_ADDRESS_0_33 Base address 39 6 0x001600000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 73862 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 73955 spio_p00_rot_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 0x187E8 R/W 0x000000ffffffe000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_SET ns_noc_io_spio_soc_ip.csr 73880 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_SET ns_noc_io_spio_soc_ip.csr 73891 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_SET ns_noc_io_spio_soc_ip.csr 73902 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_SET ns_noc_io_spio_soc_ip.csr 73913 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_SET ns_noc_io_spio_soc_ip.csr 73925 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_SET ns_noc_io_spio_soc_ip.csr 73936 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 73947 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 73954 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 74071 spio_p00_rot_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 0x18800 R/W 0x0000000060000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_SET ns_noc_io_spio_soc_ip.csr 73995 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_SET ns_noc_io_spio_soc_ip.csr 74006 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_SET ns_noc_io_spio_soc_ip.csr 74017 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 74029 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_SET ns_noc_io_spio_soc_ip.csr 74040 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_SET ns_noc_io_spio_soc_ip.csr 74052 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 74063 BASE_ADDRESS_0_33 Base address 39 6 0x001800000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 74070 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 74163 spio_p00_rot_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 0x18808 R/W 0x000000ffe0000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_SET ns_noc_io_spio_soc_ip.csr 74088 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_SET ns_noc_io_spio_soc_ip.csr 74099 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_SET ns_noc_io_spio_soc_ip.csr 74110 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_SET ns_noc_io_spio_soc_ip.csr 74121 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_SET ns_noc_io_spio_soc_ip.csr 74133 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_SET ns_noc_io_spio_soc_ip.csr 74144 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 74155 MASK_0_33 Mask 39 6 0x3ff800000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 74162 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 74279 spio_p00_rot_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 0x18820 R/W 0x0000000080000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_SET ns_noc_io_spio_soc_ip.csr 74203 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_SET ns_noc_io_spio_soc_ip.csr 74214 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_SET ns_noc_io_spio_soc_ip.csr 74225 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 74237 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_SET ns_noc_io_spio_soc_ip.csr 74248 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_SET ns_noc_io_spio_soc_ip.csr 74260 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 74271 BASE_ADDRESS_0_33 Base address 39 6 0x002000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 74278 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 74371 spio_p00_rot_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 0x18828 R/W 0x000000ff80000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_SET ns_noc_io_spio_soc_ip.csr 74296 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_SET ns_noc_io_spio_soc_ip.csr 74307 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_SET ns_noc_io_spio_soc_ip.csr 74318 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_SET ns_noc_io_spio_soc_ip.csr 74329 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_SET ns_noc_io_spio_soc_ip.csr 74341 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_SET ns_noc_io_spio_soc_ip.csr 74352 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 74363 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 74370 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 74487 spio_p00_rot_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 0x18840 R/W 0x0000000100000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_SET ns_noc_io_spio_soc_ip.csr 74411 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_SET ns_noc_io_spio_soc_ip.csr 74422 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_SET ns_noc_io_spio_soc_ip.csr 74433 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 74445 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_SET ns_noc_io_spio_soc_ip.csr 74456 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_SET ns_noc_io_spio_soc_ip.csr 74468 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 74479 BASE_ADDRESS_0_33 Base address 39 6 0x004000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 74486 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 74579 spio_p00_rot_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 0x18848 R/W 0x000000ff00000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_SET ns_noc_io_spio_soc_ip.csr 74504 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_SET ns_noc_io_spio_soc_ip.csr 74515 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_SET ns_noc_io_spio_soc_ip.csr 74526 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_SET ns_noc_io_spio_soc_ip.csr 74537 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_SET ns_noc_io_spio_soc_ip.csr 74549 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_SET ns_noc_io_spio_soc_ip.csr 74560 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 74571 MASK_0_33 Mask 39 6 0x3fc000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 74578 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 74695 spio_p00_rot_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 0x18860 R/W 0x0000008000000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_SET ns_noc_io_spio_soc_ip.csr 74619 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_SET ns_noc_io_spio_soc_ip.csr 74630 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_SET ns_noc_io_spio_soc_ip.csr 74641 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 74653 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_SET ns_noc_io_spio_soc_ip.csr 74664 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_SET ns_noc_io_spio_soc_ip.csr 74676 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 74687 BASE_ADDRESS_0_33 Base address 39 6 0x200000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 74694 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 74787 spio_p00_rot_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 0x18868 R/W 0x000000f800000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_SET ns_noc_io_spio_soc_ip.csr 74712 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_SET ns_noc_io_spio_soc_ip.csr 74723 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_SET ns_noc_io_spio_soc_ip.csr 74734 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_SET ns_noc_io_spio_soc_ip.csr 74745 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_SET ns_noc_io_spio_soc_ip.csr 74757 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_SET ns_noc_io_spio_soc_ip.csr 74768 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 74779 MASK_0_33 Mask 39 6 0x3e0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 74786 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 74903 spio_p00_rot_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 0x18880 R/W 0x000000c000000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_SET ns_noc_io_spio_soc_ip.csr 74827 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_SET ns_noc_io_spio_soc_ip.csr 74838 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_SET ns_noc_io_spio_soc_ip.csr 74849 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 74861 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_SET ns_noc_io_spio_soc_ip.csr 74872 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_SET ns_noc_io_spio_soc_ip.csr 74884 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 74895 BASE_ADDRESS_0_33 Base address 39 6 0x300000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 74902 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 74995 spio_p00_rot_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 0x18888 R/W 0x000000f800000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_SET ns_noc_io_spio_soc_ip.csr 74920 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_SET ns_noc_io_spio_soc_ip.csr 74931 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_SET ns_noc_io_spio_soc_ip.csr 74942 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_SET ns_noc_io_spio_soc_ip.csr 74953 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_SET ns_noc_io_spio_soc_ip.csr 74965 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_SET ns_noc_io_spio_soc_ip.csr 74976 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 74987 MASK_0_33 Mask 39 6 0x3e0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 74994 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_p_0 bridge_spio_p00_rot_m_2_7_p_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 75060 spio_p00_rot_m register p_0 0x1B000 R/W 0x00000003 Spio_noc_bridge_spio_p00_rot_m_2_7_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_0_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_0_SET ns_noc_io_spio_soc_ip.csr 75023 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_1_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_1_SET ns_noc_io_spio_soc_ip.csr 75035 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_2_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_2_SET ns_noc_io_spio_soc_ip.csr 75047 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_3_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_0_WT_QOS_3_SET ns_noc_io_spio_soc_ip.csr 75059 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register spio_noc.bridge_spio_p00_rot_m_2_7_p_1 bridge_spio_p00_rot_m_2_7_p_1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 75126 spio_p00_rot_m register p_1 0x1B008 R 0x00000000 Spio_noc_bridge_spio_p00_rot_m_2_7_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_4_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_4_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_4_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_4_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_4_SET ns_noc_io_spio_soc_ip.csr 75089 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_5_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_5_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_5_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_5_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_5_SET ns_noc_io_spio_soc_ip.csr 75101 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_6_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_6_SET ns_noc_io_spio_soc_ip.csr 75113 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_7_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_7_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_7_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_7_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_1_WT_QOS_7_SET ns_noc_io_spio_soc_ip.csr 75125 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register spio_noc.bridge_spio_p00_rot_m_2_7_p_2 bridge_spio_p00_rot_m_2_7_p_2 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 75192 spio_p00_rot_m register p_2 0x1B010 R 0x00000000 Spio_noc_bridge_spio_p00_rot_m_2_7_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_8_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_8_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_8_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_8_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_8_SET ns_noc_io_spio_soc_ip.csr 75155 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_9_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_9_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_9_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_9_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_9_SET ns_noc_io_spio_soc_ip.csr 75167 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_10_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_10_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_10_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_10_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_10_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_10_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_10_SET ns_noc_io_spio_soc_ip.csr 75179 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_11_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_11_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_11_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_11_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_11_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_2_WT_QOS_11_SET ns_noc_io_spio_soc_ip.csr 75191 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register spio_noc.bridge_spio_p00_rot_m_2_7_p_3 bridge_spio_p00_rot_m_2_7_p_3 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 75258 spio_p00_rot_m register p_3 0x1B018 R 0x00000000 Spio_noc_bridge_spio_p00_rot_m_2_7_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_12_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_12_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_12_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_12_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_12_SET ns_noc_io_spio_soc_ip.csr 75221 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_13_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_13_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_13_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_13_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_13_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_13_SET ns_noc_io_spio_soc_ip.csr 75233 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_14_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_14_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_14_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_14_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_14_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_14_SET ns_noc_io_spio_soc_ip.csr 75245 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_15_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_15_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_15_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_15_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_15_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_P_3_WT_QOS_15_SET ns_noc_io_spio_soc_ip.csr 75257 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register spio_noc.bridge_spio_p00_rot_m_2_7_txe bridge_spio_p00_rot_m_2_7_txe SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 75404 spio_p00_rot_m register txe 0x1B040 R/W 0x00000000 Spio_noc_bridge_spio_p00_rot_m_2_7_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_TRANS_WITHOUT_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_TRANS_WITHOUT_SOP_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_TRANS_WITHOUT_SOP_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_TRANS_WITHOUT_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_TRANS_WITHOUT_SOP_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_TRANS_WITHOUT_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_TRANS_WITHOUT_SOP_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_spio_soc_ip.csr 75285 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_SOP_AFTER_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_SOP_AFTER_SOP_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_SOP_AFTER_SOP_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_SOP_AFTER_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_SOP_AFTER_SOP_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_SOP_AFTER_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_SOP_AFTER_SOP_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_SOP_AFTER_SOP_SET ns_noc_io_spio_soc_ip.csr 75297 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 75312 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 75325 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_A_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_spio_soc_ip.csr 75339 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_B_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_spio_soc_ip.csr 75353 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_C_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_spio_soc_ip.csr 75367 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_D_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_spio_soc_ip.csr 75381 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 75392 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXE_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 75403 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_txem bridge_spio_p00_rot_m_2_7_txem SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 75483 spio_p00_rot_m register txem 0x1B048 R/W 0x00000008 Spio_noc_bridge_spio_p00_rot_m_2_7_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_UNSD_1_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_UNSD_1_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_UNSD_1_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_UNSD_1_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_UNSD_1_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_UNSD_1_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_UNSD_1_0_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_UNSD_1_0_SET ns_noc_io_spio_soc_ip.csr 75427 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 75438 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 75449 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_UNSD_7_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_UNSD_7_4_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_UNSD_7_4_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_UNSD_7_4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_UNSD_7_4_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_UNSD_7_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_UNSD_7_4_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_UNSD_7_4_SET ns_noc_io_spio_soc_ip.csr 75460 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 75471 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_TXEM_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 75482 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_btus_0 bridge_spio_p00_rot_m_2_7_btus_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 75851 spio_p00_rot_m register btus_0 0x1B058 R 0x00000000 Spio_noc_bridge_spio_p00_rot_m_2_7_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_A_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_A_SET ns_noc_io_spio_soc_ip.csr 75509 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_B_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_B_SET ns_noc_io_spio_soc_ip.csr 75520 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_C_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_C_SET ns_noc_io_spio_soc_ip.csr 75531 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_D_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L0_D_SET ns_noc_io_spio_soc_ip.csr 75542 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_A_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_A_SET ns_noc_io_spio_soc_ip.csr 75553 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_B_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_B_SET ns_noc_io_spio_soc_ip.csr 75564 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_C_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_C_SET ns_noc_io_spio_soc_ip.csr 75575 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_D_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L1_D_SET ns_noc_io_spio_soc_ip.csr 75586 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_A_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_A_SET ns_noc_io_spio_soc_ip.csr 75597 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_B_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_B_SET ns_noc_io_spio_soc_ip.csr 75608 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_C_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_C_SET ns_noc_io_spio_soc_ip.csr 75619 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_D_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L2_D_SET ns_noc_io_spio_soc_ip.csr 75630 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_A_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_A_SET ns_noc_io_spio_soc_ip.csr 75641 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_B_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_B_SET ns_noc_io_spio_soc_ip.csr 75652 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_C_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_C_SET ns_noc_io_spio_soc_ip.csr 75663 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_D_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L3_D_SET ns_noc_io_spio_soc_ip.csr 75674 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_A_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_A_SET ns_noc_io_spio_soc_ip.csr 75685 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_B_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_B_SET ns_noc_io_spio_soc_ip.csr 75696 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_C_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_C_SET ns_noc_io_spio_soc_ip.csr 75707 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_D_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L4_D_SET ns_noc_io_spio_soc_ip.csr 75718 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_A_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_A_SET ns_noc_io_spio_soc_ip.csr 75729 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_B_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_B_SET ns_noc_io_spio_soc_ip.csr 75740 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_C_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_C_SET ns_noc_io_spio_soc_ip.csr 75751 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_D_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L5_D_SET ns_noc_io_spio_soc_ip.csr 75762 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_A_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_A_SET ns_noc_io_spio_soc_ip.csr 75773 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_B_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_B_SET ns_noc_io_spio_soc_ip.csr 75784 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_C_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_C_SET ns_noc_io_spio_soc_ip.csr 75795 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_D_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L6_D_SET ns_noc_io_spio_soc_ip.csr 75806 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_A_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_A_SET ns_noc_io_spio_soc_ip.csr 75817 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_B_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_B_SET ns_noc_io_spio_soc_ip.csr 75828 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_C_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_C_SET ns_noc_io_spio_soc_ip.csr 75839 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_D_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_0_L7_D_SET ns_noc_io_spio_soc_ip.csr 75850 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register spio_noc.bridge_spio_p00_rot_m_2_7_btus_1 bridge_spio_p00_rot_m_2_7_btus_1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 76219 spio_p00_rot_m register btus_1 0x1B060 R 0x00000000 Spio_noc_bridge_spio_p00_rot_m_2_7_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_A_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_A_SET ns_noc_io_spio_soc_ip.csr 75877 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_B_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_B_SET ns_noc_io_spio_soc_ip.csr 75888 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_C_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_C_SET ns_noc_io_spio_soc_ip.csr 75899 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_D_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L8_D_SET ns_noc_io_spio_soc_ip.csr 75910 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_A_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_A_SET ns_noc_io_spio_soc_ip.csr 75921 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_B_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_B_SET ns_noc_io_spio_soc_ip.csr 75932 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_C_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_C_SET ns_noc_io_spio_soc_ip.csr 75943 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_D_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L9_D_SET ns_noc_io_spio_soc_ip.csr 75954 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_A_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_A_SET ns_noc_io_spio_soc_ip.csr 75965 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_B_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_B_SET ns_noc_io_spio_soc_ip.csr 75976 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_C_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_C_SET ns_noc_io_spio_soc_ip.csr 75987 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_D_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L10_D_SET ns_noc_io_spio_soc_ip.csr 75998 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_A_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_A_SET ns_noc_io_spio_soc_ip.csr 76009 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_B_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_B_SET ns_noc_io_spio_soc_ip.csr 76020 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_C_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_C_SET ns_noc_io_spio_soc_ip.csr 76031 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_D_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L11_D_SET ns_noc_io_spio_soc_ip.csr 76042 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_A_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_A_SET ns_noc_io_spio_soc_ip.csr 76053 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_B_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_B_SET ns_noc_io_spio_soc_ip.csr 76064 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_C_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_C_SET ns_noc_io_spio_soc_ip.csr 76075 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_D_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L12_D_SET ns_noc_io_spio_soc_ip.csr 76086 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_A_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_A_SET ns_noc_io_spio_soc_ip.csr 76097 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_B_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_B_SET ns_noc_io_spio_soc_ip.csr 76108 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_C_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_C_SET ns_noc_io_spio_soc_ip.csr 76119 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_D_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L13_D_SET ns_noc_io_spio_soc_ip.csr 76130 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_A_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_A_SET ns_noc_io_spio_soc_ip.csr 76141 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_B_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_B_SET ns_noc_io_spio_soc_ip.csr 76152 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_C_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_C_SET ns_noc_io_spio_soc_ip.csr 76163 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_D_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L14_D_SET ns_noc_io_spio_soc_ip.csr 76174 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_A_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_A_SET ns_noc_io_spio_soc_ip.csr 76185 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_B_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_B_SET ns_noc_io_spio_soc_ip.csr 76196 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_C_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_C_SET ns_noc_io_spio_soc_ip.csr 76207 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_D_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTUS_1_L15_D_SET ns_noc_io_spio_soc_ip.csr 76218 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register spio_noc.bridge_spio_p00_rot_m_2_7_btrl_0 bridge_spio_p00_rot_m_2_7_btrl_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 76295 spio_p00_rot_m register btrl_0 0x1B080 R 0x00000000 Spio_noc_bridge_spio_p00_rot_m_2_7_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_WT_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_WT_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_WT_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_WT_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_WT_SET ns_noc_io_spio_soc_ip.csr 76243 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 76254 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_CNT_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_CNT_SET ns_noc_io_spio_soc_ip.csr 76269 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_EN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_EN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_EN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_EN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_EN_SET ns_noc_io_spio_soc_ip.csr 76283 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_0_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 76294 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p00_rot_m_2_7_btrl_1 bridge_spio_p00_rot_m_2_7_btrl_1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 76371 spio_p00_rot_m register btrl_1 0x1B088 R 0x00000000 Spio_noc_bridge_spio_p00_rot_m_2_7_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_WT_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_WT_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_WT_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_WT_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_WT_SET ns_noc_io_spio_soc_ip.csr 76319 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 76330 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_CNT_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_CNT_SET ns_noc_io_spio_soc_ip.csr 76345 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_EN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_EN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_EN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_EN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_EN_SET ns_noc_io_spio_soc_ip.csr 76359 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_1_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 76370 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p00_rot_m_2_7_btrl_2 bridge_spio_p00_rot_m_2_7_btrl_2 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 76447 spio_p00_rot_m register btrl_2 0x1B090 R 0x00000000 Spio_noc_bridge_spio_p00_rot_m_2_7_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_WT_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_WT_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_WT_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_WT_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_WT_SET ns_noc_io_spio_soc_ip.csr 76395 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 76406 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_CNT_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_CNT_SET ns_noc_io_spio_soc_ip.csr 76421 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_EN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_EN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_EN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_EN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_EN_SET ns_noc_io_spio_soc_ip.csr 76435 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_2_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 76446 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p00_rot_m_2_7_btrl_3 bridge_spio_p00_rot_m_2_7_btrl_3 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 76523 spio_p00_rot_m register btrl_3 0x1B098 R 0x00000000 Spio_noc_bridge_spio_p00_rot_m_2_7_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_WT_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_WT_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_WT_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_WT_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_WT_SET ns_noc_io_spio_soc_ip.csr 76471 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 76482 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_CNT_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_CNT_SET ns_noc_io_spio_soc_ip.csr 76497 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_EN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_EN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_EN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_EN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_EN_SET ns_noc_io_spio_soc_ip.csr 76511 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTRL_3_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 76522 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p00_rot_m_2_7_btperr bridge_spio_p00_rot_m_2_7_btperr SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 76725 spio_p00_rot_m register btperr 0x1B0A8 R/W 0x00000000 Spio_noc_bridge_spio_p00_rot_m_2_7_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L0_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L0_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L0_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L0_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L0_SET ns_noc_io_spio_soc_ip.csr 76548 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L1_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L1_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L1_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L1_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L1_SET ns_noc_io_spio_soc_ip.csr 76559 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L2_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L2_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L2_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L2_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L2_SET ns_noc_io_spio_soc_ip.csr 76570 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L3_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L3_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L3_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L3_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L3_SET ns_noc_io_spio_soc_ip.csr 76581 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L4_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L4_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L4_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L4_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L4_SET ns_noc_io_spio_soc_ip.csr 76592 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L5_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L5_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L5_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L5_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L5_SET ns_noc_io_spio_soc_ip.csr 76603 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L6_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L6_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L6_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L6_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L6_SET ns_noc_io_spio_soc_ip.csr 76614 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L7_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L7_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L7_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L7_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L7_SET ns_noc_io_spio_soc_ip.csr 76625 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L8_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L8_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L8_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L8_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L8_SET ns_noc_io_spio_soc_ip.csr 76636 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L9_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L9_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L9_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L9_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L9_SET ns_noc_io_spio_soc_ip.csr 76647 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L10_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L10_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L10_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L10_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L10_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L10_SET ns_noc_io_spio_soc_ip.csr 76658 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L11_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L11_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L11_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L11_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L11_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L11_SET ns_noc_io_spio_soc_ip.csr 76669 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L12_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L12_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L12_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L12_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L12_SET ns_noc_io_spio_soc_ip.csr 76680 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L13_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L13_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L13_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L13_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L13_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L13_SET ns_noc_io_spio_soc_ip.csr 76691 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L14_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L14_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L14_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L14_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L14_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L14_SET ns_noc_io_spio_soc_ip.csr 76702 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L15_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L15_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L15_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L15_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L15_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_L15_SET ns_noc_io_spio_soc_ip.csr 76713 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_UNSD_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERR_UNSD_SET ns_noc_io_spio_soc_ip.csr 76724 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_p00_rot_m_2_7_btperrm bridge_spio_p00_rot_m_2_7_btperrm SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 76925 spio_p00_rot_m register btperrm 0x1B0B0 R/W 0x00000000 Spio_noc_bridge_spio_p00_rot_m_2_7_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L0_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L0_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L0_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L0_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L0_SET ns_noc_io_spio_soc_ip.csr 76748 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L1_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L1_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L1_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L1_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L1_SET ns_noc_io_spio_soc_ip.csr 76759 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L2_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L2_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L2_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L2_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L2_SET ns_noc_io_spio_soc_ip.csr 76770 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L3_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L3_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L3_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L3_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L3_SET ns_noc_io_spio_soc_ip.csr 76781 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L4_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L4_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L4_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L4_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L4_SET ns_noc_io_spio_soc_ip.csr 76792 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L5_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L5_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L5_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L5_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L5_SET ns_noc_io_spio_soc_ip.csr 76803 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L6_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L6_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L6_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L6_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L6_SET ns_noc_io_spio_soc_ip.csr 76814 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L7_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L7_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L7_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L7_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L7_SET ns_noc_io_spio_soc_ip.csr 76825 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L8_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L8_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L8_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L8_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L8_SET ns_noc_io_spio_soc_ip.csr 76836 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L9_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L9_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L9_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L9_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L9_SET ns_noc_io_spio_soc_ip.csr 76847 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L10_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L10_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L10_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L10_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L10_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L10_SET ns_noc_io_spio_soc_ip.csr 76858 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L11_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L11_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L11_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L11_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L11_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L11_SET ns_noc_io_spio_soc_ip.csr 76869 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L12_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L12_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L12_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L12_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L12_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L12_SET ns_noc_io_spio_soc_ip.csr 76880 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L13_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L13_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L13_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L13_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L13_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L13_SET ns_noc_io_spio_soc_ip.csr 76891 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L14_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L14_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L14_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L14_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L14_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L14_SET ns_noc_io_spio_soc_ip.csr 76902 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L15_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L15_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L15_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L15_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L15_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_L15_SET ns_noc_io_spio_soc_ip.csr 76913 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_UNSD_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BTPERRM_UNSD_SET ns_noc_io_spio_soc_ip.csr 76924 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_p00_rot_m_2_7_rxe bridge_spio_p00_rot_m_2_7_rxe SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 77033 spio_p00_rot_m register rxe 0x1B120 R/W 0x00000000 Spio_noc_bridge_spio_p00_rot_m_2_7_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_A_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_A_SET ns_noc_io_spio_soc_ip.csr 76953 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_B_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_B_SET ns_noc_io_spio_soc_ip.csr 76964 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_C_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_C_SET ns_noc_io_spio_soc_ip.csr 76975 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_D_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_CRC_OFLW_D_SET ns_noc_io_spio_soc_ip.csr 76986 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_EVC_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_EVC_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_EVC_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_EVC_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_EVC_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_EVC_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_EVC_OFLW_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_EVC_OFLW_SET ns_noc_io_spio_soc_ip.csr 76998 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 77009 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_EVC1_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_EVC1_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_EVC1_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_EVC1_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_EVC1_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_EVC1_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_EVC1_OFLW_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_EVC1_OFLW_SET ns_noc_io_spio_soc_ip.csr 77021 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXE_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 77032 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_rxem bridge_spio_p00_rot_m_2_7_rxem SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 77105 spio_p00_rot_m register rxem 0x1B128 R/W 0x00000050 Spio_noc_bridge_spio_p00_rot_m_2_7_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_UNSD_3_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_UNSD_3_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_UNSD_3_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_UNSD_3_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_UNSD_3_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_UNSD_3_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_UNSD_3_0_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_UNSD_3_0_SET ns_noc_io_spio_soc_ip.csr 77054 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_EVC_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_EVC_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_EVC_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_EVC_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_EVC_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_EVC_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_EVC_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_EVC_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 77068 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 77079 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_EVC1_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_EVC1_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_EVC1_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_EVC1_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_EVC1_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_EVC1_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_EVC1_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 77093 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_RXEM_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 77104 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_brs_0 bridge_spio_p00_rot_m_2_7_brs_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 77379 spio_p00_rot_m register brs_0 0x1B130 R 0x00000000 Spio_noc_bridge_spio_p00_rot_m_2_7_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 77129 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_0_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_0_SET ns_noc_io_spio_soc_ip.csr 77140 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_0_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_0_SET ns_noc_io_spio_soc_ip.csr 77151 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_0_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_0_SET ns_noc_io_spio_soc_ip.csr 77162 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_0_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_0_SET ns_noc_io_spio_soc_ip.csr 77173 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 77183 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 77194 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_1_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_1_SET ns_noc_io_spio_soc_ip.csr 77205 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_1_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_1_SET ns_noc_io_spio_soc_ip.csr 77216 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_1_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_1_SET ns_noc_io_spio_soc_ip.csr 77227 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_1_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_1_SET ns_noc_io_spio_soc_ip.csr 77238 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 77248 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 77259 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_2_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_2_SET ns_noc_io_spio_soc_ip.csr 77270 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_2_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_2_SET ns_noc_io_spio_soc_ip.csr 77281 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_2_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_2_SET ns_noc_io_spio_soc_ip.csr 77292 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_2_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_2_SET ns_noc_io_spio_soc_ip.csr 77303 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 77313 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 77324 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_3_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_V_3_SET ns_noc_io_spio_soc_ip.csr 77335 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_3_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_S_3_SET ns_noc_io_spio_soc_ip.csr 77346 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_3_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_B_3_SET ns_noc_io_spio_soc_ip.csr 77357 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_3_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_F_3_SET ns_noc_io_spio_soc_ip.csr 77368 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_0_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 77378 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_p00_rot_m_2_7_brs_1 bridge_spio_p00_rot_m_2_7_brs_1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 77653 spio_p00_rot_m register brs_1 0x1B138 R 0x00000000 Spio_noc_bridge_spio_p00_rot_m_2_7_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 77403 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_0_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_0_SET ns_noc_io_spio_soc_ip.csr 77414 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_0_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_0_SET ns_noc_io_spio_soc_ip.csr 77425 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_0_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_0_SET ns_noc_io_spio_soc_ip.csr 77436 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_0_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_0_SET ns_noc_io_spio_soc_ip.csr 77447 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 77457 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 77468 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_1_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_1_SET ns_noc_io_spio_soc_ip.csr 77479 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_1_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_1_SET ns_noc_io_spio_soc_ip.csr 77490 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_1_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_1_SET ns_noc_io_spio_soc_ip.csr 77501 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_1_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_1_SET ns_noc_io_spio_soc_ip.csr 77512 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 77522 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 77533 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_2_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_2_SET ns_noc_io_spio_soc_ip.csr 77544 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_2_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_2_SET ns_noc_io_spio_soc_ip.csr 77555 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_2_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_2_SET ns_noc_io_spio_soc_ip.csr 77566 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_2_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_2_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_2_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_2_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_2_SET ns_noc_io_spio_soc_ip.csr 77577 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 77587 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 77598 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_3_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_V_3_SET ns_noc_io_spio_soc_ip.csr 77609 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_3_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_S_3_SET ns_noc_io_spio_soc_ip.csr 77620 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_3_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_B_3_SET ns_noc_io_spio_soc_ip.csr 77631 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_3_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_3_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_3_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_3_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_F_3_SET ns_noc_io_spio_soc_ip.csr 77642 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRS_1_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 77652 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_p00_rot_m_2_7_brus bridge_spio_p00_rot_m_2_7_brus SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 77722 spio_p00_rot_m register brus 0x1B1B0 R 0x00000000 Spio_noc_bridge_spio_p00_rot_m_2_7_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_A_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_A_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_A_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_A_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_A_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_A_SET ns_noc_io_spio_soc_ip.csr 77678 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_B_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_B_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_B_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_B_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_B_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_B_SET ns_noc_io_spio_soc_ip.csr 77689 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_C_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_C_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_C_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_C_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_C_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_C_SET ns_noc_io_spio_soc_ip.csr 77700 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_D_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_D_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_D_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_D_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_D_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_V_D_SET ns_noc_io_spio_soc_ip.csr 77711 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_UNSD_31_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_UNSD_31_4_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_UNSD_31_4_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_UNSD_31_4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_UNSD_31_4_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_UNSD_31_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_UNSD_31_4_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRUS_UNSD_31_4_SET ns_noc_io_spio_soc_ip.csr 77721 UNSD_31_4 31 4 0x0000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_brperr0 bridge_spio_p00_rot_m_2_7_brperr0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 77950 spio_p00_rot_m register brperr0 0x1B1D0 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_rot_m_2_7_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_D0_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_D0_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_D0_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_D0_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_D0_SET ns_noc_io_spio_soc_ip.csr 77760 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_DC0_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_DC0_SET ns_noc_io_spio_soc_ip.csr 77771 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SB0_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SB0_SET ns_noc_io_spio_soc_ip.csr 77782 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SBC0_SET ns_noc_io_spio_soc_ip.csr 77794 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_PK0_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_PK0_SET ns_noc_io_spio_soc_ip.csr 77805 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 77816 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_D1_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_D1_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_D1_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_D1_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_D1_SET ns_noc_io_spio_soc_ip.csr 77827 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_DC1_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_DC1_SET ns_noc_io_spio_soc_ip.csr 77838 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SB1_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SB1_SET ns_noc_io_spio_soc_ip.csr 77849 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_SBC1_SET ns_noc_io_spio_soc_ip.csr 77861 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_PK1_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_PK1_SET ns_noc_io_spio_soc_ip.csr 77872 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 77883 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 77894 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 77905 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 77916 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 77927 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 77938 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 77949 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p00_rot_m_2_7_brperr1 bridge_spio_p00_rot_m_2_7_brperr1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 78066 spio_p00_rot_m register brperr1 0x1B1D8 R 0x0000000000000000 Spio_noc_bridge_spio_p00_rot_m_2_7_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 77988 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 77999 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 78010 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 78021 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 78032 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 78043 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 78054 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERR1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 78065 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p00_rot_m_2_7_brperrm0 bridge_spio_p00_rot_m_2_7_brperrm0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 78287 spio_p00_rot_m register brperrm0 0x1B1E0 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_rot_m_2_7_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_D0_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_D0_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_D0_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_D0_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_D0_SET ns_noc_io_spio_soc_ip.csr 78093 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_DC0_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_DC0_SET ns_noc_io_spio_soc_ip.csr 78105 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SB0_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SB0_SET ns_noc_io_spio_soc_ip.csr 78116 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SBC0_SET ns_noc_io_spio_soc_ip.csr 78128 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_PK0_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_PK0_SET ns_noc_io_spio_soc_ip.csr 78140 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 78151 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_D1_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_D1_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_D1_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_D1_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_D1_SET ns_noc_io_spio_soc_ip.csr 78162 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_DC1_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_DC1_SET ns_noc_io_spio_soc_ip.csr 78174 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SB1_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SB1_SET ns_noc_io_spio_soc_ip.csr 78185 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_SBC1_SET ns_noc_io_spio_soc_ip.csr 78197 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_PK1_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_PK1_SET ns_noc_io_spio_soc_ip.csr 78209 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 78220 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 78231 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 78242 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 78253 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 78264 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 78275 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 78286 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p00_rot_m_2_7_brperrm1 bridge_spio_p00_rot_m_2_7_brperrm1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 78392 spio_p00_rot_m register brperrm1 0x1B1E8 R 0x0000000000000000 Spio_noc_bridge_spio_p00_rot_m_2_7_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 78314 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 78325 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 78336 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 78347 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 78358 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 78369 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 78380 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_BRPERRM1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 78391 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_tocfg bridge_spio_p00_rot_m_2_7_am_tocfg SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 78466 spio_p00_rot_m register am_tocfg 0x1BC00 R/W 0x000000000000001f Spio_noc_bridge_spio_p00_rot_m_2_7_am_tocfg This register is used to configure response timeouts. AM_TOCFG[8] (En) needs to be set for timeout tracking to be enabled. When this bit is 1'b0, no timestamps are recorded to generate timeout interrupts. A 64-bit free running counter is used to time the response interval. AM_TOCFG[5:0] (TI) specifies the lower bit index into this counter, from where 2-bits are picked up and recorded as the arrival time stamp of every incoming AR and AW command. If response for a command does not return before the current time stamp rolls to arrival time stamp minus 1, the response is assumed to have timedout and an interrupt is raised along with the slave ID to which the timed out request was sent. When changing the TI field, first write to the register with the En field cleared, then write a second time with the TI field to its new value, then a 3rd write to restore the En field to Enabled. During this update while the En field is cleared, existing timers will cancelled, and new timer starts will be inhibited. false false false false TI SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_TI_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_TI_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_TI_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_TI_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_TI_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_TI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_TI_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_TI_SET ns_noc_io_spio_soc_ip.csr 78429 TI Timer index, index of a 64-bit counter from where timestamp is picked. The register value has to be 'd62 or smaller. 5 0 0x1f R/W UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 78440 UNSD_7_6 7 6 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_EN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_EN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_EN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_EN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_EN_SET ns_noc_io_spio_soc_ip.csr 78454 EN 1'b1: Enabled timeout tracking, a 64-bit free running counter is used to time the response interval. 1'b0: No timestamps are recorded to generate timeout interrupts 8 8 0x0 R/W UNSD_63_9 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_UNSD_63_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_UNSD_63_9_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_UNSD_63_9_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_UNSD_63_9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_UNSD_63_9_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_UNSD_63_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_UNSD_63_9_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOCFG_UNSD_63_9_SET ns_noc_io_spio_soc_ip.csr 78465 UNSD_63_9 63 9 0x00000000000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_osslv bridge_spio_p00_rot_m_2_7_am_osslv SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_OSSLV_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_OSSLV_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_OSSLV_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_OSSLV_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 78501 spio_p00_rot_m register am_osslv 0x1BC08 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_osslv This register is used to check if there are any outstanding read/write commands to a slave specified by field slvid. NocStudio provides a table of slvids corresponding to the slave ports accessible from a master bridge. Outstanding status is reflected in AM_STS. false false false false SLVID SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_OSSLV_SLVID_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_OSSLV_SLVID_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_OSSLV_SLVID_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_OSSLV_SLVID_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_OSSLV_SLVID_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_OSSLV_SLVID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_OSSLV_SLVID_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_OSSLV_SLVID_SET ns_noc_io_spio_soc_ip.csr 78489 SLVID A slave ID associated with the current master for command outstanding status 15 0 0x0000 R/W UNSD_63_16 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_OSSLV_UNSD_63_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_OSSLV_UNSD_63_16_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_OSSLV_UNSD_63_16_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_OSSLV_UNSD_63_16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_OSSLV_UNSD_63_16_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_OSSLV_UNSD_63_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_OSSLV_UNSD_63_16_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_OSSLV_UNSD_63_16_SET ns_noc_io_spio_soc_ip.csr 78500 UNSD_63_16 63 16 0x000000000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_cgc bridge_spio_p00_rot_m_2_7_am_cgc SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGC_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGC_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGC_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 78538 spio_p00_rot_m register am_cgc 0x1BC10 R/W 0x0000000000000064 Spio_noc_bridge_spio_p00_rot_m_2_7_am_cgc Programmable interval used by coarse clock gating logic in master bridge.This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGC_HYSTERESIS_COUNTER_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGC_HYSTERESIS_COUNTER_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGC_HYSTERESIS_COUNTER_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGC_HYSTERESIS_COUNTER_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGC_HYSTERESIS_COUNTER_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGC_HYSTERESIS_COUNTER_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGC_HYSTERESIS_COUNTER_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_spio_soc_ip.csr 78526 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGC_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGC_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGC_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGC_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGC_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGC_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGC_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGC_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 78537 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_cgo bridge_spio_p00_rot_m_2_7_am_cgo SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGO_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGO_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGO_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGO_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 78573 spio_p00_rot_m register am_cgo 0x1BC18 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the master bridge. false false false false FPO SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGO_FPO_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGO_FPO_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGO_FPO_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGO_FPO_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGO_FPO_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGO_FPO_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGO_FPO_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGO_FPO_SET ns_noc_io_spio_soc_ip.csr 78561 FPO 1'b1: Clock gating override is enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGO_UNSD_63_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGO_UNSD_63_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGO_UNSD_63_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGO_UNSD_63_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGO_UNSD_63_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGO_UNSD_63_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGO_UNSD_63_1_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CGO_UNSD_63_1_SET ns_noc_io_spio_soc_ip.csr 78572 UNSD_63_1 63 1 0x0000000000000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_cfg bridge_spio_p00_rot_m_2_7_am_cfg SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CFG_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CFG_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CFG_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CFG_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 78610 spio_p00_rot_m register am_cfg 0x1BC20 R/W 0x0000000000000001 Spio_noc_bridge_spio_p00_rot_m_2_7_am_cfg Configures the master bridge's support for autowake of power domains. When set, master bridge halts a request and issues wakeup requests for power domains that need to powered up to complete the transaction. The power domains should support auto wake. When reset, master bridge issues DECERR for any transaction which has dependent power domains in sleep state. false false false false AW SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CFG_AW_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CFG_AW_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CFG_AW_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CFG_AW_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CFG_AW_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CFG_AW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CFG_AW_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CFG_AW_SET ns_noc_io_spio_soc_ip.csr 78598 AW 1'b1: Autowake enabled 1'b0: Autowake disabled 0 0 0x1 R/W UNSD_63_1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CFG_UNSD_63_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CFG_UNSD_63_1_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CFG_UNSD_63_1_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CFG_UNSD_63_1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CFG_UNSD_63_1_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CFG_UNSD_63_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CFG_UNSD_63_1_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CFG_UNSD_63_1_SET ns_noc_io_spio_soc_ip.csr 78609 UNSD_63_1 63 1 0x0000000000000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_sts bridge_spio_p00_rot_m_2_7_am_sts SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 78738 spio_p00_rot_m register am_sts 0x1BD00 R 0x000000000000000c Spio_noc_bridge_spio_p00_rot_m_2_7_am_sts When reordering is disabled on the master bridge, hazard stall occurs if the master tries to access a new slave device while response from a different slave is outstanding on the same AID. This is because the responses can arrive out of order and the bridge is not equipped to correct the order. Without re-order buffers, hazard stalls also occur if a new large command needs to be split while there are older commands outstanding, or a large command just finished sending all its split segments but all responses have not returned yet. When reordering is enabled, stall due to hazard occurs if a new command arrives, whose NoC QoS is different from the NoC QoS of commands outstanding on that AID. false false false false ROF SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ROF_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ROF_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ROF_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ROF_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ROF_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ROF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ROF_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ROF_SET ns_noc_io_spio_soc_ip.csr 78643 ROF 1'b1: Maximum supported number of read commands are outstanding waiting for response and no more requests can be accepted 1'b0: Master bridge can accept more read requests 0 0 0x0 R WOF SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_WOF_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_WOF_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_WOF_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_WOF_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_WOF_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_WOF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_WOF_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_WOF_SET ns_noc_io_spio_soc_ip.csr 78657 WOF 1'b1: Maximum supported number of write commands are outstanding waiting for response and no more requests can be accepted 1'b0: Master bridge can accept more write requests 1 1 0x0 R ROE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ROE_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ROE_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ROE_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ROE_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ROE_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ROE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ROE_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ROE_SET ns_noc_io_spio_soc_ip.csr 78669 ROE 1'b1: There are no read commands outstanding from the attached master device 2 2 0x1 R WOE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_WOE_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_WOE_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_WOE_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_WOE_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_WOE_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_WOE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_WOE_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_WOE_SET ns_noc_io_spio_soc_ip.csr 78681 WOE 1'b1: There are no write commands outstanding from the attached master device 3 3 0x1 R ARS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ARS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ARS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ARS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ARS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ARS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ARS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ARS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ARS_SET ns_noc_io_spio_soc_ip.csr 78692 ARS 1'b1: AR channel is stalled on hazard 4 4 0x0 R AWS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_AWS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_AWS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_AWS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_AWS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_AWS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_AWS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_AWS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_AWS_SET ns_noc_io_spio_soc_ip.csr 78703 AWS 1'b1: AW channel is stalled on hazard 5 5 0x0 R ARO SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ARO_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ARO_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ARO_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ARO_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ARO_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ARO_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ARO_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_ARO_SET ns_noc_io_spio_soc_ip.csr 78715 ARO 1'b1: Read commands are outstanding to the slave specified in OSSLV register 6 6 0x0 R AWO SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_AWO_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_AWO_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_AWO_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_AWO_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_AWO_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_AWO_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_AWO_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_AWO_SET ns_noc_io_spio_soc_ip.csr 78727 AWO 1'b1: Write commands are outstanding to the slave specified in OSSLV register 7 7 0x0 R UNSD_63_8 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_UNSD_63_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_UNSD_63_8_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_UNSD_63_8_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_UNSD_63_8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_UNSD_63_8_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_UNSD_63_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_UNSD_63_8_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_STS_UNSD_63_8_SET ns_noc_io_spio_soc_ip.csr 78737 UNSD_63_8 63 8 0x00000000000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_bridge_id bridge_spio_p00_rot_m_2_7_am_bridge_id SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_BRIDGE_ID_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_BRIDGE_ID_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_BRIDGE_ID_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_BRIDGE_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 78768 spio_p00_rot_m register am_bridge_id 0x1BD08 R 0x0000000000000002 Spio_noc_bridge_spio_p00_rot_m_2_7_am_bridge_id Unique identifier assigned to the master bridge. false false false false ID SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_BRIDGE_ID_ID_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_BRIDGE_ID_ID_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_BRIDGE_ID_ID_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_BRIDGE_ID_ID_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_BRIDGE_ID_ID_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_BRIDGE_ID_ID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_BRIDGE_ID_ID_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_BRIDGE_ID_ID_SET ns_noc_io_spio_soc_ip.csr 78757 ID Unique bridge ID 15 0 0x0002 R UNSD_63_16 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_BRIDGE_ID_UNSD_63_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_BRIDGE_ID_UNSD_63_16_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_BRIDGE_ID_UNSD_63_16_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_BRIDGE_ID_UNSD_63_16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_BRIDGE_ID_UNSD_63_16_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_BRIDGE_ID_UNSD_63_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_BRIDGE_ID_UNSD_63_16_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_spio_soc_ip.csr 78767 UNSD_63_16 63 16 0x000000000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_err bridge_spio_p00_rot_m_2_7_am_err SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 79264 spio_p00_rot_m register am_err 0x1BE00 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E0_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E0_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E0_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E0_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E0_SET ns_noc_io_spio_soc_ip.csr 78790 E0 1'b1: Local read address decode error: ARADDR did not find a match in the master bridges address table and a decode error was issued 0 0 0x0 R/W E1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E1_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E1_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E1_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E1_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E1_SET ns_noc_io_spio_soc_ip.csr 78802 E1 1'b1: Read address decode error from slave: A decode error response was received from a slave device 1 1 0x0 R/W E2 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E2_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E2_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E2_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E2_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E2_SET ns_noc_io_spio_soc_ip.csr 78814 E2 1'b1: Read slave error: A slave error response was received from a slave device 2 2 0x0 R/W E3 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E3_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E3_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E3_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E3_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E3_SET ns_noc_io_spio_soc_ip.csr 78826 E3 1'b1: Non modifiable WRAP: A WRAP command marked as non-modifiable (ARCACHE[0]=0) was detected 3 3 0x0 R/W E4 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E4_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E4_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E4_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E4_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E4_SET ns_noc_io_spio_soc_ip.csr 78838 E4 1'b1: [FATAL] Read exclusive split: An AR command of FIXED burst type was detected 4 4 0x0 R/W E5 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E5_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E5_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E5_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E5_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E5_SET ns_noc_io_spio_soc_ip.csr 78850 E5 1'b1: [FATAL] Read address multi-hit: An AR command matched against multiple entries in the address table 5 5 0x0 R/W E6 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E6_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E6_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E6_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E6_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E6_SET ns_noc_io_spio_soc_ip.csr 78863 E6 1'b1: Read response timeout: Read response timeout occurred. With timeout enabled, a response wasn't received within the expected interval 6 6 0x0 R/W E7 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E7_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E7_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E7_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E7_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E7_SET ns_noc_io_spio_soc_ip.csr 78876 E7 1'b1: [FATAL] Read WRAP not equal to supported cacheline size: A WRAP command of unupported cache line size was detected 7 7 0x0 R/W E8 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E8_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E8_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E8_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E8_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E8_SET ns_noc_io_spio_soc_ip.csr 78887 E8 1'b1: [FATAL] Unexpected narrow read detected 8 8 0x0 R/W UNSD_15_9 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_15_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_15_9_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_15_9_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_15_9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_15_9_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_15_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_15_9_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_15_9_SET ns_noc_io_spio_soc_ip.csr 78898 UNSD_15_9 15 9 0x00 R E16 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E16_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E16_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E16_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E16_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E16_SET ns_noc_io_spio_soc_ip.csr 78909 E16 1'b1: Local write address decode error 16 16 0x0 R/W E17 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E17_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E17_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E17_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E17_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E17_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E17_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E17_SET ns_noc_io_spio_soc_ip.csr 78920 E17 1'b1: Write address decode error from slave 17 17 0x0 R/W E18 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E18_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E18_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E18_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E18_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E18_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E18_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E18_SET ns_noc_io_spio_soc_ip.csr 78931 E18 1'b1: Write slave error 18 18 0x0 R/W E19 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E19_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E19_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E19_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E19_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E19_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E19_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E19_SET ns_noc_io_spio_soc_ip.csr 78942 E19 1'b1: Non modifiable WRAP 19 19 0x0 R/W E20 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E20_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E20_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E20_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E20_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E20_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E20_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E20_SET ns_noc_io_spio_soc_ip.csr 78953 E20 1'b1: [FATAL] Write exclusive split 20 20 0x0 R/W E21 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E21_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E21_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E21_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E21_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E21_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E21_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E21_SET ns_noc_io_spio_soc_ip.csr 78964 E21 1'b1: [FATAL] Write address multi-hit 21 21 0x0 R/W E22 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E22_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E22_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E22_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E22_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E22_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E22_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E22_SET ns_noc_io_spio_soc_ip.csr 78975 E22 1'b1: Write respone timeout 22 22 0x0 R/W E23 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E23_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E23_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E23_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E23_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E23_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E23_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E23_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E23_SET ns_noc_io_spio_soc_ip.csr 78987 E23 1'b1: [FATAL] Write WRAP not equal to supported cacheline size 23 23 0x0 R/W E24 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E24_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E24_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E24_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E24_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E24_SET ns_noc_io_spio_soc_ip.csr 78998 E24 1'b1: [FATAL] Unexpected narrow write detected 24 24 0x0 R/W UNSD_31_25 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_31_25_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_31_25_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_31_25_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_31_25_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_31_25_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_31_25_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_31_25_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_31_25_SET ns_noc_io_spio_soc_ip.csr 79009 UNSD_31_25 31 25 0x00 R E32 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E32_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E32_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E32_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E32_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E32_SET ns_noc_io_spio_soc_ip.csr 79020 E32 1'b1: Capture counter0 overflow 32 32 0x0 R/W E33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E33_SET ns_noc_io_spio_soc_ip.csr 79031 E33 1'b1: Capture counter1 overflow 33 33 0x0 R/W E34 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E34_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E34_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E34_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E34_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E34_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E34_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E34_SET ns_noc_io_spio_soc_ip.csr 79043 E34 1'b1: [FATAL] Traffic sent to a noc layer which is power gate 34 34 0x0 R/W E35 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E35_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E35_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E35_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E35_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E35_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E35_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E35_SET ns_noc_io_spio_soc_ip.csr 79055 E35 1'b1: [FATAL] Parity error in configuration/status registers 35 35 0x0 R/W UNSD_39_36 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_39_36_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_39_36_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_39_36_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_39_36_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_39_36_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_39_36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_39_36_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_39_36_SET ns_noc_io_spio_soc_ip.csr 79066 UNSD_39_36 39 36 0x0 R E40 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E40_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E40_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E40_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E40_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E40_SET ns_noc_io_spio_soc_ip.csr 79078 E40 1'b1: [FATAL] Indicates that portcheck detected error (SIB mode only) 40 40 0x0 R/W E41 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E41_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E41_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E41_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E41_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E41_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E41_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E41_SET ns_noc_io_spio_soc_ip.csr 79089 E41 1'b1: [FATAL] AR Parity Err 41 41 0x0 R/W E42 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E42_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E42_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E42_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E42_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E42_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E42_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E42_SET ns_noc_io_spio_soc_ip.csr 79100 E42 1'b1: [FATAL] ARADDR Parity Err 42 42 0x0 R/W E43 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E43_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E43_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E43_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E43_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E43_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E43_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E43_SET ns_noc_io_spio_soc_ip.csr 79111 E43 1'b1: [FATAL] AW Parity Err 43 43 0x0 R/W E44 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E44_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E44_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E44_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E44_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E44_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E44_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E44_SET ns_noc_io_spio_soc_ip.csr 79122 E44 1'b1: [FATAL] AWADDR Parity Err 44 44 0x0 R/W E45 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E45_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E45_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E45_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E45_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E45_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E45_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E45_SET ns_noc_io_spio_soc_ip.csr 79133 E45 1'b1: [FATAL] WDATA Parity Err 45 45 0x0 R/W E46 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E46_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E46_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E46_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E46_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E46_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E46_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E46_SET ns_noc_io_spio_soc_ip.csr 79144 E46 1'b1: [FATAL] CDDATA Parity Err 46 46 0x0 R/W E47 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E47_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E47_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E47_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E47_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E47_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E47_SET ns_noc_io_spio_soc_ip.csr 79156 E47 1'b1: [FATAL] Ridtbl Entry Parity Err 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E48_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E48_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E48_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E48_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E48_SET ns_noc_io_spio_soc_ip.csr 79168 E48 1'b1: [FATAL] Widtbl Entry Parity Err 48 48 0x0 R E49 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E49_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E49_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E49_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E49_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E49_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E49_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E49_SET ns_noc_io_spio_soc_ip.csr 79180 E49 1'b1: [FATAL] Read Reorder Buffer Parity Err 49 49 0x0 R E50 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E50_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E50_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E50_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E50_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E50_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E50_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E50_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E50_SET ns_noc_io_spio_soc_ip.csr 79192 E50 1'b1: [FATAL] Write Reorder Buffer Parity Err 50 50 0x0 R E51 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E51_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E51_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E51_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E51_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E51_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E51_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E51_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E51_SET ns_noc_io_spio_soc_ip.csr 79204 E51 1'b1: [FATAL] Rx Fifo Parity Err 51 51 0x0 R E52 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E52_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E52_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E52_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E52_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E52_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E52_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E52_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E52_SET ns_noc_io_spio_soc_ip.csr 79216 E52 1'b1: [FATAL] Ack Channel Wack Fifo Parity Error 52 52 0x0 R E53 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E53_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E53_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E53_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E53_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E53_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E53_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E53_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E53_SET ns_noc_io_spio_soc_ip.csr 79228 E53 1'b1: [FATAL] Ack Channel Rack Fifo Parity Error 53 53 0x0 R E54 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E54_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E54_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E54_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E54_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E54_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E54_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E54_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E54_SET ns_noc_io_spio_soc_ip.csr 79240 E54 1'b1: [FATAL] CRCD Channel Crid Fifo Parity Error 54 54 0x0 R E55 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E55_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E55_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E55_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E55_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E55_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E55_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E55_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_E55_SET ns_noc_io_spio_soc_ip.csr 79252 E55 1'b1: [FATAL] R Channel Cpkt Fifo Parity Error 55 55 0x0 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERR_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 79263 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_toslvid bridge_spio_p00_rot_m_2_7_am_toslvid SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOSLVID_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOSLVID_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOSLVID_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOSLVID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 79309 spio_p00_rot_m register am_toslvid 0x1BE08 R 0x0000000000000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_toslvid AR slvid and AW slvid fields indicate slave IDs to which a read, write response timeout was detected. Note that slvid encoding is not same as the bridge ID of the slave. NocStudio provides a table mapping the slvids to the actual slave ports accessible from the master bridge. false false false false AR_SLVID SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOSLVID_AR_SLVID_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOSLVID_AR_SLVID_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOSLVID_AR_SLVID_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOSLVID_AR_SLVID_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOSLVID_AR_SLVID_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOSLVID_AR_SLVID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOSLVID_AR_SLVID_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOSLVID_AR_SLVID_SET ns_noc_io_spio_soc_ip.csr 79287 AR_SLVID Slave ID of timed out AR request 15 0 0x0000 R AW_SLVID SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOSLVID_AW_SLVID_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOSLVID_AW_SLVID_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOSLVID_AW_SLVID_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOSLVID_AW_SLVID_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOSLVID_AW_SLVID_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOSLVID_AW_SLVID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOSLVID_AW_SLVID_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOSLVID_AW_SLVID_SET ns_noc_io_spio_soc_ip.csr 79298 AW_SLVID Slave ID of timed out AW request 31 16 0x0000 R UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOSLVID_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOSLVID_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOSLVID_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOSLVID_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOSLVID_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOSLVID_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOSLVID_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_TOSLVID_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 79308 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_era bridge_spio_p00_rot_m_2_7_am_era SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERA_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERA_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERA_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERA_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 79331 spio_p00_rot_m register am_era 0x1BE10 R 0x0000000000000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_era This is the address on AR channel for which a decode error was detected. This corresponds to the status register bit e0 in AM_ERR. false false false false READ_DECERR_ADDRS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERA_READ_DECERR_ADDRS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERA_READ_DECERR_ADDRS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERA_READ_DECERR_ADDRS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERA_READ_DECERR_ADDRS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERA_READ_DECERR_ADDRS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERA_READ_DECERR_ADDRS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERA_READ_DECERR_ADDRS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_ERA_READ_DECERR_ADDRS_SET ns_noc_io_spio_soc_ip.csr 79330 READ_DECERR_ADDRS Read decerr address 63 0 0x0000000000000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_ewa bridge_spio_p00_rot_m_2_7_am_ewa SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_EWA_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_EWA_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_EWA_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_EWA_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 79353 spio_p00_rot_m register am_ewa 0x1BE18 R 0x0000000000000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_ewa This is the address on AW channel for which a decode error was detected. This corresponds to the status register bit e16 in AM_ERR. false false false false WRITE_DECERR_ADDRS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_EWA_WRITE_DECERR_ADDRS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_EWA_WRITE_DECERR_ADDRS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_EWA_WRITE_DECERR_ADDRS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_EWA_WRITE_DECERR_ADDRS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_EWA_WRITE_DECERR_ADDRS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_EWA_WRITE_DECERR_ADDRS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_EWA_WRITE_DECERR_ADDRS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_EWA_WRITE_DECERR_ADDRS_SET ns_noc_io_spio_soc_ip.csr 79352 WRITE_DECERR_ADDRS Write decerr address 63 0 0x0000000000000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_intm bridge_spio_p00_rot_m_2_7_am_intm SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 79837 spio_p00_rot_m register am_intm 0x1BE40 R/W 0x00007e07004f004f Spio_noc_bridge_spio_p00_rot_m_2_7_am_intm Interrupt mask register. Individual bit position matches the error bit positions in AM_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M0_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M0_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M0_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M0_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M0_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M0_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M0_SET ns_noc_io_spio_soc_ip.csr 79375 M0 1'b1: Mask interrupt for read channel 0 0 0x1 R/W M1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M1_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M1_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M1_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M1_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M1_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M1_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M1_SET ns_noc_io_spio_soc_ip.csr 79386 M1 1'b1: Mask interrupt for read channel 1 1 0x1 R/W M2 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M2_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M2_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M2_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M2_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M2_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M2_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M2_SET ns_noc_io_spio_soc_ip.csr 79397 M2 1'b1: Mask interrupt for read channel 2 2 0x1 R/W M3 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M3_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M3_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M3_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M3_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M3_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M3_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M3_SET ns_noc_io_spio_soc_ip.csr 79408 M3 1'b1: Mask interrupt for read channel 3 3 0x1 R/W M4 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M4_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M4_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M4_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M4_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M4_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M4_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M4_SET ns_noc_io_spio_soc_ip.csr 79419 M4 1'b1: Mask interrupt for read channel 4 4 0x0 R/W M5 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M5_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M5_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M5_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M5_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M5_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M5_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M5_SET ns_noc_io_spio_soc_ip.csr 79430 M5 1'b1: Mask interrupt for read channel 5 5 0x0 R/W M6 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M6_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M6_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M6_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M6_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M6_SET ns_noc_io_spio_soc_ip.csr 79441 M6 1'b1: Mask interrupt for read channel 6 6 0x1 R/W M7 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M7_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M7_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M7_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M7_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M7_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M7_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M7_SET ns_noc_io_spio_soc_ip.csr 79452 M7 1'b1: Mask interrupt for read channel 7 7 0x0 R/W M8 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M8_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M8_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M8_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M8_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M8_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M8_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M8_SET ns_noc_io_spio_soc_ip.csr 79463 M8 1'b1: Mask interrupt for read channel 8 8 0x0 R/W UNSD_15_9 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_15_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_15_9_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_15_9_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_15_9_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_15_9_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_15_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_15_9_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_15_9_SET ns_noc_io_spio_soc_ip.csr 79474 UNSD_15_9 15 9 0x00 R M16 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M16_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M16_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M16_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M16_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M16_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M16_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M16_SET ns_noc_io_spio_soc_ip.csr 79485 M16 1'b1: Mask interrupt for write channel 16 16 0x1 R/W M17 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M17_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M17_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M17_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M17_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M17_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M17_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M17_SET ns_noc_io_spio_soc_ip.csr 79496 M17 1'b1: Mask interrupt for write channel 17 17 0x1 R/W M18 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M18_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M18_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M18_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M18_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M18_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M18_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M18_SET ns_noc_io_spio_soc_ip.csr 79507 M18 1'b1: Mask interrupt for write channel 18 18 0x1 R/W M19 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M19_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M19_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M19_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M19_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M19_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M19_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M19_SET ns_noc_io_spio_soc_ip.csr 79518 M19 1'b1: Mask interrupt for write channel 19 19 0x1 R/W M20 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M20_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M20_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M20_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M20_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M20_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M20_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M20_SET ns_noc_io_spio_soc_ip.csr 79529 M20 1'b1: Mask interrupt for write channel 20 20 0x0 R/W M21 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M21_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M21_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M21_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M21_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M21_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M21_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M21_SET ns_noc_io_spio_soc_ip.csr 79540 M21 1'b1: Mask interrupt for write channel 21 21 0x0 R/W M22 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M22_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M22_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M22_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M22_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M22_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M22_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M22_SET ns_noc_io_spio_soc_ip.csr 79551 M22 1'b1: Mask interrupt for write channel 22 22 0x1 R/W M23 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M23_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M23_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M23_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M23_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M23_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M23_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M23_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M23_SET ns_noc_io_spio_soc_ip.csr 79562 M23 1'b1: Mask interrupt for write channel 23 23 0x0 R/W M24 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M24_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M24_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M24_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M24_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M24_SET ns_noc_io_spio_soc_ip.csr 79573 M24 1'b1: Mask interrupt for write channel 24 24 0x0 R/W UNSD_31_25 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_31_25_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_31_25_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_31_25_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_31_25_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_31_25_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_31_25_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_31_25_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_31_25_SET ns_noc_io_spio_soc_ip.csr 79584 UNSD_31_25 31 25 0x00 R M32 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M32_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M32_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M32_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M32_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M32_SET ns_noc_io_spio_soc_ip.csr 79595 M32 1'b1: Counter 0 overflow interrupt mask 32 32 0x1 R/W M33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M33_SET ns_noc_io_spio_soc_ip.csr 79606 M33 1'b1: Counter 1 overflow interrupt mask 33 33 0x1 R/W M34 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M34_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M34_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M34_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M34_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M34_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M34_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M34_SET ns_noc_io_spio_soc_ip.csr 79617 M34 1'b1: Mask interrupt on traffic to PG layer 34 34 0x1 R/W M35 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M35_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M35_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M35_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M35_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M35_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M35_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M35_SET ns_noc_io_spio_soc_ip.csr 79628 M35 1'b1: Mask interrupt on csr parity errors 35 35 0x0 R/W UNSD_39_36 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_39_36_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_39_36_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_39_36_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_39_36_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_39_36_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_39_36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_39_36_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_39_36_SET ns_noc_io_spio_soc_ip.csr 79639 UNSD_39_36 39 36 0x0 R M40 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M40_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M40_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M40_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M40_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M40_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M40_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M40_SET ns_noc_io_spio_soc_ip.csr 79651 M40 1'b1: Mask interrupt for SIB portcheck error (SIB mode only) 40 40 0x0 R/W M41 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M41_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M41_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M41_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M41_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M41_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M41_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M41_SET ns_noc_io_spio_soc_ip.csr 79662 M41 1'b1: AR Parity Intr Mask 41 41 0x1 R/W M42 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M42_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M42_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M42_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M42_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M42_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M42_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M42_SET ns_noc_io_spio_soc_ip.csr 79673 M42 1'b1: ARADDR Parity Intr Mask 42 42 0x1 R/W M43 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M43_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M43_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M43_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M43_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M43_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M43_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M43_SET ns_noc_io_spio_soc_ip.csr 79684 M43 1'b1: AW Parity Intr Mask 43 43 0x1 R/W M44 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M44_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M44_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M44_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M44_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M44_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M44_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M44_SET ns_noc_io_spio_soc_ip.csr 79695 M44 1'b1: AWADDR Parity Intr Mask 44 44 0x1 R/W M45 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M45_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M45_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M45_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M45_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M45_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M45_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M45_SET ns_noc_io_spio_soc_ip.csr 79706 M45 1'b1: WDATA Parity Intr Mask 45 45 0x1 R/W M46 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M46_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M46_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M46_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M46_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M46_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M46_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_M46_SET ns_noc_io_spio_soc_ip.csr 79717 M46 1'b1: CDDATA Parity Intr Mask 46 46 0x1 R/W E47 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E47_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E47_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E47_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E47_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E47_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E47_SET ns_noc_io_spio_soc_ip.csr 79729 E47 1'b1: Ridtbl Parity Intr Mask 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E48_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E48_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E48_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E48_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E48_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E48_SET ns_noc_io_spio_soc_ip.csr 79741 E48 1'b1: Widtbl Parity Intr Mask 48 48 0x0 R E49 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E49_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E49_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E49_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E49_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E49_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E49_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E49_SET ns_noc_io_spio_soc_ip.csr 79753 E49 1'b1: Read Reorder Buffer Parity Intr Mask 49 49 0x0 R E50 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E50_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E50_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E50_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E50_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E50_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E50_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E50_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E50_SET ns_noc_io_spio_soc_ip.csr 79765 E50 1'b1: Write Reorder Buffer Parity Intr Mask 50 50 0x0 R E51 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E51_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E51_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E51_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E51_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E51_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E51_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E51_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E51_SET ns_noc_io_spio_soc_ip.csr 79777 E51 1'b1: Rx Fifo Parity Intr Mask 51 51 0x0 R E52 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E52_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E52_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E52_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E52_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E52_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E52_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E52_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E52_SET ns_noc_io_spio_soc_ip.csr 79789 E52 1'b1: Ack Channel Wack Fifo Parity Intr Mask 52 52 0x0 R E53 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E53_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E53_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E53_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E53_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E53_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E53_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E53_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E53_SET ns_noc_io_spio_soc_ip.csr 79801 E53 1'b1: Ack Channel Rack Fifo Parity Intr Mask 53 53 0x0 R E54 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E54_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E54_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E54_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E54_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E54_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E54_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E54_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E54_SET ns_noc_io_spio_soc_ip.csr 79813 E54 1'b1: CRCD Channel Crid Fifo Parity Intr Mask 54 54 0x0 R E55 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E55_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E55_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E55_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E55_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E55_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E55_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E55_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_E55_SET ns_noc_io_spio_soc_ip.csr 79825 E55 1'b1: R Channel Cpkt Fifo Parity Intr Mask 55 55 0x0 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_INTM_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 79836 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_caddr bridge_spio_p00_rot_m_2_7_am_caddr SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CADDR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CADDR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CADDR_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CADDR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 79859 spio_p00_rot_m register am_caddr 0x1BF00 R/W 0xffffffffffffffff Spio_noc_bridge_spio_p00_rot_m_2_7_am_caddr This register is part of statistics gathering on the AR and AW command channels. This is the address value which is checked against AR, AW command channels in conjunction with the mask below to filter commands for statistics gathering. false false false false CAPTURE_ADDR SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CADDR_CAPTURE_ADDR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CADDR_CAPTURE_ADDR_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CADDR_CAPTURE_ADDR_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CADDR_CAPTURE_ADDR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CADDR_CAPTURE_ADDR_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CADDR_CAPTURE_ADDR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CADDR_CAPTURE_ADDR_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CADDR_CAPTURE_ADDR_SET ns_noc_io_spio_soc_ip.csr 79858 CAPTURE_ADDR Capture address 63 0 0xffffffffffffffff R/W register spio_noc.bridge_spio_p00_rot_m_2_7_am_caddrmsk bridge_spio_p00_rot_m_2_7_am_caddrmsk SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CADDRMSK_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CADDRMSK_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CADDRMSK_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CADDRMSK_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 79882 spio_p00_rot_m register am_caddrmsk 0x1BF08 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_caddrmsk If command address on the AR, AW channel logically ANDed with this mask is equal to the value specified in AM_CADDR, then an address match has occurred. Note that only lowest significant bits equal to the master's address width are used in the comparison. false false false false CAPTURE_ADDR_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_SET ns_noc_io_spio_soc_ip.csr 79881 CAPTURE_ADDR_MASK Capture address mask 63 0 0x0000000000000000 R/W register spio_noc.bridge_spio_p00_rot_m_2_7_am_ccmd0 bridge_spio_p00_rot_m_2_7_am_ccmd0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 80072 spio_p00_rot_m register am_ccmd0 0x1BF10 R/W 0x0000000003fff33f Spio_noc_bridge_spio_p00_rot_m_2_7_am_ccmd0 Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands. false false false false SNOOP SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_SNOOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_SNOOP_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_SNOOP_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_SNOOP_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_SNOOP_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_SNOOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_SNOOP_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_SNOOP_SET ns_noc_io_spio_soc_ip.csr 79904 SNOOP Snoop 3 0 0xf R/W DOMAIN SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_DOMAIN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_DOMAIN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_DOMAIN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_DOMAIN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_DOMAIN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_DOMAIN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_DOMAIN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_DOMAIN_SET ns_noc_io_spio_soc_ip.csr 79915 DOMAIN Domain 5 4 0x3 R/W UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 79926 UNSD_7_6 7 6 0x0 R BAR SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_BAR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_BAR_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_BAR_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_BAR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_BAR_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_BAR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_BAR_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_BAR_SET ns_noc_io_spio_soc_ip.csr 79937 BAR Bar 9 8 0x3 R/W UNSD_11_10 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_11_10_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_11_10_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_11_10_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_11_10_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_11_10_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_11_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_11_10_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_11_10_SET ns_noc_io_spio_soc_ip.csr 79948 UNSD_11_10 11 10 0x0 R CACHE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_CACHE_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_CACHE_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_CACHE_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_CACHE_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_CACHE_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_CACHE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_CACHE_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_CACHE_SET ns_noc_io_spio_soc_ip.csr 79959 CACHE Cache 15 12 0xf R/W QOS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_QOS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_QOS_SET ns_noc_io_spio_soc_ip.csr 79970 QOS QoS 19 16 0xf R/W PROT SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_PROT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_PROT_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_PROT_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_PROT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_PROT_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_PROT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_PROT_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_PROT_SET ns_noc_io_spio_soc_ip.csr 79981 PROT Prot 22 20 0x7 R/W LOC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_LOC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_LOC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_LOC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_LOC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_LOC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_LOC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_LOC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_LOC_SET ns_noc_io_spio_soc_ip.csr 79992 LOC 1'b1: Lock 23 23 0x1 R/W RDY SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_RDY_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_RDY_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_RDY_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_RDY_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_RDY_SET ns_noc_io_spio_soc_ip.csr 80003 RDY 1'b1: Ready 24 24 0x1 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_VAL_SET ns_noc_io_spio_soc_ip.csr 80014 VAL 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_27_26_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_27_26_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_27_26_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_27_26_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_27_26_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_27_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_27_26_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_27_26_SET ns_noc_io_spio_soc_ip.csr 80025 UNSD_27_26 27 26 0x0 R INTFID SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_INTFID_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_INTFID_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_INTFID_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_INTFID_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_INTFID_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_INTFID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_INTFID_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_INTFID_SET ns_noc_io_spio_soc_ip.csr 80037 INTFID 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_31_31 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_31_31_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_31_31_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_31_31_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_31_31_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_31_31_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_31_31_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_31_31_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_31_31_SET ns_noc_io_spio_soc_ip.csr 80048 UNSD_31_31 31 31 0x0 R TYP SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_TYP_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_TYP_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_TYP_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_TYP_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_TYP_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_TYP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_TYP_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_TYP_SET ns_noc_io_spio_soc_ip.csr 80060 TYP 1'b1: Count response latency of captured command 1'b0: Count captured command 32 32 0x0 R/W UNSD_63_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_63_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_63_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_63_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_63_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_63_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_63_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_63_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD0_UNSD_63_33_SET ns_noc_io_spio_soc_ip.csr 80071 UNSD_63_33 63 33 0x00000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_ccmdmsk0 bridge_spio_p00_rot_m_2_7_am_ccmdmsk0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 80216 spio_p00_rot_m register am_ccmdmsk0 0x1BF18 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_ccmdmsk0 If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters. false false false false SNOOP SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_SNOOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_SNOOP_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_SNOOP_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_SNOOP_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_SNOOP_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_SNOOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_SNOOP_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_SNOOP_SET ns_noc_io_spio_soc_ip.csr 80094 SNOOP Snoop 3 0 0x0 R/W DOMAIN SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_DOMAIN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_DOMAIN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_DOMAIN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_DOMAIN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_DOMAIN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_DOMAIN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_DOMAIN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_DOMAIN_SET ns_noc_io_spio_soc_ip.csr 80105 DOMAIN Domain 5 4 0x0 R/W UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 80116 UNSD_7_6 7 6 0x0 R BAR SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_BAR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_BAR_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_BAR_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_BAR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_BAR_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_BAR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_BAR_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_BAR_SET ns_noc_io_spio_soc_ip.csr 80127 BAR Bar 9 8 0x0 R/W UNSD_11_10 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_UNSD_11_10_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_UNSD_11_10_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_UNSD_11_10_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_UNSD_11_10_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_UNSD_11_10_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_UNSD_11_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_UNSD_11_10_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_UNSD_11_10_SET ns_noc_io_spio_soc_ip.csr 80138 UNSD_11_10 11 10 0x0 R CACHE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_CACHE_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_CACHE_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_CACHE_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_CACHE_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_CACHE_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_CACHE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_CACHE_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_CACHE_SET ns_noc_io_spio_soc_ip.csr 80149 CACHE Cache 15 12 0x0 R/W QOS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_QOS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_QOS_SET ns_noc_io_spio_soc_ip.csr 80160 QOS QoS 19 16 0x0 R/W PROT SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_PROT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_PROT_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_PROT_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_PROT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_PROT_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_PROT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_PROT_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_PROT_SET ns_noc_io_spio_soc_ip.csr 80171 PROT Prot 22 20 0x0 R/W LOC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_LOC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_LOC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_LOC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_LOC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_LOC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_LOC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_LOC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_LOC_SET ns_noc_io_spio_soc_ip.csr 80182 LOC 1'b1: Lock 23 23 0x0 R/W RDY SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_RDY_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_RDY_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_RDY_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_RDY_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_RDY_SET ns_noc_io_spio_soc_ip.csr 80193 RDY 1'b1: Ready 24 24 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_VAL_SET ns_noc_io_spio_soc_ip.csr 80204 VAL 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_UNSD_63_26_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_UNSD_63_26_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_UNSD_63_26_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_UNSD_63_26_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_UNSD_63_26_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_UNSD_63_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_UNSD_63_26_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK0_UNSD_63_26_SET ns_noc_io_spio_soc_ip.csr 80215 UNSD_63_26 63 26 0x0000000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_cntr0 bridge_spio_p00_rot_m_2_7_am_cntr0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 80251 spio_p00_rot_m register am_cntr0 0x1BF20 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_cntr0 32-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured. false false false false CNTR SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR0_CNTR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR0_CNTR_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR0_CNTR_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR0_CNTR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR0_CNTR_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR0_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR0_CNTR_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR0_CNTR_SET ns_noc_io_spio_soc_ip.csr 80239 CNTR Counter 31 0 0x00000000 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR0_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR0_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR0_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR0_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR0_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR0_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR0_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR0_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 80250 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_latnum0 bridge_spio_p00_rot_m_2_7_am_latnum0 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM0_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 80290 spio_p00_rot_m register am_latnum0 0x1BF28 R/W 0x0000000000000007 Spio_noc_bridge_spio_p00_rot_m_2_7_am_latnum0 This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using: Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0 There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set. false false false false CNTR SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM0_CNTR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM0_CNTR_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM0_CNTR_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM0_CNTR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM0_CNTR_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM0_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM0_CNTR_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM0_CNTR_SET ns_noc_io_spio_soc_ip.csr 80278 CNTR Counter 31 0 0x00000007 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM0_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM0_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM0_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM0_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM0_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM0_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM0_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM0_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 80289 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_ccmd1 bridge_spio_p00_rot_m_2_7_am_ccmd1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 80480 spio_p00_rot_m register am_ccmd1 0x1BF30 R/W 0x0000000003fff33f Spio_noc_bridge_spio_p00_rot_m_2_7_am_ccmd1 Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands. false false false false SNOOP SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_SNOOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_SNOOP_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_SNOOP_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_SNOOP_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_SNOOP_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_SNOOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_SNOOP_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_SNOOP_SET ns_noc_io_spio_soc_ip.csr 80312 SNOOP Snoop 3 0 0xf R/W DOMAIN SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_DOMAIN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_DOMAIN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_DOMAIN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_DOMAIN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_DOMAIN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_DOMAIN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_DOMAIN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_DOMAIN_SET ns_noc_io_spio_soc_ip.csr 80323 DOMAIN Domain 5 4 0x3 R/W UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 80334 UNSD_7_6 7 6 0x0 R BAR SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_BAR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_BAR_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_BAR_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_BAR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_BAR_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_BAR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_BAR_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_BAR_SET ns_noc_io_spio_soc_ip.csr 80345 BAR Bar 9 8 0x3 R/W UNSD_11_10 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_11_10_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_11_10_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_11_10_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_11_10_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_11_10_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_11_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_11_10_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_11_10_SET ns_noc_io_spio_soc_ip.csr 80356 UNSD_11_10 11 10 0x0 R CACHE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_CACHE_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_CACHE_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_CACHE_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_CACHE_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_CACHE_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_CACHE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_CACHE_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_CACHE_SET ns_noc_io_spio_soc_ip.csr 80367 CACHE Cache 15 12 0xf R/W QOS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_QOS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_QOS_SET ns_noc_io_spio_soc_ip.csr 80378 QOS QoS 19 16 0xf R/W PROT SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_PROT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_PROT_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_PROT_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_PROT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_PROT_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_PROT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_PROT_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_PROT_SET ns_noc_io_spio_soc_ip.csr 80389 PROT Prot 22 20 0x7 R/W LOC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_LOC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_LOC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_LOC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_LOC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_LOC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_LOC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_LOC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_LOC_SET ns_noc_io_spio_soc_ip.csr 80400 LOC 1'b1: Lock 23 23 0x1 R/W RDY SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_RDY_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_RDY_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_RDY_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_RDY_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_RDY_SET ns_noc_io_spio_soc_ip.csr 80411 RDY 1'b1: Ready 24 24 0x1 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_VAL_SET ns_noc_io_spio_soc_ip.csr 80422 VAL 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_27_26_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_27_26_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_27_26_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_27_26_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_27_26_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_27_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_27_26_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_27_26_SET ns_noc_io_spio_soc_ip.csr 80433 UNSD_27_26 27 26 0x0 R INTFID SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_INTFID_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_INTFID_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_INTFID_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_INTFID_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_INTFID_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_INTFID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_INTFID_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_INTFID_SET ns_noc_io_spio_soc_ip.csr 80445 INTFID 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_31_31 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_31_31_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_31_31_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_31_31_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_31_31_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_31_31_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_31_31_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_31_31_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_31_31_SET ns_noc_io_spio_soc_ip.csr 80456 UNSD_31_31 31 31 0x0 R TYP SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_TYP_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_TYP_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_TYP_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_TYP_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_TYP_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_TYP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_TYP_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_TYP_SET ns_noc_io_spio_soc_ip.csr 80468 TYP 1'b1: Count response latency of captured command 1'b0: Count captured command 32 32 0x0 R/W UNSD_63_33 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_63_33_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_63_33_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_63_33_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_63_33_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_63_33_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_63_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_63_33_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMD1_UNSD_63_33_SET ns_noc_io_spio_soc_ip.csr 80479 UNSD_63_33 63 33 0x00000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_ccmdmsk1 bridge_spio_p00_rot_m_2_7_am_ccmdmsk1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 80624 spio_p00_rot_m register am_ccmdmsk1 0x1BF38 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_ccmdmsk1 If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters. false false false false SNOOP SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_SNOOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_SNOOP_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_SNOOP_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_SNOOP_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_SNOOP_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_SNOOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_SNOOP_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_SNOOP_SET ns_noc_io_spio_soc_ip.csr 80502 SNOOP Snoop 3 0 0x0 R/W DOMAIN SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_DOMAIN_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_DOMAIN_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_DOMAIN_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_DOMAIN_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_DOMAIN_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_DOMAIN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_DOMAIN_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_DOMAIN_SET ns_noc_io_spio_soc_ip.csr 80513 DOMAIN Domain 5 4 0x0 R/W UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 80524 UNSD_7_6 7 6 0x0 R BAR SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_BAR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_BAR_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_BAR_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_BAR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_BAR_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_BAR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_BAR_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_BAR_SET ns_noc_io_spio_soc_ip.csr 80535 BAR Bar 9 8 0x0 R/W UNSD_11_10 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_UNSD_11_10_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_UNSD_11_10_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_UNSD_11_10_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_UNSD_11_10_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_UNSD_11_10_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_UNSD_11_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_UNSD_11_10_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_UNSD_11_10_SET ns_noc_io_spio_soc_ip.csr 80546 UNSD_11_10 11 10 0x0 R CACHE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_CACHE_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_CACHE_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_CACHE_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_CACHE_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_CACHE_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_CACHE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_CACHE_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_CACHE_SET ns_noc_io_spio_soc_ip.csr 80557 CACHE Cache 15 12 0x0 R/W QOS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_QOS_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_QOS_SET ns_noc_io_spio_soc_ip.csr 80568 QOS QoS 19 16 0x0 R/W PROT SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_PROT_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_PROT_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_PROT_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_PROT_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_PROT_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_PROT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_PROT_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_PROT_SET ns_noc_io_spio_soc_ip.csr 80579 PROT Prot 22 20 0x0 R/W LOC SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_LOC_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_LOC_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_LOC_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_LOC_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_LOC_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_LOC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_LOC_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_LOC_SET ns_noc_io_spio_soc_ip.csr 80590 LOC 1'b1: Lock 23 23 0x0 R/W RDY SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_RDY_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_RDY_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_RDY_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_RDY_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_RDY_SET ns_noc_io_spio_soc_ip.csr 80601 RDY 1'b1: Ready 24 24 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_VAL_SET ns_noc_io_spio_soc_ip.csr 80612 VAL 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_UNSD_63_26_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_UNSD_63_26_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_UNSD_63_26_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_UNSD_63_26_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_UNSD_63_26_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_UNSD_63_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_UNSD_63_26_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CCMDMSK1_UNSD_63_26_SET ns_noc_io_spio_soc_ip.csr 80623 UNSD_63_26 63 26 0x0000000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_cntr1 bridge_spio_p00_rot_m_2_7_am_cntr1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 80659 spio_p00_rot_m register am_cntr1 0x1BF40 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_cntr1 32-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured. false false false false CNTR SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR1_CNTR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR1_CNTR_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR1_CNTR_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR1_CNTR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR1_CNTR_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR1_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR1_CNTR_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR1_CNTR_SET ns_noc_io_spio_soc_ip.csr 80647 CNTR Counter 31 0 0x00000000 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR1_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR1_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR1_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR1_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR1_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR1_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR1_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_CNTR1_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 80658 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_latnum1 bridge_spio_p00_rot_m_2_7_am_latnum1 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM1_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 80698 spio_p00_rot_m register am_latnum1 0x1BF48 R/W 0x0000000000000007 Spio_noc_bridge_spio_p00_rot_m_2_7_am_latnum1 This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using: Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0 There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set. false false false false CNTR SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM1_CNTR_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM1_CNTR_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM1_CNTR_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM1_CNTR_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM1_CNTR_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM1_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM1_CNTR_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM1_CNTR_SET ns_noc_io_spio_soc_ip.csr 80686 CNTR Counter 31 0 0x00000007 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM1_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM1_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM1_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM1_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM1_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM1_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM1_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_LATNUM1_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 80697 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_arovrd bridge_spio_p00_rot_m_2_7_am_arovrd SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 80811 spio_p00_rot_m register am_arovrd 0x1BF60 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_arovrd AR override. false false false false arcache_val SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 80716 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 80729 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 80740 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 80751 UNSD_11_11 11 11 0x0 R arprot_enb SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 80764 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 80775 UNSD_15_15 15 15 0x0 R arqos_val SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 80786 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_ARQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 80799 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AROVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 80810 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_p00_rot_m_2_7_am_awovrd bridge_spio_p00_rot_m_2_7_am_awovrd SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 80924 spio_p00_rot_m register am_awovrd 0x1BF68 R/W 0x0000000000000000 Spio_noc_bridge_spio_p00_rot_m_2_7_am_awovrd AW override. false false false false awcache_val SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 80829 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 80842 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 80853 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 80864 UNSD_11_11 11 11 0x0 R awprot_enb SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 80877 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 80888 UNSD_15_15 15 15 0x0 R awqos_val SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 80899 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_AWQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 80912 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_P00_ROT_M_2_7_AM_AWOVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 80923 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_p10_apb0_s_7_8_apbslv_bridge_version bridge_spio_p10_apb0_s_7_8_apbslv_bridge_version SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_VERSION_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_VERSION_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_VERSION_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_VERSION_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 80952 spio_p10_apb0_s register apbslv_bridge_version 0x1C200 R 0x0000000000000000 Spio_noc_bridge_spio_p10_apb0_s_7_8_apbslv_bridge_version Bridge version register. false false false false VER SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_VERSION_VER_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_VERSION_VER_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_VERSION_VER_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_VERSION_VER_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_VERSION_VER_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_VERSION_VER_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_VERSION_VER_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_VERSION_VER_SET ns_noc_io_spio_soc_ip.csr 80941 VER Bridge version. 3 0 0x0 R UNSD_63_4 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_VERSION_UNSD_63_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_VERSION_UNSD_63_4_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_VERSION_UNSD_63_4_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_VERSION_UNSD_63_4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_VERSION_UNSD_63_4_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_VERSION_UNSD_63_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_VERSION_UNSD_63_4_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_VERSION_UNSD_63_4_SET ns_noc_io_spio_soc_ip.csr 80951 UNSD_63_4 63 4 0x000000000000000 R register spio_noc.bridge_spio_p10_apb0_s_7_8_apbslv_bridge_id bridge_spio_p10_apb0_s_7_8_apbslv_bridge_id SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_ID_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_ID_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_ID_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 80992 spio_p10_apb0_s register apbslv_bridge_id 0x1C208 R 0x0000000000000007 Spio_noc_bridge_spio_p10_apb0_s_7_8_apbslv_bridge_id Bridge ID register. false false false false ID SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_ID_ID_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_ID_ID_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_ID_ID_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_ID_ID_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_ID_ID_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_ID_ID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_ID_ID_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_ID_ID_SET ns_noc_io_spio_soc_ip.csr 80969 ID Unique bridge id. 9 0 0x007 R ZEROES SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_ID_ZEROES_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_ID_ZEROES_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_ID_ZEROES_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_ID_ZEROES_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_ID_ZEROES_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_ID_ZEROES_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_ID_ZEROES_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_ID_ZEROES_SET ns_noc_io_spio_soc_ip.csr 80980 ZEROES Zeroes 15 10 0x00 R UNSD_63_16 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_ID_UNSD_63_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_ID_UNSD_63_16_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_ID_UNSD_63_16_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_ID_UNSD_63_16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_ID_UNSD_63_16_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_ID_UNSD_63_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_ID_UNSD_63_16_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_spio_soc_ip.csr 80991 UNSD_63_16 Unused 63 16 0x000000000000 R register spio_noc.bridge_spio_p10_apb0_s_7_8_apbslv_slvs_sleep_status bridge_spio_p10_apb0_s_7_8_apbslv_slvs_sleep_status SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 81201 spio_p10_apb0_s register apbslv_slvs_sleep_status 0x1C210 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_apb0_s_7_8_apbslv_slvs_sleep_status Slave sleep status register. false false false false STS_0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_0_SET ns_noc_io_spio_soc_ip.csr 81009 STS_0 1'b1: Slave is in sleep mode 1'b0: Slave is active 0 0 0x0 R/W STS_1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_1_SET ns_noc_io_spio_soc_ip.csr 81021 STS_1 1'b1: Slave is in sleep mode 1'b0: Slave is active 1 1 0x0 R/W STS_2 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_2_SET ns_noc_io_spio_soc_ip.csr 81033 STS_2 1'b1: Slave is in sleep mode 1'b0: Slave is active 2 2 0x0 R/W STS_3 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_3_SET ns_noc_io_spio_soc_ip.csr 81045 STS_3 1'b1: Slave is in sleep mode 1'b0: Slave is active 3 3 0x0 R/W STS_4 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_4_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_4_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_4_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_4_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_4_SET ns_noc_io_spio_soc_ip.csr 81057 STS_4 1'b1: Slave is in sleep mode 1'b0: Slave is active 4 4 0x0 R/W STS_5 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_5_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_5_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_5_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_5_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_5_SET ns_noc_io_spio_soc_ip.csr 81069 STS_5 1'b1: Slave is in sleep mode 1'b0: Slave is active 5 5 0x0 R/W STS_6 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_6_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_6_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_6_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_6_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_6_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_6_SET ns_noc_io_spio_soc_ip.csr 81081 STS_6 1'b1: Slave is in sleep mode 1'b0: Slave is active 6 6 0x0 R/W STS_7 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_7_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_7_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_7_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_7_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_7_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_7_SET ns_noc_io_spio_soc_ip.csr 81093 STS_7 1'b1: Slave is in sleep mode 1'b0: Slave is active 7 7 0x0 R/W STS_8 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_8_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_8_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_8_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_8_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_8_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_8_SET ns_noc_io_spio_soc_ip.csr 81105 STS_8 1'b1: Slave is in sleep mode 1'b0: Slave is active 8 8 0x0 R/W STS_9 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_9_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_9_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_9_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_9_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_9_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_9_SET ns_noc_io_spio_soc_ip.csr 81117 STS_9 1'b1: Slave is in sleep mode 1'b0: Slave is active 9 9 0x0 R/W STS_10 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_10_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_10_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_10_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_10_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_10_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_10_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_10_SET ns_noc_io_spio_soc_ip.csr 81129 STS_10 1'b1: Slave is in sleep mode 1'b0: Slave is active 10 10 0x0 R/W STS_11 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_11_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_11_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_11_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_11_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_11_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_11_SET ns_noc_io_spio_soc_ip.csr 81141 STS_11 1'b1: Slave is in sleep mode 1'b0: Slave is active 11 11 0x0 R/W STS_12 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_12_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_12_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_12_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_12_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_12_SET ns_noc_io_spio_soc_ip.csr 81153 STS_12 1'b1: Slave is in sleep mode 1'b0: Slave is active 12 12 0x0 R/W STS_13 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_13_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_13_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_13_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_13_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_13_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_13_SET ns_noc_io_spio_soc_ip.csr 81165 STS_13 1'b1: Slave is in sleep mode 1'b0: Slave is active 13 13 0x0 R/W STS_14 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_14_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_14_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_14_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_14_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_14_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_14_SET ns_noc_io_spio_soc_ip.csr 81177 STS_14 1'b1: Slave is in sleep mode 1'b0: Slave is active 14 14 0x0 R/W STS_15 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_15_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_15_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_15_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_15_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_15_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_STS_15_SET ns_noc_io_spio_soc_ip.csr 81189 STS_15 1'b1: Slave is in sleep mode 1'b0: Slave is active 15 15 0x0 R/W UNSD_63_16 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_SET ns_noc_io_spio_soc_ip.csr 81200 UNSD_63_16 63 16 0x000000000000 R register spio_noc.bridge_spio_p10_apb0_s_7_8_as_cgc bridge_spio_p10_apb0_s_7_8_as_cgc SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGC_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGC_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGC_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 81238 spio_p10_apb0_s register as_cgc 0x1DC10 R/W 0x0000000000000064 Spio_noc_bridge_spio_p10_apb0_s_7_8_as_cgc Programmable intervals used by coarse clock gating logic. This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGC_HYSTERESIS_COUNTER_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGC_HYSTERESIS_COUNTER_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGC_HYSTERESIS_COUNTER_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGC_HYSTERESIS_COUNTER_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGC_HYSTERESIS_COUNTER_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGC_HYSTERESIS_COUNTER_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGC_HYSTERESIS_COUNTER_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_spio_soc_ip.csr 81226 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGC_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGC_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGC_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGC_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGC_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGC_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGC_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGC_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 81237 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p10_apb0_s_7_8_as_cgo bridge_spio_p10_apb0_s_7_8_as_cgo SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGO_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGO_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGO_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGO_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 81273 spio_p10_apb0_s register as_cgo 0x1DC18 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_apb0_s_7_8_as_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the slave bridge. false false false false FPO SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGO_FPO_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGO_FPO_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGO_FPO_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGO_FPO_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGO_FPO_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGO_FPO_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGO_FPO_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGO_FPO_SET ns_noc_io_spio_soc_ip.csr 81261 FPO 1'b1: Clock gating override enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGO_UNSD_63_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGO_UNSD_63_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGO_UNSD_63_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGO_UNSD_63_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGO_UNSD_63_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGO_UNSD_63_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGO_UNSD_63_1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CGO_UNSD_63_1_SET ns_noc_io_spio_soc_ip.csr 81272 UNSD_63_1 63 1 0x0000000000000000 R register spio_noc.bridge_spio_p10_apb0_s_7_8_as_sts bridge_spio_p10_apb0_s_7_8_as_sts SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 81347 spio_p10_apb0_s register as_sts 0x1DD00 R 0x000000000000000c Spio_noc_bridge_spio_p10_apb0_s_7_8_as_sts Slave bridge status bits. false false false false WOF SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_WOF_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_WOF_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_WOF_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_WOF_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_WOF_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_WOF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_WOF_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_WOF_SET ns_noc_io_spio_soc_ip.csr 81296 WOF 1'b1: Maximum number of supported write commands are outstanding to the attached slave device awaiting response, no more write commands will be issued to slave till responses are received. 1'b0: Slave device can expect more write commands from NoC 0 0 0x0 R ROF SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_ROF_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_ROF_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_ROF_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_ROF_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_ROF_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_ROF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_ROF_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_ROF_SET ns_noc_io_spio_soc_ip.csr 81312 ROF 1'b1: Maximum number of supported read commands are outstanding to the attached slave device awaiting response, no more read commands will be issued to slave till responses are received. 1'b0: Slave bridge can accept more read commands from the NoC 1 1 0x0 R WOE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_WOE_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_WOE_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_WOE_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_WOE_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_WOE_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_WOE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_WOE_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_WOE_SET ns_noc_io_spio_soc_ip.csr 81324 WOE 1'b1: There are no write commands outstanding to the attached slave device 2 2 0x1 R ROE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_ROE_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_ROE_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_ROE_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_ROE_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_ROE_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_ROE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_ROE_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_ROE_SET ns_noc_io_spio_soc_ip.csr 81336 ROE 1'b1: There are no read commands outstanding to the attached slave device 3 3 0x1 R UNSD_63_4 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_UNSD_63_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_UNSD_63_4_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_UNSD_63_4_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_UNSD_63_4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_UNSD_63_4_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_UNSD_63_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_UNSD_63_4_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_STS_UNSD_63_4_SET ns_noc_io_spio_soc_ip.csr 81346 UNSD_63_4 63 4 0x000000000000000 R register spio_noc.bridge_spio_p10_apb0_s_7_8_as_bridge_id bridge_spio_p10_apb0_s_7_8_as_bridge_id SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_BRIDGE_ID_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_BRIDGE_ID_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_BRIDGE_ID_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_BRIDGE_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 81377 spio_p10_apb0_s register as_bridge_id 0x1DD08 R 0x0000000000000007 Spio_noc_bridge_spio_p10_apb0_s_7_8_as_bridge_id Unique identifier assigned to the slave bridge. false false false false ID SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_BRIDGE_ID_ID_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_BRIDGE_ID_ID_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_BRIDGE_ID_ID_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_BRIDGE_ID_ID_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_BRIDGE_ID_ID_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_BRIDGE_ID_ID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_BRIDGE_ID_ID_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_BRIDGE_ID_ID_SET ns_noc_io_spio_soc_ip.csr 81366 ID Unique bridge ID 15 0 0x0007 R UNSD_63_16 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_BRIDGE_ID_UNSD_63_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_BRIDGE_ID_UNSD_63_16_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_BRIDGE_ID_UNSD_63_16_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_BRIDGE_ID_UNSD_63_16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_BRIDGE_ID_UNSD_63_16_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_BRIDGE_ID_UNSD_63_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_BRIDGE_ID_UNSD_63_16_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_spio_soc_ip.csr 81376 UNSD_63_16 63 16 0x000000000000 R register spio_noc.bridge_spio_p10_apb0_s_7_8_as_err bridge_spio_p10_apb0_s_7_8_as_err SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 81730 spio_p10_apb0_s register as_err 0x1DE00 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_apb0_s_7_8_as_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E0_SET ns_noc_io_spio_soc_ip.csr 81398 E0 1'b1: Read decode error response: Decode error response received from slave device for read command 0 0 0x0 R/W E1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E1_SET ns_noc_io_spio_soc_ip.csr 81410 E1 1'b1: Read slave error response: Slave error response received from slave device for read command 1 1 0x0 R/W E2 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E2_SET ns_noc_io_spio_soc_ip.csr 81423 E2 1'b1: [FATAL] Unknown read response destination: RID from read response produces a destination which is not present in the routing table 2 2 0x0 R/W E3 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E3_SET ns_noc_io_spio_soc_ip.csr 81437 E3 1'b1: [FATAL] Interleaved read response: Interleaved read response. This can occur if interleaved read response is received from a slave device for which a de-interleaver was not specified 3 3 0x0 R/W E4 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E4_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E4_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E4_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E4_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E4_SET ns_noc_io_spio_soc_ip.csr 81449 E4 1'b1: Read command modified: A read command which was marked as non-modifiable was modified by the slave bridge 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_UNSD_15_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_UNSD_15_5_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_UNSD_15_5_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_UNSD_15_5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_UNSD_15_5_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_UNSD_15_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_UNSD_15_5_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 81460 UNSD_15_5 15 5 0x000 R E16 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E16_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E16_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E16_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E16_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E16_SET ns_noc_io_spio_soc_ip.csr 81472 E16 1'b1: Write decode error response: Decode error response received from slave device for write command 16 16 0x0 R/W E17 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E17_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E17_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E17_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E17_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E17_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E17_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E17_SET ns_noc_io_spio_soc_ip.csr 81484 E17 1'b1: Write slave error response: Slave error response received from slave device for write command 17 17 0x0 R/W E18 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E18_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E18_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E18_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E18_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E18_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E18_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E18_SET ns_noc_io_spio_soc_ip.csr 81497 E18 1'b1: [FATAL] Unknown write response destination: BID from write response produces a destination which is not present in the routing table 18 18 0x0 R/W E19 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E19_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E19_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E19_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E19_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E19_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E19_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E19_SET ns_noc_io_spio_soc_ip.csr 81509 E19 1'b1: Write command modified: A write command which was marked as non-modifiable was modified by the slave bridge 19 19 0x0 R/W UNSD_31_20 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_UNSD_31_20_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_UNSD_31_20_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_UNSD_31_20_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_UNSD_31_20_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_UNSD_31_20_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_UNSD_31_20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_UNSD_31_20_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_UNSD_31_20_SET ns_noc_io_spio_soc_ip.csr 81520 UNSD_31_20 31 20 0x000 R E32 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E32_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E32_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E32_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E32_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E32_SET ns_noc_io_spio_soc_ip.csr 81532 E32 1'b1: [FATAL] Traffic sent to a noc layer which is power gated 32 32 0x0 R/W E33 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E33_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E33_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E33_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E33_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E33_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E33_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E33_SET ns_noc_io_spio_soc_ip.csr 81543 E33 1'b1: [FATAL] Parity error in config/status registers 33 33 0x0 R/W E34 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E34_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E34_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E34_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E34_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E34_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E34_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E34_SET ns_noc_io_spio_soc_ip.csr 81554 E34 1'b1: [FATAL] RDATA Parity error 34 34 0x0 R/W E35 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E35_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E35_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E35_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E35_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E35_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E35_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E35_SET ns_noc_io_spio_soc_ip.csr 81565 E35 1'b1: [FATAL] RRESP Parity error 35 35 0x0 R/W E36 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E36_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E36_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E36_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E36_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E36_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E36_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E36_SET ns_noc_io_spio_soc_ip.csr 81576 E36 1'b1: [FATAL] BRESP Parity error 36 36 0x0 R/W E37 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E37_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E37_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E37_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E37_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E37_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E37_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E37_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E37_SET ns_noc_io_spio_soc_ip.csr 81587 E37 1'b1: [FATAL] AC Parity error 37 37 0x0 R/W E38 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E38_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E38_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E38_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E38_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E38_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E38_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E38_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E38_SET ns_noc_io_spio_soc_ip.csr 81598 E38 1'b1: [FATAL] ACADDR Parity error 38 38 0x0 R/W E39 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E39_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E39_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E39_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E39_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E39_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E39_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E39_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E39_SET ns_noc_io_spio_soc_ip.csr 81610 E39 1'b1: [FATAL] R Ch Cmdtbl Parity Err 39 39 0x0 R E40 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E40_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E40_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E40_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E40_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E40_SET ns_noc_io_spio_soc_ip.csr 81622 E40 1'b1: [FATAL] B Ch Cmdtbl Parity Err 40 40 0x0 R E41 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E41_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E41_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E41_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E41_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E41_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E41_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E41_SET ns_noc_io_spio_soc_ip.csr 81634 E41 1'b1: [FATAL] Rx Fifo Parity Err 41 41 0x0 R E42 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E42_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E42_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E42_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E42_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E42_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E42_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E42_SET ns_noc_io_spio_soc_ip.csr 81646 E42 1'b1: [FATAL] CRCD Ch Reorder Buffer Parity Err 42 42 0x0 R E43 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E43_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E43_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E43_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E43_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E43_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E43_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E43_SET ns_noc_io_spio_soc_ip.csr 81658 E43 1'b1: [FATAL] Ack Ch Wack Reorder Buffer Parity Err 43 43 0x0 R E44 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E44_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E44_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E44_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E44_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E44_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E44_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E44_SET ns_noc_io_spio_soc_ip.csr 81670 E44 1'b1: [FATAL] Ack Ch Rack Reorder Buffer Parity Err 44 44 0x0 R E45 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E45_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E45_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E45_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E45_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E45_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E45_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E45_SET ns_noc_io_spio_soc_ip.csr 81682 E45 1'b1: [FATAL] B Ch Drain Fifo Parity Err 45 45 0x0 R E46 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E46_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E46_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E46_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E46_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E46_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E46_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E46_SET ns_noc_io_spio_soc_ip.csr 81694 E46 1'b1: [FATAL] R Ch Flush Fifo Parity Err 46 46 0x0 R E47 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E47_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E47_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E47_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E47_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E47_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E47_SET ns_noc_io_spio_soc_ip.csr 81706 E47 1'b1: [FATAL] R Ch Deinterleaver Cmdtbl Parity Err 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E48_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E48_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E48_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E48_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_E48_SET ns_noc_io_spio_soc_ip.csr 81718 E48 1'b1: [FATAL] R Ch Deinterleaver Data Buffer Parity Err 48 48 0x0 R UNSD_63_49 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_UNSD_63_49_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_UNSD_63_49_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_UNSD_63_49_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_UNSD_63_49_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_UNSD_63_49_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_UNSD_63_49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_UNSD_63_49_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_ERR_UNSD_63_49_SET ns_noc_io_spio_soc_ip.csr 81729 UNSD_63_49 63 49 0x0000 R register spio_noc.bridge_spio_p10_apb0_s_7_8_as_intm bridge_spio_p10_apb0_s_7_8_as_intm SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 82070 spio_p10_apb0_s register as_intm 0x1DE40 R/W 0x0000007d000b0013 Spio_noc_bridge_spio_p10_apb0_s_7_8_as_intm Interrupt mask register.Individual bit positions match the error bit positions in AS_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M0_SET ns_noc_io_spio_soc_ip.csr 81751 M0 Mask interrupts for read channel 0 0 0x1 R/W M1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M1_SET ns_noc_io_spio_soc_ip.csr 81762 M1 Mask interrupts for read channel 1 1 0x1 R/W M2 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M2_SET ns_noc_io_spio_soc_ip.csr 81773 M2 Mask interrupts for read channel 2 2 0x0 R/W M3 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M3_SET ns_noc_io_spio_soc_ip.csr 81784 M3 Mask interrupts for read channel 3 3 0x0 R/W M4 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M4_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M4_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M4_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M4_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M4_SET ns_noc_io_spio_soc_ip.csr 81795 M4 Mask interrupts for read channel 4 4 0x1 R/W UNSD_15_5 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_UNSD_15_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_UNSD_15_5_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_UNSD_15_5_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_UNSD_15_5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_UNSD_15_5_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_UNSD_15_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_UNSD_15_5_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 81806 UNSD_15_5 15 5 0x000 R M16 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M16_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M16_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M16_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M16_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M16_SET ns_noc_io_spio_soc_ip.csr 81817 M16 Mask interrupts for write channel 16 16 0x1 R/W M17 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M17_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M17_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M17_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M17_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M17_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M17_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M17_SET ns_noc_io_spio_soc_ip.csr 81828 M17 Mask interrupts for write channel 17 17 0x1 R/W M18 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M18_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M18_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M18_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M18_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M18_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M18_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M18_SET ns_noc_io_spio_soc_ip.csr 81839 M18 Mask interrupts for write channel 18 18 0x0 R/W M19 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M19_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M19_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M19_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M19_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M19_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M19_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M19_SET ns_noc_io_spio_soc_ip.csr 81850 M19 Mask interrupts for write channel 19 19 0x1 R/W UNSD_31_20 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_UNSD_31_20_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_UNSD_31_20_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_UNSD_31_20_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_UNSD_31_20_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_UNSD_31_20_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_UNSD_31_20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_UNSD_31_20_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_UNSD_31_20_SET ns_noc_io_spio_soc_ip.csr 81861 UNSD_31_20 31 20 0x000 R M32 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M32_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M32_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M32_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M32_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M32_SET ns_noc_io_spio_soc_ip.csr 81872 M32 Mask interrupt on traffic to PG layer 32 32 0x1 R/W M33 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M33_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M33_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M33_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M33_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M33_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M33_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M33_SET ns_noc_io_spio_soc_ip.csr 81883 M33 Mask interrupt on csr parity errors 33 33 0x0 R/W M34 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M34_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M34_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M34_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M34_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M34_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M34_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M34_SET ns_noc_io_spio_soc_ip.csr 81894 M34 RDATA parity interrupt Mask 34 34 0x1 R/W M35 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M35_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M35_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M35_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M35_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M35_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M35_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M35_SET ns_noc_io_spio_soc_ip.csr 81905 M35 RRESP parity interrupt Mask 35 35 0x1 R/W M36 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M36_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M36_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M36_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M36_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M36_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M36_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M36_SET ns_noc_io_spio_soc_ip.csr 81916 M36 BRESP parity interrupt Mask 36 36 0x1 R/W M37 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M37_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M37_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M37_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M37_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M37_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M37_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M37_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M37_SET ns_noc_io_spio_soc_ip.csr 81927 M37 AC parity interrupt Mask 37 37 0x1 R/W M38 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M38_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M38_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M38_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M38_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M38_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M38_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M38_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_M38_SET ns_noc_io_spio_soc_ip.csr 81938 M38 ACADDR parity interrupt Mask 38 38 0x1 R/W E39 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E39_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E39_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E39_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E39_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E39_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E39_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E39_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E39_SET ns_noc_io_spio_soc_ip.csr 81950 E39 1'b1: R Ch Cmdtbl Parity Err Intr Mask 39 39 0x0 R E40 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E40_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E40_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E40_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E40_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E40_SET ns_noc_io_spio_soc_ip.csr 81962 E40 1'b1: B Ch Cmdtbl Parity Err Intr Mask 40 40 0x0 R E41 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E41_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E41_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E41_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E41_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E41_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E41_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E41_SET ns_noc_io_spio_soc_ip.csr 81974 E41 1'b1: Rx Fifo Parity Err Intr Mask 41 41 0x0 R E42 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E42_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E42_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E42_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E42_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E42_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E42_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E42_SET ns_noc_io_spio_soc_ip.csr 81986 E42 1'b1: CRCD Ch Reorder Buffer Parity Err Intr Mask 42 42 0x0 R E43 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E43_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E43_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E43_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E43_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E43_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E43_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E43_SET ns_noc_io_spio_soc_ip.csr 81998 E43 1'b1: Ack Ch Wack Reorder Buffer Parity Err IntrMask 43 43 0x0 R E44 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E44_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E44_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E44_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E44_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E44_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E44_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E44_SET ns_noc_io_spio_soc_ip.csr 82010 E44 1'b1: Ack Ch Rack Reorder Buffer Parity Err Intr Mask 44 44 0x0 R E45 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E45_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E45_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E45_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E45_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E45_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E45_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E45_SET ns_noc_io_spio_soc_ip.csr 82022 E45 1'b1: B Ch Drain Fifo Parity Err Intr Mask 45 45 0x0 R E46 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E46_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E46_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E46_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E46_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E46_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E46_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E46_SET ns_noc_io_spio_soc_ip.csr 82034 E46 1'b1: R Ch Flush Fifo Parity Err Intr Mask 46 46 0x0 R E47 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E47_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E47_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E47_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E47_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E47_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E47_SET ns_noc_io_spio_soc_ip.csr 82046 E47 1'b1: R Ch Deinterleaver Cmdtbl Parity Err Intr Mask 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E48_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E48_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E48_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E48_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_E48_SET ns_noc_io_spio_soc_ip.csr 82058 E48 1'b1: R Ch Deinterleaver Data Buffer Parity Err Intr Mask 48 48 0x0 R UNSD_63_49 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_UNSD_63_49_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_UNSD_63_49_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_UNSD_63_49_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_UNSD_63_49_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_UNSD_63_49_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_UNSD_63_49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_UNSD_63_49_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_INTM_UNSD_63_49_SET ns_noc_io_spio_soc_ip.csr 82069 UNSD_63_49 63 49 0x0000 R register spio_noc.bridge_spio_p10_apb0_s_7_8_as_ccmd bridge_spio_p10_apb0_s_7_8_as_ccmd SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 82145 spio_p10_apb0_s register as_ccmd 0x1DF00 R/W 0x0000000003000000 Spio_noc_bridge_spio_p10_apb0_s_7_8_as_ccmd Not applicable for current release. false false false false UNSD_23_0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_UNSD_23_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_UNSD_23_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_UNSD_23_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_UNSD_23_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_UNSD_23_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_UNSD_23_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_UNSD_23_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_UNSD_23_0_SET ns_noc_io_spio_soc_ip.csr 82088 UNSD_23_0 23 0 0x000000 R rdy SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_RDY_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_RDY_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_RDY_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_RDY_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_RDY_SET ns_noc_io_spio_soc_ip.csr 82099 rdy 1'b1: Ready 24 24 0x1 R/W val SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_VAL_SET ns_noc_io_spio_soc_ip.csr 82110 val 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_UNSD_27_26_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_UNSD_27_26_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_UNSD_27_26_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_UNSD_27_26_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_UNSD_27_26_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_UNSD_27_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_UNSD_27_26_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_UNSD_27_26_SET ns_noc_io_spio_soc_ip.csr 82121 UNSD_27_26 27 26 0x0 R intfid SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_INTFID_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_INTFID_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_INTFID_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_INTFID_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_INTFID_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_INTFID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_INTFID_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_INTFID_SET ns_noc_io_spio_soc_ip.csr 82133 intfid 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_63_31 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_UNSD_63_31_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_UNSD_63_31_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_UNSD_63_31_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_UNSD_63_31_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_UNSD_63_31_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_UNSD_63_31_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_UNSD_63_31_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMD_UNSD_63_31_SET ns_noc_io_spio_soc_ip.csr 82144 UNSD_63_31 63 31 0x000000000 R register spio_noc.bridge_spio_p10_apb0_s_7_8_as_ccmdmsk bridge_spio_p10_apb0_s_7_8_as_ccmdmsk SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 82197 spio_p10_apb0_s register as_ccmdmsk 0x1DF08 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_apb0_s_7_8_as_ccmdmsk Not applicable for current release. false false false false UNSD_23_0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_UNSD_23_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_UNSD_23_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_UNSD_23_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_UNSD_23_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_UNSD_23_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_UNSD_23_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_UNSD_23_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_UNSD_23_0_SET ns_noc_io_spio_soc_ip.csr 82163 UNSD_23_0 23 0 0x000000 R rdy SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_RDY_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_RDY_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_RDY_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_RDY_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_RDY_SET ns_noc_io_spio_soc_ip.csr 82174 rdy 1'b1: Ready 24 24 0x0 R/W val SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_VAL_SET ns_noc_io_spio_soc_ip.csr 82185 val 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_UNSD_63_26_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_UNSD_63_26_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_UNSD_63_26_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_UNSD_63_26_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_UNSD_63_26_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_UNSD_63_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_UNSD_63_26_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CCMDMSK_UNSD_63_26_SET ns_noc_io_spio_soc_ip.csr 82196 UNSD_63_26 63 26 0x0000000000 R register spio_noc.bridge_spio_p10_apb0_s_7_8_as_cntr bridge_spio_p10_apb0_s_7_8_as_cntr SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CNTR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CNTR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CNTR_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CNTR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 82227 spio_p10_apb0_s register as_cntr 0x1DF10 R 0x0000000000000000 Spio_noc_bridge_spio_p10_apb0_s_7_8_as_cntr Not applicable for current release. false false false false CNTR SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CNTR_CNTR_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CNTR_CNTR_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CNTR_CNTR_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CNTR_CNTR_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CNTR_CNTR_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CNTR_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CNTR_CNTR_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CNTR_CNTR_SET ns_noc_io_spio_soc_ip.csr 82216 CNTR Counter 31 0 0x00000000 R UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CNTR_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CNTR_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CNTR_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CNTR_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CNTR_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CNTR_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CNTR_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_CNTR_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 82226 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p10_apb0_s_7_8_as_arovrd bridge_spio_p10_apb0_s_7_8_as_arovrd SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 82340 spio_p10_apb0_s register as_arovrd 0x1DF18 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_apb0_s_7_8_as_arovrd AR Overrides. false false false false arcache_val SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 82245 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 82258 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 82269 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 82280 UNSD_11_11 11 11 0x0 R arprot_enb SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 82293 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 82304 UNSD_15_15 15 15 0x0 R arqos_val SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 82315 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_ARQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 82328 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AROVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 82339 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_p10_apb0_s_7_8_as_awovrd bridge_spio_p10_apb0_s_7_8_as_awovrd SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 82453 spio_p10_apb0_s register as_awovrd 0x1DF20 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_apb0_s_7_8_as_awovrd AW Overrides. false false false false awcache_val SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 82358 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 82371 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 82382 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 82393 UNSD_11_11 11 11 0x0 R awprot_enb SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 82406 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 82417 UNSD_15_15 15 15 0x0 R awqos_val SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 82428 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_AWQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 82441 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_AS_AWOVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 82452 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_p10_apb0_s_7_8_p_0 bridge_spio_p10_apb0_s_7_8_p_0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 82518 spio_p10_apb0_s register p_0 0x1F000 R/W 0x00000003 Spio_noc_bridge_spio_p10_apb0_s_7_8_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_0_SET ns_noc_io_spio_soc_ip.csr 82481 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_1_SET ns_noc_io_spio_soc_ip.csr 82493 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_2_SET ns_noc_io_spio_soc_ip.csr 82505 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_0_WT_QOS_3_SET ns_noc_io_spio_soc_ip.csr 82517 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register spio_noc.bridge_spio_p10_apb0_s_7_8_p_1 bridge_spio_p10_apb0_s_7_8_p_1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 82584 spio_p10_apb0_s register p_1 0x1F008 R 0x00000000 Spio_noc_bridge_spio_p10_apb0_s_7_8_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_4_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_4_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_4_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_4_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_4_SET ns_noc_io_spio_soc_ip.csr 82547 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_5_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_5_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_5_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_5_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_5_SET ns_noc_io_spio_soc_ip.csr 82559 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_6_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_6_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_6_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_6_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_6_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_6_SET ns_noc_io_spio_soc_ip.csr 82571 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_7_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_7_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_7_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_7_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_7_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_1_WT_QOS_7_SET ns_noc_io_spio_soc_ip.csr 82583 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register spio_noc.bridge_spio_p10_apb0_s_7_8_p_2 bridge_spio_p10_apb0_s_7_8_p_2 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 82650 spio_p10_apb0_s register p_2 0x1F010 R 0x00000000 Spio_noc_bridge_spio_p10_apb0_s_7_8_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_8_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_8_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_8_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_8_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_8_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_8_SET ns_noc_io_spio_soc_ip.csr 82613 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_9_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_9_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_9_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_9_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_9_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_9_SET ns_noc_io_spio_soc_ip.csr 82625 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_10_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_10_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_10_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_10_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_10_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_10_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_10_SET ns_noc_io_spio_soc_ip.csr 82637 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_11_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_11_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_11_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_11_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_11_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_2_WT_QOS_11_SET ns_noc_io_spio_soc_ip.csr 82649 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register spio_noc.bridge_spio_p10_apb0_s_7_8_p_3 bridge_spio_p10_apb0_s_7_8_p_3 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 82716 spio_p10_apb0_s register p_3 0x1F018 R 0x00000000 Spio_noc_bridge_spio_p10_apb0_s_7_8_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_12_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_12_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_12_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_12_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_12_SET ns_noc_io_spio_soc_ip.csr 82679 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_13_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_13_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_13_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_13_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_13_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_13_SET ns_noc_io_spio_soc_ip.csr 82691 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_14_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_14_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_14_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_14_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_14_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_14_SET ns_noc_io_spio_soc_ip.csr 82703 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_15_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_15_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_15_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_15_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_15_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_P_3_WT_QOS_15_SET ns_noc_io_spio_soc_ip.csr 82715 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register spio_noc.bridge_spio_p10_apb0_s_7_8_txe bridge_spio_p10_apb0_s_7_8_txe SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 82862 spio_p10_apb0_s register txe 0x1F040 R/W 0x00000000 Spio_noc_bridge_spio_p10_apb0_s_7_8_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_TRANS_WITHOUT_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_TRANS_WITHOUT_SOP_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_TRANS_WITHOUT_SOP_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_TRANS_WITHOUT_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_TRANS_WITHOUT_SOP_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_TRANS_WITHOUT_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_TRANS_WITHOUT_SOP_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_spio_soc_ip.csr 82743 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_SOP_AFTER_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_SOP_AFTER_SOP_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_SOP_AFTER_SOP_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_SOP_AFTER_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_SOP_AFTER_SOP_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_SOP_AFTER_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_SOP_AFTER_SOP_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_SOP_AFTER_SOP_SET ns_noc_io_spio_soc_ip.csr 82755 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 82770 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 82783 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_spio_soc_ip.csr 82797 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_spio_soc_ip.csr 82811 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_spio_soc_ip.csr 82825 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_spio_soc_ip.csr 82839 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 82850 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXE_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 82861 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_p10_apb0_s_7_8_txem bridge_spio_p10_apb0_s_7_8_txem SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 82941 spio_p10_apb0_s register txem 0x1F048 R/W 0x00000008 Spio_noc_bridge_spio_p10_apb0_s_7_8_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_UNSD_1_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_UNSD_1_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_UNSD_1_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_UNSD_1_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_UNSD_1_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_UNSD_1_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_UNSD_1_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_UNSD_1_0_SET ns_noc_io_spio_soc_ip.csr 82885 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 82896 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 82907 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_UNSD_7_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_UNSD_7_4_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_UNSD_7_4_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_UNSD_7_4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_UNSD_7_4_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_UNSD_7_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_UNSD_7_4_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_UNSD_7_4_SET ns_noc_io_spio_soc_ip.csr 82918 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 82929 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_TXEM_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 82940 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_p10_apb0_s_7_8_btus_0 bridge_spio_p10_apb0_s_7_8_btus_0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 83309 spio_p10_apb0_s register btus_0 0x1F058 R 0x00000000 Spio_noc_bridge_spio_p10_apb0_s_7_8_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_A_SET ns_noc_io_spio_soc_ip.csr 82967 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_B_SET ns_noc_io_spio_soc_ip.csr 82978 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_C_SET ns_noc_io_spio_soc_ip.csr 82989 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L0_D_SET ns_noc_io_spio_soc_ip.csr 83000 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_A_SET ns_noc_io_spio_soc_ip.csr 83011 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_B_SET ns_noc_io_spio_soc_ip.csr 83022 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_C_SET ns_noc_io_spio_soc_ip.csr 83033 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L1_D_SET ns_noc_io_spio_soc_ip.csr 83044 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_A_SET ns_noc_io_spio_soc_ip.csr 83055 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_B_SET ns_noc_io_spio_soc_ip.csr 83066 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_C_SET ns_noc_io_spio_soc_ip.csr 83077 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L2_D_SET ns_noc_io_spio_soc_ip.csr 83088 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_A_SET ns_noc_io_spio_soc_ip.csr 83099 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_B_SET ns_noc_io_spio_soc_ip.csr 83110 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_C_SET ns_noc_io_spio_soc_ip.csr 83121 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L3_D_SET ns_noc_io_spio_soc_ip.csr 83132 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_A_SET ns_noc_io_spio_soc_ip.csr 83143 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_B_SET ns_noc_io_spio_soc_ip.csr 83154 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_C_SET ns_noc_io_spio_soc_ip.csr 83165 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L4_D_SET ns_noc_io_spio_soc_ip.csr 83176 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_A_SET ns_noc_io_spio_soc_ip.csr 83187 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_B_SET ns_noc_io_spio_soc_ip.csr 83198 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_C_SET ns_noc_io_spio_soc_ip.csr 83209 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L5_D_SET ns_noc_io_spio_soc_ip.csr 83220 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_A_SET ns_noc_io_spio_soc_ip.csr 83231 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_B_SET ns_noc_io_spio_soc_ip.csr 83242 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_C_SET ns_noc_io_spio_soc_ip.csr 83253 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L6_D_SET ns_noc_io_spio_soc_ip.csr 83264 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_A_SET ns_noc_io_spio_soc_ip.csr 83275 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_B_SET ns_noc_io_spio_soc_ip.csr 83286 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_C_SET ns_noc_io_spio_soc_ip.csr 83297 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_0_L7_D_SET ns_noc_io_spio_soc_ip.csr 83308 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register spio_noc.bridge_spio_p10_apb0_s_7_8_btus_1 bridge_spio_p10_apb0_s_7_8_btus_1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 83677 spio_p10_apb0_s register btus_1 0x1F060 R 0x00000000 Spio_noc_bridge_spio_p10_apb0_s_7_8_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_A_SET ns_noc_io_spio_soc_ip.csr 83335 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_B_SET ns_noc_io_spio_soc_ip.csr 83346 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_C_SET ns_noc_io_spio_soc_ip.csr 83357 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L8_D_SET ns_noc_io_spio_soc_ip.csr 83368 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_A_SET ns_noc_io_spio_soc_ip.csr 83379 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_B_SET ns_noc_io_spio_soc_ip.csr 83390 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_C_SET ns_noc_io_spio_soc_ip.csr 83401 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L9_D_SET ns_noc_io_spio_soc_ip.csr 83412 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_A_SET ns_noc_io_spio_soc_ip.csr 83423 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_B_SET ns_noc_io_spio_soc_ip.csr 83434 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_C_SET ns_noc_io_spio_soc_ip.csr 83445 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L10_D_SET ns_noc_io_spio_soc_ip.csr 83456 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_A_SET ns_noc_io_spio_soc_ip.csr 83467 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_B_SET ns_noc_io_spio_soc_ip.csr 83478 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_C_SET ns_noc_io_spio_soc_ip.csr 83489 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L11_D_SET ns_noc_io_spio_soc_ip.csr 83500 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_A_SET ns_noc_io_spio_soc_ip.csr 83511 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_B_SET ns_noc_io_spio_soc_ip.csr 83522 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_C_SET ns_noc_io_spio_soc_ip.csr 83533 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L12_D_SET ns_noc_io_spio_soc_ip.csr 83544 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_A_SET ns_noc_io_spio_soc_ip.csr 83555 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_B_SET ns_noc_io_spio_soc_ip.csr 83566 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_C_SET ns_noc_io_spio_soc_ip.csr 83577 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L13_D_SET ns_noc_io_spio_soc_ip.csr 83588 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_A_SET ns_noc_io_spio_soc_ip.csr 83599 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_B_SET ns_noc_io_spio_soc_ip.csr 83610 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_C_SET ns_noc_io_spio_soc_ip.csr 83621 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L14_D_SET ns_noc_io_spio_soc_ip.csr 83632 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_A_SET ns_noc_io_spio_soc_ip.csr 83643 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_B_SET ns_noc_io_spio_soc_ip.csr 83654 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_C_SET ns_noc_io_spio_soc_ip.csr 83665 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTUS_1_L15_D_SET ns_noc_io_spio_soc_ip.csr 83676 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register spio_noc.bridge_spio_p10_apb0_s_7_8_btrl_0 bridge_spio_p10_apb0_s_7_8_btrl_0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 83753 spio_p10_apb0_s register btrl_0 0x1F080 R 0x00000000 Spio_noc_bridge_spio_p10_apb0_s_7_8_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_WT_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_WT_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_WT_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_WT_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_WT_SET ns_noc_io_spio_soc_ip.csr 83701 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 83712 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_CNT_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_CNT_SET ns_noc_io_spio_soc_ip.csr 83727 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_EN_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_EN_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_EN_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_EN_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_EN_SET ns_noc_io_spio_soc_ip.csr 83741 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_0_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 83752 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p10_apb0_s_7_8_btrl_1 bridge_spio_p10_apb0_s_7_8_btrl_1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 83829 spio_p10_apb0_s register btrl_1 0x1F088 R 0x00000000 Spio_noc_bridge_spio_p10_apb0_s_7_8_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_WT_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_WT_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_WT_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_WT_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_WT_SET ns_noc_io_spio_soc_ip.csr 83777 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 83788 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_CNT_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_CNT_SET ns_noc_io_spio_soc_ip.csr 83803 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_EN_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_EN_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_EN_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_EN_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_EN_SET ns_noc_io_spio_soc_ip.csr 83817 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_1_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 83828 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p10_apb0_s_7_8_btrl_2 bridge_spio_p10_apb0_s_7_8_btrl_2 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 83905 spio_p10_apb0_s register btrl_2 0x1F090 R 0x00000000 Spio_noc_bridge_spio_p10_apb0_s_7_8_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_WT_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_WT_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_WT_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_WT_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_WT_SET ns_noc_io_spio_soc_ip.csr 83853 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 83864 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_CNT_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_CNT_SET ns_noc_io_spio_soc_ip.csr 83879 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_EN_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_EN_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_EN_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_EN_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_EN_SET ns_noc_io_spio_soc_ip.csr 83893 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_2_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 83904 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p10_apb0_s_7_8_btrl_3 bridge_spio_p10_apb0_s_7_8_btrl_3 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 83981 spio_p10_apb0_s register btrl_3 0x1F098 R 0x00000000 Spio_noc_bridge_spio_p10_apb0_s_7_8_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_WT_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_WT_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_WT_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_WT_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_WT_SET ns_noc_io_spio_soc_ip.csr 83929 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 83940 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_CNT_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_CNT_SET ns_noc_io_spio_soc_ip.csr 83955 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_EN_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_EN_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_EN_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_EN_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_EN_SET ns_noc_io_spio_soc_ip.csr 83969 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTRL_3_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 83980 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p10_apb0_s_7_8_btperr bridge_spio_p10_apb0_s_7_8_btperr SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 84183 spio_p10_apb0_s register btperr 0x1F0A8 R/W 0x00000000 Spio_noc_bridge_spio_p10_apb0_s_7_8_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L0_SET ns_noc_io_spio_soc_ip.csr 84006 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L1_SET ns_noc_io_spio_soc_ip.csr 84017 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L2_SET ns_noc_io_spio_soc_ip.csr 84028 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L3_SET ns_noc_io_spio_soc_ip.csr 84039 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L4_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L4_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L4_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L4_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L4_SET ns_noc_io_spio_soc_ip.csr 84050 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L5_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L5_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L5_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L5_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L5_SET ns_noc_io_spio_soc_ip.csr 84061 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L6_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L6_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L6_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L6_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L6_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L6_SET ns_noc_io_spio_soc_ip.csr 84072 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L7_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L7_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L7_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L7_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L7_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L7_SET ns_noc_io_spio_soc_ip.csr 84083 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L8_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L8_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L8_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L8_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L8_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L8_SET ns_noc_io_spio_soc_ip.csr 84094 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L9_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L9_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L9_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L9_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L9_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L9_SET ns_noc_io_spio_soc_ip.csr 84105 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L10_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L10_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L10_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L10_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L10_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L10_SET ns_noc_io_spio_soc_ip.csr 84116 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L11_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L11_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L11_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L11_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L11_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L11_SET ns_noc_io_spio_soc_ip.csr 84127 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L12_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L12_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L12_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L12_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L12_SET ns_noc_io_spio_soc_ip.csr 84138 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L13_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L13_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L13_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L13_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L13_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L13_SET ns_noc_io_spio_soc_ip.csr 84149 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L14_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L14_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L14_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L14_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L14_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L14_SET ns_noc_io_spio_soc_ip.csr 84160 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L15_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L15_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L15_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L15_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L15_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_L15_SET ns_noc_io_spio_soc_ip.csr 84171 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_UNSD_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERR_UNSD_SET ns_noc_io_spio_soc_ip.csr 84182 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_p10_apb0_s_7_8_btperrm bridge_spio_p10_apb0_s_7_8_btperrm SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 84383 spio_p10_apb0_s register btperrm 0x1F0B0 R/W 0x00000000 Spio_noc_bridge_spio_p10_apb0_s_7_8_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L0_SET ns_noc_io_spio_soc_ip.csr 84206 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L1_SET ns_noc_io_spio_soc_ip.csr 84217 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L2_SET ns_noc_io_spio_soc_ip.csr 84228 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L3_SET ns_noc_io_spio_soc_ip.csr 84239 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L4_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L4_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L4_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L4_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L4_SET ns_noc_io_spio_soc_ip.csr 84250 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L5_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L5_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L5_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L5_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L5_SET ns_noc_io_spio_soc_ip.csr 84261 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L6_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L6_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L6_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L6_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L6_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L6_SET ns_noc_io_spio_soc_ip.csr 84272 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L7_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L7_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L7_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L7_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L7_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L7_SET ns_noc_io_spio_soc_ip.csr 84283 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L8_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L8_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L8_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L8_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L8_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L8_SET ns_noc_io_spio_soc_ip.csr 84294 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L9_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L9_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L9_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L9_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L9_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L9_SET ns_noc_io_spio_soc_ip.csr 84305 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L10_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L10_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L10_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L10_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L10_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L10_SET ns_noc_io_spio_soc_ip.csr 84316 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L11_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L11_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L11_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L11_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L11_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L11_SET ns_noc_io_spio_soc_ip.csr 84327 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L12_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L12_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L12_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L12_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L12_SET ns_noc_io_spio_soc_ip.csr 84338 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L13_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L13_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L13_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L13_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L13_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L13_SET ns_noc_io_spio_soc_ip.csr 84349 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L14_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L14_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L14_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L14_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L14_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L14_SET ns_noc_io_spio_soc_ip.csr 84360 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L15_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L15_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L15_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L15_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L15_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_L15_SET ns_noc_io_spio_soc_ip.csr 84371 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_UNSD_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BTPERRM_UNSD_SET ns_noc_io_spio_soc_ip.csr 84382 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_p10_apb0_s_7_8_rxe bridge_spio_p10_apb0_s_7_8_rxe SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 84491 spio_p10_apb0_s register rxe 0x1F120 R/W 0x00000000 Spio_noc_bridge_spio_p10_apb0_s_7_8_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_A_SET ns_noc_io_spio_soc_ip.csr 84411 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_B_SET ns_noc_io_spio_soc_ip.csr 84422 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_C_SET ns_noc_io_spio_soc_ip.csr 84433 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_CRC_OFLW_D_SET ns_noc_io_spio_soc_ip.csr 84444 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_EVC_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_EVC_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_EVC_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_EVC_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_EVC_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_EVC_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_EVC_OFLW_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_EVC_OFLW_SET ns_noc_io_spio_soc_ip.csr 84456 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 84467 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_EVC1_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_EVC1_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_EVC1_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_EVC1_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_EVC1_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_EVC1_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_EVC1_OFLW_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_EVC1_OFLW_SET ns_noc_io_spio_soc_ip.csr 84479 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXE_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 84490 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_p10_apb0_s_7_8_rxem bridge_spio_p10_apb0_s_7_8_rxem SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 84563 spio_p10_apb0_s register rxem 0x1F128 R/W 0x00000050 Spio_noc_bridge_spio_p10_apb0_s_7_8_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_UNSD_3_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_UNSD_3_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_UNSD_3_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_UNSD_3_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_UNSD_3_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_UNSD_3_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_UNSD_3_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_UNSD_3_0_SET ns_noc_io_spio_soc_ip.csr 84512 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_EVC_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_EVC_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_EVC_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_EVC_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_EVC_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_EVC_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_EVC_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_EVC_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 84526 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 84537 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_EVC1_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_EVC1_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_EVC1_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_EVC1_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_EVC1_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_EVC1_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_EVC1_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 84551 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_RXEM_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 84562 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_p10_apb0_s_7_8_brs_0 bridge_spio_p10_apb0_s_7_8_brs_0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 84837 spio_p10_apb0_s register brs_0 0x1F130 R 0x00000000 Spio_noc_bridge_spio_p10_apb0_s_7_8_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 84587 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_0_SET ns_noc_io_spio_soc_ip.csr 84598 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_0_SET ns_noc_io_spio_soc_ip.csr 84609 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_0_SET ns_noc_io_spio_soc_ip.csr 84620 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_0_SET ns_noc_io_spio_soc_ip.csr 84631 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 84641 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 84652 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_1_SET ns_noc_io_spio_soc_ip.csr 84663 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_1_SET ns_noc_io_spio_soc_ip.csr 84674 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_1_SET ns_noc_io_spio_soc_ip.csr 84685 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_1_SET ns_noc_io_spio_soc_ip.csr 84696 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 84706 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 84717 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_2_SET ns_noc_io_spio_soc_ip.csr 84728 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_2_SET ns_noc_io_spio_soc_ip.csr 84739 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_2_SET ns_noc_io_spio_soc_ip.csr 84750 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_2_SET ns_noc_io_spio_soc_ip.csr 84761 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 84771 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 84782 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_V_3_SET ns_noc_io_spio_soc_ip.csr 84793 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_S_3_SET ns_noc_io_spio_soc_ip.csr 84804 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_B_3_SET ns_noc_io_spio_soc_ip.csr 84815 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_F_3_SET ns_noc_io_spio_soc_ip.csr 84826 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_0_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 84836 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_p10_apb0_s_7_8_brs_1 bridge_spio_p10_apb0_s_7_8_brs_1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 85111 spio_p10_apb0_s register brs_1 0x1F138 R 0x00000000 Spio_noc_bridge_spio_p10_apb0_s_7_8_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 84861 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_0_SET ns_noc_io_spio_soc_ip.csr 84872 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_0_SET ns_noc_io_spio_soc_ip.csr 84883 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_0_SET ns_noc_io_spio_soc_ip.csr 84894 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_0_SET ns_noc_io_spio_soc_ip.csr 84905 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 84915 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 84926 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_1_SET ns_noc_io_spio_soc_ip.csr 84937 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_1_SET ns_noc_io_spio_soc_ip.csr 84948 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_1_SET ns_noc_io_spio_soc_ip.csr 84959 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_1_SET ns_noc_io_spio_soc_ip.csr 84970 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 84980 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 84991 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_2_SET ns_noc_io_spio_soc_ip.csr 85002 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_2_SET ns_noc_io_spio_soc_ip.csr 85013 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_2_SET ns_noc_io_spio_soc_ip.csr 85024 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_2_SET ns_noc_io_spio_soc_ip.csr 85035 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 85045 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 85056 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_V_3_SET ns_noc_io_spio_soc_ip.csr 85067 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_S_3_SET ns_noc_io_spio_soc_ip.csr 85078 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_B_3_SET ns_noc_io_spio_soc_ip.csr 85089 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_F_3_SET ns_noc_io_spio_soc_ip.csr 85100 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRS_1_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 85110 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_p10_apb0_s_7_8_brus bridge_spio_p10_apb0_s_7_8_brus SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 85180 spio_p10_apb0_s register brus 0x1F1B0 R 0x00000000 Spio_noc_bridge_spio_p10_apb0_s_7_8_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_A_SET ns_noc_io_spio_soc_ip.csr 85136 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_B_SET ns_noc_io_spio_soc_ip.csr 85147 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_C_SET ns_noc_io_spio_soc_ip.csr 85158 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_V_D_SET ns_noc_io_spio_soc_ip.csr 85169 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_UNSD_31_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_UNSD_31_4_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_UNSD_31_4_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_UNSD_31_4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_UNSD_31_4_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_UNSD_31_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_UNSD_31_4_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRUS_UNSD_31_4_SET ns_noc_io_spio_soc_ip.csr 85179 UNSD_31_4 31 4 0x0000000 R register spio_noc.bridge_spio_p10_apb0_s_7_8_brperr0 bridge_spio_p10_apb0_s_7_8_brperr0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 85408 spio_p10_apb0_s register brperr0 0x1F1D0 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_apb0_s_7_8_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_D0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_D0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_D0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_D0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_D0_SET ns_noc_io_spio_soc_ip.csr 85218 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_DC0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_DC0_SET ns_noc_io_spio_soc_ip.csr 85229 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SB0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SB0_SET ns_noc_io_spio_soc_ip.csr 85240 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SBC0_SET ns_noc_io_spio_soc_ip.csr 85252 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_PK0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_PK0_SET ns_noc_io_spio_soc_ip.csr 85263 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 85274 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_D1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_D1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_D1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_D1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_D1_SET ns_noc_io_spio_soc_ip.csr 85285 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_DC1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_DC1_SET ns_noc_io_spio_soc_ip.csr 85296 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SB1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SB1_SET ns_noc_io_spio_soc_ip.csr 85307 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_SBC1_SET ns_noc_io_spio_soc_ip.csr 85319 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_PK1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_PK1_SET ns_noc_io_spio_soc_ip.csr 85330 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 85341 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 85352 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 85363 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 85374 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 85385 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 85396 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 85407 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p10_apb0_s_7_8_brperr1 bridge_spio_p10_apb0_s_7_8_brperr1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 85524 spio_p10_apb0_s register brperr1 0x1F1D8 R 0x0000000000000000 Spio_noc_bridge_spio_p10_apb0_s_7_8_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 85446 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 85457 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 85468 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 85479 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 85490 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 85501 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 85512 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERR1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 85523 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p10_apb0_s_7_8_brperrm0 bridge_spio_p10_apb0_s_7_8_brperrm0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 85745 spio_p10_apb0_s register brperrm0 0x1F1E0 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_apb0_s_7_8_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_D0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_D0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_D0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_D0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_D0_SET ns_noc_io_spio_soc_ip.csr 85551 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_DC0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_DC0_SET ns_noc_io_spio_soc_ip.csr 85563 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SB0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SB0_SET ns_noc_io_spio_soc_ip.csr 85574 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SBC0_SET ns_noc_io_spio_soc_ip.csr 85586 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_PK0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_PK0_SET ns_noc_io_spio_soc_ip.csr 85598 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 85609 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_D1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_D1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_D1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_D1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_D1_SET ns_noc_io_spio_soc_ip.csr 85620 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_DC1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_DC1_SET ns_noc_io_spio_soc_ip.csr 85632 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SB1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SB1_SET ns_noc_io_spio_soc_ip.csr 85643 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_SBC1_SET ns_noc_io_spio_soc_ip.csr 85655 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_PK1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_PK1_SET ns_noc_io_spio_soc_ip.csr 85667 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 85678 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 85689 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 85700 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 85711 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 85722 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 85733 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 85744 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p10_apb0_s_7_8_brperrm1 bridge_spio_p10_apb0_s_7_8_brperrm1 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 85850 spio_p10_apb0_s register brperrm1 0x1F1E8 R 0x0000000000000000 Spio_noc_bridge_spio_p10_apb0_s_7_8_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 85772 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 85783 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 85794 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 85805 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 85816 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 85827 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 85838 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P10_APB0_S_7_8_BRPERRM1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 85849 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p10_apb1_s_8_8_apbslv_bridge_version bridge_spio_p10_apb1_s_8_8_apbslv_bridge_version SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_VERSION_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_VERSION_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_VERSION_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_VERSION_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 85878 spio_p10_apb1_s register apbslv_bridge_version 0x20200 R 0x0000000000000000 Spio_noc_bridge_spio_p10_apb1_s_8_8_apbslv_bridge_version Bridge version register. false false false false VER SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_VERSION_VER_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_VERSION_VER_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_VERSION_VER_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_VERSION_VER_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_VERSION_VER_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_VERSION_VER_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_VERSION_VER_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_VERSION_VER_SET ns_noc_io_spio_soc_ip.csr 85867 VER Bridge version. 3 0 0x0 R UNSD_63_4 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_VERSION_UNSD_63_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_VERSION_UNSD_63_4_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_VERSION_UNSD_63_4_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_VERSION_UNSD_63_4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_VERSION_UNSD_63_4_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_VERSION_UNSD_63_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_VERSION_UNSD_63_4_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_VERSION_UNSD_63_4_SET ns_noc_io_spio_soc_ip.csr 85877 UNSD_63_4 63 4 0x000000000000000 R register spio_noc.bridge_spio_p10_apb1_s_8_8_apbslv_bridge_id bridge_spio_p10_apb1_s_8_8_apbslv_bridge_id SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_ID_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_ID_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_ID_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 85918 spio_p10_apb1_s register apbslv_bridge_id 0x20208 R 0x0000000000000008 Spio_noc_bridge_spio_p10_apb1_s_8_8_apbslv_bridge_id Bridge ID register. false false false false ID SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_ID_ID_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_ID_ID_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_ID_ID_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_ID_ID_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_ID_ID_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_ID_ID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_ID_ID_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_ID_ID_SET ns_noc_io_spio_soc_ip.csr 85895 ID Unique bridge id. 9 0 0x008 R ZEROES SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_ID_ZEROES_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_ID_ZEROES_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_ID_ZEROES_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_ID_ZEROES_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_ID_ZEROES_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_ID_ZEROES_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_ID_ZEROES_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_ID_ZEROES_SET ns_noc_io_spio_soc_ip.csr 85906 ZEROES Zeroes 15 10 0x00 R UNSD_63_16 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_ID_UNSD_63_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_ID_UNSD_63_16_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_ID_UNSD_63_16_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_ID_UNSD_63_16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_ID_UNSD_63_16_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_ID_UNSD_63_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_ID_UNSD_63_16_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_spio_soc_ip.csr 85917 UNSD_63_16 Unused 63 16 0x000000000000 R register spio_noc.bridge_spio_p10_apb1_s_8_8_apbslv_slvs_sleep_status bridge_spio_p10_apb1_s_8_8_apbslv_slvs_sleep_status SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 86127 spio_p10_apb1_s register apbslv_slvs_sleep_status 0x20210 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_apb1_s_8_8_apbslv_slvs_sleep_status Slave sleep status register. false false false false STS_0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_0_SET ns_noc_io_spio_soc_ip.csr 85935 STS_0 1'b1: Slave is in sleep mode 1'b0: Slave is active 0 0 0x0 R/W STS_1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_1_SET ns_noc_io_spio_soc_ip.csr 85947 STS_1 1'b1: Slave is in sleep mode 1'b0: Slave is active 1 1 0x0 R/W STS_2 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_2_SET ns_noc_io_spio_soc_ip.csr 85959 STS_2 1'b1: Slave is in sleep mode 1'b0: Slave is active 2 2 0x0 R/W STS_3 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_3_SET ns_noc_io_spio_soc_ip.csr 85971 STS_3 1'b1: Slave is in sleep mode 1'b0: Slave is active 3 3 0x0 R/W STS_4 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_4_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_4_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_4_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_4_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_4_SET ns_noc_io_spio_soc_ip.csr 85983 STS_4 1'b1: Slave is in sleep mode 1'b0: Slave is active 4 4 0x0 R/W STS_5 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_5_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_5_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_5_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_5_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_5_SET ns_noc_io_spio_soc_ip.csr 85995 STS_5 1'b1: Slave is in sleep mode 1'b0: Slave is active 5 5 0x0 R/W STS_6 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_6_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_6_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_6_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_6_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_6_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_6_SET ns_noc_io_spio_soc_ip.csr 86007 STS_6 1'b1: Slave is in sleep mode 1'b0: Slave is active 6 6 0x0 R/W STS_7 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_7_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_7_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_7_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_7_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_7_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_7_SET ns_noc_io_spio_soc_ip.csr 86019 STS_7 1'b1: Slave is in sleep mode 1'b0: Slave is active 7 7 0x0 R/W STS_8 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_8_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_8_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_8_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_8_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_8_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_8_SET ns_noc_io_spio_soc_ip.csr 86031 STS_8 1'b1: Slave is in sleep mode 1'b0: Slave is active 8 8 0x0 R/W STS_9 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_9_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_9_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_9_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_9_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_9_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_9_SET ns_noc_io_spio_soc_ip.csr 86043 STS_9 1'b1: Slave is in sleep mode 1'b0: Slave is active 9 9 0x0 R/W STS_10 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_10_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_10_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_10_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_10_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_10_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_10_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_10_SET ns_noc_io_spio_soc_ip.csr 86055 STS_10 1'b1: Slave is in sleep mode 1'b0: Slave is active 10 10 0x0 R/W STS_11 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_11_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_11_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_11_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_11_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_11_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_11_SET ns_noc_io_spio_soc_ip.csr 86067 STS_11 1'b1: Slave is in sleep mode 1'b0: Slave is active 11 11 0x0 R/W STS_12 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_12_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_12_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_12_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_12_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_12_SET ns_noc_io_spio_soc_ip.csr 86079 STS_12 1'b1: Slave is in sleep mode 1'b0: Slave is active 12 12 0x0 R/W STS_13 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_13_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_13_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_13_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_13_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_13_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_13_SET ns_noc_io_spio_soc_ip.csr 86091 STS_13 1'b1: Slave is in sleep mode 1'b0: Slave is active 13 13 0x0 R/W STS_14 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_14_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_14_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_14_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_14_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_14_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_14_SET ns_noc_io_spio_soc_ip.csr 86103 STS_14 1'b1: Slave is in sleep mode 1'b0: Slave is active 14 14 0x0 R/W STS_15 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_15_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_15_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_15_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_15_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_15_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_STS_15_SET ns_noc_io_spio_soc_ip.csr 86115 STS_15 1'b1: Slave is in sleep mode 1'b0: Slave is active 15 15 0x0 R/W UNSD_63_16 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_SET ns_noc_io_spio_soc_ip.csr 86126 UNSD_63_16 63 16 0x000000000000 R register spio_noc.bridge_spio_p10_apb1_s_8_8_as_cgc bridge_spio_p10_apb1_s_8_8_as_cgc SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGC_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGC_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGC_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 86164 spio_p10_apb1_s register as_cgc 0x21C10 R/W 0x0000000000000064 Spio_noc_bridge_spio_p10_apb1_s_8_8_as_cgc Programmable intervals used by coarse clock gating logic. This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGC_HYSTERESIS_COUNTER_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGC_HYSTERESIS_COUNTER_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGC_HYSTERESIS_COUNTER_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGC_HYSTERESIS_COUNTER_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGC_HYSTERESIS_COUNTER_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGC_HYSTERESIS_COUNTER_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGC_HYSTERESIS_COUNTER_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_spio_soc_ip.csr 86152 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGC_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGC_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGC_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGC_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGC_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGC_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGC_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGC_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 86163 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p10_apb1_s_8_8_as_cgo bridge_spio_p10_apb1_s_8_8_as_cgo SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGO_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGO_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGO_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGO_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 86199 spio_p10_apb1_s register as_cgo 0x21C18 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_apb1_s_8_8_as_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the slave bridge. false false false false FPO SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGO_FPO_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGO_FPO_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGO_FPO_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGO_FPO_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGO_FPO_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGO_FPO_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGO_FPO_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGO_FPO_SET ns_noc_io_spio_soc_ip.csr 86187 FPO 1'b1: Clock gating override enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGO_UNSD_63_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGO_UNSD_63_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGO_UNSD_63_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGO_UNSD_63_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGO_UNSD_63_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGO_UNSD_63_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGO_UNSD_63_1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CGO_UNSD_63_1_SET ns_noc_io_spio_soc_ip.csr 86198 UNSD_63_1 63 1 0x0000000000000000 R register spio_noc.bridge_spio_p10_apb1_s_8_8_as_sts bridge_spio_p10_apb1_s_8_8_as_sts SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 86273 spio_p10_apb1_s register as_sts 0x21D00 R 0x000000000000000c Spio_noc_bridge_spio_p10_apb1_s_8_8_as_sts Slave bridge status bits. false false false false WOF SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_WOF_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_WOF_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_WOF_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_WOF_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_WOF_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_WOF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_WOF_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_WOF_SET ns_noc_io_spio_soc_ip.csr 86222 WOF 1'b1: Maximum number of supported write commands are outstanding to the attached slave device awaiting response, no more write commands will be issued to slave till responses are received. 1'b0: Slave device can expect more write commands from NoC 0 0 0x0 R ROF SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_ROF_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_ROF_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_ROF_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_ROF_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_ROF_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_ROF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_ROF_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_ROF_SET ns_noc_io_spio_soc_ip.csr 86238 ROF 1'b1: Maximum number of supported read commands are outstanding to the attached slave device awaiting response, no more read commands will be issued to slave till responses are received. 1'b0: Slave bridge can accept more read commands from the NoC 1 1 0x0 R WOE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_WOE_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_WOE_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_WOE_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_WOE_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_WOE_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_WOE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_WOE_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_WOE_SET ns_noc_io_spio_soc_ip.csr 86250 WOE 1'b1: There are no write commands outstanding to the attached slave device 2 2 0x1 R ROE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_ROE_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_ROE_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_ROE_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_ROE_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_ROE_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_ROE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_ROE_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_ROE_SET ns_noc_io_spio_soc_ip.csr 86262 ROE 1'b1: There are no read commands outstanding to the attached slave device 3 3 0x1 R UNSD_63_4 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_UNSD_63_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_UNSD_63_4_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_UNSD_63_4_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_UNSD_63_4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_UNSD_63_4_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_UNSD_63_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_UNSD_63_4_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_STS_UNSD_63_4_SET ns_noc_io_spio_soc_ip.csr 86272 UNSD_63_4 63 4 0x000000000000000 R register spio_noc.bridge_spio_p10_apb1_s_8_8_as_bridge_id bridge_spio_p10_apb1_s_8_8_as_bridge_id SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_BRIDGE_ID_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_BRIDGE_ID_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_BRIDGE_ID_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_BRIDGE_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 86303 spio_p10_apb1_s register as_bridge_id 0x21D08 R 0x0000000000000008 Spio_noc_bridge_spio_p10_apb1_s_8_8_as_bridge_id Unique identifier assigned to the slave bridge. false false false false ID SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_BRIDGE_ID_ID_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_BRIDGE_ID_ID_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_BRIDGE_ID_ID_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_BRIDGE_ID_ID_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_BRIDGE_ID_ID_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_BRIDGE_ID_ID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_BRIDGE_ID_ID_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_BRIDGE_ID_ID_SET ns_noc_io_spio_soc_ip.csr 86292 ID Unique bridge ID 15 0 0x0008 R UNSD_63_16 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_BRIDGE_ID_UNSD_63_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_BRIDGE_ID_UNSD_63_16_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_BRIDGE_ID_UNSD_63_16_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_BRIDGE_ID_UNSD_63_16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_BRIDGE_ID_UNSD_63_16_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_BRIDGE_ID_UNSD_63_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_BRIDGE_ID_UNSD_63_16_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_spio_soc_ip.csr 86302 UNSD_63_16 63 16 0x000000000000 R register spio_noc.bridge_spio_p10_apb1_s_8_8_as_err bridge_spio_p10_apb1_s_8_8_as_err SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 86656 spio_p10_apb1_s register as_err 0x21E00 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_apb1_s_8_8_as_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E0_SET ns_noc_io_spio_soc_ip.csr 86324 E0 1'b1: Read decode error response: Decode error response received from slave device for read command 0 0 0x0 R/W E1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E1_SET ns_noc_io_spio_soc_ip.csr 86336 E1 1'b1: Read slave error response: Slave error response received from slave device for read command 1 1 0x0 R/W E2 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E2_SET ns_noc_io_spio_soc_ip.csr 86349 E2 1'b1: [FATAL] Unknown read response destination: RID from read response produces a destination which is not present in the routing table 2 2 0x0 R/W E3 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E3_SET ns_noc_io_spio_soc_ip.csr 86363 E3 1'b1: [FATAL] Interleaved read response: Interleaved read response. This can occur if interleaved read response is received from a slave device for which a de-interleaver was not specified 3 3 0x0 R/W E4 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E4_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E4_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E4_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E4_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E4_SET ns_noc_io_spio_soc_ip.csr 86375 E4 1'b1: Read command modified: A read command which was marked as non-modifiable was modified by the slave bridge 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_UNSD_15_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_UNSD_15_5_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_UNSD_15_5_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_UNSD_15_5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_UNSD_15_5_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_UNSD_15_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_UNSD_15_5_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 86386 UNSD_15_5 15 5 0x000 R E16 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E16_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E16_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E16_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E16_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E16_SET ns_noc_io_spio_soc_ip.csr 86398 E16 1'b1: Write decode error response: Decode error response received from slave device for write command 16 16 0x0 R/W E17 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E17_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E17_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E17_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E17_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E17_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E17_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E17_SET ns_noc_io_spio_soc_ip.csr 86410 E17 1'b1: Write slave error response: Slave error response received from slave device for write command 17 17 0x0 R/W E18 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E18_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E18_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E18_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E18_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E18_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E18_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E18_SET ns_noc_io_spio_soc_ip.csr 86423 E18 1'b1: [FATAL] Unknown write response destination: BID from write response produces a destination which is not present in the routing table 18 18 0x0 R/W E19 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E19_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E19_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E19_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E19_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E19_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E19_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E19_SET ns_noc_io_spio_soc_ip.csr 86435 E19 1'b1: Write command modified: A write command which was marked as non-modifiable was modified by the slave bridge 19 19 0x0 R/W UNSD_31_20 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_UNSD_31_20_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_UNSD_31_20_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_UNSD_31_20_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_UNSD_31_20_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_UNSD_31_20_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_UNSD_31_20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_UNSD_31_20_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_UNSD_31_20_SET ns_noc_io_spio_soc_ip.csr 86446 UNSD_31_20 31 20 0x000 R E32 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E32_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E32_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E32_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E32_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E32_SET ns_noc_io_spio_soc_ip.csr 86458 E32 1'b1: [FATAL] Traffic sent to a noc layer which is power gated 32 32 0x0 R/W E33 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E33_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E33_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E33_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E33_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E33_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E33_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E33_SET ns_noc_io_spio_soc_ip.csr 86469 E33 1'b1: [FATAL] Parity error in config/status registers 33 33 0x0 R/W E34 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E34_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E34_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E34_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E34_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E34_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E34_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E34_SET ns_noc_io_spio_soc_ip.csr 86480 E34 1'b1: [FATAL] RDATA Parity error 34 34 0x0 R/W E35 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E35_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E35_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E35_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E35_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E35_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E35_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E35_SET ns_noc_io_spio_soc_ip.csr 86491 E35 1'b1: [FATAL] RRESP Parity error 35 35 0x0 R/W E36 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E36_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E36_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E36_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E36_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E36_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E36_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E36_SET ns_noc_io_spio_soc_ip.csr 86502 E36 1'b1: [FATAL] BRESP Parity error 36 36 0x0 R/W E37 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E37_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E37_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E37_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E37_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E37_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E37_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E37_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E37_SET ns_noc_io_spio_soc_ip.csr 86513 E37 1'b1: [FATAL] AC Parity error 37 37 0x0 R/W E38 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E38_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E38_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E38_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E38_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E38_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E38_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E38_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E38_SET ns_noc_io_spio_soc_ip.csr 86524 E38 1'b1: [FATAL] ACADDR Parity error 38 38 0x0 R/W E39 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E39_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E39_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E39_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E39_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E39_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E39_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E39_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E39_SET ns_noc_io_spio_soc_ip.csr 86536 E39 1'b1: [FATAL] R Ch Cmdtbl Parity Err 39 39 0x0 R E40 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E40_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E40_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E40_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E40_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E40_SET ns_noc_io_spio_soc_ip.csr 86548 E40 1'b1: [FATAL] B Ch Cmdtbl Parity Err 40 40 0x0 R E41 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E41_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E41_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E41_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E41_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E41_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E41_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E41_SET ns_noc_io_spio_soc_ip.csr 86560 E41 1'b1: [FATAL] Rx Fifo Parity Err 41 41 0x0 R E42 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E42_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E42_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E42_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E42_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E42_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E42_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E42_SET ns_noc_io_spio_soc_ip.csr 86572 E42 1'b1: [FATAL] CRCD Ch Reorder Buffer Parity Err 42 42 0x0 R E43 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E43_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E43_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E43_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E43_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E43_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E43_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E43_SET ns_noc_io_spio_soc_ip.csr 86584 E43 1'b1: [FATAL] Ack Ch Wack Reorder Buffer Parity Err 43 43 0x0 R E44 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E44_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E44_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E44_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E44_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E44_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E44_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E44_SET ns_noc_io_spio_soc_ip.csr 86596 E44 1'b1: [FATAL] Ack Ch Rack Reorder Buffer Parity Err 44 44 0x0 R E45 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E45_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E45_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E45_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E45_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E45_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E45_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E45_SET ns_noc_io_spio_soc_ip.csr 86608 E45 1'b1: [FATAL] B Ch Drain Fifo Parity Err 45 45 0x0 R E46 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E46_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E46_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E46_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E46_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E46_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E46_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E46_SET ns_noc_io_spio_soc_ip.csr 86620 E46 1'b1: [FATAL] R Ch Flush Fifo Parity Err 46 46 0x0 R E47 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E47_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E47_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E47_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E47_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E47_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E47_SET ns_noc_io_spio_soc_ip.csr 86632 E47 1'b1: [FATAL] R Ch Deinterleaver Cmdtbl Parity Err 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E48_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E48_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E48_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E48_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_E48_SET ns_noc_io_spio_soc_ip.csr 86644 E48 1'b1: [FATAL] R Ch Deinterleaver Data Buffer Parity Err 48 48 0x0 R UNSD_63_49 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_UNSD_63_49_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_UNSD_63_49_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_UNSD_63_49_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_UNSD_63_49_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_UNSD_63_49_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_UNSD_63_49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_UNSD_63_49_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_ERR_UNSD_63_49_SET ns_noc_io_spio_soc_ip.csr 86655 UNSD_63_49 63 49 0x0000 R register spio_noc.bridge_spio_p10_apb1_s_8_8_as_intm bridge_spio_p10_apb1_s_8_8_as_intm SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 86996 spio_p10_apb1_s register as_intm 0x21E40 R/W 0x0000007d000b0013 Spio_noc_bridge_spio_p10_apb1_s_8_8_as_intm Interrupt mask register.Individual bit positions match the error bit positions in AS_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M0_SET ns_noc_io_spio_soc_ip.csr 86677 M0 Mask interrupts for read channel 0 0 0x1 R/W M1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M1_SET ns_noc_io_spio_soc_ip.csr 86688 M1 Mask interrupts for read channel 1 1 0x1 R/W M2 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M2_SET ns_noc_io_spio_soc_ip.csr 86699 M2 Mask interrupts for read channel 2 2 0x0 R/W M3 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M3_SET ns_noc_io_spio_soc_ip.csr 86710 M3 Mask interrupts for read channel 3 3 0x0 R/W M4 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M4_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M4_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M4_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M4_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M4_SET ns_noc_io_spio_soc_ip.csr 86721 M4 Mask interrupts for read channel 4 4 0x1 R/W UNSD_15_5 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_UNSD_15_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_UNSD_15_5_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_UNSD_15_5_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_UNSD_15_5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_UNSD_15_5_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_UNSD_15_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_UNSD_15_5_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 86732 UNSD_15_5 15 5 0x000 R M16 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M16_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M16_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M16_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M16_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M16_SET ns_noc_io_spio_soc_ip.csr 86743 M16 Mask interrupts for write channel 16 16 0x1 R/W M17 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M17_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M17_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M17_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M17_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M17_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M17_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M17_SET ns_noc_io_spio_soc_ip.csr 86754 M17 Mask interrupts for write channel 17 17 0x1 R/W M18 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M18_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M18_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M18_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M18_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M18_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M18_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M18_SET ns_noc_io_spio_soc_ip.csr 86765 M18 Mask interrupts for write channel 18 18 0x0 R/W M19 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M19_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M19_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M19_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M19_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M19_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M19_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M19_SET ns_noc_io_spio_soc_ip.csr 86776 M19 Mask interrupts for write channel 19 19 0x1 R/W UNSD_31_20 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_UNSD_31_20_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_UNSD_31_20_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_UNSD_31_20_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_UNSD_31_20_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_UNSD_31_20_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_UNSD_31_20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_UNSD_31_20_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_UNSD_31_20_SET ns_noc_io_spio_soc_ip.csr 86787 UNSD_31_20 31 20 0x000 R M32 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M32_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M32_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M32_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M32_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M32_SET ns_noc_io_spio_soc_ip.csr 86798 M32 Mask interrupt on traffic to PG layer 32 32 0x1 R/W M33 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M33_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M33_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M33_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M33_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M33_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M33_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M33_SET ns_noc_io_spio_soc_ip.csr 86809 M33 Mask interrupt on csr parity errors 33 33 0x0 R/W M34 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M34_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M34_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M34_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M34_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M34_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M34_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M34_SET ns_noc_io_spio_soc_ip.csr 86820 M34 RDATA parity interrupt Mask 34 34 0x1 R/W M35 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M35_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M35_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M35_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M35_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M35_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M35_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M35_SET ns_noc_io_spio_soc_ip.csr 86831 M35 RRESP parity interrupt Mask 35 35 0x1 R/W M36 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M36_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M36_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M36_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M36_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M36_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M36_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M36_SET ns_noc_io_spio_soc_ip.csr 86842 M36 BRESP parity interrupt Mask 36 36 0x1 R/W M37 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M37_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M37_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M37_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M37_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M37_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M37_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M37_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M37_SET ns_noc_io_spio_soc_ip.csr 86853 M37 AC parity interrupt Mask 37 37 0x1 R/W M38 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M38_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M38_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M38_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M38_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M38_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M38_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M38_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_M38_SET ns_noc_io_spio_soc_ip.csr 86864 M38 ACADDR parity interrupt Mask 38 38 0x1 R/W E39 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E39_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E39_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E39_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E39_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E39_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E39_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E39_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E39_SET ns_noc_io_spio_soc_ip.csr 86876 E39 1'b1: R Ch Cmdtbl Parity Err Intr Mask 39 39 0x0 R E40 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E40_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E40_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E40_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E40_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E40_SET ns_noc_io_spio_soc_ip.csr 86888 E40 1'b1: B Ch Cmdtbl Parity Err Intr Mask 40 40 0x0 R E41 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E41_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E41_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E41_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E41_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E41_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E41_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E41_SET ns_noc_io_spio_soc_ip.csr 86900 E41 1'b1: Rx Fifo Parity Err Intr Mask 41 41 0x0 R E42 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E42_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E42_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E42_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E42_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E42_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E42_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E42_SET ns_noc_io_spio_soc_ip.csr 86912 E42 1'b1: CRCD Ch Reorder Buffer Parity Err Intr Mask 42 42 0x0 R E43 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E43_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E43_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E43_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E43_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E43_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E43_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E43_SET ns_noc_io_spio_soc_ip.csr 86924 E43 1'b1: Ack Ch Wack Reorder Buffer Parity Err IntrMask 43 43 0x0 R E44 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E44_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E44_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E44_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E44_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E44_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E44_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E44_SET ns_noc_io_spio_soc_ip.csr 86936 E44 1'b1: Ack Ch Rack Reorder Buffer Parity Err Intr Mask 44 44 0x0 R E45 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E45_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E45_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E45_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E45_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E45_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E45_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E45_SET ns_noc_io_spio_soc_ip.csr 86948 E45 1'b1: B Ch Drain Fifo Parity Err Intr Mask 45 45 0x0 R E46 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E46_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E46_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E46_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E46_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E46_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E46_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E46_SET ns_noc_io_spio_soc_ip.csr 86960 E46 1'b1: R Ch Flush Fifo Parity Err Intr Mask 46 46 0x0 R E47 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E47_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E47_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E47_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E47_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E47_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E47_SET ns_noc_io_spio_soc_ip.csr 86972 E47 1'b1: R Ch Deinterleaver Cmdtbl Parity Err Intr Mask 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E48_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E48_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E48_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E48_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_E48_SET ns_noc_io_spio_soc_ip.csr 86984 E48 1'b1: R Ch Deinterleaver Data Buffer Parity Err Intr Mask 48 48 0x0 R UNSD_63_49 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_UNSD_63_49_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_UNSD_63_49_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_UNSD_63_49_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_UNSD_63_49_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_UNSD_63_49_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_UNSD_63_49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_UNSD_63_49_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_INTM_UNSD_63_49_SET ns_noc_io_spio_soc_ip.csr 86995 UNSD_63_49 63 49 0x0000 R register spio_noc.bridge_spio_p10_apb1_s_8_8_as_ccmd bridge_spio_p10_apb1_s_8_8_as_ccmd SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 87071 spio_p10_apb1_s register as_ccmd 0x21F00 R/W 0x0000000003000000 Spio_noc_bridge_spio_p10_apb1_s_8_8_as_ccmd Not applicable for current release. false false false false UNSD_23_0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_UNSD_23_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_UNSD_23_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_UNSD_23_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_UNSD_23_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_UNSD_23_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_UNSD_23_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_UNSD_23_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_UNSD_23_0_SET ns_noc_io_spio_soc_ip.csr 87014 UNSD_23_0 23 0 0x000000 R rdy SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_RDY_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_RDY_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_RDY_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_RDY_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_RDY_SET ns_noc_io_spio_soc_ip.csr 87025 rdy 1'b1: Ready 24 24 0x1 R/W val SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_VAL_SET ns_noc_io_spio_soc_ip.csr 87036 val 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_UNSD_27_26_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_UNSD_27_26_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_UNSD_27_26_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_UNSD_27_26_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_UNSD_27_26_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_UNSD_27_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_UNSD_27_26_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_UNSD_27_26_SET ns_noc_io_spio_soc_ip.csr 87047 UNSD_27_26 27 26 0x0 R intfid SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_INTFID_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_INTFID_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_INTFID_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_INTFID_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_INTFID_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_INTFID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_INTFID_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_INTFID_SET ns_noc_io_spio_soc_ip.csr 87059 intfid 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_63_31 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_UNSD_63_31_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_UNSD_63_31_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_UNSD_63_31_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_UNSD_63_31_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_UNSD_63_31_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_UNSD_63_31_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_UNSD_63_31_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMD_UNSD_63_31_SET ns_noc_io_spio_soc_ip.csr 87070 UNSD_63_31 63 31 0x000000000 R register spio_noc.bridge_spio_p10_apb1_s_8_8_as_ccmdmsk bridge_spio_p10_apb1_s_8_8_as_ccmdmsk SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 87123 spio_p10_apb1_s register as_ccmdmsk 0x21F08 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_apb1_s_8_8_as_ccmdmsk Not applicable for current release. false false false false UNSD_23_0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_UNSD_23_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_UNSD_23_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_UNSD_23_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_UNSD_23_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_UNSD_23_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_UNSD_23_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_UNSD_23_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_UNSD_23_0_SET ns_noc_io_spio_soc_ip.csr 87089 UNSD_23_0 23 0 0x000000 R rdy SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_RDY_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_RDY_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_RDY_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_RDY_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_RDY_SET ns_noc_io_spio_soc_ip.csr 87100 rdy 1'b1: Ready 24 24 0x0 R/W val SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_VAL_SET ns_noc_io_spio_soc_ip.csr 87111 val 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_UNSD_63_26_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_UNSD_63_26_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_UNSD_63_26_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_UNSD_63_26_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_UNSD_63_26_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_UNSD_63_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_UNSD_63_26_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CCMDMSK_UNSD_63_26_SET ns_noc_io_spio_soc_ip.csr 87122 UNSD_63_26 63 26 0x0000000000 R register spio_noc.bridge_spio_p10_apb1_s_8_8_as_cntr bridge_spio_p10_apb1_s_8_8_as_cntr SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CNTR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CNTR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CNTR_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CNTR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 87153 spio_p10_apb1_s register as_cntr 0x21F10 R 0x0000000000000000 Spio_noc_bridge_spio_p10_apb1_s_8_8_as_cntr Not applicable for current release. false false false false CNTR SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CNTR_CNTR_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CNTR_CNTR_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CNTR_CNTR_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CNTR_CNTR_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CNTR_CNTR_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CNTR_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CNTR_CNTR_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CNTR_CNTR_SET ns_noc_io_spio_soc_ip.csr 87142 CNTR Counter 31 0 0x00000000 R UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CNTR_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CNTR_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CNTR_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CNTR_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CNTR_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CNTR_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CNTR_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_CNTR_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 87152 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p10_apb1_s_8_8_as_arovrd bridge_spio_p10_apb1_s_8_8_as_arovrd SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 87266 spio_p10_apb1_s register as_arovrd 0x21F18 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_apb1_s_8_8_as_arovrd AR Overrides. false false false false arcache_val SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 87171 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 87184 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 87195 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 87206 UNSD_11_11 11 11 0x0 R arprot_enb SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 87219 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 87230 UNSD_15_15 15 15 0x0 R arqos_val SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 87241 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_ARQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 87254 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AROVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 87265 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_p10_apb1_s_8_8_as_awovrd bridge_spio_p10_apb1_s_8_8_as_awovrd SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 87379 spio_p10_apb1_s register as_awovrd 0x21F20 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_apb1_s_8_8_as_awovrd AW Overrides. false false false false awcache_val SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 87284 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 87297 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 87308 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 87319 UNSD_11_11 11 11 0x0 R awprot_enb SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 87332 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 87343 UNSD_15_15 15 15 0x0 R awqos_val SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 87354 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_AWQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 87367 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_AS_AWOVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 87378 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_p10_apb1_s_8_8_p_0 bridge_spio_p10_apb1_s_8_8_p_0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 87444 spio_p10_apb1_s register p_0 0x23000 R/W 0x00000003 Spio_noc_bridge_spio_p10_apb1_s_8_8_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_0_SET ns_noc_io_spio_soc_ip.csr 87407 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_1_SET ns_noc_io_spio_soc_ip.csr 87419 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_2_SET ns_noc_io_spio_soc_ip.csr 87431 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_0_WT_QOS_3_SET ns_noc_io_spio_soc_ip.csr 87443 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register spio_noc.bridge_spio_p10_apb1_s_8_8_p_1 bridge_spio_p10_apb1_s_8_8_p_1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 87510 spio_p10_apb1_s register p_1 0x23008 R 0x00000000 Spio_noc_bridge_spio_p10_apb1_s_8_8_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_4_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_4_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_4_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_4_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_4_SET ns_noc_io_spio_soc_ip.csr 87473 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_5_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_5_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_5_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_5_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_5_SET ns_noc_io_spio_soc_ip.csr 87485 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_6_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_6_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_6_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_6_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_6_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_6_SET ns_noc_io_spio_soc_ip.csr 87497 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_7_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_7_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_7_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_7_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_7_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_1_WT_QOS_7_SET ns_noc_io_spio_soc_ip.csr 87509 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register spio_noc.bridge_spio_p10_apb1_s_8_8_p_2 bridge_spio_p10_apb1_s_8_8_p_2 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 87576 spio_p10_apb1_s register p_2 0x23010 R 0x00000000 Spio_noc_bridge_spio_p10_apb1_s_8_8_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_8_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_8_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_8_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_8_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_8_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_8_SET ns_noc_io_spio_soc_ip.csr 87539 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_9_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_9_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_9_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_9_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_9_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_9_SET ns_noc_io_spio_soc_ip.csr 87551 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_10_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_10_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_10_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_10_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_10_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_10_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_10_SET ns_noc_io_spio_soc_ip.csr 87563 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_11_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_11_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_11_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_11_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_11_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_2_WT_QOS_11_SET ns_noc_io_spio_soc_ip.csr 87575 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register spio_noc.bridge_spio_p10_apb1_s_8_8_p_3 bridge_spio_p10_apb1_s_8_8_p_3 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 87642 spio_p10_apb1_s register p_3 0x23018 R 0x00000000 Spio_noc_bridge_spio_p10_apb1_s_8_8_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_12_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_12_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_12_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_12_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_12_SET ns_noc_io_spio_soc_ip.csr 87605 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_13_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_13_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_13_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_13_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_13_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_13_SET ns_noc_io_spio_soc_ip.csr 87617 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_14_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_14_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_14_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_14_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_14_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_14_SET ns_noc_io_spio_soc_ip.csr 87629 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_15_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_15_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_15_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_15_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_15_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_P_3_WT_QOS_15_SET ns_noc_io_spio_soc_ip.csr 87641 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register spio_noc.bridge_spio_p10_apb1_s_8_8_txe bridge_spio_p10_apb1_s_8_8_txe SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 87788 spio_p10_apb1_s register txe 0x23040 R/W 0x00000000 Spio_noc_bridge_spio_p10_apb1_s_8_8_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_TRANS_WITHOUT_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_TRANS_WITHOUT_SOP_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_TRANS_WITHOUT_SOP_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_TRANS_WITHOUT_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_TRANS_WITHOUT_SOP_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_TRANS_WITHOUT_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_TRANS_WITHOUT_SOP_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_spio_soc_ip.csr 87669 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_SOP_AFTER_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_SOP_AFTER_SOP_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_SOP_AFTER_SOP_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_SOP_AFTER_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_SOP_AFTER_SOP_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_SOP_AFTER_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_SOP_AFTER_SOP_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_SOP_AFTER_SOP_SET ns_noc_io_spio_soc_ip.csr 87681 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 87696 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 87709 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_spio_soc_ip.csr 87723 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_spio_soc_ip.csr 87737 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_spio_soc_ip.csr 87751 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_spio_soc_ip.csr 87765 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 87776 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXE_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 87787 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_p10_apb1_s_8_8_txem bridge_spio_p10_apb1_s_8_8_txem SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 87867 spio_p10_apb1_s register txem 0x23048 R/W 0x00000008 Spio_noc_bridge_spio_p10_apb1_s_8_8_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_UNSD_1_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_UNSD_1_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_UNSD_1_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_UNSD_1_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_UNSD_1_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_UNSD_1_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_UNSD_1_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_UNSD_1_0_SET ns_noc_io_spio_soc_ip.csr 87811 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 87822 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 87833 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_UNSD_7_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_UNSD_7_4_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_UNSD_7_4_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_UNSD_7_4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_UNSD_7_4_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_UNSD_7_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_UNSD_7_4_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_UNSD_7_4_SET ns_noc_io_spio_soc_ip.csr 87844 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 87855 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_TXEM_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 87866 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_p10_apb1_s_8_8_btus_0 bridge_spio_p10_apb1_s_8_8_btus_0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 88235 spio_p10_apb1_s register btus_0 0x23058 R 0x00000000 Spio_noc_bridge_spio_p10_apb1_s_8_8_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_A_SET ns_noc_io_spio_soc_ip.csr 87893 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_B_SET ns_noc_io_spio_soc_ip.csr 87904 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_C_SET ns_noc_io_spio_soc_ip.csr 87915 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L0_D_SET ns_noc_io_spio_soc_ip.csr 87926 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_A_SET ns_noc_io_spio_soc_ip.csr 87937 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_B_SET ns_noc_io_spio_soc_ip.csr 87948 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_C_SET ns_noc_io_spio_soc_ip.csr 87959 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L1_D_SET ns_noc_io_spio_soc_ip.csr 87970 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_A_SET ns_noc_io_spio_soc_ip.csr 87981 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_B_SET ns_noc_io_spio_soc_ip.csr 87992 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_C_SET ns_noc_io_spio_soc_ip.csr 88003 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L2_D_SET ns_noc_io_spio_soc_ip.csr 88014 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_A_SET ns_noc_io_spio_soc_ip.csr 88025 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_B_SET ns_noc_io_spio_soc_ip.csr 88036 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_C_SET ns_noc_io_spio_soc_ip.csr 88047 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L3_D_SET ns_noc_io_spio_soc_ip.csr 88058 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_A_SET ns_noc_io_spio_soc_ip.csr 88069 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_B_SET ns_noc_io_spio_soc_ip.csr 88080 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_C_SET ns_noc_io_spio_soc_ip.csr 88091 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L4_D_SET ns_noc_io_spio_soc_ip.csr 88102 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_A_SET ns_noc_io_spio_soc_ip.csr 88113 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_B_SET ns_noc_io_spio_soc_ip.csr 88124 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_C_SET ns_noc_io_spio_soc_ip.csr 88135 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L5_D_SET ns_noc_io_spio_soc_ip.csr 88146 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_A_SET ns_noc_io_spio_soc_ip.csr 88157 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_B_SET ns_noc_io_spio_soc_ip.csr 88168 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_C_SET ns_noc_io_spio_soc_ip.csr 88179 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L6_D_SET ns_noc_io_spio_soc_ip.csr 88190 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_A_SET ns_noc_io_spio_soc_ip.csr 88201 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_B_SET ns_noc_io_spio_soc_ip.csr 88212 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_C_SET ns_noc_io_spio_soc_ip.csr 88223 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_0_L7_D_SET ns_noc_io_spio_soc_ip.csr 88234 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register spio_noc.bridge_spio_p10_apb1_s_8_8_btus_1 bridge_spio_p10_apb1_s_8_8_btus_1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 88603 spio_p10_apb1_s register btus_1 0x23060 R 0x00000000 Spio_noc_bridge_spio_p10_apb1_s_8_8_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_A_SET ns_noc_io_spio_soc_ip.csr 88261 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_B_SET ns_noc_io_spio_soc_ip.csr 88272 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_C_SET ns_noc_io_spio_soc_ip.csr 88283 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L8_D_SET ns_noc_io_spio_soc_ip.csr 88294 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_A_SET ns_noc_io_spio_soc_ip.csr 88305 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_B_SET ns_noc_io_spio_soc_ip.csr 88316 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_C_SET ns_noc_io_spio_soc_ip.csr 88327 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L9_D_SET ns_noc_io_spio_soc_ip.csr 88338 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_A_SET ns_noc_io_spio_soc_ip.csr 88349 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_B_SET ns_noc_io_spio_soc_ip.csr 88360 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_C_SET ns_noc_io_spio_soc_ip.csr 88371 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L10_D_SET ns_noc_io_spio_soc_ip.csr 88382 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_A_SET ns_noc_io_spio_soc_ip.csr 88393 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_B_SET ns_noc_io_spio_soc_ip.csr 88404 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_C_SET ns_noc_io_spio_soc_ip.csr 88415 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L11_D_SET ns_noc_io_spio_soc_ip.csr 88426 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_A_SET ns_noc_io_spio_soc_ip.csr 88437 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_B_SET ns_noc_io_spio_soc_ip.csr 88448 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_C_SET ns_noc_io_spio_soc_ip.csr 88459 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L12_D_SET ns_noc_io_spio_soc_ip.csr 88470 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_A_SET ns_noc_io_spio_soc_ip.csr 88481 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_B_SET ns_noc_io_spio_soc_ip.csr 88492 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_C_SET ns_noc_io_spio_soc_ip.csr 88503 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L13_D_SET ns_noc_io_spio_soc_ip.csr 88514 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_A_SET ns_noc_io_spio_soc_ip.csr 88525 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_B_SET ns_noc_io_spio_soc_ip.csr 88536 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_C_SET ns_noc_io_spio_soc_ip.csr 88547 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L14_D_SET ns_noc_io_spio_soc_ip.csr 88558 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_A_SET ns_noc_io_spio_soc_ip.csr 88569 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_B_SET ns_noc_io_spio_soc_ip.csr 88580 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_C_SET ns_noc_io_spio_soc_ip.csr 88591 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTUS_1_L15_D_SET ns_noc_io_spio_soc_ip.csr 88602 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register spio_noc.bridge_spio_p10_apb1_s_8_8_btrl_0 bridge_spio_p10_apb1_s_8_8_btrl_0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 88679 spio_p10_apb1_s register btrl_0 0x23080 R 0x00000000 Spio_noc_bridge_spio_p10_apb1_s_8_8_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_WT_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_WT_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_WT_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_WT_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_WT_SET ns_noc_io_spio_soc_ip.csr 88627 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 88638 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_CNT_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_CNT_SET ns_noc_io_spio_soc_ip.csr 88653 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_EN_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_EN_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_EN_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_EN_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_EN_SET ns_noc_io_spio_soc_ip.csr 88667 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_0_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 88678 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p10_apb1_s_8_8_btrl_1 bridge_spio_p10_apb1_s_8_8_btrl_1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 88755 spio_p10_apb1_s register btrl_1 0x23088 R 0x00000000 Spio_noc_bridge_spio_p10_apb1_s_8_8_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_WT_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_WT_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_WT_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_WT_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_WT_SET ns_noc_io_spio_soc_ip.csr 88703 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 88714 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_CNT_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_CNT_SET ns_noc_io_spio_soc_ip.csr 88729 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_EN_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_EN_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_EN_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_EN_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_EN_SET ns_noc_io_spio_soc_ip.csr 88743 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_1_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 88754 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p10_apb1_s_8_8_btrl_2 bridge_spio_p10_apb1_s_8_8_btrl_2 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 88831 spio_p10_apb1_s register btrl_2 0x23090 R 0x00000000 Spio_noc_bridge_spio_p10_apb1_s_8_8_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_WT_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_WT_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_WT_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_WT_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_WT_SET ns_noc_io_spio_soc_ip.csr 88779 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 88790 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_CNT_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_CNT_SET ns_noc_io_spio_soc_ip.csr 88805 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_EN_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_EN_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_EN_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_EN_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_EN_SET ns_noc_io_spio_soc_ip.csr 88819 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_2_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 88830 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p10_apb1_s_8_8_btrl_3 bridge_spio_p10_apb1_s_8_8_btrl_3 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 88907 spio_p10_apb1_s register btrl_3 0x23098 R 0x00000000 Spio_noc_bridge_spio_p10_apb1_s_8_8_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_WT_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_WT_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_WT_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_WT_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_WT_SET ns_noc_io_spio_soc_ip.csr 88855 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 88866 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_CNT_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_CNT_SET ns_noc_io_spio_soc_ip.csr 88881 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_EN_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_EN_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_EN_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_EN_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_EN_SET ns_noc_io_spio_soc_ip.csr 88895 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTRL_3_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 88906 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p10_apb1_s_8_8_btperr bridge_spio_p10_apb1_s_8_8_btperr SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 89109 spio_p10_apb1_s register btperr 0x230A8 R/W 0x00000000 Spio_noc_bridge_spio_p10_apb1_s_8_8_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L0_SET ns_noc_io_spio_soc_ip.csr 88932 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L1_SET ns_noc_io_spio_soc_ip.csr 88943 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L2_SET ns_noc_io_spio_soc_ip.csr 88954 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L3_SET ns_noc_io_spio_soc_ip.csr 88965 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L4_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L4_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L4_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L4_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L4_SET ns_noc_io_spio_soc_ip.csr 88976 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L5_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L5_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L5_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L5_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L5_SET ns_noc_io_spio_soc_ip.csr 88987 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L6_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L6_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L6_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L6_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L6_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L6_SET ns_noc_io_spio_soc_ip.csr 88998 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L7_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L7_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L7_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L7_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L7_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L7_SET ns_noc_io_spio_soc_ip.csr 89009 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L8_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L8_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L8_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L8_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L8_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L8_SET ns_noc_io_spio_soc_ip.csr 89020 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L9_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L9_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L9_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L9_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L9_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L9_SET ns_noc_io_spio_soc_ip.csr 89031 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L10_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L10_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L10_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L10_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L10_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L10_SET ns_noc_io_spio_soc_ip.csr 89042 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L11_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L11_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L11_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L11_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L11_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L11_SET ns_noc_io_spio_soc_ip.csr 89053 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L12_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L12_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L12_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L12_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L12_SET ns_noc_io_spio_soc_ip.csr 89064 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L13_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L13_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L13_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L13_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L13_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L13_SET ns_noc_io_spio_soc_ip.csr 89075 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L14_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L14_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L14_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L14_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L14_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L14_SET ns_noc_io_spio_soc_ip.csr 89086 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L15_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L15_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L15_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L15_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L15_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_L15_SET ns_noc_io_spio_soc_ip.csr 89097 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_UNSD_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERR_UNSD_SET ns_noc_io_spio_soc_ip.csr 89108 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_p10_apb1_s_8_8_btperrm bridge_spio_p10_apb1_s_8_8_btperrm SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 89309 spio_p10_apb1_s register btperrm 0x230B0 R/W 0x00000000 Spio_noc_bridge_spio_p10_apb1_s_8_8_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L0_SET ns_noc_io_spio_soc_ip.csr 89132 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L1_SET ns_noc_io_spio_soc_ip.csr 89143 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L2_SET ns_noc_io_spio_soc_ip.csr 89154 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L3_SET ns_noc_io_spio_soc_ip.csr 89165 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L4_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L4_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L4_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L4_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L4_SET ns_noc_io_spio_soc_ip.csr 89176 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L5_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L5_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L5_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L5_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L5_SET ns_noc_io_spio_soc_ip.csr 89187 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L6_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L6_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L6_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L6_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L6_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L6_SET ns_noc_io_spio_soc_ip.csr 89198 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L7_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L7_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L7_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L7_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L7_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L7_SET ns_noc_io_spio_soc_ip.csr 89209 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L8_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L8_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L8_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L8_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L8_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L8_SET ns_noc_io_spio_soc_ip.csr 89220 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L9_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L9_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L9_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L9_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L9_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L9_SET ns_noc_io_spio_soc_ip.csr 89231 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L10_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L10_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L10_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L10_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L10_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L10_SET ns_noc_io_spio_soc_ip.csr 89242 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L11_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L11_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L11_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L11_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L11_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L11_SET ns_noc_io_spio_soc_ip.csr 89253 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L12_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L12_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L12_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L12_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L12_SET ns_noc_io_spio_soc_ip.csr 89264 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L13_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L13_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L13_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L13_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L13_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L13_SET ns_noc_io_spio_soc_ip.csr 89275 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L14_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L14_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L14_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L14_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L14_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L14_SET ns_noc_io_spio_soc_ip.csr 89286 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L15_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L15_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L15_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L15_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L15_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_L15_SET ns_noc_io_spio_soc_ip.csr 89297 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_UNSD_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BTPERRM_UNSD_SET ns_noc_io_spio_soc_ip.csr 89308 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_p10_apb1_s_8_8_rxe bridge_spio_p10_apb1_s_8_8_rxe SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 89417 spio_p10_apb1_s register rxe 0x23120 R/W 0x00000000 Spio_noc_bridge_spio_p10_apb1_s_8_8_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_A_SET ns_noc_io_spio_soc_ip.csr 89337 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_B_SET ns_noc_io_spio_soc_ip.csr 89348 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_C_SET ns_noc_io_spio_soc_ip.csr 89359 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_CRC_OFLW_D_SET ns_noc_io_spio_soc_ip.csr 89370 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_EVC_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_EVC_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_EVC_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_EVC_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_EVC_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_EVC_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_EVC_OFLW_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_EVC_OFLW_SET ns_noc_io_spio_soc_ip.csr 89382 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 89393 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_EVC1_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_EVC1_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_EVC1_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_EVC1_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_EVC1_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_EVC1_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_EVC1_OFLW_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_EVC1_OFLW_SET ns_noc_io_spio_soc_ip.csr 89405 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXE_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 89416 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_p10_apb1_s_8_8_rxem bridge_spio_p10_apb1_s_8_8_rxem SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 89489 spio_p10_apb1_s register rxem 0x23128 R/W 0x00000050 Spio_noc_bridge_spio_p10_apb1_s_8_8_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_UNSD_3_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_UNSD_3_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_UNSD_3_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_UNSD_3_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_UNSD_3_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_UNSD_3_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_UNSD_3_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_UNSD_3_0_SET ns_noc_io_spio_soc_ip.csr 89438 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_EVC_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_EVC_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_EVC_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_EVC_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_EVC_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_EVC_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_EVC_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_EVC_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 89452 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 89463 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_EVC1_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_EVC1_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_EVC1_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_EVC1_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_EVC1_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_EVC1_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_EVC1_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 89477 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_RXEM_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 89488 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_p10_apb1_s_8_8_brs_0 bridge_spio_p10_apb1_s_8_8_brs_0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 89763 spio_p10_apb1_s register brs_0 0x23130 R 0x00000000 Spio_noc_bridge_spio_p10_apb1_s_8_8_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 89513 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_0_SET ns_noc_io_spio_soc_ip.csr 89524 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_0_SET ns_noc_io_spio_soc_ip.csr 89535 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_0_SET ns_noc_io_spio_soc_ip.csr 89546 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_0_SET ns_noc_io_spio_soc_ip.csr 89557 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 89567 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 89578 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_1_SET ns_noc_io_spio_soc_ip.csr 89589 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_1_SET ns_noc_io_spio_soc_ip.csr 89600 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_1_SET ns_noc_io_spio_soc_ip.csr 89611 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_1_SET ns_noc_io_spio_soc_ip.csr 89622 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 89632 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 89643 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_2_SET ns_noc_io_spio_soc_ip.csr 89654 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_2_SET ns_noc_io_spio_soc_ip.csr 89665 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_2_SET ns_noc_io_spio_soc_ip.csr 89676 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_2_SET ns_noc_io_spio_soc_ip.csr 89687 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 89697 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 89708 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_V_3_SET ns_noc_io_spio_soc_ip.csr 89719 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_S_3_SET ns_noc_io_spio_soc_ip.csr 89730 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_B_3_SET ns_noc_io_spio_soc_ip.csr 89741 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_F_3_SET ns_noc_io_spio_soc_ip.csr 89752 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_0_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 89762 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_p10_apb1_s_8_8_brs_1 bridge_spio_p10_apb1_s_8_8_brs_1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 90037 spio_p10_apb1_s register brs_1 0x23138 R 0x00000000 Spio_noc_bridge_spio_p10_apb1_s_8_8_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 89787 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_0_SET ns_noc_io_spio_soc_ip.csr 89798 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_0_SET ns_noc_io_spio_soc_ip.csr 89809 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_0_SET ns_noc_io_spio_soc_ip.csr 89820 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_0_SET ns_noc_io_spio_soc_ip.csr 89831 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 89841 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 89852 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_1_SET ns_noc_io_spio_soc_ip.csr 89863 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_1_SET ns_noc_io_spio_soc_ip.csr 89874 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_1_SET ns_noc_io_spio_soc_ip.csr 89885 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_1_SET ns_noc_io_spio_soc_ip.csr 89896 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 89906 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 89917 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_2_SET ns_noc_io_spio_soc_ip.csr 89928 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_2_SET ns_noc_io_spio_soc_ip.csr 89939 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_2_SET ns_noc_io_spio_soc_ip.csr 89950 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_2_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_2_SET ns_noc_io_spio_soc_ip.csr 89961 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 89971 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 89982 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_V_3_SET ns_noc_io_spio_soc_ip.csr 89993 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_S_3_SET ns_noc_io_spio_soc_ip.csr 90004 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_B_3_SET ns_noc_io_spio_soc_ip.csr 90015 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_3_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_F_3_SET ns_noc_io_spio_soc_ip.csr 90026 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRS_1_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 90036 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_p10_apb1_s_8_8_brus bridge_spio_p10_apb1_s_8_8_brus SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 90106 spio_p10_apb1_s register brus 0x231B0 R 0x00000000 Spio_noc_bridge_spio_p10_apb1_s_8_8_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_A_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_A_SET ns_noc_io_spio_soc_ip.csr 90062 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_B_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_B_SET ns_noc_io_spio_soc_ip.csr 90073 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_C_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_C_SET ns_noc_io_spio_soc_ip.csr 90084 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_D_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_V_D_SET ns_noc_io_spio_soc_ip.csr 90095 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_UNSD_31_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_UNSD_31_4_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_UNSD_31_4_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_UNSD_31_4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_UNSD_31_4_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_UNSD_31_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_UNSD_31_4_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRUS_UNSD_31_4_SET ns_noc_io_spio_soc_ip.csr 90105 UNSD_31_4 31 4 0x0000000 R register spio_noc.bridge_spio_p10_apb1_s_8_8_brperr0 bridge_spio_p10_apb1_s_8_8_brperr0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 90334 spio_p10_apb1_s register brperr0 0x231D0 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_apb1_s_8_8_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_D0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_D0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_D0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_D0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_D0_SET ns_noc_io_spio_soc_ip.csr 90144 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_DC0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_DC0_SET ns_noc_io_spio_soc_ip.csr 90155 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SB0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SB0_SET ns_noc_io_spio_soc_ip.csr 90166 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SBC0_SET ns_noc_io_spio_soc_ip.csr 90178 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_PK0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_PK0_SET ns_noc_io_spio_soc_ip.csr 90189 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 90200 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_D1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_D1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_D1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_D1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_D1_SET ns_noc_io_spio_soc_ip.csr 90211 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_DC1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_DC1_SET ns_noc_io_spio_soc_ip.csr 90222 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SB1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SB1_SET ns_noc_io_spio_soc_ip.csr 90233 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_SBC1_SET ns_noc_io_spio_soc_ip.csr 90245 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_PK1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_PK1_SET ns_noc_io_spio_soc_ip.csr 90256 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 90267 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 90278 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 90289 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 90300 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 90311 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 90322 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 90333 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p10_apb1_s_8_8_brperr1 bridge_spio_p10_apb1_s_8_8_brperr1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 90450 spio_p10_apb1_s register brperr1 0x231D8 R 0x0000000000000000 Spio_noc_bridge_spio_p10_apb1_s_8_8_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 90372 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 90383 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 90394 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 90405 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 90416 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 90427 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 90438 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERR1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 90449 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p10_apb1_s_8_8_brperrm0 bridge_spio_p10_apb1_s_8_8_brperrm0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 90671 spio_p10_apb1_s register brperrm0 0x231E0 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_apb1_s_8_8_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_D0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_D0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_D0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_D0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_D0_SET ns_noc_io_spio_soc_ip.csr 90477 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_DC0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_DC0_SET ns_noc_io_spio_soc_ip.csr 90489 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SB0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SB0_SET ns_noc_io_spio_soc_ip.csr 90500 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SBC0_SET ns_noc_io_spio_soc_ip.csr 90512 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_PK0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_PK0_SET ns_noc_io_spio_soc_ip.csr 90524 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 90535 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_D1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_D1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_D1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_D1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_D1_SET ns_noc_io_spio_soc_ip.csr 90546 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_DC1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_DC1_SET ns_noc_io_spio_soc_ip.csr 90558 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SB1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SB1_SET ns_noc_io_spio_soc_ip.csr 90569 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_SBC1_SET ns_noc_io_spio_soc_ip.csr 90581 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_PK1_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_PK1_SET ns_noc_io_spio_soc_ip.csr 90593 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 90604 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 90615 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 90626 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 90637 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 90648 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 90659 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 90670 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p10_apb1_s_8_8_brperrm1 bridge_spio_p10_apb1_s_8_8_brperrm1 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 90776 spio_p10_apb1_s register brperrm1 0x231E8 R 0x0000000000000000 Spio_noc_bridge_spio_p10_apb1_s_8_8_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 90698 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 90709 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 90720 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 90731 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 90742 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 90753 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 90764 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P10_APB1_S_8_8_BRPERRM1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 90775 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_cgc bridge_spio_p10_pcie_rbm_s_9_8_as_cgc SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGC_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGC_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGC_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 90813 spio_p10_pcie_rbm_s register as_cgc 0x25C10 R/W 0x0000000000000064 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_as_cgc Programmable intervals used by coarse clock gating logic. This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGC_HYSTERESIS_COUNTER_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGC_HYSTERESIS_COUNTER_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGC_HYSTERESIS_COUNTER_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGC_HYSTERESIS_COUNTER_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGC_HYSTERESIS_COUNTER_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGC_HYSTERESIS_COUNTER_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGC_HYSTERESIS_COUNTER_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_spio_soc_ip.csr 90801 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGC_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGC_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGC_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGC_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGC_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGC_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGC_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGC_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 90812 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_cgo bridge_spio_p10_pcie_rbm_s_9_8_as_cgo SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGO_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGO_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGO_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGO_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 90848 spio_p10_pcie_rbm_s register as_cgo 0x25C18 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_as_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the slave bridge. false false false false FPO SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGO_FPO_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGO_FPO_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGO_FPO_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGO_FPO_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGO_FPO_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGO_FPO_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGO_FPO_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGO_FPO_SET ns_noc_io_spio_soc_ip.csr 90836 FPO 1'b1: Clock gating override enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGO_UNSD_63_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGO_UNSD_63_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGO_UNSD_63_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGO_UNSD_63_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGO_UNSD_63_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGO_UNSD_63_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGO_UNSD_63_1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CGO_UNSD_63_1_SET ns_noc_io_spio_soc_ip.csr 90847 UNSD_63_1 63 1 0x0000000000000000 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_sts bridge_spio_p10_pcie_rbm_s_9_8_as_sts SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 90922 spio_p10_pcie_rbm_s register as_sts 0x25D00 R 0x000000000000000c Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_as_sts Slave bridge status bits. false false false false WOF SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_WOF_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_WOF_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_WOF_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_WOF_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_WOF_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_WOF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_WOF_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_WOF_SET ns_noc_io_spio_soc_ip.csr 90871 WOF 1'b1: Maximum number of supported write commands are outstanding to the attached slave device awaiting response, no more write commands will be issued to slave till responses are received. 1'b0: Slave device can expect more write commands from NoC 0 0 0x0 R ROF SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_ROF_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_ROF_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_ROF_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_ROF_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_ROF_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_ROF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_ROF_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_ROF_SET ns_noc_io_spio_soc_ip.csr 90887 ROF 1'b1: Maximum number of supported read commands are outstanding to the attached slave device awaiting response, no more read commands will be issued to slave till responses are received. 1'b0: Slave bridge can accept more read commands from the NoC 1 1 0x0 R WOE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_WOE_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_WOE_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_WOE_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_WOE_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_WOE_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_WOE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_WOE_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_WOE_SET ns_noc_io_spio_soc_ip.csr 90899 WOE 1'b1: There are no write commands outstanding to the attached slave device 2 2 0x1 R ROE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_ROE_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_ROE_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_ROE_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_ROE_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_ROE_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_ROE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_ROE_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_ROE_SET ns_noc_io_spio_soc_ip.csr 90911 ROE 1'b1: There are no read commands outstanding to the attached slave device 3 3 0x1 R UNSD_63_4 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_UNSD_63_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_UNSD_63_4_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_UNSD_63_4_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_UNSD_63_4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_UNSD_63_4_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_UNSD_63_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_UNSD_63_4_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_STS_UNSD_63_4_SET ns_noc_io_spio_soc_ip.csr 90921 UNSD_63_4 63 4 0x000000000000000 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_bridge_id bridge_spio_p10_pcie_rbm_s_9_8_as_bridge_id SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_BRIDGE_ID_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_BRIDGE_ID_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_BRIDGE_ID_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_BRIDGE_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 90952 spio_p10_pcie_rbm_s register as_bridge_id 0x25D08 R 0x0000000000000009 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_as_bridge_id Unique identifier assigned to the slave bridge. false false false false ID SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_BRIDGE_ID_ID_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_BRIDGE_ID_ID_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_BRIDGE_ID_ID_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_BRIDGE_ID_ID_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_BRIDGE_ID_ID_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_BRIDGE_ID_ID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_BRIDGE_ID_ID_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_BRIDGE_ID_ID_SET ns_noc_io_spio_soc_ip.csr 90941 ID Unique bridge ID 15 0 0x0009 R UNSD_63_16 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_BRIDGE_ID_UNSD_63_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_BRIDGE_ID_UNSD_63_16_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_BRIDGE_ID_UNSD_63_16_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_BRIDGE_ID_UNSD_63_16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_BRIDGE_ID_UNSD_63_16_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_BRIDGE_ID_UNSD_63_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_BRIDGE_ID_UNSD_63_16_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_spio_soc_ip.csr 90951 UNSD_63_16 63 16 0x000000000000 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_err bridge_spio_p10_pcie_rbm_s_9_8_as_err SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 91305 spio_p10_pcie_rbm_s register as_err 0x25E00 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_as_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E0_SET ns_noc_io_spio_soc_ip.csr 90973 E0 1'b1: Read decode error response: Decode error response received from slave device for read command 0 0 0x0 R/W E1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E1_SET ns_noc_io_spio_soc_ip.csr 90985 E1 1'b1: Read slave error response: Slave error response received from slave device for read command 1 1 0x0 R/W E2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E2_SET ns_noc_io_spio_soc_ip.csr 90998 E2 1'b1: [FATAL] Unknown read response destination: RID from read response produces a destination which is not present in the routing table 2 2 0x0 R/W E3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E3_SET ns_noc_io_spio_soc_ip.csr 91012 E3 1'b1: [FATAL] Interleaved read response: Interleaved read response. This can occur if interleaved read response is received from a slave device for which a de-interleaver was not specified 3 3 0x0 R/W E4 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E4_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E4_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E4_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E4_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E4_SET ns_noc_io_spio_soc_ip.csr 91024 E4 1'b1: Read command modified: A read command which was marked as non-modifiable was modified by the slave bridge 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_UNSD_15_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_UNSD_15_5_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_UNSD_15_5_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_UNSD_15_5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_UNSD_15_5_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_UNSD_15_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_UNSD_15_5_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 91035 UNSD_15_5 15 5 0x000 R E16 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E16_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E16_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E16_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E16_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E16_SET ns_noc_io_spio_soc_ip.csr 91047 E16 1'b1: Write decode error response: Decode error response received from slave device for write command 16 16 0x0 R/W E17 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E17_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E17_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E17_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E17_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E17_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E17_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E17_SET ns_noc_io_spio_soc_ip.csr 91059 E17 1'b1: Write slave error response: Slave error response received from slave device for write command 17 17 0x0 R/W E18 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E18_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E18_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E18_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E18_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E18_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E18_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E18_SET ns_noc_io_spio_soc_ip.csr 91072 E18 1'b1: [FATAL] Unknown write response destination: BID from write response produces a destination which is not present in the routing table 18 18 0x0 R/W E19 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E19_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E19_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E19_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E19_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E19_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E19_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E19_SET ns_noc_io_spio_soc_ip.csr 91084 E19 1'b1: Write command modified: A write command which was marked as non-modifiable was modified by the slave bridge 19 19 0x0 R/W UNSD_31_20 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_UNSD_31_20_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_UNSD_31_20_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_UNSD_31_20_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_UNSD_31_20_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_UNSD_31_20_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_UNSD_31_20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_UNSD_31_20_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_UNSD_31_20_SET ns_noc_io_spio_soc_ip.csr 91095 UNSD_31_20 31 20 0x000 R E32 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E32_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E32_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E32_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E32_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E32_SET ns_noc_io_spio_soc_ip.csr 91107 E32 1'b1: [FATAL] Traffic sent to a noc layer which is power gated 32 32 0x0 R/W E33 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E33_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E33_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E33_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E33_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E33_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E33_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E33_SET ns_noc_io_spio_soc_ip.csr 91118 E33 1'b1: [FATAL] Parity error in config/status registers 33 33 0x0 R/W E34 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E34_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E34_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E34_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E34_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E34_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E34_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E34_SET ns_noc_io_spio_soc_ip.csr 91129 E34 1'b1: [FATAL] RDATA Parity error 34 34 0x0 R/W E35 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E35_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E35_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E35_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E35_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E35_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E35_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E35_SET ns_noc_io_spio_soc_ip.csr 91140 E35 1'b1: [FATAL] RRESP Parity error 35 35 0x0 R/W E36 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E36_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E36_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E36_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E36_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E36_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E36_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E36_SET ns_noc_io_spio_soc_ip.csr 91151 E36 1'b1: [FATAL] BRESP Parity error 36 36 0x0 R/W E37 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E37_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E37_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E37_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E37_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E37_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E37_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E37_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E37_SET ns_noc_io_spio_soc_ip.csr 91162 E37 1'b1: [FATAL] AC Parity error 37 37 0x0 R/W E38 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E38_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E38_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E38_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E38_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E38_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E38_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E38_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E38_SET ns_noc_io_spio_soc_ip.csr 91173 E38 1'b1: [FATAL] ACADDR Parity error 38 38 0x0 R/W E39 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E39_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E39_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E39_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E39_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E39_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E39_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E39_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E39_SET ns_noc_io_spio_soc_ip.csr 91185 E39 1'b1: [FATAL] R Ch Cmdtbl Parity Err 39 39 0x0 R E40 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E40_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E40_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E40_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E40_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E40_SET ns_noc_io_spio_soc_ip.csr 91197 E40 1'b1: [FATAL] B Ch Cmdtbl Parity Err 40 40 0x0 R E41 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E41_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E41_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E41_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E41_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E41_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E41_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E41_SET ns_noc_io_spio_soc_ip.csr 91209 E41 1'b1: [FATAL] Rx Fifo Parity Err 41 41 0x0 R E42 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E42_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E42_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E42_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E42_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E42_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E42_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E42_SET ns_noc_io_spio_soc_ip.csr 91221 E42 1'b1: [FATAL] CRCD Ch Reorder Buffer Parity Err 42 42 0x0 R E43 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E43_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E43_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E43_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E43_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E43_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E43_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E43_SET ns_noc_io_spio_soc_ip.csr 91233 E43 1'b1: [FATAL] Ack Ch Wack Reorder Buffer Parity Err 43 43 0x0 R E44 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E44_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E44_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E44_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E44_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E44_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E44_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E44_SET ns_noc_io_spio_soc_ip.csr 91245 E44 1'b1: [FATAL] Ack Ch Rack Reorder Buffer Parity Err 44 44 0x0 R E45 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E45_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E45_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E45_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E45_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E45_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E45_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E45_SET ns_noc_io_spio_soc_ip.csr 91257 E45 1'b1: [FATAL] B Ch Drain Fifo Parity Err 45 45 0x0 R E46 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E46_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E46_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E46_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E46_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E46_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E46_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E46_SET ns_noc_io_spio_soc_ip.csr 91269 E46 1'b1: [FATAL] R Ch Flush Fifo Parity Err 46 46 0x0 R E47 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E47_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E47_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E47_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E47_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E47_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E47_SET ns_noc_io_spio_soc_ip.csr 91281 E47 1'b1: [FATAL] R Ch Deinterleaver Cmdtbl Parity Err 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E48_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E48_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E48_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E48_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_E48_SET ns_noc_io_spio_soc_ip.csr 91293 E48 1'b1: [FATAL] R Ch Deinterleaver Data Buffer Parity Err 48 48 0x0 R UNSD_63_49 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_UNSD_63_49_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_UNSD_63_49_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_UNSD_63_49_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_UNSD_63_49_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_UNSD_63_49_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_UNSD_63_49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_UNSD_63_49_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_ERR_UNSD_63_49_SET ns_noc_io_spio_soc_ip.csr 91304 UNSD_63_49 63 49 0x0000 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_intm bridge_spio_p10_pcie_rbm_s_9_8_as_intm SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 91645 spio_p10_pcie_rbm_s register as_intm 0x25E40 R/W 0x0000007d000b0013 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_as_intm Interrupt mask register.Individual bit positions match the error bit positions in AS_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M0_SET ns_noc_io_spio_soc_ip.csr 91326 M0 Mask interrupts for read channel 0 0 0x1 R/W M1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M1_SET ns_noc_io_spio_soc_ip.csr 91337 M1 Mask interrupts for read channel 1 1 0x1 R/W M2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M2_SET ns_noc_io_spio_soc_ip.csr 91348 M2 Mask interrupts for read channel 2 2 0x0 R/W M3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M3_SET ns_noc_io_spio_soc_ip.csr 91359 M3 Mask interrupts for read channel 3 3 0x0 R/W M4 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M4_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M4_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M4_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M4_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M4_SET ns_noc_io_spio_soc_ip.csr 91370 M4 Mask interrupts for read channel 4 4 0x1 R/W UNSD_15_5 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_UNSD_15_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_UNSD_15_5_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_UNSD_15_5_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_UNSD_15_5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_UNSD_15_5_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_UNSD_15_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_UNSD_15_5_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 91381 UNSD_15_5 15 5 0x000 R M16 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M16_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M16_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M16_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M16_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M16_SET ns_noc_io_spio_soc_ip.csr 91392 M16 Mask interrupts for write channel 16 16 0x1 R/W M17 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M17_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M17_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M17_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M17_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M17_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M17_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M17_SET ns_noc_io_spio_soc_ip.csr 91403 M17 Mask interrupts for write channel 17 17 0x1 R/W M18 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M18_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M18_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M18_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M18_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M18_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M18_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M18_SET ns_noc_io_spio_soc_ip.csr 91414 M18 Mask interrupts for write channel 18 18 0x0 R/W M19 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M19_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M19_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M19_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M19_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M19_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M19_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M19_SET ns_noc_io_spio_soc_ip.csr 91425 M19 Mask interrupts for write channel 19 19 0x1 R/W UNSD_31_20 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_UNSD_31_20_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_UNSD_31_20_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_UNSD_31_20_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_UNSD_31_20_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_UNSD_31_20_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_UNSD_31_20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_UNSD_31_20_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_UNSD_31_20_SET ns_noc_io_spio_soc_ip.csr 91436 UNSD_31_20 31 20 0x000 R M32 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M32_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M32_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M32_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M32_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M32_SET ns_noc_io_spio_soc_ip.csr 91447 M32 Mask interrupt on traffic to PG layer 32 32 0x1 R/W M33 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M33_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M33_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M33_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M33_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M33_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M33_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M33_SET ns_noc_io_spio_soc_ip.csr 91458 M33 Mask interrupt on csr parity errors 33 33 0x0 R/W M34 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M34_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M34_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M34_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M34_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M34_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M34_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M34_SET ns_noc_io_spio_soc_ip.csr 91469 M34 RDATA parity interrupt Mask 34 34 0x1 R/W M35 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M35_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M35_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M35_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M35_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M35_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M35_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M35_SET ns_noc_io_spio_soc_ip.csr 91480 M35 RRESP parity interrupt Mask 35 35 0x1 R/W M36 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M36_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M36_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M36_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M36_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M36_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M36_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M36_SET ns_noc_io_spio_soc_ip.csr 91491 M36 BRESP parity interrupt Mask 36 36 0x1 R/W M37 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M37_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M37_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M37_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M37_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M37_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M37_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M37_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M37_SET ns_noc_io_spio_soc_ip.csr 91502 M37 AC parity interrupt Mask 37 37 0x1 R/W M38 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M38_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M38_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M38_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M38_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M38_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M38_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M38_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_M38_SET ns_noc_io_spio_soc_ip.csr 91513 M38 ACADDR parity interrupt Mask 38 38 0x1 R/W E39 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E39_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E39_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E39_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E39_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E39_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E39_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E39_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E39_SET ns_noc_io_spio_soc_ip.csr 91525 E39 1'b1: R Ch Cmdtbl Parity Err Intr Mask 39 39 0x0 R E40 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E40_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E40_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E40_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E40_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E40_SET ns_noc_io_spio_soc_ip.csr 91537 E40 1'b1: B Ch Cmdtbl Parity Err Intr Mask 40 40 0x0 R E41 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E41_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E41_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E41_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E41_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E41_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E41_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E41_SET ns_noc_io_spio_soc_ip.csr 91549 E41 1'b1: Rx Fifo Parity Err Intr Mask 41 41 0x0 R E42 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E42_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E42_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E42_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E42_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E42_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E42_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E42_SET ns_noc_io_spio_soc_ip.csr 91561 E42 1'b1: CRCD Ch Reorder Buffer Parity Err Intr Mask 42 42 0x0 R E43 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E43_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E43_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E43_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E43_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E43_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E43_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E43_SET ns_noc_io_spio_soc_ip.csr 91573 E43 1'b1: Ack Ch Wack Reorder Buffer Parity Err IntrMask 43 43 0x0 R E44 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E44_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E44_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E44_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E44_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E44_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E44_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E44_SET ns_noc_io_spio_soc_ip.csr 91585 E44 1'b1: Ack Ch Rack Reorder Buffer Parity Err Intr Mask 44 44 0x0 R E45 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E45_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E45_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E45_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E45_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E45_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E45_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E45_SET ns_noc_io_spio_soc_ip.csr 91597 E45 1'b1: B Ch Drain Fifo Parity Err Intr Mask 45 45 0x0 R E46 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E46_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E46_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E46_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E46_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E46_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E46_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E46_SET ns_noc_io_spio_soc_ip.csr 91609 E46 1'b1: R Ch Flush Fifo Parity Err Intr Mask 46 46 0x0 R E47 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E47_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E47_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E47_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E47_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E47_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E47_SET ns_noc_io_spio_soc_ip.csr 91621 E47 1'b1: R Ch Deinterleaver Cmdtbl Parity Err Intr Mask 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E48_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E48_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E48_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E48_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_E48_SET ns_noc_io_spio_soc_ip.csr 91633 E48 1'b1: R Ch Deinterleaver Data Buffer Parity Err Intr Mask 48 48 0x0 R UNSD_63_49 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_UNSD_63_49_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_UNSD_63_49_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_UNSD_63_49_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_UNSD_63_49_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_UNSD_63_49_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_UNSD_63_49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_UNSD_63_49_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_INTM_UNSD_63_49_SET ns_noc_io_spio_soc_ip.csr 91644 UNSD_63_49 63 49 0x0000 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_ccmd bridge_spio_p10_pcie_rbm_s_9_8_as_ccmd SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 91720 spio_p10_pcie_rbm_s register as_ccmd 0x25F00 R/W 0x0000000003000000 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_as_ccmd Not applicable for current release. false false false false UNSD_23_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_UNSD_23_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_UNSD_23_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_UNSD_23_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_UNSD_23_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_UNSD_23_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_UNSD_23_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_UNSD_23_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_UNSD_23_0_SET ns_noc_io_spio_soc_ip.csr 91663 UNSD_23_0 23 0 0x000000 R rdy SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_RDY_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_RDY_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_RDY_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_RDY_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_RDY_SET ns_noc_io_spio_soc_ip.csr 91674 rdy 1'b1: Ready 24 24 0x1 R/W val SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_VAL_SET ns_noc_io_spio_soc_ip.csr 91685 val 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_UNSD_27_26_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_UNSD_27_26_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_UNSD_27_26_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_UNSD_27_26_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_UNSD_27_26_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_UNSD_27_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_UNSD_27_26_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_UNSD_27_26_SET ns_noc_io_spio_soc_ip.csr 91696 UNSD_27_26 27 26 0x0 R intfid SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_INTFID_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_INTFID_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_INTFID_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_INTFID_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_INTFID_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_INTFID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_INTFID_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_INTFID_SET ns_noc_io_spio_soc_ip.csr 91708 intfid 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_63_31 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_UNSD_63_31_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_UNSD_63_31_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_UNSD_63_31_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_UNSD_63_31_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_UNSD_63_31_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_UNSD_63_31_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_UNSD_63_31_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMD_UNSD_63_31_SET ns_noc_io_spio_soc_ip.csr 91719 UNSD_63_31 63 31 0x000000000 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_ccmdmsk bridge_spio_p10_pcie_rbm_s_9_8_as_ccmdmsk SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 91772 spio_p10_pcie_rbm_s register as_ccmdmsk 0x25F08 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_as_ccmdmsk Not applicable for current release. false false false false UNSD_23_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_UNSD_23_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_UNSD_23_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_UNSD_23_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_UNSD_23_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_UNSD_23_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_UNSD_23_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_UNSD_23_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_UNSD_23_0_SET ns_noc_io_spio_soc_ip.csr 91738 UNSD_23_0 23 0 0x000000 R rdy SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_RDY_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_RDY_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_RDY_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_RDY_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_RDY_SET ns_noc_io_spio_soc_ip.csr 91749 rdy 1'b1: Ready 24 24 0x0 R/W val SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_VAL_SET ns_noc_io_spio_soc_ip.csr 91760 val 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_UNSD_63_26_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_UNSD_63_26_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_UNSD_63_26_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_UNSD_63_26_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_UNSD_63_26_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_UNSD_63_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_UNSD_63_26_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CCMDMSK_UNSD_63_26_SET ns_noc_io_spio_soc_ip.csr 91771 UNSD_63_26 63 26 0x0000000000 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_cntr bridge_spio_p10_pcie_rbm_s_9_8_as_cntr SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CNTR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CNTR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CNTR_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CNTR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 91802 spio_p10_pcie_rbm_s register as_cntr 0x25F10 R 0x0000000000000000 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_as_cntr Not applicable for current release. false false false false CNTR SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CNTR_CNTR_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CNTR_CNTR_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CNTR_CNTR_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CNTR_CNTR_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CNTR_CNTR_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CNTR_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CNTR_CNTR_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CNTR_CNTR_SET ns_noc_io_spio_soc_ip.csr 91791 CNTR Counter 31 0 0x00000000 R UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CNTR_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CNTR_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CNTR_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CNTR_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CNTR_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CNTR_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CNTR_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_CNTR_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 91801 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_arovrd bridge_spio_p10_pcie_rbm_s_9_8_as_arovrd SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 91915 spio_p10_pcie_rbm_s register as_arovrd 0x25F18 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_as_arovrd AR Overrides. false false false false arcache_val SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 91820 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 91833 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 91844 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 91855 UNSD_11_11 11 11 0x0 R arprot_enb SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 91868 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 91879 UNSD_15_15 15 15 0x0 R arqos_val SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 91890 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_ARQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 91903 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AROVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 91914 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_as_awovrd bridge_spio_p10_pcie_rbm_s_9_8_as_awovrd SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 92028 spio_p10_pcie_rbm_s register as_awovrd 0x25F20 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_as_awovrd AW Overrides. false false false false awcache_val SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 91933 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 91946 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 91957 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 91968 UNSD_11_11 11 11 0x0 R awprot_enb SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 91981 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 91992 UNSD_15_15 15 15 0x0 R awqos_val SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 92003 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_AWQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 92016 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_AS_AWOVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 92027 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_p_0 bridge_spio_p10_pcie_rbm_s_9_8_p_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 92093 spio_p10_pcie_rbm_s register p_0 0x27000 R/W 0x00000003 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_0_SET ns_noc_io_spio_soc_ip.csr 92056 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_1_SET ns_noc_io_spio_soc_ip.csr 92068 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_2_SET ns_noc_io_spio_soc_ip.csr 92080 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_0_WT_QOS_3_SET ns_noc_io_spio_soc_ip.csr 92092 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_p_1 bridge_spio_p10_pcie_rbm_s_9_8_p_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 92159 spio_p10_pcie_rbm_s register p_1 0x27008 R 0x00000000 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_4_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_4_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_4_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_4_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_4_SET ns_noc_io_spio_soc_ip.csr 92122 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_5_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_5_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_5_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_5_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_5_SET ns_noc_io_spio_soc_ip.csr 92134 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_6_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_6_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_6_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_6_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_6_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_6_SET ns_noc_io_spio_soc_ip.csr 92146 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_7_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_7_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_7_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_7_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_7_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_1_WT_QOS_7_SET ns_noc_io_spio_soc_ip.csr 92158 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_p_2 bridge_spio_p10_pcie_rbm_s_9_8_p_2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 92225 spio_p10_pcie_rbm_s register p_2 0x27010 R 0x00000000 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_8_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_8_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_8_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_8_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_8_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_8_SET ns_noc_io_spio_soc_ip.csr 92188 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_9_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_9_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_9_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_9_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_9_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_9_SET ns_noc_io_spio_soc_ip.csr 92200 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_10_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_10_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_10_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_10_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_10_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_10_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_10_SET ns_noc_io_spio_soc_ip.csr 92212 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_11_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_11_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_11_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_11_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_11_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_2_WT_QOS_11_SET ns_noc_io_spio_soc_ip.csr 92224 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_p_3 bridge_spio_p10_pcie_rbm_s_9_8_p_3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 92291 spio_p10_pcie_rbm_s register p_3 0x27018 R 0x00000000 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_12_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_12_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_12_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_12_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_12_SET ns_noc_io_spio_soc_ip.csr 92254 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_13_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_13_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_13_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_13_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_13_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_13_SET ns_noc_io_spio_soc_ip.csr 92266 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_14_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_14_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_14_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_14_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_14_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_14_SET ns_noc_io_spio_soc_ip.csr 92278 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_15_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_15_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_15_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_15_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_15_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_P_3_WT_QOS_15_SET ns_noc_io_spio_soc_ip.csr 92290 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_txe bridge_spio_p10_pcie_rbm_s_9_8_txe SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 92437 spio_p10_pcie_rbm_s register txe 0x27040 R/W 0x00000000 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_TRANS_WITHOUT_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_TRANS_WITHOUT_SOP_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_TRANS_WITHOUT_SOP_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_TRANS_WITHOUT_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_TRANS_WITHOUT_SOP_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_TRANS_WITHOUT_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_TRANS_WITHOUT_SOP_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_spio_soc_ip.csr 92318 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_SOP_AFTER_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_SOP_AFTER_SOP_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_SOP_AFTER_SOP_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_SOP_AFTER_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_SOP_AFTER_SOP_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_SOP_AFTER_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_SOP_AFTER_SOP_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_SOP_AFTER_SOP_SET ns_noc_io_spio_soc_ip.csr 92330 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 92345 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 92358 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_spio_soc_ip.csr 92372 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_spio_soc_ip.csr 92386 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_spio_soc_ip.csr 92400 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_spio_soc_ip.csr 92414 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 92425 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXE_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 92436 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_txem bridge_spio_p10_pcie_rbm_s_9_8_txem SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 92516 spio_p10_pcie_rbm_s register txem 0x27048 R/W 0x00000008 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_UNSD_1_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_UNSD_1_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_UNSD_1_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_UNSD_1_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_UNSD_1_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_UNSD_1_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_UNSD_1_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_UNSD_1_0_SET ns_noc_io_spio_soc_ip.csr 92460 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 92471 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 92482 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_UNSD_7_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_UNSD_7_4_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_UNSD_7_4_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_UNSD_7_4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_UNSD_7_4_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_UNSD_7_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_UNSD_7_4_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_UNSD_7_4_SET ns_noc_io_spio_soc_ip.csr 92493 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 92504 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_TXEM_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 92515 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btus_0 bridge_spio_p10_pcie_rbm_s_9_8_btus_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 92884 spio_p10_pcie_rbm_s register btus_0 0x27058 R 0x00000000 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_A_SET ns_noc_io_spio_soc_ip.csr 92542 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_B_SET ns_noc_io_spio_soc_ip.csr 92553 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_C_SET ns_noc_io_spio_soc_ip.csr 92564 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L0_D_SET ns_noc_io_spio_soc_ip.csr 92575 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_A_SET ns_noc_io_spio_soc_ip.csr 92586 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_B_SET ns_noc_io_spio_soc_ip.csr 92597 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_C_SET ns_noc_io_spio_soc_ip.csr 92608 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L1_D_SET ns_noc_io_spio_soc_ip.csr 92619 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_A_SET ns_noc_io_spio_soc_ip.csr 92630 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_B_SET ns_noc_io_spio_soc_ip.csr 92641 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_C_SET ns_noc_io_spio_soc_ip.csr 92652 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L2_D_SET ns_noc_io_spio_soc_ip.csr 92663 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_A_SET ns_noc_io_spio_soc_ip.csr 92674 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_B_SET ns_noc_io_spio_soc_ip.csr 92685 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_C_SET ns_noc_io_spio_soc_ip.csr 92696 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L3_D_SET ns_noc_io_spio_soc_ip.csr 92707 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_A_SET ns_noc_io_spio_soc_ip.csr 92718 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_B_SET ns_noc_io_spio_soc_ip.csr 92729 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_C_SET ns_noc_io_spio_soc_ip.csr 92740 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L4_D_SET ns_noc_io_spio_soc_ip.csr 92751 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_A_SET ns_noc_io_spio_soc_ip.csr 92762 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_B_SET ns_noc_io_spio_soc_ip.csr 92773 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_C_SET ns_noc_io_spio_soc_ip.csr 92784 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L5_D_SET ns_noc_io_spio_soc_ip.csr 92795 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_A_SET ns_noc_io_spio_soc_ip.csr 92806 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_B_SET ns_noc_io_spio_soc_ip.csr 92817 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_C_SET ns_noc_io_spio_soc_ip.csr 92828 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L6_D_SET ns_noc_io_spio_soc_ip.csr 92839 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_A_SET ns_noc_io_spio_soc_ip.csr 92850 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_B_SET ns_noc_io_spio_soc_ip.csr 92861 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_C_SET ns_noc_io_spio_soc_ip.csr 92872 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_0_L7_D_SET ns_noc_io_spio_soc_ip.csr 92883 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btus_1 bridge_spio_p10_pcie_rbm_s_9_8_btus_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 93252 spio_p10_pcie_rbm_s register btus_1 0x27060 R 0x00000000 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_A_SET ns_noc_io_spio_soc_ip.csr 92910 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_B_SET ns_noc_io_spio_soc_ip.csr 92921 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_C_SET ns_noc_io_spio_soc_ip.csr 92932 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L8_D_SET ns_noc_io_spio_soc_ip.csr 92943 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_A_SET ns_noc_io_spio_soc_ip.csr 92954 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_B_SET ns_noc_io_spio_soc_ip.csr 92965 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_C_SET ns_noc_io_spio_soc_ip.csr 92976 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L9_D_SET ns_noc_io_spio_soc_ip.csr 92987 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_A_SET ns_noc_io_spio_soc_ip.csr 92998 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_B_SET ns_noc_io_spio_soc_ip.csr 93009 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_C_SET ns_noc_io_spio_soc_ip.csr 93020 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L10_D_SET ns_noc_io_spio_soc_ip.csr 93031 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_A_SET ns_noc_io_spio_soc_ip.csr 93042 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_B_SET ns_noc_io_spio_soc_ip.csr 93053 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_C_SET ns_noc_io_spio_soc_ip.csr 93064 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L11_D_SET ns_noc_io_spio_soc_ip.csr 93075 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_A_SET ns_noc_io_spio_soc_ip.csr 93086 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_B_SET ns_noc_io_spio_soc_ip.csr 93097 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_C_SET ns_noc_io_spio_soc_ip.csr 93108 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L12_D_SET ns_noc_io_spio_soc_ip.csr 93119 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_A_SET ns_noc_io_spio_soc_ip.csr 93130 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_B_SET ns_noc_io_spio_soc_ip.csr 93141 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_C_SET ns_noc_io_spio_soc_ip.csr 93152 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L13_D_SET ns_noc_io_spio_soc_ip.csr 93163 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_A_SET ns_noc_io_spio_soc_ip.csr 93174 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_B_SET ns_noc_io_spio_soc_ip.csr 93185 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_C_SET ns_noc_io_spio_soc_ip.csr 93196 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L14_D_SET ns_noc_io_spio_soc_ip.csr 93207 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_A_SET ns_noc_io_spio_soc_ip.csr 93218 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_B_SET ns_noc_io_spio_soc_ip.csr 93229 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_C_SET ns_noc_io_spio_soc_ip.csr 93240 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTUS_1_L15_D_SET ns_noc_io_spio_soc_ip.csr 93251 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btrl_0 bridge_spio_p10_pcie_rbm_s_9_8_btrl_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 93328 spio_p10_pcie_rbm_s register btrl_0 0x27080 R 0x00000000 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_WT_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_WT_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_WT_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_WT_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_WT_SET ns_noc_io_spio_soc_ip.csr 93276 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 93287 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_CNT_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_CNT_SET ns_noc_io_spio_soc_ip.csr 93302 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_EN_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_EN_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_EN_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_EN_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_EN_SET ns_noc_io_spio_soc_ip.csr 93316 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_0_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 93327 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btrl_1 bridge_spio_p10_pcie_rbm_s_9_8_btrl_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 93404 spio_p10_pcie_rbm_s register btrl_1 0x27088 R 0x00000000 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_WT_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_WT_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_WT_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_WT_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_WT_SET ns_noc_io_spio_soc_ip.csr 93352 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 93363 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_CNT_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_CNT_SET ns_noc_io_spio_soc_ip.csr 93378 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_EN_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_EN_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_EN_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_EN_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_EN_SET ns_noc_io_spio_soc_ip.csr 93392 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_1_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 93403 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btrl_2 bridge_spio_p10_pcie_rbm_s_9_8_btrl_2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 93480 spio_p10_pcie_rbm_s register btrl_2 0x27090 R 0x00000000 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_WT_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_WT_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_WT_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_WT_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_WT_SET ns_noc_io_spio_soc_ip.csr 93428 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 93439 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_CNT_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_CNT_SET ns_noc_io_spio_soc_ip.csr 93454 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_EN_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_EN_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_EN_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_EN_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_EN_SET ns_noc_io_spio_soc_ip.csr 93468 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_2_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 93479 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btrl_3 bridge_spio_p10_pcie_rbm_s_9_8_btrl_3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 93556 spio_p10_pcie_rbm_s register btrl_3 0x27098 R 0x00000000 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_WT_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_WT_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_WT_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_WT_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_WT_SET ns_noc_io_spio_soc_ip.csr 93504 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 93515 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_CNT_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_CNT_SET ns_noc_io_spio_soc_ip.csr 93530 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_EN_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_EN_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_EN_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_EN_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_EN_SET ns_noc_io_spio_soc_ip.csr 93544 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTRL_3_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 93555 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btperr bridge_spio_p10_pcie_rbm_s_9_8_btperr SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 93758 spio_p10_pcie_rbm_s register btperr 0x270A8 R/W 0x00000000 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L0_SET ns_noc_io_spio_soc_ip.csr 93581 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L1_SET ns_noc_io_spio_soc_ip.csr 93592 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L2_SET ns_noc_io_spio_soc_ip.csr 93603 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L3_SET ns_noc_io_spio_soc_ip.csr 93614 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L4_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L4_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L4_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L4_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L4_SET ns_noc_io_spio_soc_ip.csr 93625 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L5_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L5_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L5_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L5_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L5_SET ns_noc_io_spio_soc_ip.csr 93636 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L6_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L6_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L6_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L6_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L6_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L6_SET ns_noc_io_spio_soc_ip.csr 93647 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L7_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L7_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L7_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L7_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L7_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L7_SET ns_noc_io_spio_soc_ip.csr 93658 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L8_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L8_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L8_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L8_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L8_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L8_SET ns_noc_io_spio_soc_ip.csr 93669 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L9_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L9_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L9_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L9_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L9_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L9_SET ns_noc_io_spio_soc_ip.csr 93680 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L10_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L10_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L10_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L10_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L10_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L10_SET ns_noc_io_spio_soc_ip.csr 93691 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L11_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L11_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L11_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L11_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L11_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L11_SET ns_noc_io_spio_soc_ip.csr 93702 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L12_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L12_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L12_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L12_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L12_SET ns_noc_io_spio_soc_ip.csr 93713 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L13_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L13_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L13_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L13_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L13_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L13_SET ns_noc_io_spio_soc_ip.csr 93724 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L14_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L14_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L14_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L14_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L14_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L14_SET ns_noc_io_spio_soc_ip.csr 93735 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L15_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L15_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L15_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L15_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L15_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_L15_SET ns_noc_io_spio_soc_ip.csr 93746 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_UNSD_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERR_UNSD_SET ns_noc_io_spio_soc_ip.csr 93757 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_btperrm bridge_spio_p10_pcie_rbm_s_9_8_btperrm SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 93958 spio_p10_pcie_rbm_s register btperrm 0x270B0 R/W 0x00000000 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L0_SET ns_noc_io_spio_soc_ip.csr 93781 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L1_SET ns_noc_io_spio_soc_ip.csr 93792 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L2_SET ns_noc_io_spio_soc_ip.csr 93803 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L3_SET ns_noc_io_spio_soc_ip.csr 93814 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L4_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L4_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L4_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L4_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L4_SET ns_noc_io_spio_soc_ip.csr 93825 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L5_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L5_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L5_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L5_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L5_SET ns_noc_io_spio_soc_ip.csr 93836 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L6_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L6_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L6_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L6_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L6_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L6_SET ns_noc_io_spio_soc_ip.csr 93847 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L7_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L7_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L7_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L7_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L7_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L7_SET ns_noc_io_spio_soc_ip.csr 93858 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L8_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L8_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L8_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L8_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L8_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L8_SET ns_noc_io_spio_soc_ip.csr 93869 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L9_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L9_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L9_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L9_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L9_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L9_SET ns_noc_io_spio_soc_ip.csr 93880 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L10_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L10_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L10_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L10_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L10_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L10_SET ns_noc_io_spio_soc_ip.csr 93891 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L11_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L11_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L11_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L11_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L11_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L11_SET ns_noc_io_spio_soc_ip.csr 93902 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L12_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L12_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L12_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L12_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L12_SET ns_noc_io_spio_soc_ip.csr 93913 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L13_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L13_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L13_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L13_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L13_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L13_SET ns_noc_io_spio_soc_ip.csr 93924 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L14_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L14_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L14_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L14_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L14_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L14_SET ns_noc_io_spio_soc_ip.csr 93935 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L15_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L15_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L15_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L15_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L15_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_L15_SET ns_noc_io_spio_soc_ip.csr 93946 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_UNSD_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BTPERRM_UNSD_SET ns_noc_io_spio_soc_ip.csr 93957 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_rxe bridge_spio_p10_pcie_rbm_s_9_8_rxe SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 94066 spio_p10_pcie_rbm_s register rxe 0x27120 R/W 0x00000000 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_A_SET ns_noc_io_spio_soc_ip.csr 93986 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_B_SET ns_noc_io_spio_soc_ip.csr 93997 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_C_SET ns_noc_io_spio_soc_ip.csr 94008 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_CRC_OFLW_D_SET ns_noc_io_spio_soc_ip.csr 94019 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_EVC_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_EVC_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_EVC_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_EVC_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_EVC_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_EVC_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_EVC_OFLW_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_EVC_OFLW_SET ns_noc_io_spio_soc_ip.csr 94031 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 94042 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_EVC1_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_EVC1_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_EVC1_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_EVC1_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_EVC1_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_EVC1_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_EVC1_OFLW_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_EVC1_OFLW_SET ns_noc_io_spio_soc_ip.csr 94054 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXE_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 94065 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_rxem bridge_spio_p10_pcie_rbm_s_9_8_rxem SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 94138 spio_p10_pcie_rbm_s register rxem 0x27128 R/W 0x00000050 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_UNSD_3_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_UNSD_3_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_UNSD_3_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_UNSD_3_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_UNSD_3_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_UNSD_3_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_UNSD_3_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_UNSD_3_0_SET ns_noc_io_spio_soc_ip.csr 94087 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_EVC_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_EVC_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_EVC_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_EVC_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_EVC_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_EVC_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_EVC_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_EVC_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 94101 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 94112 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_EVC1_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_EVC1_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_EVC1_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_EVC1_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_EVC1_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_EVC1_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_EVC1_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 94126 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_RXEM_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 94137 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_brs_0 bridge_spio_p10_pcie_rbm_s_9_8_brs_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 94412 spio_p10_pcie_rbm_s register brs_0 0x27130 R 0x00000000 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 94162 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_0_SET ns_noc_io_spio_soc_ip.csr 94173 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_0_SET ns_noc_io_spio_soc_ip.csr 94184 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_0_SET ns_noc_io_spio_soc_ip.csr 94195 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_0_SET ns_noc_io_spio_soc_ip.csr 94206 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 94216 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 94227 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_1_SET ns_noc_io_spio_soc_ip.csr 94238 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_1_SET ns_noc_io_spio_soc_ip.csr 94249 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_1_SET ns_noc_io_spio_soc_ip.csr 94260 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_1_SET ns_noc_io_spio_soc_ip.csr 94271 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 94281 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 94292 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_2_SET ns_noc_io_spio_soc_ip.csr 94303 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_2_SET ns_noc_io_spio_soc_ip.csr 94314 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_2_SET ns_noc_io_spio_soc_ip.csr 94325 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_2_SET ns_noc_io_spio_soc_ip.csr 94336 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 94346 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 94357 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_V_3_SET ns_noc_io_spio_soc_ip.csr 94368 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_S_3_SET ns_noc_io_spio_soc_ip.csr 94379 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_B_3_SET ns_noc_io_spio_soc_ip.csr 94390 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_F_3_SET ns_noc_io_spio_soc_ip.csr 94401 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_0_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 94411 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_brs_1 bridge_spio_p10_pcie_rbm_s_9_8_brs_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 94686 spio_p10_pcie_rbm_s register brs_1 0x27138 R 0x00000000 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 94436 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_0_SET ns_noc_io_spio_soc_ip.csr 94447 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_0_SET ns_noc_io_spio_soc_ip.csr 94458 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_0_SET ns_noc_io_spio_soc_ip.csr 94469 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_0_SET ns_noc_io_spio_soc_ip.csr 94480 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 94490 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 94501 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_1_SET ns_noc_io_spio_soc_ip.csr 94512 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_1_SET ns_noc_io_spio_soc_ip.csr 94523 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_1_SET ns_noc_io_spio_soc_ip.csr 94534 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_1_SET ns_noc_io_spio_soc_ip.csr 94545 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 94555 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 94566 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_2_SET ns_noc_io_spio_soc_ip.csr 94577 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_2_SET ns_noc_io_spio_soc_ip.csr 94588 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_2_SET ns_noc_io_spio_soc_ip.csr 94599 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_2_SET ns_noc_io_spio_soc_ip.csr 94610 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 94620 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 94631 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_V_3_SET ns_noc_io_spio_soc_ip.csr 94642 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_S_3_SET ns_noc_io_spio_soc_ip.csr 94653 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_B_3_SET ns_noc_io_spio_soc_ip.csr 94664 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_F_3_SET ns_noc_io_spio_soc_ip.csr 94675 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRS_1_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 94685 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_brus bridge_spio_p10_pcie_rbm_s_9_8_brus SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 94755 spio_p10_pcie_rbm_s register brus 0x271B0 R 0x00000000 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_A_SET ns_noc_io_spio_soc_ip.csr 94711 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_B_SET ns_noc_io_spio_soc_ip.csr 94722 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_C_SET ns_noc_io_spio_soc_ip.csr 94733 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_V_D_SET ns_noc_io_spio_soc_ip.csr 94744 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_UNSD_31_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_UNSD_31_4_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_UNSD_31_4_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_UNSD_31_4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_UNSD_31_4_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_UNSD_31_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_UNSD_31_4_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRUS_UNSD_31_4_SET ns_noc_io_spio_soc_ip.csr 94754 UNSD_31_4 31 4 0x0000000 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_brperr0 bridge_spio_p10_pcie_rbm_s_9_8_brperr0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 94983 spio_p10_pcie_rbm_s register brperr0 0x271D0 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_D0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_D0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_D0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_D0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_D0_SET ns_noc_io_spio_soc_ip.csr 94793 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_DC0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_DC0_SET ns_noc_io_spio_soc_ip.csr 94804 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SB0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SB0_SET ns_noc_io_spio_soc_ip.csr 94815 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SBC0_SET ns_noc_io_spio_soc_ip.csr 94827 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_PK0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_PK0_SET ns_noc_io_spio_soc_ip.csr 94838 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 94849 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_D1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_D1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_D1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_D1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_D1_SET ns_noc_io_spio_soc_ip.csr 94860 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_DC1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_DC1_SET ns_noc_io_spio_soc_ip.csr 94871 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SB1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SB1_SET ns_noc_io_spio_soc_ip.csr 94882 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_SBC1_SET ns_noc_io_spio_soc_ip.csr 94894 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_PK1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_PK1_SET ns_noc_io_spio_soc_ip.csr 94905 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 94916 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 94927 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 94938 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 94949 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 94960 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 94971 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 94982 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_brperr1 bridge_spio_p10_pcie_rbm_s_9_8_brperr1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 95099 spio_p10_pcie_rbm_s register brperr1 0x271D8 R 0x0000000000000000 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 95021 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 95032 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 95043 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 95054 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 95065 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 95076 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 95087 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERR1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 95098 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_brperrm0 bridge_spio_p10_pcie_rbm_s_9_8_brperrm0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 95320 spio_p10_pcie_rbm_s register brperrm0 0x271E0 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_D0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_D0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_D0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_D0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_D0_SET ns_noc_io_spio_soc_ip.csr 95126 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_DC0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_DC0_SET ns_noc_io_spio_soc_ip.csr 95138 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SB0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SB0_SET ns_noc_io_spio_soc_ip.csr 95149 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SBC0_SET ns_noc_io_spio_soc_ip.csr 95161 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_PK0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_PK0_SET ns_noc_io_spio_soc_ip.csr 95173 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 95184 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_D1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_D1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_D1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_D1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_D1_SET ns_noc_io_spio_soc_ip.csr 95195 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_DC1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_DC1_SET ns_noc_io_spio_soc_ip.csr 95207 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SB1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SB1_SET ns_noc_io_spio_soc_ip.csr 95218 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_SBC1_SET ns_noc_io_spio_soc_ip.csr 95230 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_PK1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_PK1_SET ns_noc_io_spio_soc_ip.csr 95242 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 95253 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 95264 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 95275 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 95286 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 95297 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 95308 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 95319 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p10_pcie_rbm_s_9_8_brperrm1 bridge_spio_p10_pcie_rbm_s_9_8_brperrm1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 95425 spio_p10_pcie_rbm_s register brperrm1 0x271E8 R 0x0000000000000000 Spio_noc_bridge_spio_p10_pcie_rbm_s_9_8_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 95347 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 95358 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 95369 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 95380 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 95391 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 95402 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 95413 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_RBM_S_9_8_BRPERRM1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 95424 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p10_pcie_s_10_9_as_cgc bridge_spio_p10_pcie_s_10_9_as_cgc SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGC_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGC_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGC_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 95462 spio_p10_pcie_s register as_cgc 0x29C10 R/W 0x0000000000000064 Spio_noc_bridge_spio_p10_pcie_s_10_9_as_cgc Programmable intervals used by coarse clock gating logic. This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGC_HYSTERESIS_COUNTER_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGC_HYSTERESIS_COUNTER_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGC_HYSTERESIS_COUNTER_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGC_HYSTERESIS_COUNTER_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGC_HYSTERESIS_COUNTER_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGC_HYSTERESIS_COUNTER_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGC_HYSTERESIS_COUNTER_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_spio_soc_ip.csr 95450 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGC_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGC_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGC_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGC_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGC_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGC_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGC_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGC_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 95461 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p10_pcie_s_10_9_as_cgo bridge_spio_p10_pcie_s_10_9_as_cgo SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGO_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGO_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGO_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGO_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 95497 spio_p10_pcie_s register as_cgo 0x29C18 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_pcie_s_10_9_as_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the slave bridge. false false false false FPO SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGO_FPO_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGO_FPO_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGO_FPO_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGO_FPO_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGO_FPO_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGO_FPO_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGO_FPO_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGO_FPO_SET ns_noc_io_spio_soc_ip.csr 95485 FPO 1'b1: Clock gating override enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGO_UNSD_63_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGO_UNSD_63_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGO_UNSD_63_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGO_UNSD_63_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGO_UNSD_63_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGO_UNSD_63_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGO_UNSD_63_1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CGO_UNSD_63_1_SET ns_noc_io_spio_soc_ip.csr 95496 UNSD_63_1 63 1 0x0000000000000000 R register spio_noc.bridge_spio_p10_pcie_s_10_9_as_sts bridge_spio_p10_pcie_s_10_9_as_sts SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 95571 spio_p10_pcie_s register as_sts 0x29D00 R 0x000000000000000c Spio_noc_bridge_spio_p10_pcie_s_10_9_as_sts Slave bridge status bits. false false false false WOF SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_WOF_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_WOF_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_WOF_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_WOF_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_WOF_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_WOF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_WOF_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_WOF_SET ns_noc_io_spio_soc_ip.csr 95520 WOF 1'b1: Maximum number of supported write commands are outstanding to the attached slave device awaiting response, no more write commands will be issued to slave till responses are received. 1'b0: Slave device can expect more write commands from NoC 0 0 0x0 R ROF SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_ROF_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_ROF_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_ROF_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_ROF_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_ROF_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_ROF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_ROF_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_ROF_SET ns_noc_io_spio_soc_ip.csr 95536 ROF 1'b1: Maximum number of supported read commands are outstanding to the attached slave device awaiting response, no more read commands will be issued to slave till responses are received. 1'b0: Slave bridge can accept more read commands from the NoC 1 1 0x0 R WOE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_WOE_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_WOE_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_WOE_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_WOE_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_WOE_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_WOE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_WOE_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_WOE_SET ns_noc_io_spio_soc_ip.csr 95548 WOE 1'b1: There are no write commands outstanding to the attached slave device 2 2 0x1 R ROE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_ROE_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_ROE_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_ROE_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_ROE_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_ROE_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_ROE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_ROE_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_ROE_SET ns_noc_io_spio_soc_ip.csr 95560 ROE 1'b1: There are no read commands outstanding to the attached slave device 3 3 0x1 R UNSD_63_4 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_UNSD_63_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_UNSD_63_4_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_UNSD_63_4_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_UNSD_63_4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_UNSD_63_4_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_UNSD_63_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_UNSD_63_4_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_STS_UNSD_63_4_SET ns_noc_io_spio_soc_ip.csr 95570 UNSD_63_4 63 4 0x000000000000000 R register spio_noc.bridge_spio_p10_pcie_s_10_9_as_bridge_id bridge_spio_p10_pcie_s_10_9_as_bridge_id SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_BRIDGE_ID_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_BRIDGE_ID_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_BRIDGE_ID_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_BRIDGE_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 95601 spio_p10_pcie_s register as_bridge_id 0x29D08 R 0x000000000000000a Spio_noc_bridge_spio_p10_pcie_s_10_9_as_bridge_id Unique identifier assigned to the slave bridge. false false false false ID SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_BRIDGE_ID_ID_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_BRIDGE_ID_ID_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_BRIDGE_ID_ID_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_BRIDGE_ID_ID_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_BRIDGE_ID_ID_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_BRIDGE_ID_ID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_BRIDGE_ID_ID_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_BRIDGE_ID_ID_SET ns_noc_io_spio_soc_ip.csr 95590 ID Unique bridge ID 15 0 0x000a R UNSD_63_16 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_BRIDGE_ID_UNSD_63_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_BRIDGE_ID_UNSD_63_16_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_BRIDGE_ID_UNSD_63_16_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_BRIDGE_ID_UNSD_63_16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_BRIDGE_ID_UNSD_63_16_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_BRIDGE_ID_UNSD_63_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_BRIDGE_ID_UNSD_63_16_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_spio_soc_ip.csr 95600 UNSD_63_16 63 16 0x000000000000 R register spio_noc.bridge_spio_p10_pcie_s_10_9_as_err bridge_spio_p10_pcie_s_10_9_as_err SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 95954 spio_p10_pcie_s register as_err 0x29E00 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_pcie_s_10_9_as_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E0_SET ns_noc_io_spio_soc_ip.csr 95622 E0 1'b1: Read decode error response: Decode error response received from slave device for read command 0 0 0x0 R/W E1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E1_SET ns_noc_io_spio_soc_ip.csr 95634 E1 1'b1: Read slave error response: Slave error response received from slave device for read command 1 1 0x0 R/W E2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E2_SET ns_noc_io_spio_soc_ip.csr 95647 E2 1'b1: [FATAL] Unknown read response destination: RID from read response produces a destination which is not present in the routing table 2 2 0x0 R/W E3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E3_SET ns_noc_io_spio_soc_ip.csr 95661 E3 1'b1: [FATAL] Interleaved read response: Interleaved read response. This can occur if interleaved read response is received from a slave device for which a de-interleaver was not specified 3 3 0x0 R/W E4 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E4_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E4_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E4_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E4_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E4_SET ns_noc_io_spio_soc_ip.csr 95673 E4 1'b1: Read command modified: A read command which was marked as non-modifiable was modified by the slave bridge 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_UNSD_15_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_UNSD_15_5_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_UNSD_15_5_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_UNSD_15_5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_UNSD_15_5_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_UNSD_15_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_UNSD_15_5_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 95684 UNSD_15_5 15 5 0x000 R E16 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E16_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E16_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E16_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E16_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E16_SET ns_noc_io_spio_soc_ip.csr 95696 E16 1'b1: Write decode error response: Decode error response received from slave device for write command 16 16 0x0 R/W E17 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E17_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E17_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E17_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E17_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E17_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E17_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E17_SET ns_noc_io_spio_soc_ip.csr 95708 E17 1'b1: Write slave error response: Slave error response received from slave device for write command 17 17 0x0 R/W E18 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E18_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E18_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E18_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E18_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E18_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E18_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E18_SET ns_noc_io_spio_soc_ip.csr 95721 E18 1'b1: [FATAL] Unknown write response destination: BID from write response produces a destination which is not present in the routing table 18 18 0x0 R/W E19 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E19_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E19_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E19_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E19_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E19_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E19_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E19_SET ns_noc_io_spio_soc_ip.csr 95733 E19 1'b1: Write command modified: A write command which was marked as non-modifiable was modified by the slave bridge 19 19 0x0 R/W UNSD_31_20 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_UNSD_31_20_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_UNSD_31_20_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_UNSD_31_20_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_UNSD_31_20_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_UNSD_31_20_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_UNSD_31_20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_UNSD_31_20_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_UNSD_31_20_SET ns_noc_io_spio_soc_ip.csr 95744 UNSD_31_20 31 20 0x000 R E32 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E32_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E32_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E32_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E32_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E32_SET ns_noc_io_spio_soc_ip.csr 95756 E32 1'b1: [FATAL] Traffic sent to a noc layer which is power gated 32 32 0x0 R/W E33 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E33_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E33_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E33_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E33_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E33_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E33_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E33_SET ns_noc_io_spio_soc_ip.csr 95767 E33 1'b1: [FATAL] Parity error in config/status registers 33 33 0x0 R/W E34 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E34_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E34_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E34_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E34_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E34_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E34_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E34_SET ns_noc_io_spio_soc_ip.csr 95778 E34 1'b1: [FATAL] RDATA Parity error 34 34 0x0 R/W E35 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E35_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E35_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E35_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E35_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E35_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E35_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E35_SET ns_noc_io_spio_soc_ip.csr 95789 E35 1'b1: [FATAL] RRESP Parity error 35 35 0x0 R/W E36 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E36_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E36_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E36_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E36_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E36_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E36_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E36_SET ns_noc_io_spio_soc_ip.csr 95800 E36 1'b1: [FATAL] BRESP Parity error 36 36 0x0 R/W E37 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E37_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E37_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E37_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E37_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E37_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E37_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E37_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E37_SET ns_noc_io_spio_soc_ip.csr 95811 E37 1'b1: [FATAL] AC Parity error 37 37 0x0 R/W E38 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E38_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E38_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E38_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E38_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E38_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E38_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E38_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E38_SET ns_noc_io_spio_soc_ip.csr 95822 E38 1'b1: [FATAL] ACADDR Parity error 38 38 0x0 R/W E39 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E39_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E39_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E39_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E39_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E39_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E39_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E39_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E39_SET ns_noc_io_spio_soc_ip.csr 95834 E39 1'b1: [FATAL] R Ch Cmdtbl Parity Err 39 39 0x0 R E40 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E40_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E40_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E40_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E40_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E40_SET ns_noc_io_spio_soc_ip.csr 95846 E40 1'b1: [FATAL] B Ch Cmdtbl Parity Err 40 40 0x0 R E41 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E41_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E41_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E41_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E41_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E41_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E41_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E41_SET ns_noc_io_spio_soc_ip.csr 95858 E41 1'b1: [FATAL] Rx Fifo Parity Err 41 41 0x0 R E42 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E42_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E42_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E42_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E42_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E42_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E42_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E42_SET ns_noc_io_spio_soc_ip.csr 95870 E42 1'b1: [FATAL] CRCD Ch Reorder Buffer Parity Err 42 42 0x0 R E43 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E43_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E43_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E43_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E43_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E43_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E43_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E43_SET ns_noc_io_spio_soc_ip.csr 95882 E43 1'b1: [FATAL] Ack Ch Wack Reorder Buffer Parity Err 43 43 0x0 R E44 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E44_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E44_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E44_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E44_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E44_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E44_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E44_SET ns_noc_io_spio_soc_ip.csr 95894 E44 1'b1: [FATAL] Ack Ch Rack Reorder Buffer Parity Err 44 44 0x0 R E45 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E45_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E45_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E45_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E45_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E45_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E45_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E45_SET ns_noc_io_spio_soc_ip.csr 95906 E45 1'b1: [FATAL] B Ch Drain Fifo Parity Err 45 45 0x0 R E46 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E46_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E46_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E46_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E46_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E46_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E46_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E46_SET ns_noc_io_spio_soc_ip.csr 95918 E46 1'b1: [FATAL] R Ch Flush Fifo Parity Err 46 46 0x0 R E47 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E47_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E47_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E47_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E47_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E47_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E47_SET ns_noc_io_spio_soc_ip.csr 95930 E47 1'b1: [FATAL] R Ch Deinterleaver Cmdtbl Parity Err 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E48_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E48_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E48_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E48_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_E48_SET ns_noc_io_spio_soc_ip.csr 95942 E48 1'b1: [FATAL] R Ch Deinterleaver Data Buffer Parity Err 48 48 0x0 R UNSD_63_49 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_UNSD_63_49_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_UNSD_63_49_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_UNSD_63_49_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_UNSD_63_49_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_UNSD_63_49_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_UNSD_63_49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_UNSD_63_49_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_ERR_UNSD_63_49_SET ns_noc_io_spio_soc_ip.csr 95953 UNSD_63_49 63 49 0x0000 R register spio_noc.bridge_spio_p10_pcie_s_10_9_as_intm bridge_spio_p10_pcie_s_10_9_as_intm SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 96294 spio_p10_pcie_s register as_intm 0x29E40 R/W 0x0000007d000b0013 Spio_noc_bridge_spio_p10_pcie_s_10_9_as_intm Interrupt mask register.Individual bit positions match the error bit positions in AS_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M0_SET ns_noc_io_spio_soc_ip.csr 95975 M0 Mask interrupts for read channel 0 0 0x1 R/W M1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M1_SET ns_noc_io_spio_soc_ip.csr 95986 M1 Mask interrupts for read channel 1 1 0x1 R/W M2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M2_SET ns_noc_io_spio_soc_ip.csr 95997 M2 Mask interrupts for read channel 2 2 0x0 R/W M3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M3_SET ns_noc_io_spio_soc_ip.csr 96008 M3 Mask interrupts for read channel 3 3 0x0 R/W M4 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M4_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M4_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M4_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M4_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M4_SET ns_noc_io_spio_soc_ip.csr 96019 M4 Mask interrupts for read channel 4 4 0x1 R/W UNSD_15_5 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_UNSD_15_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_UNSD_15_5_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_UNSD_15_5_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_UNSD_15_5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_UNSD_15_5_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_UNSD_15_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_UNSD_15_5_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 96030 UNSD_15_5 15 5 0x000 R M16 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M16_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M16_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M16_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M16_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M16_SET ns_noc_io_spio_soc_ip.csr 96041 M16 Mask interrupts for write channel 16 16 0x1 R/W M17 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M17_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M17_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M17_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M17_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M17_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M17_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M17_SET ns_noc_io_spio_soc_ip.csr 96052 M17 Mask interrupts for write channel 17 17 0x1 R/W M18 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M18_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M18_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M18_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M18_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M18_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M18_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M18_SET ns_noc_io_spio_soc_ip.csr 96063 M18 Mask interrupts for write channel 18 18 0x0 R/W M19 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M19_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M19_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M19_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M19_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M19_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M19_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M19_SET ns_noc_io_spio_soc_ip.csr 96074 M19 Mask interrupts for write channel 19 19 0x1 R/W UNSD_31_20 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_UNSD_31_20_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_UNSD_31_20_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_UNSD_31_20_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_UNSD_31_20_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_UNSD_31_20_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_UNSD_31_20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_UNSD_31_20_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_UNSD_31_20_SET ns_noc_io_spio_soc_ip.csr 96085 UNSD_31_20 31 20 0x000 R M32 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M32_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M32_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M32_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M32_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M32_SET ns_noc_io_spio_soc_ip.csr 96096 M32 Mask interrupt on traffic to PG layer 32 32 0x1 R/W M33 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M33_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M33_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M33_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M33_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M33_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M33_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M33_SET ns_noc_io_spio_soc_ip.csr 96107 M33 Mask interrupt on csr parity errors 33 33 0x0 R/W M34 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M34_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M34_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M34_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M34_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M34_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M34_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M34_SET ns_noc_io_spio_soc_ip.csr 96118 M34 RDATA parity interrupt Mask 34 34 0x1 R/W M35 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M35_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M35_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M35_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M35_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M35_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M35_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M35_SET ns_noc_io_spio_soc_ip.csr 96129 M35 RRESP parity interrupt Mask 35 35 0x1 R/W M36 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M36_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M36_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M36_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M36_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M36_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M36_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M36_SET ns_noc_io_spio_soc_ip.csr 96140 M36 BRESP parity interrupt Mask 36 36 0x1 R/W M37 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M37_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M37_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M37_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M37_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M37_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M37_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M37_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M37_SET ns_noc_io_spio_soc_ip.csr 96151 M37 AC parity interrupt Mask 37 37 0x1 R/W M38 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M38_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M38_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M38_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M38_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M38_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M38_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M38_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_M38_SET ns_noc_io_spio_soc_ip.csr 96162 M38 ACADDR parity interrupt Mask 38 38 0x1 R/W E39 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E39_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E39_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E39_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E39_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E39_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E39_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E39_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E39_SET ns_noc_io_spio_soc_ip.csr 96174 E39 1'b1: R Ch Cmdtbl Parity Err Intr Mask 39 39 0x0 R E40 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E40_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E40_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E40_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E40_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E40_SET ns_noc_io_spio_soc_ip.csr 96186 E40 1'b1: B Ch Cmdtbl Parity Err Intr Mask 40 40 0x0 R E41 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E41_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E41_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E41_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E41_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E41_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E41_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E41_SET ns_noc_io_spio_soc_ip.csr 96198 E41 1'b1: Rx Fifo Parity Err Intr Mask 41 41 0x0 R E42 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E42_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E42_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E42_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E42_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E42_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E42_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E42_SET ns_noc_io_spio_soc_ip.csr 96210 E42 1'b1: CRCD Ch Reorder Buffer Parity Err Intr Mask 42 42 0x0 R E43 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E43_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E43_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E43_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E43_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E43_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E43_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E43_SET ns_noc_io_spio_soc_ip.csr 96222 E43 1'b1: Ack Ch Wack Reorder Buffer Parity Err IntrMask 43 43 0x0 R E44 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E44_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E44_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E44_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E44_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E44_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E44_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E44_SET ns_noc_io_spio_soc_ip.csr 96234 E44 1'b1: Ack Ch Rack Reorder Buffer Parity Err Intr Mask 44 44 0x0 R E45 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E45_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E45_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E45_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E45_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E45_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E45_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E45_SET ns_noc_io_spio_soc_ip.csr 96246 E45 1'b1: B Ch Drain Fifo Parity Err Intr Mask 45 45 0x0 R E46 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E46_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E46_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E46_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E46_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E46_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E46_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E46_SET ns_noc_io_spio_soc_ip.csr 96258 E46 1'b1: R Ch Flush Fifo Parity Err Intr Mask 46 46 0x0 R E47 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E47_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E47_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E47_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E47_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E47_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E47_SET ns_noc_io_spio_soc_ip.csr 96270 E47 1'b1: R Ch Deinterleaver Cmdtbl Parity Err Intr Mask 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E48_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E48_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E48_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E48_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_E48_SET ns_noc_io_spio_soc_ip.csr 96282 E48 1'b1: R Ch Deinterleaver Data Buffer Parity Err Intr Mask 48 48 0x0 R UNSD_63_49 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_UNSD_63_49_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_UNSD_63_49_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_UNSD_63_49_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_UNSD_63_49_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_UNSD_63_49_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_UNSD_63_49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_UNSD_63_49_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_INTM_UNSD_63_49_SET ns_noc_io_spio_soc_ip.csr 96293 UNSD_63_49 63 49 0x0000 R register spio_noc.bridge_spio_p10_pcie_s_10_9_as_ccmd bridge_spio_p10_pcie_s_10_9_as_ccmd SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 96369 spio_p10_pcie_s register as_ccmd 0x29F00 R/W 0x0000000003000000 Spio_noc_bridge_spio_p10_pcie_s_10_9_as_ccmd Not applicable for current release. false false false false UNSD_23_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_UNSD_23_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_UNSD_23_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_UNSD_23_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_UNSD_23_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_UNSD_23_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_UNSD_23_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_UNSD_23_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_UNSD_23_0_SET ns_noc_io_spio_soc_ip.csr 96312 UNSD_23_0 23 0 0x000000 R rdy SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_RDY_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_RDY_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_RDY_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_RDY_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_RDY_SET ns_noc_io_spio_soc_ip.csr 96323 rdy 1'b1: Ready 24 24 0x1 R/W val SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_VAL_SET ns_noc_io_spio_soc_ip.csr 96334 val 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_UNSD_27_26_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_UNSD_27_26_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_UNSD_27_26_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_UNSD_27_26_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_UNSD_27_26_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_UNSD_27_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_UNSD_27_26_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_UNSD_27_26_SET ns_noc_io_spio_soc_ip.csr 96345 UNSD_27_26 27 26 0x0 R intfid SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_INTFID_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_INTFID_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_INTFID_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_INTFID_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_INTFID_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_INTFID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_INTFID_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_INTFID_SET ns_noc_io_spio_soc_ip.csr 96357 intfid 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_63_31 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_UNSD_63_31_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_UNSD_63_31_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_UNSD_63_31_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_UNSD_63_31_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_UNSD_63_31_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_UNSD_63_31_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_UNSD_63_31_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMD_UNSD_63_31_SET ns_noc_io_spio_soc_ip.csr 96368 UNSD_63_31 63 31 0x000000000 R register spio_noc.bridge_spio_p10_pcie_s_10_9_as_ccmdmsk bridge_spio_p10_pcie_s_10_9_as_ccmdmsk SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 96421 spio_p10_pcie_s register as_ccmdmsk 0x29F08 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_pcie_s_10_9_as_ccmdmsk Not applicable for current release. false false false false UNSD_23_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_UNSD_23_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_UNSD_23_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_UNSD_23_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_UNSD_23_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_UNSD_23_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_UNSD_23_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_UNSD_23_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_UNSD_23_0_SET ns_noc_io_spio_soc_ip.csr 96387 UNSD_23_0 23 0 0x000000 R rdy SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_RDY_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_RDY_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_RDY_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_RDY_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_RDY_SET ns_noc_io_spio_soc_ip.csr 96398 rdy 1'b1: Ready 24 24 0x0 R/W val SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_VAL_SET ns_noc_io_spio_soc_ip.csr 96409 val 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_UNSD_63_26_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_UNSD_63_26_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_UNSD_63_26_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_UNSD_63_26_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_UNSD_63_26_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_UNSD_63_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_UNSD_63_26_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CCMDMSK_UNSD_63_26_SET ns_noc_io_spio_soc_ip.csr 96420 UNSD_63_26 63 26 0x0000000000 R register spio_noc.bridge_spio_p10_pcie_s_10_9_as_cntr bridge_spio_p10_pcie_s_10_9_as_cntr SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CNTR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CNTR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CNTR_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CNTR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 96451 spio_p10_pcie_s register as_cntr 0x29F10 R 0x0000000000000000 Spio_noc_bridge_spio_p10_pcie_s_10_9_as_cntr Not applicable for current release. false false false false CNTR SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CNTR_CNTR_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CNTR_CNTR_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CNTR_CNTR_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CNTR_CNTR_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CNTR_CNTR_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CNTR_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CNTR_CNTR_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CNTR_CNTR_SET ns_noc_io_spio_soc_ip.csr 96440 CNTR Counter 31 0 0x00000000 R UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CNTR_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CNTR_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CNTR_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CNTR_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CNTR_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CNTR_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CNTR_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_CNTR_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 96450 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p10_pcie_s_10_9_as_arovrd bridge_spio_p10_pcie_s_10_9_as_arovrd SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 96564 spio_p10_pcie_s register as_arovrd 0x29F18 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_pcie_s_10_9_as_arovrd AR Overrides. false false false false arcache_val SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 96469 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 96482 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 96493 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 96504 UNSD_11_11 11 11 0x0 R arprot_enb SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 96517 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 96528 UNSD_15_15 15 15 0x0 R arqos_val SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 96539 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_ARQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 96552 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AROVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 96563 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_p10_pcie_s_10_9_as_awovrd bridge_spio_p10_pcie_s_10_9_as_awovrd SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 96677 spio_p10_pcie_s register as_awovrd 0x29F20 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_pcie_s_10_9_as_awovrd AW Overrides. false false false false awcache_val SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 96582 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 96595 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 96606 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 96617 UNSD_11_11 11 11 0x0 R awprot_enb SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 96630 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 96641 UNSD_15_15 15 15 0x0 R awqos_val SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 96652 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_AWQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 96665 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_AS_AWOVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 96676 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_p10_pcie_s_10_9_p_0 bridge_spio_p10_pcie_s_10_9_p_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 96742 spio_p10_pcie_s register p_0 0x2B000 R/W 0x00000003 Spio_noc_bridge_spio_p10_pcie_s_10_9_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_0_SET ns_noc_io_spio_soc_ip.csr 96705 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_1_SET ns_noc_io_spio_soc_ip.csr 96717 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_2_SET ns_noc_io_spio_soc_ip.csr 96729 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_0_WT_QOS_3_SET ns_noc_io_spio_soc_ip.csr 96741 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register spio_noc.bridge_spio_p10_pcie_s_10_9_p_1 bridge_spio_p10_pcie_s_10_9_p_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 96808 spio_p10_pcie_s register p_1 0x2B008 R 0x00000000 Spio_noc_bridge_spio_p10_pcie_s_10_9_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_4_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_4_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_4_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_4_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_4_SET ns_noc_io_spio_soc_ip.csr 96771 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_5_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_5_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_5_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_5_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_5_SET ns_noc_io_spio_soc_ip.csr 96783 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_6_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_6_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_6_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_6_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_6_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_6_SET ns_noc_io_spio_soc_ip.csr 96795 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_7_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_7_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_7_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_7_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_7_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_1_WT_QOS_7_SET ns_noc_io_spio_soc_ip.csr 96807 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register spio_noc.bridge_spio_p10_pcie_s_10_9_p_2 bridge_spio_p10_pcie_s_10_9_p_2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 96874 spio_p10_pcie_s register p_2 0x2B010 R 0x00000000 Spio_noc_bridge_spio_p10_pcie_s_10_9_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_8_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_8_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_8_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_8_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_8_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_8_SET ns_noc_io_spio_soc_ip.csr 96837 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_9_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_9_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_9_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_9_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_9_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_9_SET ns_noc_io_spio_soc_ip.csr 96849 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_10_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_10_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_10_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_10_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_10_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_10_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_10_SET ns_noc_io_spio_soc_ip.csr 96861 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_11_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_11_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_11_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_11_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_11_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_2_WT_QOS_11_SET ns_noc_io_spio_soc_ip.csr 96873 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register spio_noc.bridge_spio_p10_pcie_s_10_9_p_3 bridge_spio_p10_pcie_s_10_9_p_3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 96940 spio_p10_pcie_s register p_3 0x2B018 R 0x00000000 Spio_noc_bridge_spio_p10_pcie_s_10_9_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_12_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_12_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_12_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_12_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_12_SET ns_noc_io_spio_soc_ip.csr 96903 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_13_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_13_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_13_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_13_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_13_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_13_SET ns_noc_io_spio_soc_ip.csr 96915 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_14_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_14_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_14_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_14_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_14_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_14_SET ns_noc_io_spio_soc_ip.csr 96927 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_15_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_15_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_15_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_15_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_15_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_P_3_WT_QOS_15_SET ns_noc_io_spio_soc_ip.csr 96939 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register spio_noc.bridge_spio_p10_pcie_s_10_9_txe bridge_spio_p10_pcie_s_10_9_txe SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 97086 spio_p10_pcie_s register txe 0x2B040 R/W 0x00000000 Spio_noc_bridge_spio_p10_pcie_s_10_9_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_TRANS_WITHOUT_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_TRANS_WITHOUT_SOP_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_TRANS_WITHOUT_SOP_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_TRANS_WITHOUT_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_TRANS_WITHOUT_SOP_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_TRANS_WITHOUT_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_TRANS_WITHOUT_SOP_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_spio_soc_ip.csr 96967 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_SOP_AFTER_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_SOP_AFTER_SOP_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_SOP_AFTER_SOP_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_SOP_AFTER_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_SOP_AFTER_SOP_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_SOP_AFTER_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_SOP_AFTER_SOP_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_SOP_AFTER_SOP_SET ns_noc_io_spio_soc_ip.csr 96979 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 96994 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 97007 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_spio_soc_ip.csr 97021 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_spio_soc_ip.csr 97035 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_spio_soc_ip.csr 97049 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_spio_soc_ip.csr 97063 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 97074 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXE_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 97085 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_p10_pcie_s_10_9_txem bridge_spio_p10_pcie_s_10_9_txem SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 97165 spio_p10_pcie_s register txem 0x2B048 R/W 0x00000008 Spio_noc_bridge_spio_p10_pcie_s_10_9_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_UNSD_1_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_UNSD_1_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_UNSD_1_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_UNSD_1_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_UNSD_1_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_UNSD_1_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_UNSD_1_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_UNSD_1_0_SET ns_noc_io_spio_soc_ip.csr 97109 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 97120 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 97131 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_UNSD_7_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_UNSD_7_4_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_UNSD_7_4_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_UNSD_7_4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_UNSD_7_4_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_UNSD_7_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_UNSD_7_4_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_UNSD_7_4_SET ns_noc_io_spio_soc_ip.csr 97142 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 97153 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_TXEM_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 97164 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_p10_pcie_s_10_9_btus_0 bridge_spio_p10_pcie_s_10_9_btus_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 97533 spio_p10_pcie_s register btus_0 0x2B058 R 0x00000000 Spio_noc_bridge_spio_p10_pcie_s_10_9_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_A_SET ns_noc_io_spio_soc_ip.csr 97191 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_B_SET ns_noc_io_spio_soc_ip.csr 97202 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_C_SET ns_noc_io_spio_soc_ip.csr 97213 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L0_D_SET ns_noc_io_spio_soc_ip.csr 97224 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_A_SET ns_noc_io_spio_soc_ip.csr 97235 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_B_SET ns_noc_io_spio_soc_ip.csr 97246 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_C_SET ns_noc_io_spio_soc_ip.csr 97257 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L1_D_SET ns_noc_io_spio_soc_ip.csr 97268 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_A_SET ns_noc_io_spio_soc_ip.csr 97279 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_B_SET ns_noc_io_spio_soc_ip.csr 97290 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_C_SET ns_noc_io_spio_soc_ip.csr 97301 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L2_D_SET ns_noc_io_spio_soc_ip.csr 97312 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_A_SET ns_noc_io_spio_soc_ip.csr 97323 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_B_SET ns_noc_io_spio_soc_ip.csr 97334 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_C_SET ns_noc_io_spio_soc_ip.csr 97345 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L3_D_SET ns_noc_io_spio_soc_ip.csr 97356 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_A_SET ns_noc_io_spio_soc_ip.csr 97367 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_B_SET ns_noc_io_spio_soc_ip.csr 97378 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_C_SET ns_noc_io_spio_soc_ip.csr 97389 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L4_D_SET ns_noc_io_spio_soc_ip.csr 97400 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_A_SET ns_noc_io_spio_soc_ip.csr 97411 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_B_SET ns_noc_io_spio_soc_ip.csr 97422 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_C_SET ns_noc_io_spio_soc_ip.csr 97433 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L5_D_SET ns_noc_io_spio_soc_ip.csr 97444 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_A_SET ns_noc_io_spio_soc_ip.csr 97455 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_B_SET ns_noc_io_spio_soc_ip.csr 97466 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_C_SET ns_noc_io_spio_soc_ip.csr 97477 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L6_D_SET ns_noc_io_spio_soc_ip.csr 97488 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_A_SET ns_noc_io_spio_soc_ip.csr 97499 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_B_SET ns_noc_io_spio_soc_ip.csr 97510 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_C_SET ns_noc_io_spio_soc_ip.csr 97521 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_0_L7_D_SET ns_noc_io_spio_soc_ip.csr 97532 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register spio_noc.bridge_spio_p10_pcie_s_10_9_btus_1 bridge_spio_p10_pcie_s_10_9_btus_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 97901 spio_p10_pcie_s register btus_1 0x2B060 R 0x00000000 Spio_noc_bridge_spio_p10_pcie_s_10_9_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_A_SET ns_noc_io_spio_soc_ip.csr 97559 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_B_SET ns_noc_io_spio_soc_ip.csr 97570 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_C_SET ns_noc_io_spio_soc_ip.csr 97581 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L8_D_SET ns_noc_io_spio_soc_ip.csr 97592 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_A_SET ns_noc_io_spio_soc_ip.csr 97603 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_B_SET ns_noc_io_spio_soc_ip.csr 97614 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_C_SET ns_noc_io_spio_soc_ip.csr 97625 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L9_D_SET ns_noc_io_spio_soc_ip.csr 97636 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_A_SET ns_noc_io_spio_soc_ip.csr 97647 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_B_SET ns_noc_io_spio_soc_ip.csr 97658 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_C_SET ns_noc_io_spio_soc_ip.csr 97669 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L10_D_SET ns_noc_io_spio_soc_ip.csr 97680 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_A_SET ns_noc_io_spio_soc_ip.csr 97691 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_B_SET ns_noc_io_spio_soc_ip.csr 97702 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_C_SET ns_noc_io_spio_soc_ip.csr 97713 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L11_D_SET ns_noc_io_spio_soc_ip.csr 97724 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_A_SET ns_noc_io_spio_soc_ip.csr 97735 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_B_SET ns_noc_io_spio_soc_ip.csr 97746 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_C_SET ns_noc_io_spio_soc_ip.csr 97757 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L12_D_SET ns_noc_io_spio_soc_ip.csr 97768 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_A_SET ns_noc_io_spio_soc_ip.csr 97779 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_B_SET ns_noc_io_spio_soc_ip.csr 97790 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_C_SET ns_noc_io_spio_soc_ip.csr 97801 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L13_D_SET ns_noc_io_spio_soc_ip.csr 97812 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_A_SET ns_noc_io_spio_soc_ip.csr 97823 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_B_SET ns_noc_io_spio_soc_ip.csr 97834 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_C_SET ns_noc_io_spio_soc_ip.csr 97845 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L14_D_SET ns_noc_io_spio_soc_ip.csr 97856 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_A_SET ns_noc_io_spio_soc_ip.csr 97867 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_B_SET ns_noc_io_spio_soc_ip.csr 97878 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_C_SET ns_noc_io_spio_soc_ip.csr 97889 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTUS_1_L15_D_SET ns_noc_io_spio_soc_ip.csr 97900 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register spio_noc.bridge_spio_p10_pcie_s_10_9_btrl_0 bridge_spio_p10_pcie_s_10_9_btrl_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 97977 spio_p10_pcie_s register btrl_0 0x2B080 R 0x00000000 Spio_noc_bridge_spio_p10_pcie_s_10_9_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_WT_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_WT_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_WT_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_WT_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_WT_SET ns_noc_io_spio_soc_ip.csr 97925 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 97936 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_CNT_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_CNT_SET ns_noc_io_spio_soc_ip.csr 97951 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_EN_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_EN_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_EN_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_EN_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_EN_SET ns_noc_io_spio_soc_ip.csr 97965 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_0_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 97976 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p10_pcie_s_10_9_btrl_1 bridge_spio_p10_pcie_s_10_9_btrl_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 98053 spio_p10_pcie_s register btrl_1 0x2B088 R 0x00000000 Spio_noc_bridge_spio_p10_pcie_s_10_9_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_WT_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_WT_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_WT_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_WT_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_WT_SET ns_noc_io_spio_soc_ip.csr 98001 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 98012 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_CNT_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_CNT_SET ns_noc_io_spio_soc_ip.csr 98027 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_EN_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_EN_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_EN_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_EN_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_EN_SET ns_noc_io_spio_soc_ip.csr 98041 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_1_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 98052 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p10_pcie_s_10_9_btrl_2 bridge_spio_p10_pcie_s_10_9_btrl_2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 98129 spio_p10_pcie_s register btrl_2 0x2B090 R 0x00000000 Spio_noc_bridge_spio_p10_pcie_s_10_9_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_WT_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_WT_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_WT_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_WT_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_WT_SET ns_noc_io_spio_soc_ip.csr 98077 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 98088 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_CNT_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_CNT_SET ns_noc_io_spio_soc_ip.csr 98103 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_EN_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_EN_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_EN_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_EN_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_EN_SET ns_noc_io_spio_soc_ip.csr 98117 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_2_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 98128 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p10_pcie_s_10_9_btrl_3 bridge_spio_p10_pcie_s_10_9_btrl_3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 98205 spio_p10_pcie_s register btrl_3 0x2B098 R 0x00000000 Spio_noc_bridge_spio_p10_pcie_s_10_9_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_WT_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_WT_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_WT_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_WT_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_WT_SET ns_noc_io_spio_soc_ip.csr 98153 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 98164 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_CNT_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_CNT_SET ns_noc_io_spio_soc_ip.csr 98179 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_EN_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_EN_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_EN_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_EN_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_EN_SET ns_noc_io_spio_soc_ip.csr 98193 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTRL_3_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 98204 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p10_pcie_s_10_9_btperr bridge_spio_p10_pcie_s_10_9_btperr SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 98407 spio_p10_pcie_s register btperr 0x2B0A8 R/W 0x00000000 Spio_noc_bridge_spio_p10_pcie_s_10_9_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L0_SET ns_noc_io_spio_soc_ip.csr 98230 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L1_SET ns_noc_io_spio_soc_ip.csr 98241 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L2_SET ns_noc_io_spio_soc_ip.csr 98252 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L3_SET ns_noc_io_spio_soc_ip.csr 98263 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L4_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L4_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L4_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L4_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L4_SET ns_noc_io_spio_soc_ip.csr 98274 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L5_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L5_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L5_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L5_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L5_SET ns_noc_io_spio_soc_ip.csr 98285 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L6_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L6_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L6_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L6_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L6_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L6_SET ns_noc_io_spio_soc_ip.csr 98296 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L7_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L7_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L7_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L7_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L7_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L7_SET ns_noc_io_spio_soc_ip.csr 98307 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L8_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L8_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L8_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L8_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L8_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L8_SET ns_noc_io_spio_soc_ip.csr 98318 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L9_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L9_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L9_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L9_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L9_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L9_SET ns_noc_io_spio_soc_ip.csr 98329 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L10_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L10_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L10_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L10_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L10_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L10_SET ns_noc_io_spio_soc_ip.csr 98340 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L11_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L11_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L11_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L11_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L11_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L11_SET ns_noc_io_spio_soc_ip.csr 98351 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L12_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L12_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L12_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L12_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L12_SET ns_noc_io_spio_soc_ip.csr 98362 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L13_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L13_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L13_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L13_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L13_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L13_SET ns_noc_io_spio_soc_ip.csr 98373 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L14_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L14_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L14_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L14_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L14_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L14_SET ns_noc_io_spio_soc_ip.csr 98384 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L15_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L15_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L15_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L15_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L15_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_L15_SET ns_noc_io_spio_soc_ip.csr 98395 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_UNSD_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERR_UNSD_SET ns_noc_io_spio_soc_ip.csr 98406 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_p10_pcie_s_10_9_btperrm bridge_spio_p10_pcie_s_10_9_btperrm SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 98607 spio_p10_pcie_s register btperrm 0x2B0B0 R/W 0x00000000 Spio_noc_bridge_spio_p10_pcie_s_10_9_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L0_SET ns_noc_io_spio_soc_ip.csr 98430 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L1_SET ns_noc_io_spio_soc_ip.csr 98441 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L2_SET ns_noc_io_spio_soc_ip.csr 98452 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L3_SET ns_noc_io_spio_soc_ip.csr 98463 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L4_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L4_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L4_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L4_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L4_SET ns_noc_io_spio_soc_ip.csr 98474 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L5_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L5_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L5_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L5_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L5_SET ns_noc_io_spio_soc_ip.csr 98485 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L6_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L6_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L6_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L6_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L6_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L6_SET ns_noc_io_spio_soc_ip.csr 98496 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L7_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L7_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L7_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L7_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L7_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L7_SET ns_noc_io_spio_soc_ip.csr 98507 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L8_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L8_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L8_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L8_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L8_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L8_SET ns_noc_io_spio_soc_ip.csr 98518 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L9_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L9_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L9_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L9_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L9_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L9_SET ns_noc_io_spio_soc_ip.csr 98529 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L10_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L10_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L10_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L10_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L10_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L10_SET ns_noc_io_spio_soc_ip.csr 98540 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L11_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L11_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L11_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L11_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L11_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L11_SET ns_noc_io_spio_soc_ip.csr 98551 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L12_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L12_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L12_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L12_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L12_SET ns_noc_io_spio_soc_ip.csr 98562 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L13_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L13_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L13_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L13_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L13_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L13_SET ns_noc_io_spio_soc_ip.csr 98573 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L14_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L14_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L14_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L14_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L14_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L14_SET ns_noc_io_spio_soc_ip.csr 98584 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L15_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L15_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L15_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L15_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L15_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_L15_SET ns_noc_io_spio_soc_ip.csr 98595 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_UNSD_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BTPERRM_UNSD_SET ns_noc_io_spio_soc_ip.csr 98606 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_p10_pcie_s_10_9_rxe bridge_spio_p10_pcie_s_10_9_rxe SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 98715 spio_p10_pcie_s register rxe 0x2B120 R/W 0x00000000 Spio_noc_bridge_spio_p10_pcie_s_10_9_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_A_SET ns_noc_io_spio_soc_ip.csr 98635 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_B_SET ns_noc_io_spio_soc_ip.csr 98646 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_C_SET ns_noc_io_spio_soc_ip.csr 98657 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_CRC_OFLW_D_SET ns_noc_io_spio_soc_ip.csr 98668 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_EVC_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_EVC_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_EVC_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_EVC_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_EVC_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_EVC_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_EVC_OFLW_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_EVC_OFLW_SET ns_noc_io_spio_soc_ip.csr 98680 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 98691 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_EVC1_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_EVC1_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_EVC1_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_EVC1_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_EVC1_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_EVC1_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_EVC1_OFLW_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_EVC1_OFLW_SET ns_noc_io_spio_soc_ip.csr 98703 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXE_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 98714 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_p10_pcie_s_10_9_rxem bridge_spio_p10_pcie_s_10_9_rxem SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 98787 spio_p10_pcie_s register rxem 0x2B128 R/W 0x00000050 Spio_noc_bridge_spio_p10_pcie_s_10_9_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_UNSD_3_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_UNSD_3_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_UNSD_3_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_UNSD_3_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_UNSD_3_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_UNSD_3_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_UNSD_3_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_UNSD_3_0_SET ns_noc_io_spio_soc_ip.csr 98736 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_EVC_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_EVC_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_EVC_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_EVC_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_EVC_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_EVC_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_EVC_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_EVC_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 98750 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 98761 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_EVC1_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_EVC1_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_EVC1_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_EVC1_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_EVC1_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_EVC1_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_EVC1_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 98775 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_RXEM_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 98786 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_p10_pcie_s_10_9_brs_0 bridge_spio_p10_pcie_s_10_9_brs_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 99061 spio_p10_pcie_s register brs_0 0x2B130 R 0x00000000 Spio_noc_bridge_spio_p10_pcie_s_10_9_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 98811 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_0_SET ns_noc_io_spio_soc_ip.csr 98822 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_0_SET ns_noc_io_spio_soc_ip.csr 98833 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_0_SET ns_noc_io_spio_soc_ip.csr 98844 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_0_SET ns_noc_io_spio_soc_ip.csr 98855 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 98865 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 98876 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_1_SET ns_noc_io_spio_soc_ip.csr 98887 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_1_SET ns_noc_io_spio_soc_ip.csr 98898 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_1_SET ns_noc_io_spio_soc_ip.csr 98909 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_1_SET ns_noc_io_spio_soc_ip.csr 98920 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 98930 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 98941 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_2_SET ns_noc_io_spio_soc_ip.csr 98952 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_2_SET ns_noc_io_spio_soc_ip.csr 98963 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_2_SET ns_noc_io_spio_soc_ip.csr 98974 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_2_SET ns_noc_io_spio_soc_ip.csr 98985 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 98995 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 99006 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_V_3_SET ns_noc_io_spio_soc_ip.csr 99017 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_S_3_SET ns_noc_io_spio_soc_ip.csr 99028 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_B_3_SET ns_noc_io_spio_soc_ip.csr 99039 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_F_3_SET ns_noc_io_spio_soc_ip.csr 99050 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_0_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 99060 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_p10_pcie_s_10_9_brs_1 bridge_spio_p10_pcie_s_10_9_brs_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 99335 spio_p10_pcie_s register brs_1 0x2B138 R 0x00000000 Spio_noc_bridge_spio_p10_pcie_s_10_9_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 99085 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_0_SET ns_noc_io_spio_soc_ip.csr 99096 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_0_SET ns_noc_io_spio_soc_ip.csr 99107 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_0_SET ns_noc_io_spio_soc_ip.csr 99118 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_0_SET ns_noc_io_spio_soc_ip.csr 99129 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 99139 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 99150 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_1_SET ns_noc_io_spio_soc_ip.csr 99161 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_1_SET ns_noc_io_spio_soc_ip.csr 99172 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_1_SET ns_noc_io_spio_soc_ip.csr 99183 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_1_SET ns_noc_io_spio_soc_ip.csr 99194 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 99204 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 99215 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_2_SET ns_noc_io_spio_soc_ip.csr 99226 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_2_SET ns_noc_io_spio_soc_ip.csr 99237 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_2_SET ns_noc_io_spio_soc_ip.csr 99248 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_2_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_2_SET ns_noc_io_spio_soc_ip.csr 99259 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 99269 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 99280 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_V_3_SET ns_noc_io_spio_soc_ip.csr 99291 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_S_3_SET ns_noc_io_spio_soc_ip.csr 99302 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_B_3_SET ns_noc_io_spio_soc_ip.csr 99313 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_3_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_F_3_SET ns_noc_io_spio_soc_ip.csr 99324 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRS_1_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 99334 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_p10_pcie_s_10_9_brus bridge_spio_p10_pcie_s_10_9_brus SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 99404 spio_p10_pcie_s register brus 0x2B1B0 R 0x00000000 Spio_noc_bridge_spio_p10_pcie_s_10_9_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_A_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_A_SET ns_noc_io_spio_soc_ip.csr 99360 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_B_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_B_SET ns_noc_io_spio_soc_ip.csr 99371 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_C_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_C_SET ns_noc_io_spio_soc_ip.csr 99382 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_D_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_V_D_SET ns_noc_io_spio_soc_ip.csr 99393 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_UNSD_31_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_UNSD_31_4_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_UNSD_31_4_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_UNSD_31_4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_UNSD_31_4_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_UNSD_31_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_UNSD_31_4_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRUS_UNSD_31_4_SET ns_noc_io_spio_soc_ip.csr 99403 UNSD_31_4 31 4 0x0000000 R register spio_noc.bridge_spio_p10_pcie_s_10_9_brperr0 bridge_spio_p10_pcie_s_10_9_brperr0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 99632 spio_p10_pcie_s register brperr0 0x2B1D0 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_pcie_s_10_9_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_D0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_D0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_D0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_D0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_D0_SET ns_noc_io_spio_soc_ip.csr 99442 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_DC0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_DC0_SET ns_noc_io_spio_soc_ip.csr 99453 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SB0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SB0_SET ns_noc_io_spio_soc_ip.csr 99464 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SBC0_SET ns_noc_io_spio_soc_ip.csr 99476 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_PK0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_PK0_SET ns_noc_io_spio_soc_ip.csr 99487 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 99498 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_D1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_D1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_D1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_D1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_D1_SET ns_noc_io_spio_soc_ip.csr 99509 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_DC1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_DC1_SET ns_noc_io_spio_soc_ip.csr 99520 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SB1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SB1_SET ns_noc_io_spio_soc_ip.csr 99531 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_SBC1_SET ns_noc_io_spio_soc_ip.csr 99543 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_PK1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_PK1_SET ns_noc_io_spio_soc_ip.csr 99554 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 99565 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 99576 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 99587 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 99598 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 99609 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 99620 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 99631 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p10_pcie_s_10_9_brperr1 bridge_spio_p10_pcie_s_10_9_brperr1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 99748 spio_p10_pcie_s register brperr1 0x2B1D8 R 0x0000000000000000 Spio_noc_bridge_spio_p10_pcie_s_10_9_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 99670 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 99681 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 99692 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 99703 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 99714 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 99725 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 99736 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERR1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 99747 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p10_pcie_s_10_9_brperrm0 bridge_spio_p10_pcie_s_10_9_brperrm0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 99969 spio_p10_pcie_s register brperrm0 0x2B1E0 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_pcie_s_10_9_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_D0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_D0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_D0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_D0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_D0_SET ns_noc_io_spio_soc_ip.csr 99775 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_DC0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_DC0_SET ns_noc_io_spio_soc_ip.csr 99787 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SB0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SB0_SET ns_noc_io_spio_soc_ip.csr 99798 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SBC0_SET ns_noc_io_spio_soc_ip.csr 99810 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_PK0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_PK0_SET ns_noc_io_spio_soc_ip.csr 99822 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 99833 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_D1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_D1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_D1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_D1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_D1_SET ns_noc_io_spio_soc_ip.csr 99844 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_DC1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_DC1_SET ns_noc_io_spio_soc_ip.csr 99856 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SB1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SB1_SET ns_noc_io_spio_soc_ip.csr 99867 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_SBC1_SET ns_noc_io_spio_soc_ip.csr 99879 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_PK1_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_PK1_SET ns_noc_io_spio_soc_ip.csr 99891 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 99902 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 99913 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 99924 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 99935 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 99946 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 99957 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 99968 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p10_pcie_s_10_9_brperrm1 bridge_spio_p10_pcie_s_10_9_brperrm1 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 100074 spio_p10_pcie_s register brperrm1 0x2B1E8 R 0x0000000000000000 Spio_noc_bridge_spio_p10_pcie_s_10_9_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 99996 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 100007 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 100018 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 100029 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 100040 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 100051 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 100062 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P10_PCIE_S_10_9_BRPERRM1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 100073 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_ahbs_ctl bridge_spio_p10_rvt_ahb0_s_11_8_ahbs_ctl SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_CTL_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_CTL_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_CTL_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_CTL_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 100115 spio_p10_rvt_ahb0_s register ahbs_ctl 0x2C200 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_ahbs_ctl Control Register. false false false false ZEROES SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_CTL_ZEROES_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_CTL_ZEROES_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_CTL_ZEROES_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_CTL_ZEROES_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_CTL_ZEROES_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_CTL_ZEROES_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_CTL_ZEROES_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_CTL_ZEROES_SET ns_noc_io_spio_soc_ip.csr 100090 ZEROES Zeroes 15 0 0x0000 R/W REG SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_CTL_REG_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_CTL_REG_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_CTL_REG_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_CTL_REG_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_CTL_REG_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_CTL_REG_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_CTL_REG_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_CTL_REG_SET ns_noc_io_spio_soc_ip.csr 100103 REG 1'b1: Issue error response on unaligned read address. 1'b0: Issue OK response even if unaligned adress was aligned and issued. 16 16 0x0 R/W UNSD_63_17 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_CTL_UNSD_63_17_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_CTL_UNSD_63_17_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_CTL_UNSD_63_17_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_CTL_UNSD_63_17_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_CTL_UNSD_63_17_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_CTL_UNSD_63_17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_CTL_UNSD_63_17_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_CTL_UNSD_63_17_SET ns_noc_io_spio_soc_ip.csr 100114 UNSD_63_17 63 17 0x000000000000 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_ahbs_sts bridge_spio_p10_rvt_ahb0_s_11_8_ahbs_sts SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 100166 spio_p10_rvt_ahb0_s register ahbs_sts 0x2C208 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_ahbs_sts Status Register. false false false false ZEROES SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_ZEROES_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_ZEROES_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_ZEROES_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_ZEROES_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_ZEROES_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_ZEROES_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_ZEROES_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_ZEROES_SET ns_noc_io_spio_soc_ip.csr 100131 ZEROES Zeroes 15 0 0x0000 R/W WE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_WE_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_WE_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_WE_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_WE_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_WE_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_WE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_WE_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_WE_SET ns_noc_io_spio_soc_ip.csr 100143 WE 1'b1: Unaligned write address (wrt asize)., or partial write strobes (wrt asize) was received. 16 16 0x0 R/W RE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_RE_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_RE_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_RE_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_RE_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_RE_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_RE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_RE_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_RE_SET ns_noc_io_spio_soc_ip.csr 100154 RE 1'b1: Unaligned read address was received. 17 17 0x0 R/W UNSD_63_18 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_UNSD_63_18_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_UNSD_63_18_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_UNSD_63_18_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_UNSD_63_18_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_UNSD_63_18_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_UNSD_63_18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_UNSD_63_18_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_STS_UNSD_63_18_SET ns_noc_io_spio_soc_ip.csr 100165 UNSD_63_18 63 18 0x000000000000 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_ahbs_im bridge_spio_p10_rvt_ahb0_s_11_8_ahbs_im SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 100218 spio_p10_rvt_ahb0_s register ahbs_im 0x2C210 R/W 0x0000000000030000 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_ahbs_im Interrupt Mask Register. false false false false ZEROES SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_ZEROES_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_ZEROES_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_ZEROES_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_ZEROES_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_ZEROES_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_ZEROES_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_ZEROES_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_ZEROES_SET ns_noc_io_spio_soc_ip.csr 100182 ZEROES Zeroes 15 0 0x0000 R/W WEM SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_WEM_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_WEM_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_WEM_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_WEM_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_WEM_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_WEM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_WEM_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_WEM_SET ns_noc_io_spio_soc_ip.csr 100194 WEM 1'b1: No interrupt raised on WE. 1'b0: Interrupt raised on WE. 16 16 0x1 R/W REM SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_REM_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_REM_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_REM_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_REM_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_REM_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_REM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_REM_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_REM_SET ns_noc_io_spio_soc_ip.csr 100206 REM 1'b1: No interrupt raised on RE. 1'b0: Interrupt raised on RE. 17 17 0x1 R/W UNSD_63_18 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_UNSD_63_18_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_UNSD_63_18_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_UNSD_63_18_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_UNSD_63_18_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_UNSD_63_18_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_UNSD_63_18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_UNSD_63_18_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AHBS_IM_UNSD_63_18_SET ns_noc_io_spio_soc_ip.csr 100217 UNSD_63_18 63 18 0x000000000000 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_cgc bridge_spio_p10_rvt_ahb0_s_11_8_as_cgc SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGC_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGC_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGC_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 100255 spio_p10_rvt_ahb0_s register as_cgc 0x2DC10 R/W 0x0000000000000064 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_as_cgc Programmable intervals used by coarse clock gating logic. This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGC_HYSTERESIS_COUNTER_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGC_HYSTERESIS_COUNTER_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGC_HYSTERESIS_COUNTER_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGC_HYSTERESIS_COUNTER_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGC_HYSTERESIS_COUNTER_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGC_HYSTERESIS_COUNTER_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGC_HYSTERESIS_COUNTER_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_spio_soc_ip.csr 100243 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGC_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGC_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGC_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGC_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGC_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGC_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGC_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGC_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 100254 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_cgo bridge_spio_p10_rvt_ahb0_s_11_8_as_cgo SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGO_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGO_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGO_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGO_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 100290 spio_p10_rvt_ahb0_s register as_cgo 0x2DC18 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_as_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the slave bridge. false false false false FPO SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGO_FPO_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGO_FPO_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGO_FPO_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGO_FPO_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGO_FPO_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGO_FPO_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGO_FPO_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGO_FPO_SET ns_noc_io_spio_soc_ip.csr 100278 FPO 1'b1: Clock gating override enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGO_UNSD_63_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGO_UNSD_63_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGO_UNSD_63_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGO_UNSD_63_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGO_UNSD_63_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGO_UNSD_63_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGO_UNSD_63_1_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CGO_UNSD_63_1_SET ns_noc_io_spio_soc_ip.csr 100289 UNSD_63_1 63 1 0x0000000000000000 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_sts bridge_spio_p10_rvt_ahb0_s_11_8_as_sts SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 100364 spio_p10_rvt_ahb0_s register as_sts 0x2DD00 R 0x000000000000000c Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_as_sts Slave bridge status bits. false false false false WOF SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_WOF_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_WOF_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_WOF_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_WOF_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_WOF_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_WOF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_WOF_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_WOF_SET ns_noc_io_spio_soc_ip.csr 100313 WOF 1'b1: Maximum number of supported write commands are outstanding to the attached slave device awaiting response, no more write commands will be issued to slave till responses are received. 1'b0: Slave device can expect more write commands from NoC 0 0 0x0 R ROF SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_ROF_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_ROF_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_ROF_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_ROF_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_ROF_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_ROF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_ROF_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_ROF_SET ns_noc_io_spio_soc_ip.csr 100329 ROF 1'b1: Maximum number of supported read commands are outstanding to the attached slave device awaiting response, no more read commands will be issued to slave till responses are received. 1'b0: Slave bridge can accept more read commands from the NoC 1 1 0x0 R WOE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_WOE_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_WOE_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_WOE_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_WOE_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_WOE_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_WOE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_WOE_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_WOE_SET ns_noc_io_spio_soc_ip.csr 100341 WOE 1'b1: There are no write commands outstanding to the attached slave device 2 2 0x1 R ROE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_ROE_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_ROE_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_ROE_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_ROE_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_ROE_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_ROE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_ROE_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_ROE_SET ns_noc_io_spio_soc_ip.csr 100353 ROE 1'b1: There are no read commands outstanding to the attached slave device 3 3 0x1 R UNSD_63_4 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_UNSD_63_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_UNSD_63_4_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_UNSD_63_4_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_UNSD_63_4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_UNSD_63_4_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_UNSD_63_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_UNSD_63_4_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_STS_UNSD_63_4_SET ns_noc_io_spio_soc_ip.csr 100363 UNSD_63_4 63 4 0x000000000000000 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_bridge_id bridge_spio_p10_rvt_ahb0_s_11_8_as_bridge_id SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_BRIDGE_ID_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_BRIDGE_ID_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_BRIDGE_ID_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_BRIDGE_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 100394 spio_p10_rvt_ahb0_s register as_bridge_id 0x2DD08 R 0x000000000000000b Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_as_bridge_id Unique identifier assigned to the slave bridge. false false false false ID SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_BRIDGE_ID_ID_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_BRIDGE_ID_ID_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_BRIDGE_ID_ID_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_BRIDGE_ID_ID_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_BRIDGE_ID_ID_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_BRIDGE_ID_ID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_BRIDGE_ID_ID_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_BRIDGE_ID_ID_SET ns_noc_io_spio_soc_ip.csr 100383 ID Unique bridge ID 15 0 0x000b R UNSD_63_16 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_BRIDGE_ID_UNSD_63_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_BRIDGE_ID_UNSD_63_16_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_BRIDGE_ID_UNSD_63_16_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_BRIDGE_ID_UNSD_63_16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_BRIDGE_ID_UNSD_63_16_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_BRIDGE_ID_UNSD_63_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_BRIDGE_ID_UNSD_63_16_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_spio_soc_ip.csr 100393 UNSD_63_16 63 16 0x000000000000 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_err bridge_spio_p10_rvt_ahb0_s_11_8_as_err SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 100747 spio_p10_rvt_ahb0_s register as_err 0x2DE00 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_as_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E0_SET ns_noc_io_spio_soc_ip.csr 100415 E0 1'b1: Read decode error response: Decode error response received from slave device for read command 0 0 0x0 R/W E1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E1_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E1_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E1_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E1_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E1_SET ns_noc_io_spio_soc_ip.csr 100427 E1 1'b1: Read slave error response: Slave error response received from slave device for read command 1 1 0x0 R/W E2 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E2_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E2_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E2_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E2_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E2_SET ns_noc_io_spio_soc_ip.csr 100440 E2 1'b1: [FATAL] Unknown read response destination: RID from read response produces a destination which is not present in the routing table 2 2 0x0 R/W E3 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E3_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E3_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E3_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E3_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E3_SET ns_noc_io_spio_soc_ip.csr 100454 E3 1'b1: [FATAL] Interleaved read response: Interleaved read response. This can occur if interleaved read response is received from a slave device for which a de-interleaver was not specified 3 3 0x0 R/W E4 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E4_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E4_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E4_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E4_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E4_SET ns_noc_io_spio_soc_ip.csr 100466 E4 1'b1: Read command modified: A read command which was marked as non-modifiable was modified by the slave bridge 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_UNSD_15_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_UNSD_15_5_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_UNSD_15_5_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_UNSD_15_5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_UNSD_15_5_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_UNSD_15_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_UNSD_15_5_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 100477 UNSD_15_5 15 5 0x000 R E16 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E16_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E16_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E16_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E16_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E16_SET ns_noc_io_spio_soc_ip.csr 100489 E16 1'b1: Write decode error response: Decode error response received from slave device for write command 16 16 0x0 R/W E17 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E17_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E17_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E17_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E17_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E17_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E17_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E17_SET ns_noc_io_spio_soc_ip.csr 100501 E17 1'b1: Write slave error response: Slave error response received from slave device for write command 17 17 0x0 R/W E18 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E18_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E18_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E18_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E18_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E18_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E18_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E18_SET ns_noc_io_spio_soc_ip.csr 100514 E18 1'b1: [FATAL] Unknown write response destination: BID from write response produces a destination which is not present in the routing table 18 18 0x0 R/W E19 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E19_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E19_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E19_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E19_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E19_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E19_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E19_SET ns_noc_io_spio_soc_ip.csr 100526 E19 1'b1: Write command modified: A write command which was marked as non-modifiable was modified by the slave bridge 19 19 0x0 R/W UNSD_31_20 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_UNSD_31_20_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_UNSD_31_20_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_UNSD_31_20_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_UNSD_31_20_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_UNSD_31_20_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_UNSD_31_20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_UNSD_31_20_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_UNSD_31_20_SET ns_noc_io_spio_soc_ip.csr 100537 UNSD_31_20 31 20 0x000 R E32 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E32_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E32_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E32_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E32_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E32_SET ns_noc_io_spio_soc_ip.csr 100549 E32 1'b1: [FATAL] Traffic sent to a noc layer which is power gated 32 32 0x0 R/W E33 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E33_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E33_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E33_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E33_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E33_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E33_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E33_SET ns_noc_io_spio_soc_ip.csr 100560 E33 1'b1: [FATAL] Parity error in config/status registers 33 33 0x0 R/W E34 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E34_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E34_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E34_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E34_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E34_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E34_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E34_SET ns_noc_io_spio_soc_ip.csr 100571 E34 1'b1: [FATAL] RDATA Parity error 34 34 0x0 R/W E35 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E35_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E35_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E35_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E35_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E35_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E35_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E35_SET ns_noc_io_spio_soc_ip.csr 100582 E35 1'b1: [FATAL] RRESP Parity error 35 35 0x0 R/W E36 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E36_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E36_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E36_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E36_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E36_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E36_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E36_SET ns_noc_io_spio_soc_ip.csr 100593 E36 1'b1: [FATAL] BRESP Parity error 36 36 0x0 R/W E37 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E37_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E37_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E37_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E37_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E37_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E37_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E37_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E37_SET ns_noc_io_spio_soc_ip.csr 100604 E37 1'b1: [FATAL] AC Parity error 37 37 0x0 R/W E38 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E38_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E38_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E38_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E38_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E38_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E38_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E38_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E38_SET ns_noc_io_spio_soc_ip.csr 100615 E38 1'b1: [FATAL] ACADDR Parity error 38 38 0x0 R/W E39 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E39_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E39_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E39_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E39_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E39_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E39_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E39_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E39_SET ns_noc_io_spio_soc_ip.csr 100627 E39 1'b1: [FATAL] R Ch Cmdtbl Parity Err 39 39 0x0 R E40 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E40_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E40_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E40_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E40_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E40_SET ns_noc_io_spio_soc_ip.csr 100639 E40 1'b1: [FATAL] B Ch Cmdtbl Parity Err 40 40 0x0 R E41 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E41_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E41_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E41_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E41_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E41_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E41_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E41_SET ns_noc_io_spio_soc_ip.csr 100651 E41 1'b1: [FATAL] Rx Fifo Parity Err 41 41 0x0 R E42 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E42_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E42_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E42_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E42_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E42_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E42_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E42_SET ns_noc_io_spio_soc_ip.csr 100663 E42 1'b1: [FATAL] CRCD Ch Reorder Buffer Parity Err 42 42 0x0 R E43 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E43_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E43_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E43_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E43_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E43_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E43_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E43_SET ns_noc_io_spio_soc_ip.csr 100675 E43 1'b1: [FATAL] Ack Ch Wack Reorder Buffer Parity Err 43 43 0x0 R E44 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E44_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E44_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E44_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E44_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E44_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E44_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E44_SET ns_noc_io_spio_soc_ip.csr 100687 E44 1'b1: [FATAL] Ack Ch Rack Reorder Buffer Parity Err 44 44 0x0 R E45 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E45_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E45_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E45_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E45_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E45_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E45_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E45_SET ns_noc_io_spio_soc_ip.csr 100699 E45 1'b1: [FATAL] B Ch Drain Fifo Parity Err 45 45 0x0 R E46 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E46_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E46_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E46_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E46_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E46_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E46_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E46_SET ns_noc_io_spio_soc_ip.csr 100711 E46 1'b1: [FATAL] R Ch Flush Fifo Parity Err 46 46 0x0 R E47 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E47_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E47_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E47_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E47_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E47_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E47_SET ns_noc_io_spio_soc_ip.csr 100723 E47 1'b1: [FATAL] R Ch Deinterleaver Cmdtbl Parity Err 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E48_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E48_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E48_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E48_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_E48_SET ns_noc_io_spio_soc_ip.csr 100735 E48 1'b1: [FATAL] R Ch Deinterleaver Data Buffer Parity Err 48 48 0x0 R UNSD_63_49 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_UNSD_63_49_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_UNSD_63_49_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_UNSD_63_49_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_UNSD_63_49_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_UNSD_63_49_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_UNSD_63_49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_UNSD_63_49_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_ERR_UNSD_63_49_SET ns_noc_io_spio_soc_ip.csr 100746 UNSD_63_49 63 49 0x0000 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_intm bridge_spio_p10_rvt_ahb0_s_11_8_as_intm SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 101087 spio_p10_rvt_ahb0_s register as_intm 0x2DE40 R/W 0x0000007d000b0013 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_as_intm Interrupt mask register.Individual bit positions match the error bit positions in AS_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M0_SET ns_noc_io_spio_soc_ip.csr 100768 M0 Mask interrupts for read channel 0 0 0x1 R/W M1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M1_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M1_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M1_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M1_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M1_SET ns_noc_io_spio_soc_ip.csr 100779 M1 Mask interrupts for read channel 1 1 0x1 R/W M2 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M2_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M2_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M2_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M2_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M2_SET ns_noc_io_spio_soc_ip.csr 100790 M2 Mask interrupts for read channel 2 2 0x0 R/W M3 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M3_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M3_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M3_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M3_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M3_SET ns_noc_io_spio_soc_ip.csr 100801 M3 Mask interrupts for read channel 3 3 0x0 R/W M4 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M4_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M4_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M4_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M4_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M4_SET ns_noc_io_spio_soc_ip.csr 100812 M4 Mask interrupts for read channel 4 4 0x1 R/W UNSD_15_5 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_UNSD_15_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_UNSD_15_5_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_UNSD_15_5_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_UNSD_15_5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_UNSD_15_5_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_UNSD_15_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_UNSD_15_5_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 100823 UNSD_15_5 15 5 0x000 R M16 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M16_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M16_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M16_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M16_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M16_SET ns_noc_io_spio_soc_ip.csr 100834 M16 Mask interrupts for write channel 16 16 0x1 R/W M17 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M17_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M17_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M17_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M17_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M17_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M17_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M17_SET ns_noc_io_spio_soc_ip.csr 100845 M17 Mask interrupts for write channel 17 17 0x1 R/W M18 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M18_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M18_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M18_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M18_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M18_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M18_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M18_SET ns_noc_io_spio_soc_ip.csr 100856 M18 Mask interrupts for write channel 18 18 0x0 R/W M19 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M19_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M19_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M19_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M19_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M19_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M19_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M19_SET ns_noc_io_spio_soc_ip.csr 100867 M19 Mask interrupts for write channel 19 19 0x1 R/W UNSD_31_20 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_UNSD_31_20_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_UNSD_31_20_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_UNSD_31_20_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_UNSD_31_20_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_UNSD_31_20_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_UNSD_31_20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_UNSD_31_20_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_UNSD_31_20_SET ns_noc_io_spio_soc_ip.csr 100878 UNSD_31_20 31 20 0x000 R M32 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M32_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M32_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M32_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M32_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M32_SET ns_noc_io_spio_soc_ip.csr 100889 M32 Mask interrupt on traffic to PG layer 32 32 0x1 R/W M33 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M33_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M33_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M33_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M33_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M33_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M33_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M33_SET ns_noc_io_spio_soc_ip.csr 100900 M33 Mask interrupt on csr parity errors 33 33 0x0 R/W M34 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M34_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M34_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M34_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M34_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M34_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M34_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M34_SET ns_noc_io_spio_soc_ip.csr 100911 M34 RDATA parity interrupt Mask 34 34 0x1 R/W M35 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M35_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M35_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M35_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M35_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M35_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M35_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M35_SET ns_noc_io_spio_soc_ip.csr 100922 M35 RRESP parity interrupt Mask 35 35 0x1 R/W M36 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M36_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M36_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M36_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M36_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M36_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M36_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M36_SET ns_noc_io_spio_soc_ip.csr 100933 M36 BRESP parity interrupt Mask 36 36 0x1 R/W M37 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M37_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M37_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M37_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M37_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M37_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M37_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M37_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M37_SET ns_noc_io_spio_soc_ip.csr 100944 M37 AC parity interrupt Mask 37 37 0x1 R/W M38 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M38_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M38_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M38_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M38_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M38_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M38_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M38_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_M38_SET ns_noc_io_spio_soc_ip.csr 100955 M38 ACADDR parity interrupt Mask 38 38 0x1 R/W E39 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E39_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E39_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E39_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E39_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E39_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E39_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E39_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E39_SET ns_noc_io_spio_soc_ip.csr 100967 E39 1'b1: R Ch Cmdtbl Parity Err Intr Mask 39 39 0x0 R E40 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E40_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E40_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E40_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E40_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E40_SET ns_noc_io_spio_soc_ip.csr 100979 E40 1'b1: B Ch Cmdtbl Parity Err Intr Mask 40 40 0x0 R E41 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E41_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E41_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E41_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E41_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E41_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E41_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E41_SET ns_noc_io_spio_soc_ip.csr 100991 E41 1'b1: Rx Fifo Parity Err Intr Mask 41 41 0x0 R E42 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E42_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E42_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E42_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E42_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E42_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E42_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E42_SET ns_noc_io_spio_soc_ip.csr 101003 E42 1'b1: CRCD Ch Reorder Buffer Parity Err Intr Mask 42 42 0x0 R E43 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E43_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E43_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E43_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E43_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E43_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E43_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E43_SET ns_noc_io_spio_soc_ip.csr 101015 E43 1'b1: Ack Ch Wack Reorder Buffer Parity Err IntrMask 43 43 0x0 R E44 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E44_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E44_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E44_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E44_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E44_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E44_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E44_SET ns_noc_io_spio_soc_ip.csr 101027 E44 1'b1: Ack Ch Rack Reorder Buffer Parity Err Intr Mask 44 44 0x0 R E45 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E45_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E45_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E45_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E45_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E45_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E45_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E45_SET ns_noc_io_spio_soc_ip.csr 101039 E45 1'b1: B Ch Drain Fifo Parity Err Intr Mask 45 45 0x0 R E46 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E46_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E46_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E46_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E46_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E46_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E46_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E46_SET ns_noc_io_spio_soc_ip.csr 101051 E46 1'b1: R Ch Flush Fifo Parity Err Intr Mask 46 46 0x0 R E47 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E47_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E47_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E47_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E47_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E47_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E47_SET ns_noc_io_spio_soc_ip.csr 101063 E47 1'b1: R Ch Deinterleaver Cmdtbl Parity Err Intr Mask 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E48_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E48_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E48_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E48_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_E48_SET ns_noc_io_spio_soc_ip.csr 101075 E48 1'b1: R Ch Deinterleaver Data Buffer Parity Err Intr Mask 48 48 0x0 R UNSD_63_49 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_UNSD_63_49_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_UNSD_63_49_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_UNSD_63_49_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_UNSD_63_49_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_UNSD_63_49_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_UNSD_63_49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_UNSD_63_49_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_INTM_UNSD_63_49_SET ns_noc_io_spio_soc_ip.csr 101086 UNSD_63_49 63 49 0x0000 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_ccmd bridge_spio_p10_rvt_ahb0_s_11_8_as_ccmd SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 101162 spio_p10_rvt_ahb0_s register as_ccmd 0x2DF00 R/W 0x0000000003000000 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_as_ccmd Not applicable for current release. false false false false UNSD_23_0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_UNSD_23_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_UNSD_23_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_UNSD_23_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_UNSD_23_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_UNSD_23_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_UNSD_23_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_UNSD_23_0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_UNSD_23_0_SET ns_noc_io_spio_soc_ip.csr 101105 UNSD_23_0 23 0 0x000000 R rdy SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_RDY_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_RDY_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_RDY_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_RDY_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_RDY_SET ns_noc_io_spio_soc_ip.csr 101116 rdy 1'b1: Ready 24 24 0x1 R/W val SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_VAL_SET ns_noc_io_spio_soc_ip.csr 101127 val 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_UNSD_27_26_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_UNSD_27_26_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_UNSD_27_26_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_UNSD_27_26_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_UNSD_27_26_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_UNSD_27_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_UNSD_27_26_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_UNSD_27_26_SET ns_noc_io_spio_soc_ip.csr 101138 UNSD_27_26 27 26 0x0 R intfid SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_INTFID_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_INTFID_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_INTFID_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_INTFID_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_INTFID_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_INTFID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_INTFID_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_INTFID_SET ns_noc_io_spio_soc_ip.csr 101150 intfid 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_63_31 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_UNSD_63_31_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_UNSD_63_31_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_UNSD_63_31_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_UNSD_63_31_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_UNSD_63_31_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_UNSD_63_31_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_UNSD_63_31_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMD_UNSD_63_31_SET ns_noc_io_spio_soc_ip.csr 101161 UNSD_63_31 63 31 0x000000000 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_ccmdmsk bridge_spio_p10_rvt_ahb0_s_11_8_as_ccmdmsk SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 101214 spio_p10_rvt_ahb0_s register as_ccmdmsk 0x2DF08 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_as_ccmdmsk Not applicable for current release. false false false false UNSD_23_0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_UNSD_23_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_UNSD_23_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_UNSD_23_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_UNSD_23_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_UNSD_23_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_UNSD_23_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_UNSD_23_0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_UNSD_23_0_SET ns_noc_io_spio_soc_ip.csr 101180 UNSD_23_0 23 0 0x000000 R rdy SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_RDY_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_RDY_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_RDY_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_RDY_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_RDY_SET ns_noc_io_spio_soc_ip.csr 101191 rdy 1'b1: Ready 24 24 0x0 R/W val SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_VAL_SET ns_noc_io_spio_soc_ip.csr 101202 val 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_UNSD_63_26_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_UNSD_63_26_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_UNSD_63_26_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_UNSD_63_26_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_UNSD_63_26_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_UNSD_63_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_UNSD_63_26_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CCMDMSK_UNSD_63_26_SET ns_noc_io_spio_soc_ip.csr 101213 UNSD_63_26 63 26 0x0000000000 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_cntr bridge_spio_p10_rvt_ahb0_s_11_8_as_cntr SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CNTR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CNTR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CNTR_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CNTR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 101244 spio_p10_rvt_ahb0_s register as_cntr 0x2DF10 R 0x0000000000000000 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_as_cntr Not applicable for current release. false false false false CNTR SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CNTR_CNTR_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CNTR_CNTR_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CNTR_CNTR_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CNTR_CNTR_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CNTR_CNTR_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CNTR_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CNTR_CNTR_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CNTR_CNTR_SET ns_noc_io_spio_soc_ip.csr 101233 CNTR Counter 31 0 0x00000000 R UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CNTR_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CNTR_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CNTR_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CNTR_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CNTR_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CNTR_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CNTR_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_CNTR_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 101243 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_arovrd bridge_spio_p10_rvt_ahb0_s_11_8_as_arovrd SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 101357 spio_p10_rvt_ahb0_s register as_arovrd 0x2DF18 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_as_arovrd AR Overrides. false false false false arcache_val SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 101262 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 101275 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 101286 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 101297 UNSD_11_11 11 11 0x0 R arprot_enb SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 101310 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 101321 UNSD_15_15 15 15 0x0 R arqos_val SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 101332 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_ARQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 101345 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AROVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 101356 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_as_awovrd bridge_spio_p10_rvt_ahb0_s_11_8_as_awovrd SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 101470 spio_p10_rvt_ahb0_s register as_awovrd 0x2DF20 R/W 0x0000000000000020 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_as_awovrd AW Overrides. false false false false awcache_val SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 101375 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 101388 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x2 R/W awprot_val SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 101399 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 101410 UNSD_11_11 11 11 0x0 R awprot_enb SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 101423 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 101434 UNSD_15_15 15 15 0x0 R awqos_val SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 101445 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_AWQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 101458 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_AS_AWOVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 101469 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_p_0 bridge_spio_p10_rvt_ahb0_s_11_8_p_0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 101535 spio_p10_rvt_ahb0_s register p_0 0x2F000 R/W 0x00000003 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_0_SET ns_noc_io_spio_soc_ip.csr 101498 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_1_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_1_SET ns_noc_io_spio_soc_ip.csr 101510 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_2_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_2_SET ns_noc_io_spio_soc_ip.csr 101522 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_3_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_0_WT_QOS_3_SET ns_noc_io_spio_soc_ip.csr 101534 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_p_1 bridge_spio_p10_rvt_ahb0_s_11_8_p_1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 101601 spio_p10_rvt_ahb0_s register p_1 0x2F008 R 0x00000000 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_4_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_4_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_4_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_4_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_4_SET ns_noc_io_spio_soc_ip.csr 101564 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_5_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_5_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_5_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_5_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_5_SET ns_noc_io_spio_soc_ip.csr 101576 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_6_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_6_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_6_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_6_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_6_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_6_SET ns_noc_io_spio_soc_ip.csr 101588 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_7_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_7_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_7_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_7_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_7_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_1_WT_QOS_7_SET ns_noc_io_spio_soc_ip.csr 101600 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_p_2 bridge_spio_p10_rvt_ahb0_s_11_8_p_2 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 101667 spio_p10_rvt_ahb0_s register p_2 0x2F010 R 0x00000000 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_8_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_8_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_8_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_8_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_8_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_8_SET ns_noc_io_spio_soc_ip.csr 101630 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_9_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_9_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_9_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_9_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_9_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_9_SET ns_noc_io_spio_soc_ip.csr 101642 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_10_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_10_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_10_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_10_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_10_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_10_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_10_SET ns_noc_io_spio_soc_ip.csr 101654 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_11_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_11_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_11_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_11_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_11_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_11_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_2_WT_QOS_11_SET ns_noc_io_spio_soc_ip.csr 101666 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_p_3 bridge_spio_p10_rvt_ahb0_s_11_8_p_3 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 101733 spio_p10_rvt_ahb0_s register p_3 0x2F018 R 0x00000000 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_12_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_12_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_12_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_12_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_12_SET ns_noc_io_spio_soc_ip.csr 101696 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_13_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_13_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_13_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_13_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_13_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_13_SET ns_noc_io_spio_soc_ip.csr 101708 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_14_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_14_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_14_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_14_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_14_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_14_SET ns_noc_io_spio_soc_ip.csr 101720 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_15_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_15_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_15_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_15_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_15_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_15_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_P_3_WT_QOS_15_SET ns_noc_io_spio_soc_ip.csr 101732 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_txe bridge_spio_p10_rvt_ahb0_s_11_8_txe SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 101879 spio_p10_rvt_ahb0_s register txe 0x2F040 R/W 0x00000000 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_TRANS_WITHOUT_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_TRANS_WITHOUT_SOP_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_TRANS_WITHOUT_SOP_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_TRANS_WITHOUT_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_TRANS_WITHOUT_SOP_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_TRANS_WITHOUT_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_TRANS_WITHOUT_SOP_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_spio_soc_ip.csr 101760 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_SOP_AFTER_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_SOP_AFTER_SOP_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_SOP_AFTER_SOP_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_SOP_AFTER_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_SOP_AFTER_SOP_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_SOP_AFTER_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_SOP_AFTER_SOP_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_SOP_AFTER_SOP_SET ns_noc_io_spio_soc_ip.csr 101772 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 101787 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 101800 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_A_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_spio_soc_ip.csr 101814 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_B_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_spio_soc_ip.csr 101828 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_C_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_spio_soc_ip.csr 101842 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_D_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_spio_soc_ip.csr 101856 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 101867 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXE_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 101878 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_txem bridge_spio_p10_rvt_ahb0_s_11_8_txem SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 101958 spio_p10_rvt_ahb0_s register txem 0x2F048 R/W 0x00000008 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_UNSD_1_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_UNSD_1_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_UNSD_1_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_UNSD_1_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_UNSD_1_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_UNSD_1_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_UNSD_1_0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_UNSD_1_0_SET ns_noc_io_spio_soc_ip.csr 101902 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 101913 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 101924 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_UNSD_7_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_UNSD_7_4_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_UNSD_7_4_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_UNSD_7_4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_UNSD_7_4_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_UNSD_7_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_UNSD_7_4_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_UNSD_7_4_SET ns_noc_io_spio_soc_ip.csr 101935 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 101946 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_TXEM_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 101957 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btus_0 bridge_spio_p10_rvt_ahb0_s_11_8_btus_0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 102326 spio_p10_rvt_ahb0_s register btus_0 0x2F058 R 0x00000000 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_A_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_A_SET ns_noc_io_spio_soc_ip.csr 101984 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_B_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_B_SET ns_noc_io_spio_soc_ip.csr 101995 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_C_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_C_SET ns_noc_io_spio_soc_ip.csr 102006 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_D_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L0_D_SET ns_noc_io_spio_soc_ip.csr 102017 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_A_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_A_SET ns_noc_io_spio_soc_ip.csr 102028 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_B_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_B_SET ns_noc_io_spio_soc_ip.csr 102039 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_C_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_C_SET ns_noc_io_spio_soc_ip.csr 102050 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_D_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L1_D_SET ns_noc_io_spio_soc_ip.csr 102061 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_A_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_A_SET ns_noc_io_spio_soc_ip.csr 102072 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_B_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_B_SET ns_noc_io_spio_soc_ip.csr 102083 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_C_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_C_SET ns_noc_io_spio_soc_ip.csr 102094 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_D_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L2_D_SET ns_noc_io_spio_soc_ip.csr 102105 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_A_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_A_SET ns_noc_io_spio_soc_ip.csr 102116 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_B_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_B_SET ns_noc_io_spio_soc_ip.csr 102127 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_C_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_C_SET ns_noc_io_spio_soc_ip.csr 102138 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_D_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L3_D_SET ns_noc_io_spio_soc_ip.csr 102149 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_A_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_A_SET ns_noc_io_spio_soc_ip.csr 102160 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_B_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_B_SET ns_noc_io_spio_soc_ip.csr 102171 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_C_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_C_SET ns_noc_io_spio_soc_ip.csr 102182 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_D_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L4_D_SET ns_noc_io_spio_soc_ip.csr 102193 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_A_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_A_SET ns_noc_io_spio_soc_ip.csr 102204 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_B_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_B_SET ns_noc_io_spio_soc_ip.csr 102215 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_C_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_C_SET ns_noc_io_spio_soc_ip.csr 102226 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_D_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L5_D_SET ns_noc_io_spio_soc_ip.csr 102237 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_A_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_A_SET ns_noc_io_spio_soc_ip.csr 102248 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_B_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_B_SET ns_noc_io_spio_soc_ip.csr 102259 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_C_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_C_SET ns_noc_io_spio_soc_ip.csr 102270 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_D_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L6_D_SET ns_noc_io_spio_soc_ip.csr 102281 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_A_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_A_SET ns_noc_io_spio_soc_ip.csr 102292 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_B_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_B_SET ns_noc_io_spio_soc_ip.csr 102303 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_C_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_C_SET ns_noc_io_spio_soc_ip.csr 102314 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_D_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_0_L7_D_SET ns_noc_io_spio_soc_ip.csr 102325 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btus_1 bridge_spio_p10_rvt_ahb0_s_11_8_btus_1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 102694 spio_p10_rvt_ahb0_s register btus_1 0x2F060 R 0x00000000 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_A_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_A_SET ns_noc_io_spio_soc_ip.csr 102352 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_B_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_B_SET ns_noc_io_spio_soc_ip.csr 102363 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_C_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_C_SET ns_noc_io_spio_soc_ip.csr 102374 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_D_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L8_D_SET ns_noc_io_spio_soc_ip.csr 102385 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_A_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_A_SET ns_noc_io_spio_soc_ip.csr 102396 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_B_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_B_SET ns_noc_io_spio_soc_ip.csr 102407 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_C_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_C_SET ns_noc_io_spio_soc_ip.csr 102418 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_D_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L9_D_SET ns_noc_io_spio_soc_ip.csr 102429 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_A_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_A_SET ns_noc_io_spio_soc_ip.csr 102440 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_B_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_B_SET ns_noc_io_spio_soc_ip.csr 102451 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_C_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_C_SET ns_noc_io_spio_soc_ip.csr 102462 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_D_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L10_D_SET ns_noc_io_spio_soc_ip.csr 102473 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_A_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_A_SET ns_noc_io_spio_soc_ip.csr 102484 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_B_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_B_SET ns_noc_io_spio_soc_ip.csr 102495 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_C_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_C_SET ns_noc_io_spio_soc_ip.csr 102506 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_D_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L11_D_SET ns_noc_io_spio_soc_ip.csr 102517 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_A_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_A_SET ns_noc_io_spio_soc_ip.csr 102528 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_B_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_B_SET ns_noc_io_spio_soc_ip.csr 102539 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_C_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_C_SET ns_noc_io_spio_soc_ip.csr 102550 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_D_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L12_D_SET ns_noc_io_spio_soc_ip.csr 102561 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_A_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_A_SET ns_noc_io_spio_soc_ip.csr 102572 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_B_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_B_SET ns_noc_io_spio_soc_ip.csr 102583 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_C_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_C_SET ns_noc_io_spio_soc_ip.csr 102594 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_D_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L13_D_SET ns_noc_io_spio_soc_ip.csr 102605 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_A_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_A_SET ns_noc_io_spio_soc_ip.csr 102616 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_B_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_B_SET ns_noc_io_spio_soc_ip.csr 102627 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_C_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_C_SET ns_noc_io_spio_soc_ip.csr 102638 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_D_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L14_D_SET ns_noc_io_spio_soc_ip.csr 102649 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_A_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_A_SET ns_noc_io_spio_soc_ip.csr 102660 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_B_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_B_SET ns_noc_io_spio_soc_ip.csr 102671 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_C_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_C_SET ns_noc_io_spio_soc_ip.csr 102682 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_D_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTUS_1_L15_D_SET ns_noc_io_spio_soc_ip.csr 102693 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btrl_0 bridge_spio_p10_rvt_ahb0_s_11_8_btrl_0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 102770 spio_p10_rvt_ahb0_s register btrl_0 0x2F080 R 0x00000000 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_WT_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_WT_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_WT_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_WT_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_WT_SET ns_noc_io_spio_soc_ip.csr 102718 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 102729 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_CNT_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_CNT_SET ns_noc_io_spio_soc_ip.csr 102744 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_EN_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_EN_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_EN_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_EN_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_EN_SET ns_noc_io_spio_soc_ip.csr 102758 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_0_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 102769 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btrl_1 bridge_spio_p10_rvt_ahb0_s_11_8_btrl_1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 102846 spio_p10_rvt_ahb0_s register btrl_1 0x2F088 R 0x00000000 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_WT_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_WT_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_WT_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_WT_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_WT_SET ns_noc_io_spio_soc_ip.csr 102794 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 102805 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_CNT_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_CNT_SET ns_noc_io_spio_soc_ip.csr 102820 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_EN_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_EN_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_EN_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_EN_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_EN_SET ns_noc_io_spio_soc_ip.csr 102834 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_1_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 102845 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btrl_2 bridge_spio_p10_rvt_ahb0_s_11_8_btrl_2 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 102922 spio_p10_rvt_ahb0_s register btrl_2 0x2F090 R 0x00000000 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_WT_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_WT_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_WT_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_WT_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_WT_SET ns_noc_io_spio_soc_ip.csr 102870 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 102881 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_CNT_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_CNT_SET ns_noc_io_spio_soc_ip.csr 102896 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_EN_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_EN_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_EN_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_EN_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_EN_SET ns_noc_io_spio_soc_ip.csr 102910 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_2_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 102921 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btrl_3 bridge_spio_p10_rvt_ahb0_s_11_8_btrl_3 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 102998 spio_p10_rvt_ahb0_s register btrl_3 0x2F098 R 0x00000000 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_WT_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_WT_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_WT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_WT_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_WT_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_WT_SET ns_noc_io_spio_soc_ip.csr 102946 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 102957 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_CNT_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_CNT_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_CNT_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_CNT_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_CNT_SET ns_noc_io_spio_soc_ip.csr 102972 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_EN_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_EN_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_EN_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_EN_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_EN_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_EN_SET ns_noc_io_spio_soc_ip.csr 102986 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTRL_3_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 102997 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btperr bridge_spio_p10_rvt_ahb0_s_11_8_btperr SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 103200 spio_p10_rvt_ahb0_s register btperr 0x2F0A8 R/W 0x00000000 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L0_SET ns_noc_io_spio_soc_ip.csr 103023 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L1_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L1_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L1_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L1_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L1_SET ns_noc_io_spio_soc_ip.csr 103034 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L2_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L2_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L2_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L2_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L2_SET ns_noc_io_spio_soc_ip.csr 103045 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L3_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L3_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L3_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L3_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L3_SET ns_noc_io_spio_soc_ip.csr 103056 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L4_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L4_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L4_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L4_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L4_SET ns_noc_io_spio_soc_ip.csr 103067 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L5_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L5_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L5_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L5_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L5_SET ns_noc_io_spio_soc_ip.csr 103078 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L6_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L6_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L6_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L6_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L6_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L6_SET ns_noc_io_spio_soc_ip.csr 103089 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L7_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L7_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L7_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L7_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L7_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L7_SET ns_noc_io_spio_soc_ip.csr 103100 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L8_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L8_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L8_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L8_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L8_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L8_SET ns_noc_io_spio_soc_ip.csr 103111 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L9_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L9_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L9_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L9_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L9_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L9_SET ns_noc_io_spio_soc_ip.csr 103122 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L10_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L10_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L10_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L10_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L10_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L10_SET ns_noc_io_spio_soc_ip.csr 103133 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L11_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L11_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L11_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L11_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L11_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L11_SET ns_noc_io_spio_soc_ip.csr 103144 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L12_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L12_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L12_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L12_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L12_SET ns_noc_io_spio_soc_ip.csr 103155 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L13_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L13_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L13_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L13_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L13_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L13_SET ns_noc_io_spio_soc_ip.csr 103166 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L14_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L14_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L14_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L14_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L14_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L14_SET ns_noc_io_spio_soc_ip.csr 103177 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L15_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L15_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L15_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L15_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L15_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_L15_SET ns_noc_io_spio_soc_ip.csr 103188 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_UNSD_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERR_UNSD_SET ns_noc_io_spio_soc_ip.csr 103199 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_btperrm bridge_spio_p10_rvt_ahb0_s_11_8_btperrm SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 103400 spio_p10_rvt_ahb0_s register btperrm 0x2F0B0 R/W 0x00000000 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L0_SET ns_noc_io_spio_soc_ip.csr 103223 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L1_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L1_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L1_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L1_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L1_SET ns_noc_io_spio_soc_ip.csr 103234 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L2_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L2_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L2_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L2_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L2_SET ns_noc_io_spio_soc_ip.csr 103245 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L3_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L3_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L3_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L3_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L3_SET ns_noc_io_spio_soc_ip.csr 103256 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L4_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L4_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L4_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L4_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L4_SET ns_noc_io_spio_soc_ip.csr 103267 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L5_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L5_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L5_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L5_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L5_SET ns_noc_io_spio_soc_ip.csr 103278 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L6_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L6_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L6_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L6_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L6_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L6_SET ns_noc_io_spio_soc_ip.csr 103289 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L7_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L7_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L7_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L7_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L7_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L7_SET ns_noc_io_spio_soc_ip.csr 103300 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L8_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L8_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L8_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L8_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L8_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L8_SET ns_noc_io_spio_soc_ip.csr 103311 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L9_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L9_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L9_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L9_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L9_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L9_SET ns_noc_io_spio_soc_ip.csr 103322 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L10_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L10_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L10_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L10_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L10_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L10_SET ns_noc_io_spio_soc_ip.csr 103333 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L11_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L11_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L11_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L11_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L11_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L11_SET ns_noc_io_spio_soc_ip.csr 103344 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L12_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L12_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L12_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L12_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L12_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L12_SET ns_noc_io_spio_soc_ip.csr 103355 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L13_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L13_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L13_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L13_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L13_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L13_SET ns_noc_io_spio_soc_ip.csr 103366 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L14_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L14_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L14_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L14_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L14_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L14_SET ns_noc_io_spio_soc_ip.csr 103377 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L15_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L15_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L15_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L15_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L15_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_L15_SET ns_noc_io_spio_soc_ip.csr 103388 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_UNSD_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BTPERRM_UNSD_SET ns_noc_io_spio_soc_ip.csr 103399 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_rxe bridge_spio_p10_rvt_ahb0_s_11_8_rxe SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 103508 spio_p10_rvt_ahb0_s register rxe 0x2F120 R/W 0x00000000 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_A_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_A_SET ns_noc_io_spio_soc_ip.csr 103428 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_B_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_B_SET ns_noc_io_spio_soc_ip.csr 103439 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_C_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_C_SET ns_noc_io_spio_soc_ip.csr 103450 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_D_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_CRC_OFLW_D_SET ns_noc_io_spio_soc_ip.csr 103461 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_EVC_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_EVC_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_EVC_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_EVC_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_EVC_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_EVC_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_EVC_OFLW_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_EVC_OFLW_SET ns_noc_io_spio_soc_ip.csr 103473 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 103484 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_EVC1_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_EVC1_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_EVC1_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_EVC1_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_EVC1_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_EVC1_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_EVC1_OFLW_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_EVC1_OFLW_SET ns_noc_io_spio_soc_ip.csr 103496 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXE_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 103507 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_rxem bridge_spio_p10_rvt_ahb0_s_11_8_rxem SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 103580 spio_p10_rvt_ahb0_s register rxem 0x2F128 R/W 0x00000050 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_UNSD_3_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_UNSD_3_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_UNSD_3_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_UNSD_3_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_UNSD_3_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_UNSD_3_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_UNSD_3_0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_UNSD_3_0_SET ns_noc_io_spio_soc_ip.csr 103529 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_EVC_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_EVC_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_EVC_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_EVC_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_EVC_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_EVC_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_EVC_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_EVC_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 103543 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 103554 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_EVC1_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_EVC1_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_EVC1_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_EVC1_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_EVC1_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_EVC1_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_EVC1_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 103568 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_RXEM_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 103579 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_brs_0 bridge_spio_p10_rvt_ahb0_s_11_8_brs_0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 103854 spio_p10_rvt_ahb0_s register brs_0 0x2F130 R 0x00000000 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 103604 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_0_SET ns_noc_io_spio_soc_ip.csr 103615 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_0_SET ns_noc_io_spio_soc_ip.csr 103626 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_0_SET ns_noc_io_spio_soc_ip.csr 103637 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_0_SET ns_noc_io_spio_soc_ip.csr 103648 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 103658 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 103669 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_1_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_1_SET ns_noc_io_spio_soc_ip.csr 103680 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_1_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_1_SET ns_noc_io_spio_soc_ip.csr 103691 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_1_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_1_SET ns_noc_io_spio_soc_ip.csr 103702 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_1_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_1_SET ns_noc_io_spio_soc_ip.csr 103713 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 103723 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 103734 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_2_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_2_SET ns_noc_io_spio_soc_ip.csr 103745 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_2_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_2_SET ns_noc_io_spio_soc_ip.csr 103756 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_2_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_2_SET ns_noc_io_spio_soc_ip.csr 103767 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_2_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_2_SET ns_noc_io_spio_soc_ip.csr 103778 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 103788 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 103799 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_3_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_V_3_SET ns_noc_io_spio_soc_ip.csr 103810 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_3_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_S_3_SET ns_noc_io_spio_soc_ip.csr 103821 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_3_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_B_3_SET ns_noc_io_spio_soc_ip.csr 103832 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_3_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_F_3_SET ns_noc_io_spio_soc_ip.csr 103843 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_0_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 103853 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_brs_1 bridge_spio_p10_rvt_ahb0_s_11_8_brs_1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 104128 spio_p10_rvt_ahb0_s register brs_1 0x2F138 R 0x00000000 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 103878 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_0_SET ns_noc_io_spio_soc_ip.csr 103889 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_0_SET ns_noc_io_spio_soc_ip.csr 103900 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_0_SET ns_noc_io_spio_soc_ip.csr 103911 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_0_SET ns_noc_io_spio_soc_ip.csr 103922 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 103932 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 103943 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_1_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_1_SET ns_noc_io_spio_soc_ip.csr 103954 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_1_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_1_SET ns_noc_io_spio_soc_ip.csr 103965 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_1_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_1_SET ns_noc_io_spio_soc_ip.csr 103976 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_1_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_1_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_1_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_1_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_1_SET ns_noc_io_spio_soc_ip.csr 103987 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 103997 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 104008 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_2_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_2_SET ns_noc_io_spio_soc_ip.csr 104019 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_2_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_2_SET ns_noc_io_spio_soc_ip.csr 104030 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_2_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_2_SET ns_noc_io_spio_soc_ip.csr 104041 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_2_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_2_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_2_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_2_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_2_SET ns_noc_io_spio_soc_ip.csr 104052 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 104062 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 104073 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_3_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_V_3_SET ns_noc_io_spio_soc_ip.csr 104084 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_3_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_S_3_SET ns_noc_io_spio_soc_ip.csr 104095 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_3_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_B_3_SET ns_noc_io_spio_soc_ip.csr 104106 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_3_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_3_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_3_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_3_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_F_3_SET ns_noc_io_spio_soc_ip.csr 104117 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRS_1_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 104127 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_brus bridge_spio_p10_rvt_ahb0_s_11_8_brus SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 104197 spio_p10_rvt_ahb0_s register brus 0x2F1B0 R 0x00000000 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_A_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_A_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_A_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_A_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_A_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_A_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_A_SET ns_noc_io_spio_soc_ip.csr 104153 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_B_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_B_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_B_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_B_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_B_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_B_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_B_SET ns_noc_io_spio_soc_ip.csr 104164 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_C_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_C_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_C_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_C_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_C_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_C_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_C_SET ns_noc_io_spio_soc_ip.csr 104175 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_D_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_D_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_D_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_D_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_D_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_D_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_V_D_SET ns_noc_io_spio_soc_ip.csr 104186 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_UNSD_31_4_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_UNSD_31_4_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_UNSD_31_4_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_UNSD_31_4_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_UNSD_31_4_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_UNSD_31_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_UNSD_31_4_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRUS_UNSD_31_4_SET ns_noc_io_spio_soc_ip.csr 104196 UNSD_31_4 31 4 0x0000000 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_brperr0 bridge_spio_p10_rvt_ahb0_s_11_8_brperr0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 104425 spio_p10_rvt_ahb0_s register brperr0 0x2F1D0 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_D0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_D0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_D0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_D0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_D0_SET ns_noc_io_spio_soc_ip.csr 104235 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_DC0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_DC0_SET ns_noc_io_spio_soc_ip.csr 104246 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SB0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SB0_SET ns_noc_io_spio_soc_ip.csr 104257 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SBC0_SET ns_noc_io_spio_soc_ip.csr 104269 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_PK0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_PK0_SET ns_noc_io_spio_soc_ip.csr 104280 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 104291 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_D1_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_D1_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_D1_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_D1_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_D1_SET ns_noc_io_spio_soc_ip.csr 104302 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_DC1_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_DC1_SET ns_noc_io_spio_soc_ip.csr 104313 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SB1_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SB1_SET ns_noc_io_spio_soc_ip.csr 104324 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_SBC1_SET ns_noc_io_spio_soc_ip.csr 104336 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_PK1_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_PK1_SET ns_noc_io_spio_soc_ip.csr 104347 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 104358 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 104369 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 104380 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 104391 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 104402 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 104413 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 104424 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_brperr1 bridge_spio_p10_rvt_ahb0_s_11_8_brperr1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 104541 spio_p10_rvt_ahb0_s register brperr1 0x2F1D8 R 0x0000000000000000 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 104463 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 104474 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 104485 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 104496 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 104507 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 104518 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 104529 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERR1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 104540 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_brperrm0 bridge_spio_p10_rvt_ahb0_s_11_8_brperrm0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 104762 spio_p10_rvt_ahb0_s register brperrm0 0x2F1E0 R/W 0x0000000000000000 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_D0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_D0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_D0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_D0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_D0_SET ns_noc_io_spio_soc_ip.csr 104568 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_DC0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_DC0_SET ns_noc_io_spio_soc_ip.csr 104580 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SB0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SB0_SET ns_noc_io_spio_soc_ip.csr 104591 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SBC0_SET ns_noc_io_spio_soc_ip.csr 104603 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_PK0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_PK0_SET ns_noc_io_spio_soc_ip.csr 104615 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 104626 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_D1_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_D1_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_D1_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_D1_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_D1_SET ns_noc_io_spio_soc_ip.csr 104637 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_DC1_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_DC1_SET ns_noc_io_spio_soc_ip.csr 104649 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SB1_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SB1_SET ns_noc_io_spio_soc_ip.csr 104660 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_SBC1_SET ns_noc_io_spio_soc_ip.csr 104672 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_PK1_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_PK1_SET ns_noc_io_spio_soc_ip.csr 104684 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 104695 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 104706 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 104717 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 104728 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 104739 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 104750 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 104761 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_p10_rvt_ahb0_s_11_8_brperrm1 bridge_spio_p10_rvt_ahb0_s_11_8_brperrm1 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_OFFSET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 104867 spio_p10_rvt_ahb0_s register brperrm1 0x2F1E8 R 0x0000000000000000 Spio_noc_bridge_spio_p10_rvt_ahb0_s_11_8_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 104789 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 104800 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 104811 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 104822 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 104833 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 104844 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 104855 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_P10_RVT_AHB0_S_11_8_BRPERRM1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 104866 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_cgc bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_cgc SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGC_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGC_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGC_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 104904 spio_sp_main0_main_noc_rbm_s register as_cgc 0x31C10 R/W 0x0000000000000064 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_cgc Programmable intervals used by coarse clock gating logic. This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGC_HYSTERESIS_COUNTER_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGC_HYSTERESIS_COUNTER_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGC_HYSTERESIS_COUNTER_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGC_HYSTERESIS_COUNTER_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGC_HYSTERESIS_COUNTER_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGC_HYSTERESIS_COUNTER_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGC_HYSTERESIS_COUNTER_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_spio_soc_ip.csr 104892 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGC_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGC_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGC_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGC_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGC_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGC_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGC_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGC_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 104903 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_cgo bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_cgo SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGO_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGO_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGO_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGO_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 104939 spio_sp_main0_main_noc_rbm_s register as_cgo 0x31C18 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the slave bridge. false false false false FPO SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGO_FPO_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGO_FPO_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGO_FPO_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGO_FPO_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGO_FPO_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGO_FPO_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGO_FPO_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGO_FPO_SET ns_noc_io_spio_soc_ip.csr 104927 FPO 1'b1: Clock gating override enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGO_UNSD_63_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGO_UNSD_63_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGO_UNSD_63_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGO_UNSD_63_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGO_UNSD_63_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGO_UNSD_63_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGO_UNSD_63_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CGO_UNSD_63_1_SET ns_noc_io_spio_soc_ip.csr 104938 UNSD_63_1 63 1 0x0000000000000000 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_sts bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_sts SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 105013 spio_sp_main0_main_noc_rbm_s register as_sts 0x31D00 R 0x000000000000000c Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_sts Slave bridge status bits. false false false false WOF SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_WOF_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_WOF_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_WOF_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_WOF_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_WOF_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_WOF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_WOF_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_WOF_SET ns_noc_io_spio_soc_ip.csr 104962 WOF 1'b1: Maximum number of supported write commands are outstanding to the attached slave device awaiting response, no more write commands will be issued to slave till responses are received. 1'b0: Slave device can expect more write commands from NoC 0 0 0x0 R ROF SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_ROF_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_ROF_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_ROF_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_ROF_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_ROF_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_ROF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_ROF_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_ROF_SET ns_noc_io_spio_soc_ip.csr 104978 ROF 1'b1: Maximum number of supported read commands are outstanding to the attached slave device awaiting response, no more read commands will be issued to slave till responses are received. 1'b0: Slave bridge can accept more read commands from the NoC 1 1 0x0 R WOE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_WOE_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_WOE_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_WOE_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_WOE_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_WOE_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_WOE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_WOE_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_WOE_SET ns_noc_io_spio_soc_ip.csr 104990 WOE 1'b1: There are no write commands outstanding to the attached slave device 2 2 0x1 R ROE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_ROE_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_ROE_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_ROE_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_ROE_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_ROE_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_ROE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_ROE_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_ROE_SET ns_noc_io_spio_soc_ip.csr 105002 ROE 1'b1: There are no read commands outstanding to the attached slave device 3 3 0x1 R UNSD_63_4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_UNSD_63_4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_UNSD_63_4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_UNSD_63_4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_UNSD_63_4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_UNSD_63_4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_UNSD_63_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_UNSD_63_4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_STS_UNSD_63_4_SET ns_noc_io_spio_soc_ip.csr 105012 UNSD_63_4 63 4 0x000000000000000 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_bridge_id bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_bridge_id SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_BRIDGE_ID_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_BRIDGE_ID_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_BRIDGE_ID_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_BRIDGE_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 105043 spio_sp_main0_main_noc_rbm_s register as_bridge_id 0x31D08 R 0x000000000000000c Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_bridge_id Unique identifier assigned to the slave bridge. false false false false ID SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_BRIDGE_ID_ID_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_BRIDGE_ID_ID_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_BRIDGE_ID_ID_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_BRIDGE_ID_ID_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_BRIDGE_ID_ID_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_BRIDGE_ID_ID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_BRIDGE_ID_ID_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_BRIDGE_ID_ID_SET ns_noc_io_spio_soc_ip.csr 105032 ID Unique bridge ID 15 0 0x000c R UNSD_63_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_BRIDGE_ID_UNSD_63_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_BRIDGE_ID_UNSD_63_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_BRIDGE_ID_UNSD_63_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_BRIDGE_ID_UNSD_63_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_BRIDGE_ID_UNSD_63_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_BRIDGE_ID_UNSD_63_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_BRIDGE_ID_UNSD_63_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_spio_soc_ip.csr 105042 UNSD_63_16 63 16 0x000000000000 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_err bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_err SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 105396 spio_sp_main0_main_noc_rbm_s register as_err 0x31E00 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E0_SET ns_noc_io_spio_soc_ip.csr 105064 E0 1'b1: Read decode error response: Decode error response received from slave device for read command 0 0 0x0 R/W E1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E1_SET ns_noc_io_spio_soc_ip.csr 105076 E1 1'b1: Read slave error response: Slave error response received from slave device for read command 1 1 0x0 R/W E2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E2_SET ns_noc_io_spio_soc_ip.csr 105089 E2 1'b1: [FATAL] Unknown read response destination: RID from read response produces a destination which is not present in the routing table 2 2 0x0 R/W E3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E3_SET ns_noc_io_spio_soc_ip.csr 105103 E3 1'b1: [FATAL] Interleaved read response: Interleaved read response. This can occur if interleaved read response is received from a slave device for which a de-interleaver was not specified 3 3 0x0 R/W E4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E4_SET ns_noc_io_spio_soc_ip.csr 105115 E4 1'b1: Read command modified: A read command which was marked as non-modifiable was modified by the slave bridge 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_UNSD_15_5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_UNSD_15_5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_UNSD_15_5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_UNSD_15_5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_UNSD_15_5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_UNSD_15_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_UNSD_15_5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 105126 UNSD_15_5 15 5 0x000 R E16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E16_SET ns_noc_io_spio_soc_ip.csr 105138 E16 1'b1: Write decode error response: Decode error response received from slave device for write command 16 16 0x0 R/W E17 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E17_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E17_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E17_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E17_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E17_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E17_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E17_SET ns_noc_io_spio_soc_ip.csr 105150 E17 1'b1: Write slave error response: Slave error response received from slave device for write command 17 17 0x0 R/W E18 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E18_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E18_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E18_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E18_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E18_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E18_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E18_SET ns_noc_io_spio_soc_ip.csr 105163 E18 1'b1: [FATAL] Unknown write response destination: BID from write response produces a destination which is not present in the routing table 18 18 0x0 R/W E19 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E19_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E19_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E19_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E19_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E19_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E19_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E19_SET ns_noc_io_spio_soc_ip.csr 105175 E19 1'b1: Write command modified: A write command which was marked as non-modifiable was modified by the slave bridge 19 19 0x0 R/W UNSD_31_20 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_UNSD_31_20_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_UNSD_31_20_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_UNSD_31_20_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_UNSD_31_20_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_UNSD_31_20_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_UNSD_31_20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_UNSD_31_20_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_UNSD_31_20_SET ns_noc_io_spio_soc_ip.csr 105186 UNSD_31_20 31 20 0x000 R E32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E32_SET ns_noc_io_spio_soc_ip.csr 105198 E32 1'b1: [FATAL] Traffic sent to a noc layer which is power gated 32 32 0x0 R/W E33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E33_SET ns_noc_io_spio_soc_ip.csr 105209 E33 1'b1: [FATAL] Parity error in config/status registers 33 33 0x0 R/W E34 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E34_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E34_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E34_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E34_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E34_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E34_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E34_SET ns_noc_io_spio_soc_ip.csr 105220 E34 1'b1: [FATAL] RDATA Parity error 34 34 0x0 R/W E35 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E35_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E35_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E35_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E35_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E35_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E35_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E35_SET ns_noc_io_spio_soc_ip.csr 105231 E35 1'b1: [FATAL] RRESP Parity error 35 35 0x0 R/W E36 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E36_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E36_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E36_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E36_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E36_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E36_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E36_SET ns_noc_io_spio_soc_ip.csr 105242 E36 1'b1: [FATAL] BRESP Parity error 36 36 0x0 R/W E37 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E37_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E37_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E37_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E37_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E37_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E37_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E37_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E37_SET ns_noc_io_spio_soc_ip.csr 105253 E37 1'b1: [FATAL] AC Parity error 37 37 0x0 R/W E38 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E38_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E38_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E38_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E38_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E38_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E38_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E38_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E38_SET ns_noc_io_spio_soc_ip.csr 105264 E38 1'b1: [FATAL] ACADDR Parity error 38 38 0x0 R/W E39 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E39_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E39_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E39_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E39_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E39_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E39_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E39_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E39_SET ns_noc_io_spio_soc_ip.csr 105276 E39 1'b1: [FATAL] R Ch Cmdtbl Parity Err 39 39 0x0 R E40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E40_SET ns_noc_io_spio_soc_ip.csr 105288 E40 1'b1: [FATAL] B Ch Cmdtbl Parity Err 40 40 0x0 R E41 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E41_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E41_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E41_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E41_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E41_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E41_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E41_SET ns_noc_io_spio_soc_ip.csr 105300 E41 1'b1: [FATAL] Rx Fifo Parity Err 41 41 0x0 R E42 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E42_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E42_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E42_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E42_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E42_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E42_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E42_SET ns_noc_io_spio_soc_ip.csr 105312 E42 1'b1: [FATAL] CRCD Ch Reorder Buffer Parity Err 42 42 0x0 R E43 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E43_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E43_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E43_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E43_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E43_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E43_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E43_SET ns_noc_io_spio_soc_ip.csr 105324 E43 1'b1: [FATAL] Ack Ch Wack Reorder Buffer Parity Err 43 43 0x0 R E44 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E44_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E44_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E44_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E44_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E44_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E44_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E44_SET ns_noc_io_spio_soc_ip.csr 105336 E44 1'b1: [FATAL] Ack Ch Rack Reorder Buffer Parity Err 44 44 0x0 R E45 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E45_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E45_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E45_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E45_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E45_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E45_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E45_SET ns_noc_io_spio_soc_ip.csr 105348 E45 1'b1: [FATAL] B Ch Drain Fifo Parity Err 45 45 0x0 R E46 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E46_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E46_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E46_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E46_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E46_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E46_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E46_SET ns_noc_io_spio_soc_ip.csr 105360 E46 1'b1: [FATAL] R Ch Flush Fifo Parity Err 46 46 0x0 R E47 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E47_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E47_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E47_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E47_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E47_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E47_SET ns_noc_io_spio_soc_ip.csr 105372 E47 1'b1: [FATAL] R Ch Deinterleaver Cmdtbl Parity Err 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_E48_SET ns_noc_io_spio_soc_ip.csr 105384 E48 1'b1: [FATAL] R Ch Deinterleaver Data Buffer Parity Err 48 48 0x0 R UNSD_63_49 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_UNSD_63_49_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_UNSD_63_49_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_UNSD_63_49_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_UNSD_63_49_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_UNSD_63_49_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_UNSD_63_49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_UNSD_63_49_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_ERR_UNSD_63_49_SET ns_noc_io_spio_soc_ip.csr 105395 UNSD_63_49 63 49 0x0000 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_intm bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_intm SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 105736 spio_sp_main0_main_noc_rbm_s register as_intm 0x31E40 R/W 0x0000007d000b0013 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_intm Interrupt mask register.Individual bit positions match the error bit positions in AS_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M0_SET ns_noc_io_spio_soc_ip.csr 105417 M0 Mask interrupts for read channel 0 0 0x1 R/W M1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M1_SET ns_noc_io_spio_soc_ip.csr 105428 M1 Mask interrupts for read channel 1 1 0x1 R/W M2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M2_SET ns_noc_io_spio_soc_ip.csr 105439 M2 Mask interrupts for read channel 2 2 0x0 R/W M3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M3_SET ns_noc_io_spio_soc_ip.csr 105450 M3 Mask interrupts for read channel 3 3 0x0 R/W M4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M4_SET ns_noc_io_spio_soc_ip.csr 105461 M4 Mask interrupts for read channel 4 4 0x1 R/W UNSD_15_5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_UNSD_15_5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_UNSD_15_5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_UNSD_15_5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_UNSD_15_5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_UNSD_15_5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_UNSD_15_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_UNSD_15_5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 105472 UNSD_15_5 15 5 0x000 R M16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M16_SET ns_noc_io_spio_soc_ip.csr 105483 M16 Mask interrupts for write channel 16 16 0x1 R/W M17 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M17_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M17_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M17_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M17_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M17_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M17_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M17_SET ns_noc_io_spio_soc_ip.csr 105494 M17 Mask interrupts for write channel 17 17 0x1 R/W M18 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M18_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M18_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M18_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M18_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M18_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M18_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M18_SET ns_noc_io_spio_soc_ip.csr 105505 M18 Mask interrupts for write channel 18 18 0x0 R/W M19 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M19_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M19_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M19_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M19_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M19_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M19_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M19_SET ns_noc_io_spio_soc_ip.csr 105516 M19 Mask interrupts for write channel 19 19 0x1 R/W UNSD_31_20 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_UNSD_31_20_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_UNSD_31_20_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_UNSD_31_20_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_UNSD_31_20_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_UNSD_31_20_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_UNSD_31_20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_UNSD_31_20_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_UNSD_31_20_SET ns_noc_io_spio_soc_ip.csr 105527 UNSD_31_20 31 20 0x000 R M32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M32_SET ns_noc_io_spio_soc_ip.csr 105538 M32 Mask interrupt on traffic to PG layer 32 32 0x1 R/W M33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M33_SET ns_noc_io_spio_soc_ip.csr 105549 M33 Mask interrupt on csr parity errors 33 33 0x0 R/W M34 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M34_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M34_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M34_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M34_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M34_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M34_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M34_SET ns_noc_io_spio_soc_ip.csr 105560 M34 RDATA parity interrupt Mask 34 34 0x1 R/W M35 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M35_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M35_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M35_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M35_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M35_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M35_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M35_SET ns_noc_io_spio_soc_ip.csr 105571 M35 RRESP parity interrupt Mask 35 35 0x1 R/W M36 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M36_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M36_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M36_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M36_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M36_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M36_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M36_SET ns_noc_io_spio_soc_ip.csr 105582 M36 BRESP parity interrupt Mask 36 36 0x1 R/W M37 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M37_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M37_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M37_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M37_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M37_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M37_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M37_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M37_SET ns_noc_io_spio_soc_ip.csr 105593 M37 AC parity interrupt Mask 37 37 0x1 R/W M38 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M38_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M38_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M38_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M38_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M38_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M38_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M38_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_M38_SET ns_noc_io_spio_soc_ip.csr 105604 M38 ACADDR parity interrupt Mask 38 38 0x1 R/W E39 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E39_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E39_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E39_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E39_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E39_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E39_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E39_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E39_SET ns_noc_io_spio_soc_ip.csr 105616 E39 1'b1: R Ch Cmdtbl Parity Err Intr Mask 39 39 0x0 R E40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E40_SET ns_noc_io_spio_soc_ip.csr 105628 E40 1'b1: B Ch Cmdtbl Parity Err Intr Mask 40 40 0x0 R E41 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E41_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E41_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E41_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E41_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E41_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E41_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E41_SET ns_noc_io_spio_soc_ip.csr 105640 E41 1'b1: Rx Fifo Parity Err Intr Mask 41 41 0x0 R E42 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E42_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E42_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E42_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E42_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E42_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E42_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E42_SET ns_noc_io_spio_soc_ip.csr 105652 E42 1'b1: CRCD Ch Reorder Buffer Parity Err Intr Mask 42 42 0x0 R E43 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E43_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E43_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E43_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E43_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E43_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E43_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E43_SET ns_noc_io_spio_soc_ip.csr 105664 E43 1'b1: Ack Ch Wack Reorder Buffer Parity Err IntrMask 43 43 0x0 R E44 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E44_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E44_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E44_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E44_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E44_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E44_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E44_SET ns_noc_io_spio_soc_ip.csr 105676 E44 1'b1: Ack Ch Rack Reorder Buffer Parity Err Intr Mask 44 44 0x0 R E45 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E45_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E45_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E45_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E45_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E45_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E45_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E45_SET ns_noc_io_spio_soc_ip.csr 105688 E45 1'b1: B Ch Drain Fifo Parity Err Intr Mask 45 45 0x0 R E46 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E46_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E46_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E46_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E46_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E46_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E46_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E46_SET ns_noc_io_spio_soc_ip.csr 105700 E46 1'b1: R Ch Flush Fifo Parity Err Intr Mask 46 46 0x0 R E47 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E47_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E47_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E47_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E47_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E47_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E47_SET ns_noc_io_spio_soc_ip.csr 105712 E47 1'b1: R Ch Deinterleaver Cmdtbl Parity Err Intr Mask 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_E48_SET ns_noc_io_spio_soc_ip.csr 105724 E48 1'b1: R Ch Deinterleaver Data Buffer Parity Err Intr Mask 48 48 0x0 R UNSD_63_49 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_UNSD_63_49_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_UNSD_63_49_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_UNSD_63_49_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_UNSD_63_49_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_UNSD_63_49_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_UNSD_63_49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_UNSD_63_49_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_INTM_UNSD_63_49_SET ns_noc_io_spio_soc_ip.csr 105735 UNSD_63_49 63 49 0x0000 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_ccmd bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_ccmd SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 105811 spio_sp_main0_main_noc_rbm_s register as_ccmd 0x31F00 R/W 0x0000000003000000 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_ccmd Not applicable for current release. false false false false UNSD_23_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_UNSD_23_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_UNSD_23_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_UNSD_23_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_UNSD_23_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_UNSD_23_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_UNSD_23_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_UNSD_23_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_UNSD_23_0_SET ns_noc_io_spio_soc_ip.csr 105754 UNSD_23_0 23 0 0x000000 R rdy SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_RDY_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_RDY_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_RDY_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_RDY_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_RDY_SET ns_noc_io_spio_soc_ip.csr 105765 rdy 1'b1: Ready 24 24 0x1 R/W val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_VAL_SET ns_noc_io_spio_soc_ip.csr 105776 val 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_UNSD_27_26_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_UNSD_27_26_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_UNSD_27_26_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_UNSD_27_26_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_UNSD_27_26_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_UNSD_27_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_UNSD_27_26_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_UNSD_27_26_SET ns_noc_io_spio_soc_ip.csr 105787 UNSD_27_26 27 26 0x0 R intfid SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_INTFID_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_INTFID_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_INTFID_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_INTFID_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_INTFID_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_INTFID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_INTFID_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_INTFID_SET ns_noc_io_spio_soc_ip.csr 105799 intfid 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_63_31 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_UNSD_63_31_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_UNSD_63_31_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_UNSD_63_31_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_UNSD_63_31_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_UNSD_63_31_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_UNSD_63_31_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_UNSD_63_31_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMD_UNSD_63_31_SET ns_noc_io_spio_soc_ip.csr 105810 UNSD_63_31 63 31 0x000000000 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_ccmdmsk bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_ccmdmsk SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 105863 spio_sp_main0_main_noc_rbm_s register as_ccmdmsk 0x31F08 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_ccmdmsk Not applicable for current release. false false false false UNSD_23_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_UNSD_23_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_UNSD_23_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_UNSD_23_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_UNSD_23_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_UNSD_23_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_UNSD_23_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_UNSD_23_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_UNSD_23_0_SET ns_noc_io_spio_soc_ip.csr 105829 UNSD_23_0 23 0 0x000000 R rdy SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_RDY_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_RDY_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_RDY_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_RDY_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_RDY_SET ns_noc_io_spio_soc_ip.csr 105840 rdy 1'b1: Ready 24 24 0x0 R/W val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_VAL_SET ns_noc_io_spio_soc_ip.csr 105851 val 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_UNSD_63_26_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_UNSD_63_26_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_UNSD_63_26_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_UNSD_63_26_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_UNSD_63_26_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_UNSD_63_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_UNSD_63_26_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CCMDMSK_UNSD_63_26_SET ns_noc_io_spio_soc_ip.csr 105862 UNSD_63_26 63 26 0x0000000000 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_cntr bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_cntr SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CNTR_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CNTR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CNTR_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CNTR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 105893 spio_sp_main0_main_noc_rbm_s register as_cntr 0x31F10 R 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_cntr Not applicable for current release. false false false false CNTR SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CNTR_CNTR_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CNTR_CNTR_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CNTR_CNTR_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CNTR_CNTR_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CNTR_CNTR_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CNTR_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CNTR_CNTR_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CNTR_CNTR_SET ns_noc_io_spio_soc_ip.csr 105882 CNTR Counter 31 0 0x00000000 R UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CNTR_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CNTR_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CNTR_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CNTR_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CNTR_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CNTR_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CNTR_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_CNTR_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 105892 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_arovrd bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_arovrd SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 106006 spio_sp_main0_main_noc_rbm_s register as_arovrd 0x31F18 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_arovrd AR Overrides. false false false false arcache_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 105911 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 105924 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 105935 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 105946 UNSD_11_11 11 11 0x0 R arprot_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 105959 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 105970 UNSD_15_15 15 15 0x0 R arqos_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 105981 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_ARQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 105994 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AROVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 106005 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_awovrd bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_awovrd SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 106119 spio_sp_main0_main_noc_rbm_s register as_awovrd 0x31F20 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_as_awovrd AW Overrides. false false false false awcache_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 106024 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 106037 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 106048 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 106059 UNSD_11_11 11 11 0x0 R awprot_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 106072 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 106083 UNSD_15_15 15 15 0x0 R awqos_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 106094 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_AWQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 106107 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_AS_AWOVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 106118 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_p_0 bridge_spio_sp_main0_main_noc_rbm_s_12_6_p_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 106184 spio_sp_main0_main_noc_rbm_s register p_0 0x33000 R/W 0x00000003 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_0_SET ns_noc_io_spio_soc_ip.csr 106147 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_1_SET ns_noc_io_spio_soc_ip.csr 106159 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_2_SET ns_noc_io_spio_soc_ip.csr 106171 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_0_WT_QOS_3_SET ns_noc_io_spio_soc_ip.csr 106183 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_p_1 bridge_spio_sp_main0_main_noc_rbm_s_12_6_p_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 106250 spio_sp_main0_main_noc_rbm_s register p_1 0x33008 R 0x00000000 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_4_SET ns_noc_io_spio_soc_ip.csr 106213 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_5_SET ns_noc_io_spio_soc_ip.csr 106225 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_6_SET ns_noc_io_spio_soc_ip.csr 106237 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_1_WT_QOS_7_SET ns_noc_io_spio_soc_ip.csr 106249 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_p_2 bridge_spio_sp_main0_main_noc_rbm_s_12_6_p_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 106316 spio_sp_main0_main_noc_rbm_s register p_2 0x33010 R 0x00000000 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_8_SET ns_noc_io_spio_soc_ip.csr 106279 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_9_SET ns_noc_io_spio_soc_ip.csr 106291 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_10_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_10_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_10_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_10_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_10_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_10_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_10_SET ns_noc_io_spio_soc_ip.csr 106303 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_2_WT_QOS_11_SET ns_noc_io_spio_soc_ip.csr 106315 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_p_3 bridge_spio_sp_main0_main_noc_rbm_s_12_6_p_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 106382 spio_sp_main0_main_noc_rbm_s register p_3 0x33018 R 0x00000000 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_12_SET ns_noc_io_spio_soc_ip.csr 106345 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_13_SET ns_noc_io_spio_soc_ip.csr 106357 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_14_SET ns_noc_io_spio_soc_ip.csr 106369 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_P_3_WT_QOS_15_SET ns_noc_io_spio_soc_ip.csr 106381 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_txe bridge_spio_sp_main0_main_noc_rbm_s_12_6_txe SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 106528 spio_sp_main0_main_noc_rbm_s register txe 0x33040 R/W 0x00000000 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_TRANS_WITHOUT_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_TRANS_WITHOUT_SOP_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_TRANS_WITHOUT_SOP_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_TRANS_WITHOUT_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_TRANS_WITHOUT_SOP_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_TRANS_WITHOUT_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_TRANS_WITHOUT_SOP_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_spio_soc_ip.csr 106409 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_SOP_AFTER_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_SOP_AFTER_SOP_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_SOP_AFTER_SOP_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_SOP_AFTER_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_SOP_AFTER_SOP_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_SOP_AFTER_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_SOP_AFTER_SOP_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_SOP_AFTER_SOP_SET ns_noc_io_spio_soc_ip.csr 106421 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 106436 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 106449 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_spio_soc_ip.csr 106463 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_spio_soc_ip.csr 106477 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_spio_soc_ip.csr 106491 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_spio_soc_ip.csr 106505 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 106516 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXE_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 106527 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_txem bridge_spio_sp_main0_main_noc_rbm_s_12_6_txem SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 106607 spio_sp_main0_main_noc_rbm_s register txem 0x33048 R/W 0x00000008 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_UNSD_1_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_UNSD_1_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_UNSD_1_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_UNSD_1_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_UNSD_1_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_UNSD_1_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_UNSD_1_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_UNSD_1_0_SET ns_noc_io_spio_soc_ip.csr 106551 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 106562 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 106573 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_UNSD_7_4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_UNSD_7_4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_UNSD_7_4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_UNSD_7_4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_UNSD_7_4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_UNSD_7_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_UNSD_7_4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_UNSD_7_4_SET ns_noc_io_spio_soc_ip.csr 106584 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 106595 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_TXEM_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 106606 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btus_0 bridge_spio_sp_main0_main_noc_rbm_s_12_6_btus_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 106975 spio_sp_main0_main_noc_rbm_s register btus_0 0x33058 R 0x00000000 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_A_SET ns_noc_io_spio_soc_ip.csr 106633 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_B_SET ns_noc_io_spio_soc_ip.csr 106644 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_C_SET ns_noc_io_spio_soc_ip.csr 106655 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L0_D_SET ns_noc_io_spio_soc_ip.csr 106666 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_A_SET ns_noc_io_spio_soc_ip.csr 106677 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_B_SET ns_noc_io_spio_soc_ip.csr 106688 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_C_SET ns_noc_io_spio_soc_ip.csr 106699 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L1_D_SET ns_noc_io_spio_soc_ip.csr 106710 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_A_SET ns_noc_io_spio_soc_ip.csr 106721 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_B_SET ns_noc_io_spio_soc_ip.csr 106732 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_C_SET ns_noc_io_spio_soc_ip.csr 106743 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L2_D_SET ns_noc_io_spio_soc_ip.csr 106754 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_A_SET ns_noc_io_spio_soc_ip.csr 106765 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_B_SET ns_noc_io_spio_soc_ip.csr 106776 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_C_SET ns_noc_io_spio_soc_ip.csr 106787 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L3_D_SET ns_noc_io_spio_soc_ip.csr 106798 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_A_SET ns_noc_io_spio_soc_ip.csr 106809 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_B_SET ns_noc_io_spio_soc_ip.csr 106820 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_C_SET ns_noc_io_spio_soc_ip.csr 106831 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L4_D_SET ns_noc_io_spio_soc_ip.csr 106842 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_A_SET ns_noc_io_spio_soc_ip.csr 106853 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_B_SET ns_noc_io_spio_soc_ip.csr 106864 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_C_SET ns_noc_io_spio_soc_ip.csr 106875 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L5_D_SET ns_noc_io_spio_soc_ip.csr 106886 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_A_SET ns_noc_io_spio_soc_ip.csr 106897 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_B_SET ns_noc_io_spio_soc_ip.csr 106908 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_C_SET ns_noc_io_spio_soc_ip.csr 106919 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L6_D_SET ns_noc_io_spio_soc_ip.csr 106930 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_A_SET ns_noc_io_spio_soc_ip.csr 106941 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_B_SET ns_noc_io_spio_soc_ip.csr 106952 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_C_SET ns_noc_io_spio_soc_ip.csr 106963 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_0_L7_D_SET ns_noc_io_spio_soc_ip.csr 106974 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btus_1 bridge_spio_sp_main0_main_noc_rbm_s_12_6_btus_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 107343 spio_sp_main0_main_noc_rbm_s register btus_1 0x33060 R 0x00000000 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_A_SET ns_noc_io_spio_soc_ip.csr 107001 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_B_SET ns_noc_io_spio_soc_ip.csr 107012 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_C_SET ns_noc_io_spio_soc_ip.csr 107023 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L8_D_SET ns_noc_io_spio_soc_ip.csr 107034 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_A_SET ns_noc_io_spio_soc_ip.csr 107045 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_B_SET ns_noc_io_spio_soc_ip.csr 107056 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_C_SET ns_noc_io_spio_soc_ip.csr 107067 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L9_D_SET ns_noc_io_spio_soc_ip.csr 107078 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_A_SET ns_noc_io_spio_soc_ip.csr 107089 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_B_SET ns_noc_io_spio_soc_ip.csr 107100 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_C_SET ns_noc_io_spio_soc_ip.csr 107111 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L10_D_SET ns_noc_io_spio_soc_ip.csr 107122 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_A_SET ns_noc_io_spio_soc_ip.csr 107133 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_B_SET ns_noc_io_spio_soc_ip.csr 107144 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_C_SET ns_noc_io_spio_soc_ip.csr 107155 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L11_D_SET ns_noc_io_spio_soc_ip.csr 107166 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_A_SET ns_noc_io_spio_soc_ip.csr 107177 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_B_SET ns_noc_io_spio_soc_ip.csr 107188 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_C_SET ns_noc_io_spio_soc_ip.csr 107199 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L12_D_SET ns_noc_io_spio_soc_ip.csr 107210 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_A_SET ns_noc_io_spio_soc_ip.csr 107221 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_B_SET ns_noc_io_spio_soc_ip.csr 107232 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_C_SET ns_noc_io_spio_soc_ip.csr 107243 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L13_D_SET ns_noc_io_spio_soc_ip.csr 107254 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_A_SET ns_noc_io_spio_soc_ip.csr 107265 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_B_SET ns_noc_io_spio_soc_ip.csr 107276 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_C_SET ns_noc_io_spio_soc_ip.csr 107287 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L14_D_SET ns_noc_io_spio_soc_ip.csr 107298 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_A_SET ns_noc_io_spio_soc_ip.csr 107309 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_B_SET ns_noc_io_spio_soc_ip.csr 107320 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_C_SET ns_noc_io_spio_soc_ip.csr 107331 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTUS_1_L15_D_SET ns_noc_io_spio_soc_ip.csr 107342 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btrl_0 bridge_spio_sp_main0_main_noc_rbm_s_12_6_btrl_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 107419 spio_sp_main0_main_noc_rbm_s register btrl_0 0x33080 R 0x00000000 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_WT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_WT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_WT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_WT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_WT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_WT_SET ns_noc_io_spio_soc_ip.csr 107367 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 107378 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_CNT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_CNT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_CNT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_CNT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_CNT_SET ns_noc_io_spio_soc_ip.csr 107393 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_EN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_EN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_EN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_EN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_EN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_EN_SET ns_noc_io_spio_soc_ip.csr 107407 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_0_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 107418 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btrl_1 bridge_spio_sp_main0_main_noc_rbm_s_12_6_btrl_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 107495 spio_sp_main0_main_noc_rbm_s register btrl_1 0x33088 R 0x00000000 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_WT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_WT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_WT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_WT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_WT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_WT_SET ns_noc_io_spio_soc_ip.csr 107443 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 107454 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_CNT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_CNT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_CNT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_CNT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_CNT_SET ns_noc_io_spio_soc_ip.csr 107469 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_EN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_EN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_EN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_EN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_EN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_EN_SET ns_noc_io_spio_soc_ip.csr 107483 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_1_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 107494 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btrl_2 bridge_spio_sp_main0_main_noc_rbm_s_12_6_btrl_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 107571 spio_sp_main0_main_noc_rbm_s register btrl_2 0x33090 R 0x00000000 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_WT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_WT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_WT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_WT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_WT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_WT_SET ns_noc_io_spio_soc_ip.csr 107519 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 107530 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_CNT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_CNT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_CNT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_CNT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_CNT_SET ns_noc_io_spio_soc_ip.csr 107545 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_EN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_EN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_EN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_EN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_EN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_EN_SET ns_noc_io_spio_soc_ip.csr 107559 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_2_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 107570 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btrl_3 bridge_spio_sp_main0_main_noc_rbm_s_12_6_btrl_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 107647 spio_sp_main0_main_noc_rbm_s register btrl_3 0x33098 R 0x00000000 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_WT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_WT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_WT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_WT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_WT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_WT_SET ns_noc_io_spio_soc_ip.csr 107595 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 107606 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_CNT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_CNT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_CNT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_CNT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_CNT_SET ns_noc_io_spio_soc_ip.csr 107621 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_EN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_EN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_EN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_EN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_EN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_EN_SET ns_noc_io_spio_soc_ip.csr 107635 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTRL_3_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 107646 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btperr bridge_spio_sp_main0_main_noc_rbm_s_12_6_btperr SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 107849 spio_sp_main0_main_noc_rbm_s register btperr 0x330A8 R/W 0x00000000 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L0_SET ns_noc_io_spio_soc_ip.csr 107672 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L1_SET ns_noc_io_spio_soc_ip.csr 107683 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L2_SET ns_noc_io_spio_soc_ip.csr 107694 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L3_SET ns_noc_io_spio_soc_ip.csr 107705 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L4_SET ns_noc_io_spio_soc_ip.csr 107716 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L5_SET ns_noc_io_spio_soc_ip.csr 107727 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L6_SET ns_noc_io_spio_soc_ip.csr 107738 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L7_SET ns_noc_io_spio_soc_ip.csr 107749 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L8_SET ns_noc_io_spio_soc_ip.csr 107760 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L9_SET ns_noc_io_spio_soc_ip.csr 107771 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L10_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L10_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L10_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L10_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L10_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L10_SET ns_noc_io_spio_soc_ip.csr 107782 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L11_SET ns_noc_io_spio_soc_ip.csr 107793 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L12_SET ns_noc_io_spio_soc_ip.csr 107804 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L13_SET ns_noc_io_spio_soc_ip.csr 107815 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L14_SET ns_noc_io_spio_soc_ip.csr 107826 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_L15_SET ns_noc_io_spio_soc_ip.csr 107837 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_UNSD_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERR_UNSD_SET ns_noc_io_spio_soc_ip.csr 107848 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_btperrm bridge_spio_sp_main0_main_noc_rbm_s_12_6_btperrm SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 108049 spio_sp_main0_main_noc_rbm_s register btperrm 0x330B0 R/W 0x00000000 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L0_SET ns_noc_io_spio_soc_ip.csr 107872 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L1_SET ns_noc_io_spio_soc_ip.csr 107883 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L2_SET ns_noc_io_spio_soc_ip.csr 107894 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L3_SET ns_noc_io_spio_soc_ip.csr 107905 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L4_SET ns_noc_io_spio_soc_ip.csr 107916 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L5_SET ns_noc_io_spio_soc_ip.csr 107927 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L6_SET ns_noc_io_spio_soc_ip.csr 107938 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L7_SET ns_noc_io_spio_soc_ip.csr 107949 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L8_SET ns_noc_io_spio_soc_ip.csr 107960 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L9_SET ns_noc_io_spio_soc_ip.csr 107971 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L10_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L10_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L10_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L10_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L10_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L10_SET ns_noc_io_spio_soc_ip.csr 107982 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L11_SET ns_noc_io_spio_soc_ip.csr 107993 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L12_SET ns_noc_io_spio_soc_ip.csr 108004 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L13_SET ns_noc_io_spio_soc_ip.csr 108015 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L14_SET ns_noc_io_spio_soc_ip.csr 108026 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_L15_SET ns_noc_io_spio_soc_ip.csr 108037 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_UNSD_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BTPERRM_UNSD_SET ns_noc_io_spio_soc_ip.csr 108048 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_rxe bridge_spio_sp_main0_main_noc_rbm_s_12_6_rxe SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 108157 spio_sp_main0_main_noc_rbm_s register rxe 0x33120 R/W 0x00000000 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_A_SET ns_noc_io_spio_soc_ip.csr 108077 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_B_SET ns_noc_io_spio_soc_ip.csr 108088 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_C_SET ns_noc_io_spio_soc_ip.csr 108099 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_CRC_OFLW_D_SET ns_noc_io_spio_soc_ip.csr 108110 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_EVC_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_EVC_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_EVC_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_EVC_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_EVC_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_EVC_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_EVC_OFLW_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_EVC_OFLW_SET ns_noc_io_spio_soc_ip.csr 108122 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 108133 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_EVC1_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_EVC1_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_EVC1_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_EVC1_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_EVC1_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_EVC1_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_EVC1_OFLW_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_EVC1_OFLW_SET ns_noc_io_spio_soc_ip.csr 108145 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXE_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 108156 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_rxem bridge_spio_sp_main0_main_noc_rbm_s_12_6_rxem SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 108229 spio_sp_main0_main_noc_rbm_s register rxem 0x33128 R/W 0x00000050 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_UNSD_3_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_UNSD_3_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_UNSD_3_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_UNSD_3_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_UNSD_3_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_UNSD_3_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_UNSD_3_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_UNSD_3_0_SET ns_noc_io_spio_soc_ip.csr 108178 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_EVC_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_EVC_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_EVC_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_EVC_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_EVC_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_EVC_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_EVC_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_EVC_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 108192 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 108203 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_EVC1_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_EVC1_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_EVC1_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_EVC1_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_EVC1_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_EVC1_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_EVC1_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 108217 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_RXEM_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 108228 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_brs_0 bridge_spio_sp_main0_main_noc_rbm_s_12_6_brs_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 108503 spio_sp_main0_main_noc_rbm_s register brs_0 0x33130 R 0x00000000 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 108253 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_0_SET ns_noc_io_spio_soc_ip.csr 108264 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_0_SET ns_noc_io_spio_soc_ip.csr 108275 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_0_SET ns_noc_io_spio_soc_ip.csr 108286 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_0_SET ns_noc_io_spio_soc_ip.csr 108297 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 108307 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 108318 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_1_SET ns_noc_io_spio_soc_ip.csr 108329 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_1_SET ns_noc_io_spio_soc_ip.csr 108340 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_1_SET ns_noc_io_spio_soc_ip.csr 108351 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_1_SET ns_noc_io_spio_soc_ip.csr 108362 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 108372 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 108383 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_2_SET ns_noc_io_spio_soc_ip.csr 108394 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_2_SET ns_noc_io_spio_soc_ip.csr 108405 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_2_SET ns_noc_io_spio_soc_ip.csr 108416 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_2_SET ns_noc_io_spio_soc_ip.csr 108427 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 108437 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 108448 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_V_3_SET ns_noc_io_spio_soc_ip.csr 108459 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_S_3_SET ns_noc_io_spio_soc_ip.csr 108470 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_B_3_SET ns_noc_io_spio_soc_ip.csr 108481 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_F_3_SET ns_noc_io_spio_soc_ip.csr 108492 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_0_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 108502 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_brs_1 bridge_spio_sp_main0_main_noc_rbm_s_12_6_brs_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 108777 spio_sp_main0_main_noc_rbm_s register brs_1 0x33138 R 0x00000000 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 108527 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_0_SET ns_noc_io_spio_soc_ip.csr 108538 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_0_SET ns_noc_io_spio_soc_ip.csr 108549 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_0_SET ns_noc_io_spio_soc_ip.csr 108560 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_0_SET ns_noc_io_spio_soc_ip.csr 108571 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 108581 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 108592 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_1_SET ns_noc_io_spio_soc_ip.csr 108603 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_1_SET ns_noc_io_spio_soc_ip.csr 108614 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_1_SET ns_noc_io_spio_soc_ip.csr 108625 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_1_SET ns_noc_io_spio_soc_ip.csr 108636 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 108646 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 108657 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_2_SET ns_noc_io_spio_soc_ip.csr 108668 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_2_SET ns_noc_io_spio_soc_ip.csr 108679 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_2_SET ns_noc_io_spio_soc_ip.csr 108690 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_2_SET ns_noc_io_spio_soc_ip.csr 108701 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 108711 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 108722 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_V_3_SET ns_noc_io_spio_soc_ip.csr 108733 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_S_3_SET ns_noc_io_spio_soc_ip.csr 108744 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_B_3_SET ns_noc_io_spio_soc_ip.csr 108755 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_F_3_SET ns_noc_io_spio_soc_ip.csr 108766 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRS_1_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 108776 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_brus bridge_spio_sp_main0_main_noc_rbm_s_12_6_brus SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 108846 spio_sp_main0_main_noc_rbm_s register brus 0x331B0 R 0x00000000 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_A_SET ns_noc_io_spio_soc_ip.csr 108802 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_B_SET ns_noc_io_spio_soc_ip.csr 108813 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_C_SET ns_noc_io_spio_soc_ip.csr 108824 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_V_D_SET ns_noc_io_spio_soc_ip.csr 108835 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_UNSD_31_4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_UNSD_31_4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_UNSD_31_4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_UNSD_31_4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_UNSD_31_4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_UNSD_31_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_UNSD_31_4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRUS_UNSD_31_4_SET ns_noc_io_spio_soc_ip.csr 108845 UNSD_31_4 31 4 0x0000000 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_brperr0 bridge_spio_sp_main0_main_noc_rbm_s_12_6_brperr0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 109074 spio_sp_main0_main_noc_rbm_s register brperr0 0x331D0 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_D0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_D0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_D0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_D0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_D0_SET ns_noc_io_spio_soc_ip.csr 108884 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_DC0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_DC0_SET ns_noc_io_spio_soc_ip.csr 108895 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SB0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SB0_SET ns_noc_io_spio_soc_ip.csr 108906 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SBC0_SET ns_noc_io_spio_soc_ip.csr 108918 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_PK0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_PK0_SET ns_noc_io_spio_soc_ip.csr 108929 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 108940 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_D1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_D1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_D1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_D1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_D1_SET ns_noc_io_spio_soc_ip.csr 108951 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_DC1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_DC1_SET ns_noc_io_spio_soc_ip.csr 108962 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SB1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SB1_SET ns_noc_io_spio_soc_ip.csr 108973 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_SBC1_SET ns_noc_io_spio_soc_ip.csr 108985 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_PK1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_PK1_SET ns_noc_io_spio_soc_ip.csr 108996 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 109007 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 109018 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 109029 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 109040 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 109051 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 109062 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 109073 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_brperr1 bridge_spio_sp_main0_main_noc_rbm_s_12_6_brperr1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 109190 spio_sp_main0_main_noc_rbm_s register brperr1 0x331D8 R 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 109112 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 109123 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 109134 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 109145 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 109156 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 109167 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 109178 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERR1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 109189 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_brperrm0 bridge_spio_sp_main0_main_noc_rbm_s_12_6_brperrm0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 109411 spio_sp_main0_main_noc_rbm_s register brperrm0 0x331E0 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_D0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_D0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_D0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_D0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_D0_SET ns_noc_io_spio_soc_ip.csr 109217 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_DC0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_DC0_SET ns_noc_io_spio_soc_ip.csr 109229 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SB0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SB0_SET ns_noc_io_spio_soc_ip.csr 109240 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SBC0_SET ns_noc_io_spio_soc_ip.csr 109252 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_PK0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_PK0_SET ns_noc_io_spio_soc_ip.csr 109264 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 109275 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_D1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_D1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_D1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_D1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_D1_SET ns_noc_io_spio_soc_ip.csr 109286 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_DC1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_DC1_SET ns_noc_io_spio_soc_ip.csr 109298 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SB1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SB1_SET ns_noc_io_spio_soc_ip.csr 109309 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_SBC1_SET ns_noc_io_spio_soc_ip.csr 109321 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_PK1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_PK1_SET ns_noc_io_spio_soc_ip.csr 109333 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 109344 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 109355 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 109366 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 109377 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 109388 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 109399 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 109410 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_sp_main0_main_noc_rbm_s_12_6_brperrm1 bridge_spio_sp_main0_main_noc_rbm_s_12_6_brperrm1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 109516 spio_sp_main0_main_noc_rbm_s register brperrm1 0x331E8 R 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_main_noc_rbm_s_12_6_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 109438 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 109449 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 109460 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 109471 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 109482 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 109493 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 109504 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_12_6_BRPERRM1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 109515 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_cgc bridge_spio_sp_main0_pu_rbm_s_13_7_as_cgc SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGC_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGC_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGC_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 109553 spio_sp_main0_pu_rbm_s register as_cgc 0x35C10 R/W 0x0000000000000064 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_as_cgc Programmable intervals used by coarse clock gating logic. This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGC_HYSTERESIS_COUNTER_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGC_HYSTERESIS_COUNTER_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGC_HYSTERESIS_COUNTER_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGC_HYSTERESIS_COUNTER_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGC_HYSTERESIS_COUNTER_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGC_HYSTERESIS_COUNTER_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGC_HYSTERESIS_COUNTER_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_spio_soc_ip.csr 109541 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGC_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGC_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGC_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGC_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGC_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGC_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGC_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGC_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 109552 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_cgo bridge_spio_sp_main0_pu_rbm_s_13_7_as_cgo SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGO_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGO_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGO_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGO_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 109588 spio_sp_main0_pu_rbm_s register as_cgo 0x35C18 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_as_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the slave bridge. false false false false FPO SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGO_FPO_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGO_FPO_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGO_FPO_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGO_FPO_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGO_FPO_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGO_FPO_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGO_FPO_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGO_FPO_SET ns_noc_io_spio_soc_ip.csr 109576 FPO 1'b1: Clock gating override enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGO_UNSD_63_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGO_UNSD_63_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGO_UNSD_63_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGO_UNSD_63_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGO_UNSD_63_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGO_UNSD_63_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGO_UNSD_63_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CGO_UNSD_63_1_SET ns_noc_io_spio_soc_ip.csr 109587 UNSD_63_1 63 1 0x0000000000000000 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_sts bridge_spio_sp_main0_pu_rbm_s_13_7_as_sts SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 109662 spio_sp_main0_pu_rbm_s register as_sts 0x35D00 R 0x000000000000000c Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_as_sts Slave bridge status bits. false false false false WOF SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_WOF_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_WOF_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_WOF_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_WOF_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_WOF_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_WOF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_WOF_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_WOF_SET ns_noc_io_spio_soc_ip.csr 109611 WOF 1'b1: Maximum number of supported write commands are outstanding to the attached slave device awaiting response, no more write commands will be issued to slave till responses are received. 1'b0: Slave device can expect more write commands from NoC 0 0 0x0 R ROF SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_ROF_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_ROF_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_ROF_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_ROF_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_ROF_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_ROF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_ROF_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_ROF_SET ns_noc_io_spio_soc_ip.csr 109627 ROF 1'b1: Maximum number of supported read commands are outstanding to the attached slave device awaiting response, no more read commands will be issued to slave till responses are received. 1'b0: Slave bridge can accept more read commands from the NoC 1 1 0x0 R WOE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_WOE_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_WOE_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_WOE_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_WOE_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_WOE_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_WOE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_WOE_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_WOE_SET ns_noc_io_spio_soc_ip.csr 109639 WOE 1'b1: There are no write commands outstanding to the attached slave device 2 2 0x1 R ROE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_ROE_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_ROE_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_ROE_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_ROE_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_ROE_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_ROE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_ROE_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_ROE_SET ns_noc_io_spio_soc_ip.csr 109651 ROE 1'b1: There are no read commands outstanding to the attached slave device 3 3 0x1 R UNSD_63_4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_UNSD_63_4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_UNSD_63_4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_UNSD_63_4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_UNSD_63_4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_UNSD_63_4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_UNSD_63_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_UNSD_63_4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_STS_UNSD_63_4_SET ns_noc_io_spio_soc_ip.csr 109661 UNSD_63_4 63 4 0x000000000000000 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_bridge_id bridge_spio_sp_main0_pu_rbm_s_13_7_as_bridge_id SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_BRIDGE_ID_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_BRIDGE_ID_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_BRIDGE_ID_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_BRIDGE_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 109692 spio_sp_main0_pu_rbm_s register as_bridge_id 0x35D08 R 0x000000000000000d Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_as_bridge_id Unique identifier assigned to the slave bridge. false false false false ID SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_BRIDGE_ID_ID_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_BRIDGE_ID_ID_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_BRIDGE_ID_ID_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_BRIDGE_ID_ID_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_BRIDGE_ID_ID_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_BRIDGE_ID_ID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_BRIDGE_ID_ID_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_BRIDGE_ID_ID_SET ns_noc_io_spio_soc_ip.csr 109681 ID Unique bridge ID 15 0 0x000d R UNSD_63_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_BRIDGE_ID_UNSD_63_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_BRIDGE_ID_UNSD_63_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_BRIDGE_ID_UNSD_63_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_BRIDGE_ID_UNSD_63_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_BRIDGE_ID_UNSD_63_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_BRIDGE_ID_UNSD_63_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_BRIDGE_ID_UNSD_63_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_spio_soc_ip.csr 109691 UNSD_63_16 63 16 0x000000000000 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_err bridge_spio_sp_main0_pu_rbm_s_13_7_as_err SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 110045 spio_sp_main0_pu_rbm_s register as_err 0x35E00 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_as_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E0_SET ns_noc_io_spio_soc_ip.csr 109713 E0 1'b1: Read decode error response: Decode error response received from slave device for read command 0 0 0x0 R/W E1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E1_SET ns_noc_io_spio_soc_ip.csr 109725 E1 1'b1: Read slave error response: Slave error response received from slave device for read command 1 1 0x0 R/W E2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E2_SET ns_noc_io_spio_soc_ip.csr 109738 E2 1'b1: [FATAL] Unknown read response destination: RID from read response produces a destination which is not present in the routing table 2 2 0x0 R/W E3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E3_SET ns_noc_io_spio_soc_ip.csr 109752 E3 1'b1: [FATAL] Interleaved read response: Interleaved read response. This can occur if interleaved read response is received from a slave device for which a de-interleaver was not specified 3 3 0x0 R/W E4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E4_SET ns_noc_io_spio_soc_ip.csr 109764 E4 1'b1: Read command modified: A read command which was marked as non-modifiable was modified by the slave bridge 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_UNSD_15_5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_UNSD_15_5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_UNSD_15_5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_UNSD_15_5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_UNSD_15_5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_UNSD_15_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_UNSD_15_5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 109775 UNSD_15_5 15 5 0x000 R E16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E16_SET ns_noc_io_spio_soc_ip.csr 109787 E16 1'b1: Write decode error response: Decode error response received from slave device for write command 16 16 0x0 R/W E17 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E17_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E17_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E17_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E17_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E17_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E17_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E17_SET ns_noc_io_spio_soc_ip.csr 109799 E17 1'b1: Write slave error response: Slave error response received from slave device for write command 17 17 0x0 R/W E18 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E18_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E18_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E18_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E18_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E18_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E18_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E18_SET ns_noc_io_spio_soc_ip.csr 109812 E18 1'b1: [FATAL] Unknown write response destination: BID from write response produces a destination which is not present in the routing table 18 18 0x0 R/W E19 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E19_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E19_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E19_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E19_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E19_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E19_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E19_SET ns_noc_io_spio_soc_ip.csr 109824 E19 1'b1: Write command modified: A write command which was marked as non-modifiable was modified by the slave bridge 19 19 0x0 R/W UNSD_31_20 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_UNSD_31_20_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_UNSD_31_20_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_UNSD_31_20_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_UNSD_31_20_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_UNSD_31_20_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_UNSD_31_20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_UNSD_31_20_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_UNSD_31_20_SET ns_noc_io_spio_soc_ip.csr 109835 UNSD_31_20 31 20 0x000 R E32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E32_SET ns_noc_io_spio_soc_ip.csr 109847 E32 1'b1: [FATAL] Traffic sent to a noc layer which is power gated 32 32 0x0 R/W E33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E33_SET ns_noc_io_spio_soc_ip.csr 109858 E33 1'b1: [FATAL] Parity error in config/status registers 33 33 0x0 R/W E34 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E34_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E34_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E34_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E34_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E34_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E34_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E34_SET ns_noc_io_spio_soc_ip.csr 109869 E34 1'b1: [FATAL] RDATA Parity error 34 34 0x0 R/W E35 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E35_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E35_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E35_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E35_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E35_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E35_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E35_SET ns_noc_io_spio_soc_ip.csr 109880 E35 1'b1: [FATAL] RRESP Parity error 35 35 0x0 R/W E36 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E36_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E36_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E36_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E36_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E36_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E36_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E36_SET ns_noc_io_spio_soc_ip.csr 109891 E36 1'b1: [FATAL] BRESP Parity error 36 36 0x0 R/W E37 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E37_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E37_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E37_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E37_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E37_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E37_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E37_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E37_SET ns_noc_io_spio_soc_ip.csr 109902 E37 1'b1: [FATAL] AC Parity error 37 37 0x0 R/W E38 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E38_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E38_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E38_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E38_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E38_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E38_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E38_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E38_SET ns_noc_io_spio_soc_ip.csr 109913 E38 1'b1: [FATAL] ACADDR Parity error 38 38 0x0 R/W E39 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E39_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E39_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E39_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E39_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E39_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E39_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E39_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E39_SET ns_noc_io_spio_soc_ip.csr 109925 E39 1'b1: [FATAL] R Ch Cmdtbl Parity Err 39 39 0x0 R E40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E40_SET ns_noc_io_spio_soc_ip.csr 109937 E40 1'b1: [FATAL] B Ch Cmdtbl Parity Err 40 40 0x0 R E41 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E41_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E41_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E41_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E41_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E41_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E41_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E41_SET ns_noc_io_spio_soc_ip.csr 109949 E41 1'b1: [FATAL] Rx Fifo Parity Err 41 41 0x0 R E42 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E42_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E42_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E42_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E42_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E42_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E42_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E42_SET ns_noc_io_spio_soc_ip.csr 109961 E42 1'b1: [FATAL] CRCD Ch Reorder Buffer Parity Err 42 42 0x0 R E43 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E43_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E43_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E43_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E43_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E43_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E43_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E43_SET ns_noc_io_spio_soc_ip.csr 109973 E43 1'b1: [FATAL] Ack Ch Wack Reorder Buffer Parity Err 43 43 0x0 R E44 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E44_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E44_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E44_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E44_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E44_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E44_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E44_SET ns_noc_io_spio_soc_ip.csr 109985 E44 1'b1: [FATAL] Ack Ch Rack Reorder Buffer Parity Err 44 44 0x0 R E45 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E45_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E45_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E45_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E45_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E45_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E45_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E45_SET ns_noc_io_spio_soc_ip.csr 109997 E45 1'b1: [FATAL] B Ch Drain Fifo Parity Err 45 45 0x0 R E46 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E46_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E46_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E46_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E46_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E46_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E46_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E46_SET ns_noc_io_spio_soc_ip.csr 110009 E46 1'b1: [FATAL] R Ch Flush Fifo Parity Err 46 46 0x0 R E47 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E47_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E47_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E47_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E47_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E47_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E47_SET ns_noc_io_spio_soc_ip.csr 110021 E47 1'b1: [FATAL] R Ch Deinterleaver Cmdtbl Parity Err 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_E48_SET ns_noc_io_spio_soc_ip.csr 110033 E48 1'b1: [FATAL] R Ch Deinterleaver Data Buffer Parity Err 48 48 0x0 R UNSD_63_49 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_UNSD_63_49_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_UNSD_63_49_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_UNSD_63_49_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_UNSD_63_49_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_UNSD_63_49_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_UNSD_63_49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_UNSD_63_49_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_ERR_UNSD_63_49_SET ns_noc_io_spio_soc_ip.csr 110044 UNSD_63_49 63 49 0x0000 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_intm bridge_spio_sp_main0_pu_rbm_s_13_7_as_intm SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 110385 spio_sp_main0_pu_rbm_s register as_intm 0x35E40 R/W 0x0000007d000b0013 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_as_intm Interrupt mask register.Individual bit positions match the error bit positions in AS_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M0_SET ns_noc_io_spio_soc_ip.csr 110066 M0 Mask interrupts for read channel 0 0 0x1 R/W M1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M1_SET ns_noc_io_spio_soc_ip.csr 110077 M1 Mask interrupts for read channel 1 1 0x1 R/W M2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M2_SET ns_noc_io_spio_soc_ip.csr 110088 M2 Mask interrupts for read channel 2 2 0x0 R/W M3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M3_SET ns_noc_io_spio_soc_ip.csr 110099 M3 Mask interrupts for read channel 3 3 0x0 R/W M4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M4_SET ns_noc_io_spio_soc_ip.csr 110110 M4 Mask interrupts for read channel 4 4 0x1 R/W UNSD_15_5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_UNSD_15_5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_UNSD_15_5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_UNSD_15_5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_UNSD_15_5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_UNSD_15_5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_UNSD_15_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_UNSD_15_5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 110121 UNSD_15_5 15 5 0x000 R M16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M16_SET ns_noc_io_spio_soc_ip.csr 110132 M16 Mask interrupts for write channel 16 16 0x1 R/W M17 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M17_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M17_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M17_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M17_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M17_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M17_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M17_SET ns_noc_io_spio_soc_ip.csr 110143 M17 Mask interrupts for write channel 17 17 0x1 R/W M18 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M18_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M18_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M18_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M18_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M18_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M18_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M18_SET ns_noc_io_spio_soc_ip.csr 110154 M18 Mask interrupts for write channel 18 18 0x0 R/W M19 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M19_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M19_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M19_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M19_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M19_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M19_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M19_SET ns_noc_io_spio_soc_ip.csr 110165 M19 Mask interrupts for write channel 19 19 0x1 R/W UNSD_31_20 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_UNSD_31_20_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_UNSD_31_20_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_UNSD_31_20_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_UNSD_31_20_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_UNSD_31_20_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_UNSD_31_20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_UNSD_31_20_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_UNSD_31_20_SET ns_noc_io_spio_soc_ip.csr 110176 UNSD_31_20 31 20 0x000 R M32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M32_SET ns_noc_io_spio_soc_ip.csr 110187 M32 Mask interrupt on traffic to PG layer 32 32 0x1 R/W M33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M33_SET ns_noc_io_spio_soc_ip.csr 110198 M33 Mask interrupt on csr parity errors 33 33 0x0 R/W M34 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M34_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M34_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M34_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M34_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M34_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M34_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M34_SET ns_noc_io_spio_soc_ip.csr 110209 M34 RDATA parity interrupt Mask 34 34 0x1 R/W M35 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M35_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M35_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M35_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M35_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M35_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M35_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M35_SET ns_noc_io_spio_soc_ip.csr 110220 M35 RRESP parity interrupt Mask 35 35 0x1 R/W M36 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M36_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M36_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M36_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M36_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M36_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M36_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M36_SET ns_noc_io_spio_soc_ip.csr 110231 M36 BRESP parity interrupt Mask 36 36 0x1 R/W M37 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M37_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M37_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M37_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M37_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M37_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M37_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M37_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M37_SET ns_noc_io_spio_soc_ip.csr 110242 M37 AC parity interrupt Mask 37 37 0x1 R/W M38 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M38_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M38_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M38_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M38_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M38_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M38_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M38_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_M38_SET ns_noc_io_spio_soc_ip.csr 110253 M38 ACADDR parity interrupt Mask 38 38 0x1 R/W E39 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E39_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E39_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E39_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E39_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E39_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E39_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E39_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E39_SET ns_noc_io_spio_soc_ip.csr 110265 E39 1'b1: R Ch Cmdtbl Parity Err Intr Mask 39 39 0x0 R E40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E40_SET ns_noc_io_spio_soc_ip.csr 110277 E40 1'b1: B Ch Cmdtbl Parity Err Intr Mask 40 40 0x0 R E41 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E41_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E41_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E41_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E41_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E41_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E41_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E41_SET ns_noc_io_spio_soc_ip.csr 110289 E41 1'b1: Rx Fifo Parity Err Intr Mask 41 41 0x0 R E42 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E42_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E42_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E42_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E42_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E42_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E42_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E42_SET ns_noc_io_spio_soc_ip.csr 110301 E42 1'b1: CRCD Ch Reorder Buffer Parity Err Intr Mask 42 42 0x0 R E43 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E43_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E43_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E43_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E43_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E43_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E43_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E43_SET ns_noc_io_spio_soc_ip.csr 110313 E43 1'b1: Ack Ch Wack Reorder Buffer Parity Err IntrMask 43 43 0x0 R E44 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E44_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E44_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E44_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E44_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E44_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E44_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E44_SET ns_noc_io_spio_soc_ip.csr 110325 E44 1'b1: Ack Ch Rack Reorder Buffer Parity Err Intr Mask 44 44 0x0 R E45 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E45_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E45_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E45_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E45_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E45_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E45_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E45_SET ns_noc_io_spio_soc_ip.csr 110337 E45 1'b1: B Ch Drain Fifo Parity Err Intr Mask 45 45 0x0 R E46 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E46_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E46_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E46_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E46_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E46_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E46_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E46_SET ns_noc_io_spio_soc_ip.csr 110349 E46 1'b1: R Ch Flush Fifo Parity Err Intr Mask 46 46 0x0 R E47 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E47_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E47_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E47_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E47_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E47_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E47_SET ns_noc_io_spio_soc_ip.csr 110361 E47 1'b1: R Ch Deinterleaver Cmdtbl Parity Err Intr Mask 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_E48_SET ns_noc_io_spio_soc_ip.csr 110373 E48 1'b1: R Ch Deinterleaver Data Buffer Parity Err Intr Mask 48 48 0x0 R UNSD_63_49 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_UNSD_63_49_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_UNSD_63_49_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_UNSD_63_49_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_UNSD_63_49_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_UNSD_63_49_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_UNSD_63_49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_UNSD_63_49_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_INTM_UNSD_63_49_SET ns_noc_io_spio_soc_ip.csr 110384 UNSD_63_49 63 49 0x0000 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_ccmd bridge_spio_sp_main0_pu_rbm_s_13_7_as_ccmd SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 110460 spio_sp_main0_pu_rbm_s register as_ccmd 0x35F00 R/W 0x0000000003000000 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_as_ccmd Not applicable for current release. false false false false UNSD_23_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_UNSD_23_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_UNSD_23_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_UNSD_23_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_UNSD_23_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_UNSD_23_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_UNSD_23_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_UNSD_23_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_UNSD_23_0_SET ns_noc_io_spio_soc_ip.csr 110403 UNSD_23_0 23 0 0x000000 R rdy SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_RDY_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_RDY_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_RDY_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_RDY_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_RDY_SET ns_noc_io_spio_soc_ip.csr 110414 rdy 1'b1: Ready 24 24 0x1 R/W val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_VAL_SET ns_noc_io_spio_soc_ip.csr 110425 val 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_UNSD_27_26_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_UNSD_27_26_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_UNSD_27_26_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_UNSD_27_26_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_UNSD_27_26_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_UNSD_27_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_UNSD_27_26_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_UNSD_27_26_SET ns_noc_io_spio_soc_ip.csr 110436 UNSD_27_26 27 26 0x0 R intfid SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_INTFID_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_INTFID_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_INTFID_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_INTFID_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_INTFID_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_INTFID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_INTFID_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_INTFID_SET ns_noc_io_spio_soc_ip.csr 110448 intfid 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_63_31 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_UNSD_63_31_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_UNSD_63_31_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_UNSD_63_31_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_UNSD_63_31_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_UNSD_63_31_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_UNSD_63_31_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_UNSD_63_31_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMD_UNSD_63_31_SET ns_noc_io_spio_soc_ip.csr 110459 UNSD_63_31 63 31 0x000000000 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_ccmdmsk bridge_spio_sp_main0_pu_rbm_s_13_7_as_ccmdmsk SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 110512 spio_sp_main0_pu_rbm_s register as_ccmdmsk 0x35F08 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_as_ccmdmsk Not applicable for current release. false false false false UNSD_23_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_UNSD_23_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_UNSD_23_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_UNSD_23_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_UNSD_23_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_UNSD_23_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_UNSD_23_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_UNSD_23_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_UNSD_23_0_SET ns_noc_io_spio_soc_ip.csr 110478 UNSD_23_0 23 0 0x000000 R rdy SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_RDY_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_RDY_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_RDY_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_RDY_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_RDY_SET ns_noc_io_spio_soc_ip.csr 110489 rdy 1'b1: Ready 24 24 0x0 R/W val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_VAL_SET ns_noc_io_spio_soc_ip.csr 110500 val 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_UNSD_63_26_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_UNSD_63_26_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_UNSD_63_26_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_UNSD_63_26_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_UNSD_63_26_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_UNSD_63_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_UNSD_63_26_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CCMDMSK_UNSD_63_26_SET ns_noc_io_spio_soc_ip.csr 110511 UNSD_63_26 63 26 0x0000000000 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_cntr bridge_spio_sp_main0_pu_rbm_s_13_7_as_cntr SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CNTR_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CNTR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CNTR_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CNTR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 110542 spio_sp_main0_pu_rbm_s register as_cntr 0x35F10 R 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_as_cntr Not applicable for current release. false false false false CNTR SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CNTR_CNTR_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CNTR_CNTR_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CNTR_CNTR_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CNTR_CNTR_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CNTR_CNTR_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CNTR_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CNTR_CNTR_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CNTR_CNTR_SET ns_noc_io_spio_soc_ip.csr 110531 CNTR Counter 31 0 0x00000000 R UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CNTR_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CNTR_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CNTR_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CNTR_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CNTR_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CNTR_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CNTR_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_CNTR_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 110541 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_arovrd bridge_spio_sp_main0_pu_rbm_s_13_7_as_arovrd SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 110655 spio_sp_main0_pu_rbm_s register as_arovrd 0x35F18 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_as_arovrd AR Overrides. false false false false arcache_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 110560 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 110573 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 110584 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 110595 UNSD_11_11 11 11 0x0 R arprot_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 110608 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 110619 UNSD_15_15 15 15 0x0 R arqos_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 110630 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_ARQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 110643 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AROVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 110654 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_as_awovrd bridge_spio_sp_main0_pu_rbm_s_13_7_as_awovrd SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 110768 spio_sp_main0_pu_rbm_s register as_awovrd 0x35F20 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_as_awovrd AW Overrides. false false false false awcache_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 110673 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 110686 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 110697 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 110708 UNSD_11_11 11 11 0x0 R awprot_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 110721 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 110732 UNSD_15_15 15 15 0x0 R awqos_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 110743 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_AWQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 110756 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_AS_AWOVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 110767 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_p_0 bridge_spio_sp_main0_pu_rbm_s_13_7_p_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 110833 spio_sp_main0_pu_rbm_s register p_0 0x37000 R/W 0x00000003 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_0_SET ns_noc_io_spio_soc_ip.csr 110796 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_1_SET ns_noc_io_spio_soc_ip.csr 110808 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_2_SET ns_noc_io_spio_soc_ip.csr 110820 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_0_WT_QOS_3_SET ns_noc_io_spio_soc_ip.csr 110832 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_p_1 bridge_spio_sp_main0_pu_rbm_s_13_7_p_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 110899 spio_sp_main0_pu_rbm_s register p_1 0x37008 R 0x00000000 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_4_SET ns_noc_io_spio_soc_ip.csr 110862 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_5_SET ns_noc_io_spio_soc_ip.csr 110874 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_6_SET ns_noc_io_spio_soc_ip.csr 110886 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_1_WT_QOS_7_SET ns_noc_io_spio_soc_ip.csr 110898 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_p_2 bridge_spio_sp_main0_pu_rbm_s_13_7_p_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 110965 spio_sp_main0_pu_rbm_s register p_2 0x37010 R 0x00000000 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_8_SET ns_noc_io_spio_soc_ip.csr 110928 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_9_SET ns_noc_io_spio_soc_ip.csr 110940 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_10_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_10_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_10_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_10_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_10_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_10_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_10_SET ns_noc_io_spio_soc_ip.csr 110952 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_2_WT_QOS_11_SET ns_noc_io_spio_soc_ip.csr 110964 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_p_3 bridge_spio_sp_main0_pu_rbm_s_13_7_p_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 111031 spio_sp_main0_pu_rbm_s register p_3 0x37018 R 0x00000000 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_12_SET ns_noc_io_spio_soc_ip.csr 110994 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_13_SET ns_noc_io_spio_soc_ip.csr 111006 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_14_SET ns_noc_io_spio_soc_ip.csr 111018 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_P_3_WT_QOS_15_SET ns_noc_io_spio_soc_ip.csr 111030 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_txe bridge_spio_sp_main0_pu_rbm_s_13_7_txe SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 111177 spio_sp_main0_pu_rbm_s register txe 0x37040 R/W 0x00000000 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_TRANS_WITHOUT_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_TRANS_WITHOUT_SOP_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_TRANS_WITHOUT_SOP_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_TRANS_WITHOUT_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_TRANS_WITHOUT_SOP_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_TRANS_WITHOUT_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_TRANS_WITHOUT_SOP_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_spio_soc_ip.csr 111058 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_SOP_AFTER_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_SOP_AFTER_SOP_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_SOP_AFTER_SOP_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_SOP_AFTER_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_SOP_AFTER_SOP_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_SOP_AFTER_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_SOP_AFTER_SOP_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_SOP_AFTER_SOP_SET ns_noc_io_spio_soc_ip.csr 111070 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 111085 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 111098 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_spio_soc_ip.csr 111112 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_spio_soc_ip.csr 111126 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_spio_soc_ip.csr 111140 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_spio_soc_ip.csr 111154 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 111165 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXE_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 111176 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_txem bridge_spio_sp_main0_pu_rbm_s_13_7_txem SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 111256 spio_sp_main0_pu_rbm_s register txem 0x37048 R/W 0x00000008 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_UNSD_1_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_UNSD_1_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_UNSD_1_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_UNSD_1_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_UNSD_1_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_UNSD_1_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_UNSD_1_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_UNSD_1_0_SET ns_noc_io_spio_soc_ip.csr 111200 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 111211 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 111222 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_UNSD_7_4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_UNSD_7_4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_UNSD_7_4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_UNSD_7_4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_UNSD_7_4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_UNSD_7_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_UNSD_7_4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_UNSD_7_4_SET ns_noc_io_spio_soc_ip.csr 111233 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 111244 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_TXEM_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 111255 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btus_0 bridge_spio_sp_main0_pu_rbm_s_13_7_btus_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 111624 spio_sp_main0_pu_rbm_s register btus_0 0x37058 R 0x00000000 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_A_SET ns_noc_io_spio_soc_ip.csr 111282 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_B_SET ns_noc_io_spio_soc_ip.csr 111293 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_C_SET ns_noc_io_spio_soc_ip.csr 111304 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L0_D_SET ns_noc_io_spio_soc_ip.csr 111315 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_A_SET ns_noc_io_spio_soc_ip.csr 111326 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_B_SET ns_noc_io_spio_soc_ip.csr 111337 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_C_SET ns_noc_io_spio_soc_ip.csr 111348 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L1_D_SET ns_noc_io_spio_soc_ip.csr 111359 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_A_SET ns_noc_io_spio_soc_ip.csr 111370 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_B_SET ns_noc_io_spio_soc_ip.csr 111381 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_C_SET ns_noc_io_spio_soc_ip.csr 111392 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L2_D_SET ns_noc_io_spio_soc_ip.csr 111403 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_A_SET ns_noc_io_spio_soc_ip.csr 111414 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_B_SET ns_noc_io_spio_soc_ip.csr 111425 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_C_SET ns_noc_io_spio_soc_ip.csr 111436 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L3_D_SET ns_noc_io_spio_soc_ip.csr 111447 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_A_SET ns_noc_io_spio_soc_ip.csr 111458 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_B_SET ns_noc_io_spio_soc_ip.csr 111469 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_C_SET ns_noc_io_spio_soc_ip.csr 111480 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L4_D_SET ns_noc_io_spio_soc_ip.csr 111491 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_A_SET ns_noc_io_spio_soc_ip.csr 111502 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_B_SET ns_noc_io_spio_soc_ip.csr 111513 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_C_SET ns_noc_io_spio_soc_ip.csr 111524 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L5_D_SET ns_noc_io_spio_soc_ip.csr 111535 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_A_SET ns_noc_io_spio_soc_ip.csr 111546 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_B_SET ns_noc_io_spio_soc_ip.csr 111557 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_C_SET ns_noc_io_spio_soc_ip.csr 111568 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L6_D_SET ns_noc_io_spio_soc_ip.csr 111579 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_A_SET ns_noc_io_spio_soc_ip.csr 111590 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_B_SET ns_noc_io_spio_soc_ip.csr 111601 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_C_SET ns_noc_io_spio_soc_ip.csr 111612 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_0_L7_D_SET ns_noc_io_spio_soc_ip.csr 111623 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btus_1 bridge_spio_sp_main0_pu_rbm_s_13_7_btus_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 111992 spio_sp_main0_pu_rbm_s register btus_1 0x37060 R 0x00000000 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_A_SET ns_noc_io_spio_soc_ip.csr 111650 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_B_SET ns_noc_io_spio_soc_ip.csr 111661 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_C_SET ns_noc_io_spio_soc_ip.csr 111672 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L8_D_SET ns_noc_io_spio_soc_ip.csr 111683 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_A_SET ns_noc_io_spio_soc_ip.csr 111694 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_B_SET ns_noc_io_spio_soc_ip.csr 111705 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_C_SET ns_noc_io_spio_soc_ip.csr 111716 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L9_D_SET ns_noc_io_spio_soc_ip.csr 111727 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_A_SET ns_noc_io_spio_soc_ip.csr 111738 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_B_SET ns_noc_io_spio_soc_ip.csr 111749 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_C_SET ns_noc_io_spio_soc_ip.csr 111760 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L10_D_SET ns_noc_io_spio_soc_ip.csr 111771 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_A_SET ns_noc_io_spio_soc_ip.csr 111782 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_B_SET ns_noc_io_spio_soc_ip.csr 111793 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_C_SET ns_noc_io_spio_soc_ip.csr 111804 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L11_D_SET ns_noc_io_spio_soc_ip.csr 111815 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_A_SET ns_noc_io_spio_soc_ip.csr 111826 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_B_SET ns_noc_io_spio_soc_ip.csr 111837 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_C_SET ns_noc_io_spio_soc_ip.csr 111848 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L12_D_SET ns_noc_io_spio_soc_ip.csr 111859 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_A_SET ns_noc_io_spio_soc_ip.csr 111870 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_B_SET ns_noc_io_spio_soc_ip.csr 111881 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_C_SET ns_noc_io_spio_soc_ip.csr 111892 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L13_D_SET ns_noc_io_spio_soc_ip.csr 111903 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_A_SET ns_noc_io_spio_soc_ip.csr 111914 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_B_SET ns_noc_io_spio_soc_ip.csr 111925 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_C_SET ns_noc_io_spio_soc_ip.csr 111936 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L14_D_SET ns_noc_io_spio_soc_ip.csr 111947 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_A_SET ns_noc_io_spio_soc_ip.csr 111958 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_B_SET ns_noc_io_spio_soc_ip.csr 111969 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_C_SET ns_noc_io_spio_soc_ip.csr 111980 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTUS_1_L15_D_SET ns_noc_io_spio_soc_ip.csr 111991 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btrl_0 bridge_spio_sp_main0_pu_rbm_s_13_7_btrl_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 112068 spio_sp_main0_pu_rbm_s register btrl_0 0x37080 R 0x00000000 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_WT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_WT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_WT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_WT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_WT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_WT_SET ns_noc_io_spio_soc_ip.csr 112016 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 112027 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_CNT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_CNT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_CNT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_CNT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_CNT_SET ns_noc_io_spio_soc_ip.csr 112042 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_EN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_EN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_EN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_EN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_EN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_EN_SET ns_noc_io_spio_soc_ip.csr 112056 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_0_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 112067 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btrl_1 bridge_spio_sp_main0_pu_rbm_s_13_7_btrl_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 112144 spio_sp_main0_pu_rbm_s register btrl_1 0x37088 R 0x00000000 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_WT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_WT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_WT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_WT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_WT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_WT_SET ns_noc_io_spio_soc_ip.csr 112092 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 112103 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_CNT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_CNT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_CNT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_CNT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_CNT_SET ns_noc_io_spio_soc_ip.csr 112118 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_EN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_EN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_EN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_EN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_EN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_EN_SET ns_noc_io_spio_soc_ip.csr 112132 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_1_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 112143 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btrl_2 bridge_spio_sp_main0_pu_rbm_s_13_7_btrl_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 112220 spio_sp_main0_pu_rbm_s register btrl_2 0x37090 R 0x00000000 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_WT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_WT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_WT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_WT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_WT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_WT_SET ns_noc_io_spio_soc_ip.csr 112168 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 112179 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_CNT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_CNT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_CNT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_CNT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_CNT_SET ns_noc_io_spio_soc_ip.csr 112194 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_EN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_EN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_EN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_EN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_EN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_EN_SET ns_noc_io_spio_soc_ip.csr 112208 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_2_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 112219 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btrl_3 bridge_spio_sp_main0_pu_rbm_s_13_7_btrl_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 112296 spio_sp_main0_pu_rbm_s register btrl_3 0x37098 R 0x00000000 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_WT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_WT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_WT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_WT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_WT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_WT_SET ns_noc_io_spio_soc_ip.csr 112244 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 112255 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_CNT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_CNT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_CNT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_CNT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_CNT_SET ns_noc_io_spio_soc_ip.csr 112270 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_EN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_EN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_EN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_EN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_EN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_EN_SET ns_noc_io_spio_soc_ip.csr 112284 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTRL_3_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 112295 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btperr bridge_spio_sp_main0_pu_rbm_s_13_7_btperr SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 112498 spio_sp_main0_pu_rbm_s register btperr 0x370A8 R/W 0x00000000 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L0_SET ns_noc_io_spio_soc_ip.csr 112321 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L1_SET ns_noc_io_spio_soc_ip.csr 112332 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L2_SET ns_noc_io_spio_soc_ip.csr 112343 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L3_SET ns_noc_io_spio_soc_ip.csr 112354 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L4_SET ns_noc_io_spio_soc_ip.csr 112365 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L5_SET ns_noc_io_spio_soc_ip.csr 112376 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L6_SET ns_noc_io_spio_soc_ip.csr 112387 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L7_SET ns_noc_io_spio_soc_ip.csr 112398 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L8_SET ns_noc_io_spio_soc_ip.csr 112409 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L9_SET ns_noc_io_spio_soc_ip.csr 112420 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L10_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L10_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L10_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L10_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L10_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L10_SET ns_noc_io_spio_soc_ip.csr 112431 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L11_SET ns_noc_io_spio_soc_ip.csr 112442 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L12_SET ns_noc_io_spio_soc_ip.csr 112453 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L13_SET ns_noc_io_spio_soc_ip.csr 112464 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L14_SET ns_noc_io_spio_soc_ip.csr 112475 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_L15_SET ns_noc_io_spio_soc_ip.csr 112486 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_UNSD_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERR_UNSD_SET ns_noc_io_spio_soc_ip.csr 112497 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_btperrm bridge_spio_sp_main0_pu_rbm_s_13_7_btperrm SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 112698 spio_sp_main0_pu_rbm_s register btperrm 0x370B0 R/W 0x00000000 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L0_SET ns_noc_io_spio_soc_ip.csr 112521 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L1_SET ns_noc_io_spio_soc_ip.csr 112532 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L2_SET ns_noc_io_spio_soc_ip.csr 112543 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L3_SET ns_noc_io_spio_soc_ip.csr 112554 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L4_SET ns_noc_io_spio_soc_ip.csr 112565 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L5_SET ns_noc_io_spio_soc_ip.csr 112576 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L6_SET ns_noc_io_spio_soc_ip.csr 112587 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L7_SET ns_noc_io_spio_soc_ip.csr 112598 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L8_SET ns_noc_io_spio_soc_ip.csr 112609 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L9_SET ns_noc_io_spio_soc_ip.csr 112620 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L10_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L10_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L10_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L10_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L10_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L10_SET ns_noc_io_spio_soc_ip.csr 112631 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L11_SET ns_noc_io_spio_soc_ip.csr 112642 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L12_SET ns_noc_io_spio_soc_ip.csr 112653 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L13_SET ns_noc_io_spio_soc_ip.csr 112664 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L14_SET ns_noc_io_spio_soc_ip.csr 112675 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_L15_SET ns_noc_io_spio_soc_ip.csr 112686 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_UNSD_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BTPERRM_UNSD_SET ns_noc_io_spio_soc_ip.csr 112697 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_rxe bridge_spio_sp_main0_pu_rbm_s_13_7_rxe SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 112806 spio_sp_main0_pu_rbm_s register rxe 0x37120 R/W 0x00000000 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_A_SET ns_noc_io_spio_soc_ip.csr 112726 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_B_SET ns_noc_io_spio_soc_ip.csr 112737 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_C_SET ns_noc_io_spio_soc_ip.csr 112748 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_CRC_OFLW_D_SET ns_noc_io_spio_soc_ip.csr 112759 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_EVC_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_EVC_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_EVC_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_EVC_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_EVC_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_EVC_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_EVC_OFLW_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_EVC_OFLW_SET ns_noc_io_spio_soc_ip.csr 112771 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 112782 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_EVC1_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_EVC1_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_EVC1_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_EVC1_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_EVC1_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_EVC1_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_EVC1_OFLW_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_EVC1_OFLW_SET ns_noc_io_spio_soc_ip.csr 112794 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXE_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 112805 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_rxem bridge_spio_sp_main0_pu_rbm_s_13_7_rxem SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 112878 spio_sp_main0_pu_rbm_s register rxem 0x37128 R/W 0x00000050 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_UNSD_3_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_UNSD_3_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_UNSD_3_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_UNSD_3_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_UNSD_3_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_UNSD_3_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_UNSD_3_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_UNSD_3_0_SET ns_noc_io_spio_soc_ip.csr 112827 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_EVC_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_EVC_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_EVC_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_EVC_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_EVC_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_EVC_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_EVC_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_EVC_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 112841 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 112852 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_EVC1_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_EVC1_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_EVC1_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_EVC1_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_EVC1_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_EVC1_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_EVC1_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 112866 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_RXEM_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 112877 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_brs_0 bridge_spio_sp_main0_pu_rbm_s_13_7_brs_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 113152 spio_sp_main0_pu_rbm_s register brs_0 0x37130 R 0x00000000 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 112902 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_0_SET ns_noc_io_spio_soc_ip.csr 112913 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_0_SET ns_noc_io_spio_soc_ip.csr 112924 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_0_SET ns_noc_io_spio_soc_ip.csr 112935 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_0_SET ns_noc_io_spio_soc_ip.csr 112946 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 112956 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 112967 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_1_SET ns_noc_io_spio_soc_ip.csr 112978 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_1_SET ns_noc_io_spio_soc_ip.csr 112989 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_1_SET ns_noc_io_spio_soc_ip.csr 113000 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_1_SET ns_noc_io_spio_soc_ip.csr 113011 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 113021 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 113032 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_2_SET ns_noc_io_spio_soc_ip.csr 113043 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_2_SET ns_noc_io_spio_soc_ip.csr 113054 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_2_SET ns_noc_io_spio_soc_ip.csr 113065 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_2_SET ns_noc_io_spio_soc_ip.csr 113076 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 113086 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 113097 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_V_3_SET ns_noc_io_spio_soc_ip.csr 113108 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_S_3_SET ns_noc_io_spio_soc_ip.csr 113119 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_B_3_SET ns_noc_io_spio_soc_ip.csr 113130 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_F_3_SET ns_noc_io_spio_soc_ip.csr 113141 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_0_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 113151 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_brs_1 bridge_spio_sp_main0_pu_rbm_s_13_7_brs_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 113426 spio_sp_main0_pu_rbm_s register brs_1 0x37138 R 0x00000000 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 113176 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_0_SET ns_noc_io_spio_soc_ip.csr 113187 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_0_SET ns_noc_io_spio_soc_ip.csr 113198 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_0_SET ns_noc_io_spio_soc_ip.csr 113209 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_0_SET ns_noc_io_spio_soc_ip.csr 113220 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 113230 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 113241 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_1_SET ns_noc_io_spio_soc_ip.csr 113252 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_1_SET ns_noc_io_spio_soc_ip.csr 113263 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_1_SET ns_noc_io_spio_soc_ip.csr 113274 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_1_SET ns_noc_io_spio_soc_ip.csr 113285 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 113295 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 113306 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_2_SET ns_noc_io_spio_soc_ip.csr 113317 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_2_SET ns_noc_io_spio_soc_ip.csr 113328 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_2_SET ns_noc_io_spio_soc_ip.csr 113339 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_2_SET ns_noc_io_spio_soc_ip.csr 113350 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 113360 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 113371 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_V_3_SET ns_noc_io_spio_soc_ip.csr 113382 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_S_3_SET ns_noc_io_spio_soc_ip.csr 113393 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_B_3_SET ns_noc_io_spio_soc_ip.csr 113404 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_F_3_SET ns_noc_io_spio_soc_ip.csr 113415 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRS_1_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 113425 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_brus bridge_spio_sp_main0_pu_rbm_s_13_7_brus SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 113495 spio_sp_main0_pu_rbm_s register brus 0x371B0 R 0x00000000 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_A_SET ns_noc_io_spio_soc_ip.csr 113451 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_B_SET ns_noc_io_spio_soc_ip.csr 113462 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_C_SET ns_noc_io_spio_soc_ip.csr 113473 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_V_D_SET ns_noc_io_spio_soc_ip.csr 113484 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_UNSD_31_4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_UNSD_31_4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_UNSD_31_4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_UNSD_31_4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_UNSD_31_4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_UNSD_31_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_UNSD_31_4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRUS_UNSD_31_4_SET ns_noc_io_spio_soc_ip.csr 113494 UNSD_31_4 31 4 0x0000000 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_brperr0 bridge_spio_sp_main0_pu_rbm_s_13_7_brperr0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 113723 spio_sp_main0_pu_rbm_s register brperr0 0x371D0 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_D0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_D0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_D0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_D0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_D0_SET ns_noc_io_spio_soc_ip.csr 113533 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_DC0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_DC0_SET ns_noc_io_spio_soc_ip.csr 113544 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SB0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SB0_SET ns_noc_io_spio_soc_ip.csr 113555 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SBC0_SET ns_noc_io_spio_soc_ip.csr 113567 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_PK0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_PK0_SET ns_noc_io_spio_soc_ip.csr 113578 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 113589 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_D1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_D1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_D1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_D1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_D1_SET ns_noc_io_spio_soc_ip.csr 113600 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_DC1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_DC1_SET ns_noc_io_spio_soc_ip.csr 113611 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SB1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SB1_SET ns_noc_io_spio_soc_ip.csr 113622 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_SBC1_SET ns_noc_io_spio_soc_ip.csr 113634 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_PK1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_PK1_SET ns_noc_io_spio_soc_ip.csr 113645 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 113656 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 113667 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 113678 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 113689 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 113700 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 113711 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 113722 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_brperr1 bridge_spio_sp_main0_pu_rbm_s_13_7_brperr1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 113839 spio_sp_main0_pu_rbm_s register brperr1 0x371D8 R 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 113761 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 113772 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 113783 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 113794 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 113805 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 113816 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 113827 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERR1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 113838 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_brperrm0 bridge_spio_sp_main0_pu_rbm_s_13_7_brperrm0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 114060 spio_sp_main0_pu_rbm_s register brperrm0 0x371E0 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_D0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_D0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_D0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_D0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_D0_SET ns_noc_io_spio_soc_ip.csr 113866 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_DC0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_DC0_SET ns_noc_io_spio_soc_ip.csr 113878 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SB0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SB0_SET ns_noc_io_spio_soc_ip.csr 113889 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SBC0_SET ns_noc_io_spio_soc_ip.csr 113901 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_PK0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_PK0_SET ns_noc_io_spio_soc_ip.csr 113913 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 113924 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_D1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_D1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_D1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_D1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_D1_SET ns_noc_io_spio_soc_ip.csr 113935 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_DC1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_DC1_SET ns_noc_io_spio_soc_ip.csr 113947 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SB1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SB1_SET ns_noc_io_spio_soc_ip.csr 113958 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_SBC1_SET ns_noc_io_spio_soc_ip.csr 113970 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_PK1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_PK1_SET ns_noc_io_spio_soc_ip.csr 113982 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 113993 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 114004 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 114015 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 114026 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 114037 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 114048 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 114059 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_sp_main0_pu_rbm_s_13_7_brperrm1 bridge_spio_sp_main0_pu_rbm_s_13_7_brperrm1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 114165 spio_sp_main0_pu_rbm_s register brperrm1 0x371E8 R 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_pu_rbm_s_13_7_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 114087 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 114098 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 114109 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 114120 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 114131 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 114142 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 114153 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_PU_RBM_S_13_7_BRPERRM1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 114164 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_cgc bridge_spio_sp_main0_ram_s_14_11_as_cgc SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGC_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGC_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGC_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 114202 spio_sp_main0_ram_s register as_cgc 0x39C10 R/W 0x0000000000000064 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_as_cgc Programmable intervals used by coarse clock gating logic. This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGC_HYSTERESIS_COUNTER_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGC_HYSTERESIS_COUNTER_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGC_HYSTERESIS_COUNTER_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGC_HYSTERESIS_COUNTER_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGC_HYSTERESIS_COUNTER_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGC_HYSTERESIS_COUNTER_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGC_HYSTERESIS_COUNTER_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_spio_soc_ip.csr 114190 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGC_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGC_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGC_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGC_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGC_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGC_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGC_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGC_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 114201 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_cgo bridge_spio_sp_main0_ram_s_14_11_as_cgo SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGO_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGO_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGO_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGO_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 114237 spio_sp_main0_ram_s register as_cgo 0x39C18 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_as_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the slave bridge. false false false false FPO SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGO_FPO_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGO_FPO_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGO_FPO_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGO_FPO_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGO_FPO_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGO_FPO_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGO_FPO_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGO_FPO_SET ns_noc_io_spio_soc_ip.csr 114225 FPO 1'b1: Clock gating override enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGO_UNSD_63_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGO_UNSD_63_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGO_UNSD_63_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGO_UNSD_63_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGO_UNSD_63_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGO_UNSD_63_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGO_UNSD_63_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CGO_UNSD_63_1_SET ns_noc_io_spio_soc_ip.csr 114236 UNSD_63_1 63 1 0x0000000000000000 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_sts bridge_spio_sp_main0_ram_s_14_11_as_sts SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 114311 spio_sp_main0_ram_s register as_sts 0x39D00 R 0x000000000000000c Spio_noc_bridge_spio_sp_main0_ram_s_14_11_as_sts Slave bridge status bits. false false false false WOF SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_WOF_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_WOF_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_WOF_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_WOF_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_WOF_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_WOF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_WOF_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_WOF_SET ns_noc_io_spio_soc_ip.csr 114260 WOF 1'b1: Maximum number of supported write commands are outstanding to the attached slave device awaiting response, no more write commands will be issued to slave till responses are received. 1'b0: Slave device can expect more write commands from NoC 0 0 0x0 R ROF SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_ROF_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_ROF_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_ROF_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_ROF_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_ROF_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_ROF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_ROF_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_ROF_SET ns_noc_io_spio_soc_ip.csr 114276 ROF 1'b1: Maximum number of supported read commands are outstanding to the attached slave device awaiting response, no more read commands will be issued to slave till responses are received. 1'b0: Slave bridge can accept more read commands from the NoC 1 1 0x0 R WOE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_WOE_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_WOE_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_WOE_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_WOE_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_WOE_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_WOE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_WOE_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_WOE_SET ns_noc_io_spio_soc_ip.csr 114288 WOE 1'b1: There are no write commands outstanding to the attached slave device 2 2 0x1 R ROE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_ROE_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_ROE_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_ROE_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_ROE_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_ROE_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_ROE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_ROE_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_ROE_SET ns_noc_io_spio_soc_ip.csr 114300 ROE 1'b1: There are no read commands outstanding to the attached slave device 3 3 0x1 R UNSD_63_4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_UNSD_63_4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_UNSD_63_4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_UNSD_63_4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_UNSD_63_4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_UNSD_63_4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_UNSD_63_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_UNSD_63_4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_STS_UNSD_63_4_SET ns_noc_io_spio_soc_ip.csr 114310 UNSD_63_4 63 4 0x000000000000000 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_bridge_id bridge_spio_sp_main0_ram_s_14_11_as_bridge_id SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_BRIDGE_ID_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_BRIDGE_ID_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_BRIDGE_ID_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_BRIDGE_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 114341 spio_sp_main0_ram_s register as_bridge_id 0x39D08 R 0x000000000000000e Spio_noc_bridge_spio_sp_main0_ram_s_14_11_as_bridge_id Unique identifier assigned to the slave bridge. false false false false ID SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_BRIDGE_ID_ID_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_BRIDGE_ID_ID_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_BRIDGE_ID_ID_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_BRIDGE_ID_ID_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_BRIDGE_ID_ID_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_BRIDGE_ID_ID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_BRIDGE_ID_ID_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_BRIDGE_ID_ID_SET ns_noc_io_spio_soc_ip.csr 114330 ID Unique bridge ID 15 0 0x000e R UNSD_63_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_BRIDGE_ID_UNSD_63_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_BRIDGE_ID_UNSD_63_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_BRIDGE_ID_UNSD_63_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_BRIDGE_ID_UNSD_63_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_BRIDGE_ID_UNSD_63_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_BRIDGE_ID_UNSD_63_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_BRIDGE_ID_UNSD_63_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_spio_soc_ip.csr 114340 UNSD_63_16 63 16 0x000000000000 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_err bridge_spio_sp_main0_ram_s_14_11_as_err SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 114694 spio_sp_main0_ram_s register as_err 0x39E00 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_as_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E0_SET ns_noc_io_spio_soc_ip.csr 114362 E0 1'b1: Read decode error response: Decode error response received from slave device for read command 0 0 0x0 R/W E1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E1_SET ns_noc_io_spio_soc_ip.csr 114374 E1 1'b1: Read slave error response: Slave error response received from slave device for read command 1 1 0x0 R/W E2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E2_SET ns_noc_io_spio_soc_ip.csr 114387 E2 1'b1: [FATAL] Unknown read response destination: RID from read response produces a destination which is not present in the routing table 2 2 0x0 R/W E3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E3_SET ns_noc_io_spio_soc_ip.csr 114401 E3 1'b1: [FATAL] Interleaved read response: Interleaved read response. This can occur if interleaved read response is received from a slave device for which a de-interleaver was not specified 3 3 0x0 R/W E4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E4_SET ns_noc_io_spio_soc_ip.csr 114413 E4 1'b1: Read command modified: A read command which was marked as non-modifiable was modified by the slave bridge 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_UNSD_15_5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_UNSD_15_5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_UNSD_15_5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_UNSD_15_5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_UNSD_15_5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_UNSD_15_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_UNSD_15_5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 114424 UNSD_15_5 15 5 0x000 R E16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E16_SET ns_noc_io_spio_soc_ip.csr 114436 E16 1'b1: Write decode error response: Decode error response received from slave device for write command 16 16 0x0 R/W E17 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E17_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E17_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E17_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E17_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E17_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E17_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E17_SET ns_noc_io_spio_soc_ip.csr 114448 E17 1'b1: Write slave error response: Slave error response received from slave device for write command 17 17 0x0 R/W E18 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E18_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E18_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E18_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E18_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E18_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E18_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E18_SET ns_noc_io_spio_soc_ip.csr 114461 E18 1'b1: [FATAL] Unknown write response destination: BID from write response produces a destination which is not present in the routing table 18 18 0x0 R/W E19 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E19_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E19_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E19_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E19_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E19_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E19_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E19_SET ns_noc_io_spio_soc_ip.csr 114473 E19 1'b1: Write command modified: A write command which was marked as non-modifiable was modified by the slave bridge 19 19 0x0 R/W UNSD_31_20 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_UNSD_31_20_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_UNSD_31_20_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_UNSD_31_20_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_UNSD_31_20_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_UNSD_31_20_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_UNSD_31_20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_UNSD_31_20_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_UNSD_31_20_SET ns_noc_io_spio_soc_ip.csr 114484 UNSD_31_20 31 20 0x000 R E32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E32_SET ns_noc_io_spio_soc_ip.csr 114496 E32 1'b1: [FATAL] Traffic sent to a noc layer which is power gated 32 32 0x0 R/W E33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E33_SET ns_noc_io_spio_soc_ip.csr 114507 E33 1'b1: [FATAL] Parity error in config/status registers 33 33 0x0 R/W E34 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E34_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E34_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E34_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E34_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E34_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E34_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E34_SET ns_noc_io_spio_soc_ip.csr 114518 E34 1'b1: [FATAL] RDATA Parity error 34 34 0x0 R/W E35 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E35_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E35_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E35_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E35_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E35_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E35_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E35_SET ns_noc_io_spio_soc_ip.csr 114529 E35 1'b1: [FATAL] RRESP Parity error 35 35 0x0 R/W E36 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E36_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E36_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E36_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E36_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E36_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E36_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E36_SET ns_noc_io_spio_soc_ip.csr 114540 E36 1'b1: [FATAL] BRESP Parity error 36 36 0x0 R/W E37 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E37_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E37_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E37_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E37_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E37_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E37_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E37_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E37_SET ns_noc_io_spio_soc_ip.csr 114551 E37 1'b1: [FATAL] AC Parity error 37 37 0x0 R/W E38 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E38_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E38_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E38_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E38_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E38_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E38_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E38_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E38_SET ns_noc_io_spio_soc_ip.csr 114562 E38 1'b1: [FATAL] ACADDR Parity error 38 38 0x0 R/W E39 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E39_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E39_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E39_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E39_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E39_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E39_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E39_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E39_SET ns_noc_io_spio_soc_ip.csr 114574 E39 1'b1: [FATAL] R Ch Cmdtbl Parity Err 39 39 0x0 R E40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E40_SET ns_noc_io_spio_soc_ip.csr 114586 E40 1'b1: [FATAL] B Ch Cmdtbl Parity Err 40 40 0x0 R E41 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E41_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E41_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E41_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E41_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E41_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E41_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E41_SET ns_noc_io_spio_soc_ip.csr 114598 E41 1'b1: [FATAL] Rx Fifo Parity Err 41 41 0x0 R E42 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E42_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E42_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E42_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E42_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E42_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E42_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E42_SET ns_noc_io_spio_soc_ip.csr 114610 E42 1'b1: [FATAL] CRCD Ch Reorder Buffer Parity Err 42 42 0x0 R E43 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E43_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E43_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E43_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E43_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E43_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E43_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E43_SET ns_noc_io_spio_soc_ip.csr 114622 E43 1'b1: [FATAL] Ack Ch Wack Reorder Buffer Parity Err 43 43 0x0 R E44 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E44_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E44_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E44_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E44_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E44_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E44_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E44_SET ns_noc_io_spio_soc_ip.csr 114634 E44 1'b1: [FATAL] Ack Ch Rack Reorder Buffer Parity Err 44 44 0x0 R E45 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E45_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E45_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E45_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E45_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E45_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E45_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E45_SET ns_noc_io_spio_soc_ip.csr 114646 E45 1'b1: [FATAL] B Ch Drain Fifo Parity Err 45 45 0x0 R E46 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E46_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E46_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E46_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E46_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E46_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E46_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E46_SET ns_noc_io_spio_soc_ip.csr 114658 E46 1'b1: [FATAL] R Ch Flush Fifo Parity Err 46 46 0x0 R E47 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E47_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E47_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E47_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E47_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E47_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E47_SET ns_noc_io_spio_soc_ip.csr 114670 E47 1'b1: [FATAL] R Ch Deinterleaver Cmdtbl Parity Err 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_E48_SET ns_noc_io_spio_soc_ip.csr 114682 E48 1'b1: [FATAL] R Ch Deinterleaver Data Buffer Parity Err 48 48 0x0 R UNSD_63_49 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_UNSD_63_49_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_UNSD_63_49_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_UNSD_63_49_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_UNSD_63_49_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_UNSD_63_49_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_UNSD_63_49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_UNSD_63_49_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_ERR_UNSD_63_49_SET ns_noc_io_spio_soc_ip.csr 114693 UNSD_63_49 63 49 0x0000 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_intm bridge_spio_sp_main0_ram_s_14_11_as_intm SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 115034 spio_sp_main0_ram_s register as_intm 0x39E40 R/W 0x0000007d000b0013 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_as_intm Interrupt mask register.Individual bit positions match the error bit positions in AS_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M0_SET ns_noc_io_spio_soc_ip.csr 114715 M0 Mask interrupts for read channel 0 0 0x1 R/W M1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M1_SET ns_noc_io_spio_soc_ip.csr 114726 M1 Mask interrupts for read channel 1 1 0x1 R/W M2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M2_SET ns_noc_io_spio_soc_ip.csr 114737 M2 Mask interrupts for read channel 2 2 0x0 R/W M3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M3_SET ns_noc_io_spio_soc_ip.csr 114748 M3 Mask interrupts for read channel 3 3 0x0 R/W M4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M4_SET ns_noc_io_spio_soc_ip.csr 114759 M4 Mask interrupts for read channel 4 4 0x1 R/W UNSD_15_5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_UNSD_15_5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_UNSD_15_5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_UNSD_15_5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_UNSD_15_5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_UNSD_15_5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_UNSD_15_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_UNSD_15_5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 114770 UNSD_15_5 15 5 0x000 R M16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M16_SET ns_noc_io_spio_soc_ip.csr 114781 M16 Mask interrupts for write channel 16 16 0x1 R/W M17 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M17_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M17_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M17_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M17_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M17_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M17_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M17_SET ns_noc_io_spio_soc_ip.csr 114792 M17 Mask interrupts for write channel 17 17 0x1 R/W M18 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M18_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M18_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M18_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M18_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M18_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M18_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M18_SET ns_noc_io_spio_soc_ip.csr 114803 M18 Mask interrupts for write channel 18 18 0x0 R/W M19 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M19_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M19_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M19_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M19_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M19_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M19_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M19_SET ns_noc_io_spio_soc_ip.csr 114814 M19 Mask interrupts for write channel 19 19 0x1 R/W UNSD_31_20 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_UNSD_31_20_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_UNSD_31_20_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_UNSD_31_20_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_UNSD_31_20_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_UNSD_31_20_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_UNSD_31_20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_UNSD_31_20_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_UNSD_31_20_SET ns_noc_io_spio_soc_ip.csr 114825 UNSD_31_20 31 20 0x000 R M32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M32_SET ns_noc_io_spio_soc_ip.csr 114836 M32 Mask interrupt on traffic to PG layer 32 32 0x1 R/W M33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M33_SET ns_noc_io_spio_soc_ip.csr 114847 M33 Mask interrupt on csr parity errors 33 33 0x0 R/W M34 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M34_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M34_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M34_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M34_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M34_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M34_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M34_SET ns_noc_io_spio_soc_ip.csr 114858 M34 RDATA parity interrupt Mask 34 34 0x1 R/W M35 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M35_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M35_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M35_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M35_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M35_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M35_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M35_SET ns_noc_io_spio_soc_ip.csr 114869 M35 RRESP parity interrupt Mask 35 35 0x1 R/W M36 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M36_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M36_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M36_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M36_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M36_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M36_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M36_SET ns_noc_io_spio_soc_ip.csr 114880 M36 BRESP parity interrupt Mask 36 36 0x1 R/W M37 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M37_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M37_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M37_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M37_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M37_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M37_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M37_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M37_SET ns_noc_io_spio_soc_ip.csr 114891 M37 AC parity interrupt Mask 37 37 0x1 R/W M38 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M38_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M38_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M38_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M38_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M38_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M38_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M38_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_M38_SET ns_noc_io_spio_soc_ip.csr 114902 M38 ACADDR parity interrupt Mask 38 38 0x1 R/W E39 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E39_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E39_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E39_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E39_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E39_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E39_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E39_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E39_SET ns_noc_io_spio_soc_ip.csr 114914 E39 1'b1: R Ch Cmdtbl Parity Err Intr Mask 39 39 0x0 R E40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E40_SET ns_noc_io_spio_soc_ip.csr 114926 E40 1'b1: B Ch Cmdtbl Parity Err Intr Mask 40 40 0x0 R E41 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E41_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E41_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E41_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E41_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E41_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E41_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E41_SET ns_noc_io_spio_soc_ip.csr 114938 E41 1'b1: Rx Fifo Parity Err Intr Mask 41 41 0x0 R E42 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E42_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E42_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E42_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E42_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E42_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E42_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E42_SET ns_noc_io_spio_soc_ip.csr 114950 E42 1'b1: CRCD Ch Reorder Buffer Parity Err Intr Mask 42 42 0x0 R E43 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E43_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E43_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E43_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E43_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E43_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E43_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E43_SET ns_noc_io_spio_soc_ip.csr 114962 E43 1'b1: Ack Ch Wack Reorder Buffer Parity Err IntrMask 43 43 0x0 R E44 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E44_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E44_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E44_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E44_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E44_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E44_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E44_SET ns_noc_io_spio_soc_ip.csr 114974 E44 1'b1: Ack Ch Rack Reorder Buffer Parity Err Intr Mask 44 44 0x0 R E45 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E45_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E45_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E45_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E45_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E45_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E45_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E45_SET ns_noc_io_spio_soc_ip.csr 114986 E45 1'b1: B Ch Drain Fifo Parity Err Intr Mask 45 45 0x0 R E46 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E46_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E46_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E46_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E46_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E46_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E46_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E46_SET ns_noc_io_spio_soc_ip.csr 114998 E46 1'b1: R Ch Flush Fifo Parity Err Intr Mask 46 46 0x0 R E47 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E47_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E47_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E47_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E47_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E47_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E47_SET ns_noc_io_spio_soc_ip.csr 115010 E47 1'b1: R Ch Deinterleaver Cmdtbl Parity Err Intr Mask 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_E48_SET ns_noc_io_spio_soc_ip.csr 115022 E48 1'b1: R Ch Deinterleaver Data Buffer Parity Err Intr Mask 48 48 0x0 R UNSD_63_49 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_UNSD_63_49_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_UNSD_63_49_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_UNSD_63_49_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_UNSD_63_49_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_UNSD_63_49_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_UNSD_63_49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_UNSD_63_49_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_INTM_UNSD_63_49_SET ns_noc_io_spio_soc_ip.csr 115033 UNSD_63_49 63 49 0x0000 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_ccmd bridge_spio_sp_main0_ram_s_14_11_as_ccmd SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 115109 spio_sp_main0_ram_s register as_ccmd 0x39F00 R/W 0x0000000003000000 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_as_ccmd Not applicable for current release. false false false false UNSD_23_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_UNSD_23_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_UNSD_23_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_UNSD_23_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_UNSD_23_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_UNSD_23_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_UNSD_23_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_UNSD_23_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_UNSD_23_0_SET ns_noc_io_spio_soc_ip.csr 115052 UNSD_23_0 23 0 0x000000 R rdy SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_RDY_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_RDY_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_RDY_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_RDY_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_RDY_SET ns_noc_io_spio_soc_ip.csr 115063 rdy 1'b1: Ready 24 24 0x1 R/W val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_VAL_SET ns_noc_io_spio_soc_ip.csr 115074 val 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_UNSD_27_26_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_UNSD_27_26_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_UNSD_27_26_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_UNSD_27_26_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_UNSD_27_26_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_UNSD_27_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_UNSD_27_26_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_UNSD_27_26_SET ns_noc_io_spio_soc_ip.csr 115085 UNSD_27_26 27 26 0x0 R intfid SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_INTFID_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_INTFID_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_INTFID_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_INTFID_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_INTFID_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_INTFID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_INTFID_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_INTFID_SET ns_noc_io_spio_soc_ip.csr 115097 intfid 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_63_31 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_UNSD_63_31_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_UNSD_63_31_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_UNSD_63_31_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_UNSD_63_31_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_UNSD_63_31_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_UNSD_63_31_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_UNSD_63_31_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMD_UNSD_63_31_SET ns_noc_io_spio_soc_ip.csr 115108 UNSD_63_31 63 31 0x000000000 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_ccmdmsk bridge_spio_sp_main0_ram_s_14_11_as_ccmdmsk SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 115161 spio_sp_main0_ram_s register as_ccmdmsk 0x39F08 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_as_ccmdmsk Not applicable for current release. false false false false UNSD_23_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_UNSD_23_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_UNSD_23_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_UNSD_23_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_UNSD_23_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_UNSD_23_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_UNSD_23_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_UNSD_23_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_UNSD_23_0_SET ns_noc_io_spio_soc_ip.csr 115127 UNSD_23_0 23 0 0x000000 R rdy SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_RDY_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_RDY_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_RDY_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_RDY_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_RDY_SET ns_noc_io_spio_soc_ip.csr 115138 rdy 1'b1: Ready 24 24 0x0 R/W val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_VAL_SET ns_noc_io_spio_soc_ip.csr 115149 val 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_UNSD_63_26_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_UNSD_63_26_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_UNSD_63_26_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_UNSD_63_26_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_UNSD_63_26_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_UNSD_63_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_UNSD_63_26_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CCMDMSK_UNSD_63_26_SET ns_noc_io_spio_soc_ip.csr 115160 UNSD_63_26 63 26 0x0000000000 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_cntr bridge_spio_sp_main0_ram_s_14_11_as_cntr SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CNTR_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CNTR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CNTR_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CNTR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 115191 spio_sp_main0_ram_s register as_cntr 0x39F10 R 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_as_cntr Not applicable for current release. false false false false CNTR SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CNTR_CNTR_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CNTR_CNTR_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CNTR_CNTR_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CNTR_CNTR_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CNTR_CNTR_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CNTR_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CNTR_CNTR_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CNTR_CNTR_SET ns_noc_io_spio_soc_ip.csr 115180 CNTR Counter 31 0 0x00000000 R UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CNTR_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CNTR_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CNTR_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CNTR_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CNTR_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CNTR_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CNTR_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_CNTR_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 115190 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_arovrd bridge_spio_sp_main0_ram_s_14_11_as_arovrd SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 115304 spio_sp_main0_ram_s register as_arovrd 0x39F18 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_as_arovrd AR Overrides. false false false false arcache_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 115209 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 115222 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 115233 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 115244 UNSD_11_11 11 11 0x0 R arprot_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 115257 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 115268 UNSD_15_15 15 15 0x0 R arqos_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 115279 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_ARQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 115292 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AROVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 115303 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_as_awovrd bridge_spio_sp_main0_ram_s_14_11_as_awovrd SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 115417 spio_sp_main0_ram_s register as_awovrd 0x39F20 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_as_awovrd AW Overrides. false false false false awcache_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 115322 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 115335 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 115346 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 115357 UNSD_11_11 11 11 0x0 R awprot_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 115370 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 115381 UNSD_15_15 15 15 0x0 R awqos_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 115392 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_AWQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 115405 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_AS_AWOVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 115416 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_p_0 bridge_spio_sp_main0_ram_s_14_11_p_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 115482 spio_sp_main0_ram_s register p_0 0x3B000 R/W 0x00000003 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_0_SET ns_noc_io_spio_soc_ip.csr 115445 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_1_SET ns_noc_io_spio_soc_ip.csr 115457 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_2_SET ns_noc_io_spio_soc_ip.csr 115469 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_0_WT_QOS_3_SET ns_noc_io_spio_soc_ip.csr 115481 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_p_1 bridge_spio_sp_main0_ram_s_14_11_p_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 115548 spio_sp_main0_ram_s register p_1 0x3B008 R 0x00000000 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_4_SET ns_noc_io_spio_soc_ip.csr 115511 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_5_SET ns_noc_io_spio_soc_ip.csr 115523 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_6_SET ns_noc_io_spio_soc_ip.csr 115535 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_1_WT_QOS_7_SET ns_noc_io_spio_soc_ip.csr 115547 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_p_2 bridge_spio_sp_main0_ram_s_14_11_p_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 115614 spio_sp_main0_ram_s register p_2 0x3B010 R 0x00000000 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_8_SET ns_noc_io_spio_soc_ip.csr 115577 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_9_SET ns_noc_io_spio_soc_ip.csr 115589 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_10_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_10_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_10_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_10_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_10_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_10_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_10_SET ns_noc_io_spio_soc_ip.csr 115601 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_2_WT_QOS_11_SET ns_noc_io_spio_soc_ip.csr 115613 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_p_3 bridge_spio_sp_main0_ram_s_14_11_p_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 115680 spio_sp_main0_ram_s register p_3 0x3B018 R 0x00000000 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_12_SET ns_noc_io_spio_soc_ip.csr 115643 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_13_SET ns_noc_io_spio_soc_ip.csr 115655 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_14_SET ns_noc_io_spio_soc_ip.csr 115667 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_P_3_WT_QOS_15_SET ns_noc_io_spio_soc_ip.csr 115679 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_txe bridge_spio_sp_main0_ram_s_14_11_txe SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 115826 spio_sp_main0_ram_s register txe 0x3B040 R/W 0x00000000 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_TRANS_WITHOUT_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_TRANS_WITHOUT_SOP_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_TRANS_WITHOUT_SOP_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_TRANS_WITHOUT_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_TRANS_WITHOUT_SOP_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_TRANS_WITHOUT_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_TRANS_WITHOUT_SOP_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_spio_soc_ip.csr 115707 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_SOP_AFTER_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_SOP_AFTER_SOP_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_SOP_AFTER_SOP_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_SOP_AFTER_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_SOP_AFTER_SOP_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_SOP_AFTER_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_SOP_AFTER_SOP_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_SOP_AFTER_SOP_SET ns_noc_io_spio_soc_ip.csr 115719 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 115734 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 115747 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_spio_soc_ip.csr 115761 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_spio_soc_ip.csr 115775 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_spio_soc_ip.csr 115789 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_spio_soc_ip.csr 115803 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 115814 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXE_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 115825 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_txem bridge_spio_sp_main0_ram_s_14_11_txem SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 115905 spio_sp_main0_ram_s register txem 0x3B048 R/W 0x00000008 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_UNSD_1_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_UNSD_1_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_UNSD_1_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_UNSD_1_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_UNSD_1_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_UNSD_1_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_UNSD_1_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_UNSD_1_0_SET ns_noc_io_spio_soc_ip.csr 115849 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 115860 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 115871 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_UNSD_7_4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_UNSD_7_4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_UNSD_7_4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_UNSD_7_4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_UNSD_7_4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_UNSD_7_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_UNSD_7_4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_UNSD_7_4_SET ns_noc_io_spio_soc_ip.csr 115882 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 115893 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_TXEM_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 115904 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_btus_0 bridge_spio_sp_main0_ram_s_14_11_btus_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 116273 spio_sp_main0_ram_s register btus_0 0x3B058 R 0x00000000 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_A_SET ns_noc_io_spio_soc_ip.csr 115931 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_B_SET ns_noc_io_spio_soc_ip.csr 115942 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_C_SET ns_noc_io_spio_soc_ip.csr 115953 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L0_D_SET ns_noc_io_spio_soc_ip.csr 115964 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_A_SET ns_noc_io_spio_soc_ip.csr 115975 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_B_SET ns_noc_io_spio_soc_ip.csr 115986 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_C_SET ns_noc_io_spio_soc_ip.csr 115997 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L1_D_SET ns_noc_io_spio_soc_ip.csr 116008 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_A_SET ns_noc_io_spio_soc_ip.csr 116019 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_B_SET ns_noc_io_spio_soc_ip.csr 116030 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_C_SET ns_noc_io_spio_soc_ip.csr 116041 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L2_D_SET ns_noc_io_spio_soc_ip.csr 116052 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_A_SET ns_noc_io_spio_soc_ip.csr 116063 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_B_SET ns_noc_io_spio_soc_ip.csr 116074 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_C_SET ns_noc_io_spio_soc_ip.csr 116085 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L3_D_SET ns_noc_io_spio_soc_ip.csr 116096 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_A_SET ns_noc_io_spio_soc_ip.csr 116107 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_B_SET ns_noc_io_spio_soc_ip.csr 116118 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_C_SET ns_noc_io_spio_soc_ip.csr 116129 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L4_D_SET ns_noc_io_spio_soc_ip.csr 116140 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_A_SET ns_noc_io_spio_soc_ip.csr 116151 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_B_SET ns_noc_io_spio_soc_ip.csr 116162 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_C_SET ns_noc_io_spio_soc_ip.csr 116173 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L5_D_SET ns_noc_io_spio_soc_ip.csr 116184 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_A_SET ns_noc_io_spio_soc_ip.csr 116195 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_B_SET ns_noc_io_spio_soc_ip.csr 116206 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_C_SET ns_noc_io_spio_soc_ip.csr 116217 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L6_D_SET ns_noc_io_spio_soc_ip.csr 116228 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_A_SET ns_noc_io_spio_soc_ip.csr 116239 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_B_SET ns_noc_io_spio_soc_ip.csr 116250 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_C_SET ns_noc_io_spio_soc_ip.csr 116261 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_0_L7_D_SET ns_noc_io_spio_soc_ip.csr 116272 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_btus_1 bridge_spio_sp_main0_ram_s_14_11_btus_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 116641 spio_sp_main0_ram_s register btus_1 0x3B060 R 0x00000000 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_A_SET ns_noc_io_spio_soc_ip.csr 116299 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_B_SET ns_noc_io_spio_soc_ip.csr 116310 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_C_SET ns_noc_io_spio_soc_ip.csr 116321 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L8_D_SET ns_noc_io_spio_soc_ip.csr 116332 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_A_SET ns_noc_io_spio_soc_ip.csr 116343 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_B_SET ns_noc_io_spio_soc_ip.csr 116354 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_C_SET ns_noc_io_spio_soc_ip.csr 116365 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L9_D_SET ns_noc_io_spio_soc_ip.csr 116376 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_A_SET ns_noc_io_spio_soc_ip.csr 116387 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_B_SET ns_noc_io_spio_soc_ip.csr 116398 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_C_SET ns_noc_io_spio_soc_ip.csr 116409 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L10_D_SET ns_noc_io_spio_soc_ip.csr 116420 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_A_SET ns_noc_io_spio_soc_ip.csr 116431 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_B_SET ns_noc_io_spio_soc_ip.csr 116442 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_C_SET ns_noc_io_spio_soc_ip.csr 116453 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L11_D_SET ns_noc_io_spio_soc_ip.csr 116464 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_A_SET ns_noc_io_spio_soc_ip.csr 116475 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_B_SET ns_noc_io_spio_soc_ip.csr 116486 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_C_SET ns_noc_io_spio_soc_ip.csr 116497 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L12_D_SET ns_noc_io_spio_soc_ip.csr 116508 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_A_SET ns_noc_io_spio_soc_ip.csr 116519 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_B_SET ns_noc_io_spio_soc_ip.csr 116530 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_C_SET ns_noc_io_spio_soc_ip.csr 116541 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L13_D_SET ns_noc_io_spio_soc_ip.csr 116552 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_A_SET ns_noc_io_spio_soc_ip.csr 116563 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_B_SET ns_noc_io_spio_soc_ip.csr 116574 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_C_SET ns_noc_io_spio_soc_ip.csr 116585 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L14_D_SET ns_noc_io_spio_soc_ip.csr 116596 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_A_SET ns_noc_io_spio_soc_ip.csr 116607 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_B_SET ns_noc_io_spio_soc_ip.csr 116618 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_C_SET ns_noc_io_spio_soc_ip.csr 116629 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTUS_1_L15_D_SET ns_noc_io_spio_soc_ip.csr 116640 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_btrl_0 bridge_spio_sp_main0_ram_s_14_11_btrl_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 116717 spio_sp_main0_ram_s register btrl_0 0x3B080 R 0x00000000 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_WT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_WT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_WT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_WT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_WT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_WT_SET ns_noc_io_spio_soc_ip.csr 116665 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 116676 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_CNT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_CNT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_CNT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_CNT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_CNT_SET ns_noc_io_spio_soc_ip.csr 116691 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_EN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_EN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_EN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_EN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_EN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_EN_SET ns_noc_io_spio_soc_ip.csr 116705 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_0_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 116716 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_btrl_1 bridge_spio_sp_main0_ram_s_14_11_btrl_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 116793 spio_sp_main0_ram_s register btrl_1 0x3B088 R 0x00000000 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_WT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_WT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_WT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_WT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_WT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_WT_SET ns_noc_io_spio_soc_ip.csr 116741 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 116752 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_CNT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_CNT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_CNT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_CNT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_CNT_SET ns_noc_io_spio_soc_ip.csr 116767 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_EN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_EN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_EN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_EN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_EN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_EN_SET ns_noc_io_spio_soc_ip.csr 116781 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_1_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 116792 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_btrl_2 bridge_spio_sp_main0_ram_s_14_11_btrl_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 116869 spio_sp_main0_ram_s register btrl_2 0x3B090 R 0x00000000 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_WT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_WT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_WT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_WT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_WT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_WT_SET ns_noc_io_spio_soc_ip.csr 116817 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 116828 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_CNT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_CNT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_CNT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_CNT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_CNT_SET ns_noc_io_spio_soc_ip.csr 116843 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_EN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_EN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_EN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_EN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_EN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_EN_SET ns_noc_io_spio_soc_ip.csr 116857 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_2_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 116868 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_btrl_3 bridge_spio_sp_main0_ram_s_14_11_btrl_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 116945 spio_sp_main0_ram_s register btrl_3 0x3B098 R 0x00000000 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_WT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_WT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_WT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_WT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_WT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_WT_SET ns_noc_io_spio_soc_ip.csr 116893 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 116904 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_CNT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_CNT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_CNT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_CNT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_CNT_SET ns_noc_io_spio_soc_ip.csr 116919 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_EN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_EN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_EN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_EN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_EN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_EN_SET ns_noc_io_spio_soc_ip.csr 116933 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTRL_3_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 116944 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_btperr bridge_spio_sp_main0_ram_s_14_11_btperr SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 117147 spio_sp_main0_ram_s register btperr 0x3B0A8 R/W 0x00000000 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L0_SET ns_noc_io_spio_soc_ip.csr 116970 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L1_SET ns_noc_io_spio_soc_ip.csr 116981 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L2_SET ns_noc_io_spio_soc_ip.csr 116992 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L3_SET ns_noc_io_spio_soc_ip.csr 117003 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L4_SET ns_noc_io_spio_soc_ip.csr 117014 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L5_SET ns_noc_io_spio_soc_ip.csr 117025 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L6_SET ns_noc_io_spio_soc_ip.csr 117036 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L7_SET ns_noc_io_spio_soc_ip.csr 117047 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L8_SET ns_noc_io_spio_soc_ip.csr 117058 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L9_SET ns_noc_io_spio_soc_ip.csr 117069 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L10_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L10_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L10_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L10_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L10_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L10_SET ns_noc_io_spio_soc_ip.csr 117080 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L11_SET ns_noc_io_spio_soc_ip.csr 117091 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L12_SET ns_noc_io_spio_soc_ip.csr 117102 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L13_SET ns_noc_io_spio_soc_ip.csr 117113 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L14_SET ns_noc_io_spio_soc_ip.csr 117124 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_L15_SET ns_noc_io_spio_soc_ip.csr 117135 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_UNSD_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERR_UNSD_SET ns_noc_io_spio_soc_ip.csr 117146 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_btperrm bridge_spio_sp_main0_ram_s_14_11_btperrm SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 117347 spio_sp_main0_ram_s register btperrm 0x3B0B0 R/W 0x00000000 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L0_SET ns_noc_io_spio_soc_ip.csr 117170 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L1_SET ns_noc_io_spio_soc_ip.csr 117181 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L2_SET ns_noc_io_spio_soc_ip.csr 117192 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L3_SET ns_noc_io_spio_soc_ip.csr 117203 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L4_SET ns_noc_io_spio_soc_ip.csr 117214 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L5_SET ns_noc_io_spio_soc_ip.csr 117225 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L6_SET ns_noc_io_spio_soc_ip.csr 117236 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L7_SET ns_noc_io_spio_soc_ip.csr 117247 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L8_SET ns_noc_io_spio_soc_ip.csr 117258 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L9_SET ns_noc_io_spio_soc_ip.csr 117269 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L10_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L10_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L10_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L10_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L10_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L10_SET ns_noc_io_spio_soc_ip.csr 117280 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L11_SET ns_noc_io_spio_soc_ip.csr 117291 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L12_SET ns_noc_io_spio_soc_ip.csr 117302 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L13_SET ns_noc_io_spio_soc_ip.csr 117313 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L14_SET ns_noc_io_spio_soc_ip.csr 117324 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_L15_SET ns_noc_io_spio_soc_ip.csr 117335 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_UNSD_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BTPERRM_UNSD_SET ns_noc_io_spio_soc_ip.csr 117346 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_rxe bridge_spio_sp_main0_ram_s_14_11_rxe SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 117455 spio_sp_main0_ram_s register rxe 0x3B120 R/W 0x00000000 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_A_SET ns_noc_io_spio_soc_ip.csr 117375 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_B_SET ns_noc_io_spio_soc_ip.csr 117386 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_C_SET ns_noc_io_spio_soc_ip.csr 117397 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_CRC_OFLW_D_SET ns_noc_io_spio_soc_ip.csr 117408 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_EVC_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_EVC_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_EVC_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_EVC_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_EVC_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_EVC_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_EVC_OFLW_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_EVC_OFLW_SET ns_noc_io_spio_soc_ip.csr 117420 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 117431 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_EVC1_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_EVC1_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_EVC1_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_EVC1_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_EVC1_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_EVC1_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_EVC1_OFLW_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_EVC1_OFLW_SET ns_noc_io_spio_soc_ip.csr 117443 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXE_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 117454 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_rxem bridge_spio_sp_main0_ram_s_14_11_rxem SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 117527 spio_sp_main0_ram_s register rxem 0x3B128 R/W 0x00000050 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_UNSD_3_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_UNSD_3_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_UNSD_3_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_UNSD_3_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_UNSD_3_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_UNSD_3_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_UNSD_3_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_UNSD_3_0_SET ns_noc_io_spio_soc_ip.csr 117476 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_EVC_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_EVC_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_EVC_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_EVC_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_EVC_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_EVC_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_EVC_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_EVC_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 117490 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 117501 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_EVC1_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_EVC1_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_EVC1_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_EVC1_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_EVC1_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_EVC1_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_EVC1_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 117515 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_RXEM_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 117526 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_brs_0 bridge_spio_sp_main0_ram_s_14_11_brs_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 117801 spio_sp_main0_ram_s register brs_0 0x3B130 R 0x00000000 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 117551 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_0_SET ns_noc_io_spio_soc_ip.csr 117562 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_0_SET ns_noc_io_spio_soc_ip.csr 117573 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_0_SET ns_noc_io_spio_soc_ip.csr 117584 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_0_SET ns_noc_io_spio_soc_ip.csr 117595 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 117605 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 117616 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_1_SET ns_noc_io_spio_soc_ip.csr 117627 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_1_SET ns_noc_io_spio_soc_ip.csr 117638 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_1_SET ns_noc_io_spio_soc_ip.csr 117649 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_1_SET ns_noc_io_spio_soc_ip.csr 117660 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 117670 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 117681 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_2_SET ns_noc_io_spio_soc_ip.csr 117692 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_2_SET ns_noc_io_spio_soc_ip.csr 117703 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_2_SET ns_noc_io_spio_soc_ip.csr 117714 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_2_SET ns_noc_io_spio_soc_ip.csr 117725 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 117735 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 117746 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_V_3_SET ns_noc_io_spio_soc_ip.csr 117757 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_S_3_SET ns_noc_io_spio_soc_ip.csr 117768 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_B_3_SET ns_noc_io_spio_soc_ip.csr 117779 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_F_3_SET ns_noc_io_spio_soc_ip.csr 117790 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_0_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 117800 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_brs_1 bridge_spio_sp_main0_ram_s_14_11_brs_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 118075 spio_sp_main0_ram_s register brs_1 0x3B138 R 0x00000000 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 117825 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_0_SET ns_noc_io_spio_soc_ip.csr 117836 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_0_SET ns_noc_io_spio_soc_ip.csr 117847 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_0_SET ns_noc_io_spio_soc_ip.csr 117858 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_0_SET ns_noc_io_spio_soc_ip.csr 117869 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 117879 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 117890 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_1_SET ns_noc_io_spio_soc_ip.csr 117901 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_1_SET ns_noc_io_spio_soc_ip.csr 117912 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_1_SET ns_noc_io_spio_soc_ip.csr 117923 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_1_SET ns_noc_io_spio_soc_ip.csr 117934 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 117944 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 117955 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_2_SET ns_noc_io_spio_soc_ip.csr 117966 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_2_SET ns_noc_io_spio_soc_ip.csr 117977 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_2_SET ns_noc_io_spio_soc_ip.csr 117988 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_2_SET ns_noc_io_spio_soc_ip.csr 117999 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 118009 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 118020 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_V_3_SET ns_noc_io_spio_soc_ip.csr 118031 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_S_3_SET ns_noc_io_spio_soc_ip.csr 118042 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_B_3_SET ns_noc_io_spio_soc_ip.csr 118053 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_F_3_SET ns_noc_io_spio_soc_ip.csr 118064 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRS_1_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 118074 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_brus bridge_spio_sp_main0_ram_s_14_11_brus SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 118144 spio_sp_main0_ram_s register brus 0x3B1B0 R 0x00000000 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_A_SET ns_noc_io_spio_soc_ip.csr 118100 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_B_SET ns_noc_io_spio_soc_ip.csr 118111 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_C_SET ns_noc_io_spio_soc_ip.csr 118122 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_V_D_SET ns_noc_io_spio_soc_ip.csr 118133 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_UNSD_31_4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_UNSD_31_4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_UNSD_31_4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_UNSD_31_4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_UNSD_31_4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_UNSD_31_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_UNSD_31_4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRUS_UNSD_31_4_SET ns_noc_io_spio_soc_ip.csr 118143 UNSD_31_4 31 4 0x0000000 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_brperr0 bridge_spio_sp_main0_ram_s_14_11_brperr0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 118372 spio_sp_main0_ram_s register brperr0 0x3B1D0 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_D0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_D0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_D0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_D0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_D0_SET ns_noc_io_spio_soc_ip.csr 118182 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_DC0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_DC0_SET ns_noc_io_spio_soc_ip.csr 118193 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SB0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SB0_SET ns_noc_io_spio_soc_ip.csr 118204 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SBC0_SET ns_noc_io_spio_soc_ip.csr 118216 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_PK0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_PK0_SET ns_noc_io_spio_soc_ip.csr 118227 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 118238 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_D1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_D1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_D1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_D1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_D1_SET ns_noc_io_spio_soc_ip.csr 118249 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_DC1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_DC1_SET ns_noc_io_spio_soc_ip.csr 118260 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SB1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SB1_SET ns_noc_io_spio_soc_ip.csr 118271 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_SBC1_SET ns_noc_io_spio_soc_ip.csr 118283 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_PK1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_PK1_SET ns_noc_io_spio_soc_ip.csr 118294 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 118305 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 118316 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 118327 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 118338 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 118349 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 118360 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 118371 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_brperr1 bridge_spio_sp_main0_ram_s_14_11_brperr1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 118488 spio_sp_main0_ram_s register brperr1 0x3B1D8 R 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 118410 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 118421 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 118432 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 118443 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 118454 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 118465 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 118476 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERR1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 118487 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_brperrm0 bridge_spio_sp_main0_ram_s_14_11_brperrm0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 118709 spio_sp_main0_ram_s register brperrm0 0x3B1E0 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_D0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_D0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_D0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_D0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_D0_SET ns_noc_io_spio_soc_ip.csr 118515 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_DC0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_DC0_SET ns_noc_io_spio_soc_ip.csr 118527 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SB0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SB0_SET ns_noc_io_spio_soc_ip.csr 118538 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SBC0_SET ns_noc_io_spio_soc_ip.csr 118550 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_PK0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_PK0_SET ns_noc_io_spio_soc_ip.csr 118562 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 118573 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_D1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_D1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_D1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_D1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_D1_SET ns_noc_io_spio_soc_ip.csr 118584 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_DC1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_DC1_SET ns_noc_io_spio_soc_ip.csr 118596 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SB1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SB1_SET ns_noc_io_spio_soc_ip.csr 118607 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_SBC1_SET ns_noc_io_spio_soc_ip.csr 118619 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_PK1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_PK1_SET ns_noc_io_spio_soc_ip.csr 118631 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 118642 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 118653 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 118664 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 118675 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 118686 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 118697 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 118708 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_sp_main0_ram_s_14_11_brperrm1 bridge_spio_sp_main0_ram_s_14_11_brperrm1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 118814 spio_sp_main0_ram_s register brperrm1 0x3B1E8 R 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_ram_s_14_11_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 118736 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 118747 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 118758 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 118769 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 118780 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 118791 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 118802 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_RAM_S_14_11_BRPERRM1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 118813 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_cgc bridge_spio_sp_main0_rom_s_15_6_as_cgc SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGC_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGC_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGC_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 118851 spio_sp_main0_rom_s register as_cgc 0x3DC10 R/W 0x0000000000000064 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_as_cgc Programmable intervals used by coarse clock gating logic. This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGC_HYSTERESIS_COUNTER_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGC_HYSTERESIS_COUNTER_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGC_HYSTERESIS_COUNTER_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGC_HYSTERESIS_COUNTER_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGC_HYSTERESIS_COUNTER_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGC_HYSTERESIS_COUNTER_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGC_HYSTERESIS_COUNTER_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_spio_soc_ip.csr 118839 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGC_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGC_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGC_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGC_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGC_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGC_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGC_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGC_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 118850 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_cgo bridge_spio_sp_main0_rom_s_15_6_as_cgo SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGO_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGO_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGO_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGO_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 118886 spio_sp_main0_rom_s register as_cgo 0x3DC18 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_as_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the slave bridge. false false false false FPO SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGO_FPO_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGO_FPO_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGO_FPO_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGO_FPO_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGO_FPO_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGO_FPO_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGO_FPO_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGO_FPO_SET ns_noc_io_spio_soc_ip.csr 118874 FPO 1'b1: Clock gating override enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGO_UNSD_63_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGO_UNSD_63_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGO_UNSD_63_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGO_UNSD_63_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGO_UNSD_63_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGO_UNSD_63_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGO_UNSD_63_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CGO_UNSD_63_1_SET ns_noc_io_spio_soc_ip.csr 118885 UNSD_63_1 63 1 0x0000000000000000 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_sts bridge_spio_sp_main0_rom_s_15_6_as_sts SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 118960 spio_sp_main0_rom_s register as_sts 0x3DD00 R 0x000000000000000c Spio_noc_bridge_spio_sp_main0_rom_s_15_6_as_sts Slave bridge status bits. false false false false WOF SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_WOF_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_WOF_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_WOF_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_WOF_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_WOF_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_WOF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_WOF_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_WOF_SET ns_noc_io_spio_soc_ip.csr 118909 WOF 1'b1: Maximum number of supported write commands are outstanding to the attached slave device awaiting response, no more write commands will be issued to slave till responses are received. 1'b0: Slave device can expect more write commands from NoC 0 0 0x0 R ROF SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_ROF_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_ROF_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_ROF_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_ROF_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_ROF_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_ROF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_ROF_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_ROF_SET ns_noc_io_spio_soc_ip.csr 118925 ROF 1'b1: Maximum number of supported read commands are outstanding to the attached slave device awaiting response, no more read commands will be issued to slave till responses are received. 1'b0: Slave bridge can accept more read commands from the NoC 1 1 0x0 R WOE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_WOE_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_WOE_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_WOE_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_WOE_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_WOE_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_WOE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_WOE_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_WOE_SET ns_noc_io_spio_soc_ip.csr 118937 WOE 1'b1: There are no write commands outstanding to the attached slave device 2 2 0x1 R ROE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_ROE_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_ROE_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_ROE_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_ROE_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_ROE_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_ROE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_ROE_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_ROE_SET ns_noc_io_spio_soc_ip.csr 118949 ROE 1'b1: There are no read commands outstanding to the attached slave device 3 3 0x1 R UNSD_63_4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_UNSD_63_4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_UNSD_63_4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_UNSD_63_4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_UNSD_63_4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_UNSD_63_4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_UNSD_63_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_UNSD_63_4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_STS_UNSD_63_4_SET ns_noc_io_spio_soc_ip.csr 118959 UNSD_63_4 63 4 0x000000000000000 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_bridge_id bridge_spio_sp_main0_rom_s_15_6_as_bridge_id SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_BRIDGE_ID_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_BRIDGE_ID_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_BRIDGE_ID_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_BRIDGE_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 118990 spio_sp_main0_rom_s register as_bridge_id 0x3DD08 R 0x000000000000000f Spio_noc_bridge_spio_sp_main0_rom_s_15_6_as_bridge_id Unique identifier assigned to the slave bridge. false false false false ID SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_BRIDGE_ID_ID_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_BRIDGE_ID_ID_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_BRIDGE_ID_ID_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_BRIDGE_ID_ID_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_BRIDGE_ID_ID_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_BRIDGE_ID_ID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_BRIDGE_ID_ID_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_BRIDGE_ID_ID_SET ns_noc_io_spio_soc_ip.csr 118979 ID Unique bridge ID 15 0 0x000f R UNSD_63_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_BRIDGE_ID_UNSD_63_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_BRIDGE_ID_UNSD_63_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_BRIDGE_ID_UNSD_63_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_BRIDGE_ID_UNSD_63_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_BRIDGE_ID_UNSD_63_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_BRIDGE_ID_UNSD_63_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_BRIDGE_ID_UNSD_63_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_spio_soc_ip.csr 118989 UNSD_63_16 63 16 0x000000000000 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_err bridge_spio_sp_main0_rom_s_15_6_as_err SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 119343 spio_sp_main0_rom_s register as_err 0x3DE00 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_as_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E0_SET ns_noc_io_spio_soc_ip.csr 119011 E0 1'b1: Read decode error response: Decode error response received from slave device for read command 0 0 0x0 R/W E1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E1_SET ns_noc_io_spio_soc_ip.csr 119023 E1 1'b1: Read slave error response: Slave error response received from slave device for read command 1 1 0x0 R/W E2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E2_SET ns_noc_io_spio_soc_ip.csr 119036 E2 1'b1: [FATAL] Unknown read response destination: RID from read response produces a destination which is not present in the routing table 2 2 0x0 R/W E3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E3_SET ns_noc_io_spio_soc_ip.csr 119050 E3 1'b1: [FATAL] Interleaved read response: Interleaved read response. This can occur if interleaved read response is received from a slave device for which a de-interleaver was not specified 3 3 0x0 R/W E4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E4_SET ns_noc_io_spio_soc_ip.csr 119062 E4 1'b1: Read command modified: A read command which was marked as non-modifiable was modified by the slave bridge 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_UNSD_15_5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_UNSD_15_5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_UNSD_15_5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_UNSD_15_5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_UNSD_15_5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_UNSD_15_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_UNSD_15_5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 119073 UNSD_15_5 15 5 0x000 R E16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E16_SET ns_noc_io_spio_soc_ip.csr 119085 E16 1'b1: Write decode error response: Decode error response received from slave device for write command 16 16 0x0 R/W E17 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E17_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E17_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E17_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E17_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E17_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E17_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E17_SET ns_noc_io_spio_soc_ip.csr 119097 E17 1'b1: Write slave error response: Slave error response received from slave device for write command 17 17 0x0 R/W E18 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E18_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E18_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E18_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E18_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E18_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E18_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E18_SET ns_noc_io_spio_soc_ip.csr 119110 E18 1'b1: [FATAL] Unknown write response destination: BID from write response produces a destination which is not present in the routing table 18 18 0x0 R/W E19 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E19_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E19_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E19_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E19_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E19_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E19_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E19_SET ns_noc_io_spio_soc_ip.csr 119122 E19 1'b1: Write command modified: A write command which was marked as non-modifiable was modified by the slave bridge 19 19 0x0 R/W UNSD_31_20 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_UNSD_31_20_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_UNSD_31_20_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_UNSD_31_20_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_UNSD_31_20_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_UNSD_31_20_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_UNSD_31_20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_UNSD_31_20_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_UNSD_31_20_SET ns_noc_io_spio_soc_ip.csr 119133 UNSD_31_20 31 20 0x000 R E32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E32_SET ns_noc_io_spio_soc_ip.csr 119145 E32 1'b1: [FATAL] Traffic sent to a noc layer which is power gated 32 32 0x0 R/W E33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E33_SET ns_noc_io_spio_soc_ip.csr 119156 E33 1'b1: [FATAL] Parity error in config/status registers 33 33 0x0 R/W E34 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E34_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E34_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E34_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E34_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E34_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E34_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E34_SET ns_noc_io_spio_soc_ip.csr 119167 E34 1'b1: [FATAL] RDATA Parity error 34 34 0x0 R/W E35 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E35_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E35_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E35_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E35_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E35_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E35_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E35_SET ns_noc_io_spio_soc_ip.csr 119178 E35 1'b1: [FATAL] RRESP Parity error 35 35 0x0 R/W E36 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E36_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E36_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E36_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E36_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E36_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E36_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E36_SET ns_noc_io_spio_soc_ip.csr 119189 E36 1'b1: [FATAL] BRESP Parity error 36 36 0x0 R/W E37 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E37_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E37_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E37_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E37_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E37_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E37_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E37_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E37_SET ns_noc_io_spio_soc_ip.csr 119200 E37 1'b1: [FATAL] AC Parity error 37 37 0x0 R/W E38 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E38_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E38_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E38_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E38_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E38_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E38_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E38_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E38_SET ns_noc_io_spio_soc_ip.csr 119211 E38 1'b1: [FATAL] ACADDR Parity error 38 38 0x0 R/W E39 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E39_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E39_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E39_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E39_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E39_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E39_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E39_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E39_SET ns_noc_io_spio_soc_ip.csr 119223 E39 1'b1: [FATAL] R Ch Cmdtbl Parity Err 39 39 0x0 R E40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E40_SET ns_noc_io_spio_soc_ip.csr 119235 E40 1'b1: [FATAL] B Ch Cmdtbl Parity Err 40 40 0x0 R E41 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E41_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E41_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E41_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E41_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E41_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E41_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E41_SET ns_noc_io_spio_soc_ip.csr 119247 E41 1'b1: [FATAL] Rx Fifo Parity Err 41 41 0x0 R E42 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E42_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E42_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E42_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E42_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E42_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E42_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E42_SET ns_noc_io_spio_soc_ip.csr 119259 E42 1'b1: [FATAL] CRCD Ch Reorder Buffer Parity Err 42 42 0x0 R E43 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E43_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E43_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E43_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E43_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E43_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E43_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E43_SET ns_noc_io_spio_soc_ip.csr 119271 E43 1'b1: [FATAL] Ack Ch Wack Reorder Buffer Parity Err 43 43 0x0 R E44 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E44_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E44_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E44_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E44_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E44_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E44_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E44_SET ns_noc_io_spio_soc_ip.csr 119283 E44 1'b1: [FATAL] Ack Ch Rack Reorder Buffer Parity Err 44 44 0x0 R E45 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E45_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E45_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E45_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E45_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E45_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E45_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E45_SET ns_noc_io_spio_soc_ip.csr 119295 E45 1'b1: [FATAL] B Ch Drain Fifo Parity Err 45 45 0x0 R E46 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E46_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E46_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E46_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E46_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E46_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E46_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E46_SET ns_noc_io_spio_soc_ip.csr 119307 E46 1'b1: [FATAL] R Ch Flush Fifo Parity Err 46 46 0x0 R E47 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E47_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E47_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E47_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E47_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E47_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E47_SET ns_noc_io_spio_soc_ip.csr 119319 E47 1'b1: [FATAL] R Ch Deinterleaver Cmdtbl Parity Err 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_E48_SET ns_noc_io_spio_soc_ip.csr 119331 E48 1'b1: [FATAL] R Ch Deinterleaver Data Buffer Parity Err 48 48 0x0 R UNSD_63_49 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_UNSD_63_49_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_UNSD_63_49_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_UNSD_63_49_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_UNSD_63_49_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_UNSD_63_49_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_UNSD_63_49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_UNSD_63_49_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_ERR_UNSD_63_49_SET ns_noc_io_spio_soc_ip.csr 119342 UNSD_63_49 63 49 0x0000 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_intm bridge_spio_sp_main0_rom_s_15_6_as_intm SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 119683 spio_sp_main0_rom_s register as_intm 0x3DE40 R/W 0x0000007d000b0013 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_as_intm Interrupt mask register.Individual bit positions match the error bit positions in AS_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M0_SET ns_noc_io_spio_soc_ip.csr 119364 M0 Mask interrupts for read channel 0 0 0x1 R/W M1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M1_SET ns_noc_io_spio_soc_ip.csr 119375 M1 Mask interrupts for read channel 1 1 0x1 R/W M2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M2_SET ns_noc_io_spio_soc_ip.csr 119386 M2 Mask interrupts for read channel 2 2 0x0 R/W M3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M3_SET ns_noc_io_spio_soc_ip.csr 119397 M3 Mask interrupts for read channel 3 3 0x0 R/W M4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M4_SET ns_noc_io_spio_soc_ip.csr 119408 M4 Mask interrupts for read channel 4 4 0x1 R/W UNSD_15_5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_UNSD_15_5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_UNSD_15_5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_UNSD_15_5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_UNSD_15_5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_UNSD_15_5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_UNSD_15_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_UNSD_15_5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 119419 UNSD_15_5 15 5 0x000 R M16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M16_SET ns_noc_io_spio_soc_ip.csr 119430 M16 Mask interrupts for write channel 16 16 0x1 R/W M17 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M17_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M17_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M17_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M17_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M17_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M17_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M17_SET ns_noc_io_spio_soc_ip.csr 119441 M17 Mask interrupts for write channel 17 17 0x1 R/W M18 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M18_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M18_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M18_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M18_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M18_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M18_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M18_SET ns_noc_io_spio_soc_ip.csr 119452 M18 Mask interrupts for write channel 18 18 0x0 R/W M19 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M19_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M19_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M19_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M19_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M19_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M19_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M19_SET ns_noc_io_spio_soc_ip.csr 119463 M19 Mask interrupts for write channel 19 19 0x1 R/W UNSD_31_20 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_UNSD_31_20_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_UNSD_31_20_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_UNSD_31_20_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_UNSD_31_20_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_UNSD_31_20_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_UNSD_31_20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_UNSD_31_20_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_UNSD_31_20_SET ns_noc_io_spio_soc_ip.csr 119474 UNSD_31_20 31 20 0x000 R M32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M32_SET ns_noc_io_spio_soc_ip.csr 119485 M32 Mask interrupt on traffic to PG layer 32 32 0x1 R/W M33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M33_SET ns_noc_io_spio_soc_ip.csr 119496 M33 Mask interrupt on csr parity errors 33 33 0x0 R/W M34 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M34_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M34_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M34_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M34_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M34_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M34_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M34_SET ns_noc_io_spio_soc_ip.csr 119507 M34 RDATA parity interrupt Mask 34 34 0x1 R/W M35 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M35_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M35_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M35_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M35_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M35_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M35_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M35_SET ns_noc_io_spio_soc_ip.csr 119518 M35 RRESP parity interrupt Mask 35 35 0x1 R/W M36 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M36_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M36_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M36_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M36_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M36_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M36_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M36_SET ns_noc_io_spio_soc_ip.csr 119529 M36 BRESP parity interrupt Mask 36 36 0x1 R/W M37 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M37_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M37_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M37_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M37_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M37_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M37_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M37_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M37_SET ns_noc_io_spio_soc_ip.csr 119540 M37 AC parity interrupt Mask 37 37 0x1 R/W M38 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M38_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M38_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M38_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M38_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M38_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M38_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M38_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_M38_SET ns_noc_io_spio_soc_ip.csr 119551 M38 ACADDR parity interrupt Mask 38 38 0x1 R/W E39 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E39_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E39_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E39_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E39_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E39_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E39_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E39_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E39_SET ns_noc_io_spio_soc_ip.csr 119563 E39 1'b1: R Ch Cmdtbl Parity Err Intr Mask 39 39 0x0 R E40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E40_SET ns_noc_io_spio_soc_ip.csr 119575 E40 1'b1: B Ch Cmdtbl Parity Err Intr Mask 40 40 0x0 R E41 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E41_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E41_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E41_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E41_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E41_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E41_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E41_SET ns_noc_io_spio_soc_ip.csr 119587 E41 1'b1: Rx Fifo Parity Err Intr Mask 41 41 0x0 R E42 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E42_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E42_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E42_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E42_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E42_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E42_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E42_SET ns_noc_io_spio_soc_ip.csr 119599 E42 1'b1: CRCD Ch Reorder Buffer Parity Err Intr Mask 42 42 0x0 R E43 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E43_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E43_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E43_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E43_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E43_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E43_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E43_SET ns_noc_io_spio_soc_ip.csr 119611 E43 1'b1: Ack Ch Wack Reorder Buffer Parity Err IntrMask 43 43 0x0 R E44 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E44_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E44_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E44_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E44_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E44_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E44_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E44_SET ns_noc_io_spio_soc_ip.csr 119623 E44 1'b1: Ack Ch Rack Reorder Buffer Parity Err Intr Mask 44 44 0x0 R E45 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E45_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E45_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E45_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E45_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E45_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E45_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E45_SET ns_noc_io_spio_soc_ip.csr 119635 E45 1'b1: B Ch Drain Fifo Parity Err Intr Mask 45 45 0x0 R E46 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E46_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E46_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E46_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E46_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E46_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E46_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E46_SET ns_noc_io_spio_soc_ip.csr 119647 E46 1'b1: R Ch Flush Fifo Parity Err Intr Mask 46 46 0x0 R E47 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E47_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E47_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E47_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E47_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E47_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E47_SET ns_noc_io_spio_soc_ip.csr 119659 E47 1'b1: R Ch Deinterleaver Cmdtbl Parity Err Intr Mask 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_E48_SET ns_noc_io_spio_soc_ip.csr 119671 E48 1'b1: R Ch Deinterleaver Data Buffer Parity Err Intr Mask 48 48 0x0 R UNSD_63_49 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_UNSD_63_49_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_UNSD_63_49_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_UNSD_63_49_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_UNSD_63_49_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_UNSD_63_49_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_UNSD_63_49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_UNSD_63_49_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_INTM_UNSD_63_49_SET ns_noc_io_spio_soc_ip.csr 119682 UNSD_63_49 63 49 0x0000 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_ccmd bridge_spio_sp_main0_rom_s_15_6_as_ccmd SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 119758 spio_sp_main0_rom_s register as_ccmd 0x3DF00 R/W 0x0000000003000000 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_as_ccmd Not applicable for current release. false false false false UNSD_23_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_UNSD_23_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_UNSD_23_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_UNSD_23_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_UNSD_23_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_UNSD_23_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_UNSD_23_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_UNSD_23_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_UNSD_23_0_SET ns_noc_io_spio_soc_ip.csr 119701 UNSD_23_0 23 0 0x000000 R rdy SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_RDY_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_RDY_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_RDY_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_RDY_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_RDY_SET ns_noc_io_spio_soc_ip.csr 119712 rdy 1'b1: Ready 24 24 0x1 R/W val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_VAL_SET ns_noc_io_spio_soc_ip.csr 119723 val 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_UNSD_27_26_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_UNSD_27_26_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_UNSD_27_26_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_UNSD_27_26_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_UNSD_27_26_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_UNSD_27_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_UNSD_27_26_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_UNSD_27_26_SET ns_noc_io_spio_soc_ip.csr 119734 UNSD_27_26 27 26 0x0 R intfid SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_INTFID_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_INTFID_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_INTFID_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_INTFID_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_INTFID_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_INTFID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_INTFID_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_INTFID_SET ns_noc_io_spio_soc_ip.csr 119746 intfid 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_63_31 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_UNSD_63_31_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_UNSD_63_31_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_UNSD_63_31_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_UNSD_63_31_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_UNSD_63_31_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_UNSD_63_31_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_UNSD_63_31_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMD_UNSD_63_31_SET ns_noc_io_spio_soc_ip.csr 119757 UNSD_63_31 63 31 0x000000000 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_ccmdmsk bridge_spio_sp_main0_rom_s_15_6_as_ccmdmsk SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 119810 spio_sp_main0_rom_s register as_ccmdmsk 0x3DF08 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_as_ccmdmsk Not applicable for current release. false false false false UNSD_23_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_UNSD_23_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_UNSD_23_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_UNSD_23_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_UNSD_23_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_UNSD_23_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_UNSD_23_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_UNSD_23_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_UNSD_23_0_SET ns_noc_io_spio_soc_ip.csr 119776 UNSD_23_0 23 0 0x000000 R rdy SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_RDY_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_RDY_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_RDY_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_RDY_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_RDY_SET ns_noc_io_spio_soc_ip.csr 119787 rdy 1'b1: Ready 24 24 0x0 R/W val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_VAL_SET ns_noc_io_spio_soc_ip.csr 119798 val 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_UNSD_63_26_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_UNSD_63_26_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_UNSD_63_26_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_UNSD_63_26_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_UNSD_63_26_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_UNSD_63_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_UNSD_63_26_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CCMDMSK_UNSD_63_26_SET ns_noc_io_spio_soc_ip.csr 119809 UNSD_63_26 63 26 0x0000000000 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_cntr bridge_spio_sp_main0_rom_s_15_6_as_cntr SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CNTR_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CNTR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CNTR_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CNTR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 119840 spio_sp_main0_rom_s register as_cntr 0x3DF10 R 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_as_cntr Not applicable for current release. false false false false CNTR SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CNTR_CNTR_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CNTR_CNTR_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CNTR_CNTR_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CNTR_CNTR_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CNTR_CNTR_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CNTR_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CNTR_CNTR_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CNTR_CNTR_SET ns_noc_io_spio_soc_ip.csr 119829 CNTR Counter 31 0 0x00000000 R UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CNTR_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CNTR_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CNTR_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CNTR_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CNTR_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CNTR_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CNTR_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_CNTR_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 119839 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_arovrd bridge_spio_sp_main0_rom_s_15_6_as_arovrd SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 119953 spio_sp_main0_rom_s register as_arovrd 0x3DF18 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_as_arovrd AR Overrides. false false false false arcache_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 119858 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 119871 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 119882 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 119893 UNSD_11_11 11 11 0x0 R arprot_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 119906 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 119917 UNSD_15_15 15 15 0x0 R arqos_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 119928 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_ARQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 119941 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AROVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 119952 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_as_awovrd bridge_spio_sp_main0_rom_s_15_6_as_awovrd SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 120066 spio_sp_main0_rom_s register as_awovrd 0x3DF20 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_as_awovrd AW Overrides. false false false false awcache_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 119971 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 119984 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 119995 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 120006 UNSD_11_11 11 11 0x0 R awprot_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 120019 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 120030 UNSD_15_15 15 15 0x0 R awqos_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 120041 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_AWQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 120054 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_AS_AWOVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 120065 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_p_0 bridge_spio_sp_main0_rom_s_15_6_p_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 120131 spio_sp_main0_rom_s register p_0 0x3F000 R/W 0x00000003 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_0_SET ns_noc_io_spio_soc_ip.csr 120094 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_1_SET ns_noc_io_spio_soc_ip.csr 120106 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_2_SET ns_noc_io_spio_soc_ip.csr 120118 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_0_WT_QOS_3_SET ns_noc_io_spio_soc_ip.csr 120130 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_p_1 bridge_spio_sp_main0_rom_s_15_6_p_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 120197 spio_sp_main0_rom_s register p_1 0x3F008 R 0x00000000 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_4_SET ns_noc_io_spio_soc_ip.csr 120160 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_5_SET ns_noc_io_spio_soc_ip.csr 120172 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_6_SET ns_noc_io_spio_soc_ip.csr 120184 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_1_WT_QOS_7_SET ns_noc_io_spio_soc_ip.csr 120196 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_p_2 bridge_spio_sp_main0_rom_s_15_6_p_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 120263 spio_sp_main0_rom_s register p_2 0x3F010 R 0x00000000 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_8_SET ns_noc_io_spio_soc_ip.csr 120226 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_9_SET ns_noc_io_spio_soc_ip.csr 120238 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_10_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_10_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_10_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_10_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_10_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_10_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_10_SET ns_noc_io_spio_soc_ip.csr 120250 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_2_WT_QOS_11_SET ns_noc_io_spio_soc_ip.csr 120262 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_p_3 bridge_spio_sp_main0_rom_s_15_6_p_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 120329 spio_sp_main0_rom_s register p_3 0x3F018 R 0x00000000 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_12_SET ns_noc_io_spio_soc_ip.csr 120292 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_13_SET ns_noc_io_spio_soc_ip.csr 120304 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_14_SET ns_noc_io_spio_soc_ip.csr 120316 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_P_3_WT_QOS_15_SET ns_noc_io_spio_soc_ip.csr 120328 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_txe bridge_spio_sp_main0_rom_s_15_6_txe SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 120475 spio_sp_main0_rom_s register txe 0x3F040 R/W 0x00000000 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_TRANS_WITHOUT_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_TRANS_WITHOUT_SOP_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_TRANS_WITHOUT_SOP_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_TRANS_WITHOUT_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_TRANS_WITHOUT_SOP_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_TRANS_WITHOUT_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_TRANS_WITHOUT_SOP_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_spio_soc_ip.csr 120356 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_SOP_AFTER_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_SOP_AFTER_SOP_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_SOP_AFTER_SOP_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_SOP_AFTER_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_SOP_AFTER_SOP_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_SOP_AFTER_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_SOP_AFTER_SOP_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_SOP_AFTER_SOP_SET ns_noc_io_spio_soc_ip.csr 120368 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 120383 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 120396 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_spio_soc_ip.csr 120410 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_spio_soc_ip.csr 120424 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_spio_soc_ip.csr 120438 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_spio_soc_ip.csr 120452 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 120463 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXE_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 120474 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_txem bridge_spio_sp_main0_rom_s_15_6_txem SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 120554 spio_sp_main0_rom_s register txem 0x3F048 R/W 0x00000008 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_UNSD_1_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_UNSD_1_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_UNSD_1_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_UNSD_1_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_UNSD_1_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_UNSD_1_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_UNSD_1_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_UNSD_1_0_SET ns_noc_io_spio_soc_ip.csr 120498 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 120509 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 120520 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_UNSD_7_4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_UNSD_7_4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_UNSD_7_4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_UNSD_7_4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_UNSD_7_4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_UNSD_7_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_UNSD_7_4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_UNSD_7_4_SET ns_noc_io_spio_soc_ip.csr 120531 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 120542 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_TXEM_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 120553 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_btus_0 bridge_spio_sp_main0_rom_s_15_6_btus_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 120922 spio_sp_main0_rom_s register btus_0 0x3F058 R 0x00000000 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_A_SET ns_noc_io_spio_soc_ip.csr 120580 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_B_SET ns_noc_io_spio_soc_ip.csr 120591 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_C_SET ns_noc_io_spio_soc_ip.csr 120602 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L0_D_SET ns_noc_io_spio_soc_ip.csr 120613 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_A_SET ns_noc_io_spio_soc_ip.csr 120624 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_B_SET ns_noc_io_spio_soc_ip.csr 120635 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_C_SET ns_noc_io_spio_soc_ip.csr 120646 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L1_D_SET ns_noc_io_spio_soc_ip.csr 120657 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_A_SET ns_noc_io_spio_soc_ip.csr 120668 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_B_SET ns_noc_io_spio_soc_ip.csr 120679 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_C_SET ns_noc_io_spio_soc_ip.csr 120690 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L2_D_SET ns_noc_io_spio_soc_ip.csr 120701 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_A_SET ns_noc_io_spio_soc_ip.csr 120712 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_B_SET ns_noc_io_spio_soc_ip.csr 120723 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_C_SET ns_noc_io_spio_soc_ip.csr 120734 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L3_D_SET ns_noc_io_spio_soc_ip.csr 120745 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_A_SET ns_noc_io_spio_soc_ip.csr 120756 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_B_SET ns_noc_io_spio_soc_ip.csr 120767 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_C_SET ns_noc_io_spio_soc_ip.csr 120778 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L4_D_SET ns_noc_io_spio_soc_ip.csr 120789 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_A_SET ns_noc_io_spio_soc_ip.csr 120800 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_B_SET ns_noc_io_spio_soc_ip.csr 120811 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_C_SET ns_noc_io_spio_soc_ip.csr 120822 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L5_D_SET ns_noc_io_spio_soc_ip.csr 120833 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_A_SET ns_noc_io_spio_soc_ip.csr 120844 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_B_SET ns_noc_io_spio_soc_ip.csr 120855 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_C_SET ns_noc_io_spio_soc_ip.csr 120866 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L6_D_SET ns_noc_io_spio_soc_ip.csr 120877 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_A_SET ns_noc_io_spio_soc_ip.csr 120888 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_B_SET ns_noc_io_spio_soc_ip.csr 120899 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_C_SET ns_noc_io_spio_soc_ip.csr 120910 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_0_L7_D_SET ns_noc_io_spio_soc_ip.csr 120921 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_btus_1 bridge_spio_sp_main0_rom_s_15_6_btus_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 121290 spio_sp_main0_rom_s register btus_1 0x3F060 R 0x00000000 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_A_SET ns_noc_io_spio_soc_ip.csr 120948 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_B_SET ns_noc_io_spio_soc_ip.csr 120959 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_C_SET ns_noc_io_spio_soc_ip.csr 120970 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L8_D_SET ns_noc_io_spio_soc_ip.csr 120981 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_A_SET ns_noc_io_spio_soc_ip.csr 120992 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_B_SET ns_noc_io_spio_soc_ip.csr 121003 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_C_SET ns_noc_io_spio_soc_ip.csr 121014 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L9_D_SET ns_noc_io_spio_soc_ip.csr 121025 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_A_SET ns_noc_io_spio_soc_ip.csr 121036 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_B_SET ns_noc_io_spio_soc_ip.csr 121047 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_C_SET ns_noc_io_spio_soc_ip.csr 121058 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L10_D_SET ns_noc_io_spio_soc_ip.csr 121069 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_A_SET ns_noc_io_spio_soc_ip.csr 121080 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_B_SET ns_noc_io_spio_soc_ip.csr 121091 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_C_SET ns_noc_io_spio_soc_ip.csr 121102 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L11_D_SET ns_noc_io_spio_soc_ip.csr 121113 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_A_SET ns_noc_io_spio_soc_ip.csr 121124 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_B_SET ns_noc_io_spio_soc_ip.csr 121135 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_C_SET ns_noc_io_spio_soc_ip.csr 121146 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L12_D_SET ns_noc_io_spio_soc_ip.csr 121157 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_A_SET ns_noc_io_spio_soc_ip.csr 121168 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_B_SET ns_noc_io_spio_soc_ip.csr 121179 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_C_SET ns_noc_io_spio_soc_ip.csr 121190 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L13_D_SET ns_noc_io_spio_soc_ip.csr 121201 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_A_SET ns_noc_io_spio_soc_ip.csr 121212 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_B_SET ns_noc_io_spio_soc_ip.csr 121223 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_C_SET ns_noc_io_spio_soc_ip.csr 121234 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L14_D_SET ns_noc_io_spio_soc_ip.csr 121245 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_A_SET ns_noc_io_spio_soc_ip.csr 121256 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_B_SET ns_noc_io_spio_soc_ip.csr 121267 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_C_SET ns_noc_io_spio_soc_ip.csr 121278 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTUS_1_L15_D_SET ns_noc_io_spio_soc_ip.csr 121289 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_btrl_0 bridge_spio_sp_main0_rom_s_15_6_btrl_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 121366 spio_sp_main0_rom_s register btrl_0 0x3F080 R 0x00000000 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_WT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_WT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_WT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_WT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_WT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_WT_SET ns_noc_io_spio_soc_ip.csr 121314 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 121325 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_CNT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_CNT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_CNT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_CNT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_CNT_SET ns_noc_io_spio_soc_ip.csr 121340 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_EN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_EN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_EN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_EN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_EN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_EN_SET ns_noc_io_spio_soc_ip.csr 121354 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_0_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 121365 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_btrl_1 bridge_spio_sp_main0_rom_s_15_6_btrl_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 121442 spio_sp_main0_rom_s register btrl_1 0x3F088 R 0x00000000 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_WT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_WT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_WT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_WT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_WT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_WT_SET ns_noc_io_spio_soc_ip.csr 121390 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 121401 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_CNT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_CNT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_CNT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_CNT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_CNT_SET ns_noc_io_spio_soc_ip.csr 121416 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_EN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_EN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_EN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_EN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_EN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_EN_SET ns_noc_io_spio_soc_ip.csr 121430 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_1_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 121441 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_btrl_2 bridge_spio_sp_main0_rom_s_15_6_btrl_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 121518 spio_sp_main0_rom_s register btrl_2 0x3F090 R 0x00000000 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_WT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_WT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_WT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_WT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_WT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_WT_SET ns_noc_io_spio_soc_ip.csr 121466 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 121477 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_CNT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_CNT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_CNT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_CNT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_CNT_SET ns_noc_io_spio_soc_ip.csr 121492 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_EN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_EN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_EN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_EN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_EN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_EN_SET ns_noc_io_spio_soc_ip.csr 121506 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_2_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 121517 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_btrl_3 bridge_spio_sp_main0_rom_s_15_6_btrl_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 121594 spio_sp_main0_rom_s register btrl_3 0x3F098 R 0x00000000 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_WT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_WT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_WT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_WT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_WT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_WT_SET ns_noc_io_spio_soc_ip.csr 121542 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 121553 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_CNT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_CNT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_CNT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_CNT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_CNT_SET ns_noc_io_spio_soc_ip.csr 121568 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_EN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_EN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_EN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_EN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_EN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_EN_SET ns_noc_io_spio_soc_ip.csr 121582 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTRL_3_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 121593 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_btperr bridge_spio_sp_main0_rom_s_15_6_btperr SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 121796 spio_sp_main0_rom_s register btperr 0x3F0A8 R/W 0x00000000 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L0_SET ns_noc_io_spio_soc_ip.csr 121619 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L1_SET ns_noc_io_spio_soc_ip.csr 121630 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L2_SET ns_noc_io_spio_soc_ip.csr 121641 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L3_SET ns_noc_io_spio_soc_ip.csr 121652 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L4_SET ns_noc_io_spio_soc_ip.csr 121663 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L5_SET ns_noc_io_spio_soc_ip.csr 121674 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L6_SET ns_noc_io_spio_soc_ip.csr 121685 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L7_SET ns_noc_io_spio_soc_ip.csr 121696 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L8_SET ns_noc_io_spio_soc_ip.csr 121707 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L9_SET ns_noc_io_spio_soc_ip.csr 121718 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L10_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L10_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L10_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L10_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L10_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L10_SET ns_noc_io_spio_soc_ip.csr 121729 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L11_SET ns_noc_io_spio_soc_ip.csr 121740 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L12_SET ns_noc_io_spio_soc_ip.csr 121751 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L13_SET ns_noc_io_spio_soc_ip.csr 121762 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L14_SET ns_noc_io_spio_soc_ip.csr 121773 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_L15_SET ns_noc_io_spio_soc_ip.csr 121784 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_UNSD_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERR_UNSD_SET ns_noc_io_spio_soc_ip.csr 121795 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_btperrm bridge_spio_sp_main0_rom_s_15_6_btperrm SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 121996 spio_sp_main0_rom_s register btperrm 0x3F0B0 R/W 0x00000000 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L0_SET ns_noc_io_spio_soc_ip.csr 121819 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L1_SET ns_noc_io_spio_soc_ip.csr 121830 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L2_SET ns_noc_io_spio_soc_ip.csr 121841 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L3_SET ns_noc_io_spio_soc_ip.csr 121852 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L4_SET ns_noc_io_spio_soc_ip.csr 121863 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L5_SET ns_noc_io_spio_soc_ip.csr 121874 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L6_SET ns_noc_io_spio_soc_ip.csr 121885 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L7_SET ns_noc_io_spio_soc_ip.csr 121896 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L8_SET ns_noc_io_spio_soc_ip.csr 121907 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L9_SET ns_noc_io_spio_soc_ip.csr 121918 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L10_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L10_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L10_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L10_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L10_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L10_SET ns_noc_io_spio_soc_ip.csr 121929 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L11_SET ns_noc_io_spio_soc_ip.csr 121940 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L12_SET ns_noc_io_spio_soc_ip.csr 121951 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L13_SET ns_noc_io_spio_soc_ip.csr 121962 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L14_SET ns_noc_io_spio_soc_ip.csr 121973 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_L15_SET ns_noc_io_spio_soc_ip.csr 121984 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_UNSD_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BTPERRM_UNSD_SET ns_noc_io_spio_soc_ip.csr 121995 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_rxe bridge_spio_sp_main0_rom_s_15_6_rxe SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 122104 spio_sp_main0_rom_s register rxe 0x3F120 R/W 0x00000000 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_A_SET ns_noc_io_spio_soc_ip.csr 122024 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_B_SET ns_noc_io_spio_soc_ip.csr 122035 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_C_SET ns_noc_io_spio_soc_ip.csr 122046 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_CRC_OFLW_D_SET ns_noc_io_spio_soc_ip.csr 122057 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_EVC_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_EVC_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_EVC_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_EVC_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_EVC_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_EVC_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_EVC_OFLW_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_EVC_OFLW_SET ns_noc_io_spio_soc_ip.csr 122069 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 122080 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_EVC1_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_EVC1_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_EVC1_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_EVC1_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_EVC1_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_EVC1_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_EVC1_OFLW_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_EVC1_OFLW_SET ns_noc_io_spio_soc_ip.csr 122092 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXE_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 122103 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_rxem bridge_spio_sp_main0_rom_s_15_6_rxem SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 122176 spio_sp_main0_rom_s register rxem 0x3F128 R/W 0x00000050 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_UNSD_3_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_UNSD_3_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_UNSD_3_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_UNSD_3_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_UNSD_3_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_UNSD_3_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_UNSD_3_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_UNSD_3_0_SET ns_noc_io_spio_soc_ip.csr 122125 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_EVC_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_EVC_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_EVC_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_EVC_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_EVC_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_EVC_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_EVC_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_EVC_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 122139 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 122150 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_EVC1_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_EVC1_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_EVC1_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_EVC1_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_EVC1_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_EVC1_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_EVC1_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 122164 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_RXEM_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 122175 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_brs_0 bridge_spio_sp_main0_rom_s_15_6_brs_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 122450 spio_sp_main0_rom_s register brs_0 0x3F130 R 0x00000000 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 122200 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_0_SET ns_noc_io_spio_soc_ip.csr 122211 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_0_SET ns_noc_io_spio_soc_ip.csr 122222 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_0_SET ns_noc_io_spio_soc_ip.csr 122233 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_0_SET ns_noc_io_spio_soc_ip.csr 122244 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 122254 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 122265 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_1_SET ns_noc_io_spio_soc_ip.csr 122276 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_1_SET ns_noc_io_spio_soc_ip.csr 122287 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_1_SET ns_noc_io_spio_soc_ip.csr 122298 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_1_SET ns_noc_io_spio_soc_ip.csr 122309 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 122319 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 122330 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_2_SET ns_noc_io_spio_soc_ip.csr 122341 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_2_SET ns_noc_io_spio_soc_ip.csr 122352 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_2_SET ns_noc_io_spio_soc_ip.csr 122363 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_2_SET ns_noc_io_spio_soc_ip.csr 122374 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 122384 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 122395 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_V_3_SET ns_noc_io_spio_soc_ip.csr 122406 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_S_3_SET ns_noc_io_spio_soc_ip.csr 122417 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_B_3_SET ns_noc_io_spio_soc_ip.csr 122428 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_F_3_SET ns_noc_io_spio_soc_ip.csr 122439 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_0_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 122449 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_brs_1 bridge_spio_sp_main0_rom_s_15_6_brs_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 122724 spio_sp_main0_rom_s register brs_1 0x3F138 R 0x00000000 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 122474 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_0_SET ns_noc_io_spio_soc_ip.csr 122485 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_0_SET ns_noc_io_spio_soc_ip.csr 122496 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_0_SET ns_noc_io_spio_soc_ip.csr 122507 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_0_SET ns_noc_io_spio_soc_ip.csr 122518 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 122528 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 122539 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_1_SET ns_noc_io_spio_soc_ip.csr 122550 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_1_SET ns_noc_io_spio_soc_ip.csr 122561 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_1_SET ns_noc_io_spio_soc_ip.csr 122572 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_1_SET ns_noc_io_spio_soc_ip.csr 122583 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 122593 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 122604 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_2_SET ns_noc_io_spio_soc_ip.csr 122615 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_2_SET ns_noc_io_spio_soc_ip.csr 122626 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_2_SET ns_noc_io_spio_soc_ip.csr 122637 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_2_SET ns_noc_io_spio_soc_ip.csr 122648 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 122658 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 122669 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_V_3_SET ns_noc_io_spio_soc_ip.csr 122680 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_S_3_SET ns_noc_io_spio_soc_ip.csr 122691 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_B_3_SET ns_noc_io_spio_soc_ip.csr 122702 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_F_3_SET ns_noc_io_spio_soc_ip.csr 122713 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRS_1_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 122723 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_brus bridge_spio_sp_main0_rom_s_15_6_brus SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 122793 spio_sp_main0_rom_s register brus 0x3F1B0 R 0x00000000 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_A_SET ns_noc_io_spio_soc_ip.csr 122749 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_B_SET ns_noc_io_spio_soc_ip.csr 122760 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_C_SET ns_noc_io_spio_soc_ip.csr 122771 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_V_D_SET ns_noc_io_spio_soc_ip.csr 122782 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_UNSD_31_4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_UNSD_31_4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_UNSD_31_4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_UNSD_31_4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_UNSD_31_4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_UNSD_31_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_UNSD_31_4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRUS_UNSD_31_4_SET ns_noc_io_spio_soc_ip.csr 122792 UNSD_31_4 31 4 0x0000000 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_brperr0 bridge_spio_sp_main0_rom_s_15_6_brperr0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 123021 spio_sp_main0_rom_s register brperr0 0x3F1D0 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_D0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_D0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_D0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_D0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_D0_SET ns_noc_io_spio_soc_ip.csr 122831 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_DC0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_DC0_SET ns_noc_io_spio_soc_ip.csr 122842 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SB0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SB0_SET ns_noc_io_spio_soc_ip.csr 122853 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SBC0_SET ns_noc_io_spio_soc_ip.csr 122865 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_PK0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_PK0_SET ns_noc_io_spio_soc_ip.csr 122876 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 122887 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_D1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_D1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_D1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_D1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_D1_SET ns_noc_io_spio_soc_ip.csr 122898 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_DC1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_DC1_SET ns_noc_io_spio_soc_ip.csr 122909 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SB1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SB1_SET ns_noc_io_spio_soc_ip.csr 122920 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_SBC1_SET ns_noc_io_spio_soc_ip.csr 122932 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_PK1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_PK1_SET ns_noc_io_spio_soc_ip.csr 122943 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 122954 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 122965 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 122976 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 122987 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 122998 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 123009 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 123020 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_brperr1 bridge_spio_sp_main0_rom_s_15_6_brperr1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 123137 spio_sp_main0_rom_s register brperr1 0x3F1D8 R 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 123059 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 123070 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 123081 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 123092 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 123103 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 123114 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 123125 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERR1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 123136 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_brperrm0 bridge_spio_sp_main0_rom_s_15_6_brperrm0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 123358 spio_sp_main0_rom_s register brperrm0 0x3F1E0 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_D0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_D0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_D0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_D0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_D0_SET ns_noc_io_spio_soc_ip.csr 123164 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_DC0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_DC0_SET ns_noc_io_spio_soc_ip.csr 123176 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SB0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SB0_SET ns_noc_io_spio_soc_ip.csr 123187 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SBC0_SET ns_noc_io_spio_soc_ip.csr 123199 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_PK0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_PK0_SET ns_noc_io_spio_soc_ip.csr 123211 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 123222 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_D1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_D1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_D1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_D1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_D1_SET ns_noc_io_spio_soc_ip.csr 123233 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_DC1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_DC1_SET ns_noc_io_spio_soc_ip.csr 123245 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SB1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SB1_SET ns_noc_io_spio_soc_ip.csr 123256 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_SBC1_SET ns_noc_io_spio_soc_ip.csr 123268 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_PK1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_PK1_SET ns_noc_io_spio_soc_ip.csr 123280 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 123291 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 123302 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 123313 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 123324 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 123335 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 123346 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 123357 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_sp_main0_rom_s_15_6_brperrm1 bridge_spio_sp_main0_rom_s_15_6_brperrm1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 123463 spio_sp_main0_rom_s register brperrm1 0x3F1E8 R 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_rom_s_15_6_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 123385 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 123396 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 123407 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 123418 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 123429 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 123440 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 123451 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_ROM_S_15_6_BRPERRM1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 123462 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_cgc bridge_spio_sp_main0_sp_main_pu_s_16_6_as_cgc SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGC_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGC_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGC_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 123500 spio_sp_main0_sp_main_pu_s register as_cgc 0x41C10 R/W 0x0000000000000064 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_as_cgc Programmable intervals used by coarse clock gating logic. This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGC_HYSTERESIS_COUNTER_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGC_HYSTERESIS_COUNTER_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGC_HYSTERESIS_COUNTER_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGC_HYSTERESIS_COUNTER_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGC_HYSTERESIS_COUNTER_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGC_HYSTERESIS_COUNTER_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGC_HYSTERESIS_COUNTER_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_spio_soc_ip.csr 123488 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGC_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGC_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGC_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGC_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGC_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGC_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGC_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGC_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 123499 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_cgo bridge_spio_sp_main0_sp_main_pu_s_16_6_as_cgo SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGO_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGO_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGO_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGO_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 123535 spio_sp_main0_sp_main_pu_s register as_cgo 0x41C18 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_as_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the slave bridge. false false false false FPO SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGO_FPO_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGO_FPO_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGO_FPO_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGO_FPO_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGO_FPO_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGO_FPO_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGO_FPO_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGO_FPO_SET ns_noc_io_spio_soc_ip.csr 123523 FPO 1'b1: Clock gating override enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGO_UNSD_63_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGO_UNSD_63_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGO_UNSD_63_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGO_UNSD_63_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGO_UNSD_63_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGO_UNSD_63_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGO_UNSD_63_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CGO_UNSD_63_1_SET ns_noc_io_spio_soc_ip.csr 123534 UNSD_63_1 63 1 0x0000000000000000 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_sts bridge_spio_sp_main0_sp_main_pu_s_16_6_as_sts SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 123609 spio_sp_main0_sp_main_pu_s register as_sts 0x41D00 R 0x000000000000000c Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_as_sts Slave bridge status bits. false false false false WOF SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_WOF_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_WOF_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_WOF_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_WOF_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_WOF_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_WOF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_WOF_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_WOF_SET ns_noc_io_spio_soc_ip.csr 123558 WOF 1'b1: Maximum number of supported write commands are outstanding to the attached slave device awaiting response, no more write commands will be issued to slave till responses are received. 1'b0: Slave device can expect more write commands from NoC 0 0 0x0 R ROF SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_ROF_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_ROF_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_ROF_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_ROF_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_ROF_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_ROF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_ROF_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_ROF_SET ns_noc_io_spio_soc_ip.csr 123574 ROF 1'b1: Maximum number of supported read commands are outstanding to the attached slave device awaiting response, no more read commands will be issued to slave till responses are received. 1'b0: Slave bridge can accept more read commands from the NoC 1 1 0x0 R WOE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_WOE_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_WOE_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_WOE_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_WOE_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_WOE_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_WOE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_WOE_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_WOE_SET ns_noc_io_spio_soc_ip.csr 123586 WOE 1'b1: There are no write commands outstanding to the attached slave device 2 2 0x1 R ROE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_ROE_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_ROE_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_ROE_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_ROE_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_ROE_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_ROE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_ROE_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_ROE_SET ns_noc_io_spio_soc_ip.csr 123598 ROE 1'b1: There are no read commands outstanding to the attached slave device 3 3 0x1 R UNSD_63_4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_UNSD_63_4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_UNSD_63_4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_UNSD_63_4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_UNSD_63_4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_UNSD_63_4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_UNSD_63_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_UNSD_63_4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_STS_UNSD_63_4_SET ns_noc_io_spio_soc_ip.csr 123608 UNSD_63_4 63 4 0x000000000000000 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_bridge_id bridge_spio_sp_main0_sp_main_pu_s_16_6_as_bridge_id SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_BRIDGE_ID_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_BRIDGE_ID_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_BRIDGE_ID_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_BRIDGE_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 123639 spio_sp_main0_sp_main_pu_s register as_bridge_id 0x41D08 R 0x0000000000000010 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_as_bridge_id Unique identifier assigned to the slave bridge. false false false false ID SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_BRIDGE_ID_ID_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_BRIDGE_ID_ID_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_BRIDGE_ID_ID_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_BRIDGE_ID_ID_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_BRIDGE_ID_ID_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_BRIDGE_ID_ID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_BRIDGE_ID_ID_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_BRIDGE_ID_ID_SET ns_noc_io_spio_soc_ip.csr 123628 ID Unique bridge ID 15 0 0x0010 R UNSD_63_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_BRIDGE_ID_UNSD_63_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_BRIDGE_ID_UNSD_63_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_BRIDGE_ID_UNSD_63_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_BRIDGE_ID_UNSD_63_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_BRIDGE_ID_UNSD_63_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_BRIDGE_ID_UNSD_63_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_BRIDGE_ID_UNSD_63_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_spio_soc_ip.csr 123638 UNSD_63_16 63 16 0x000000000000 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_err bridge_spio_sp_main0_sp_main_pu_s_16_6_as_err SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 123992 spio_sp_main0_sp_main_pu_s register as_err 0x41E00 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_as_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E0_SET ns_noc_io_spio_soc_ip.csr 123660 E0 1'b1: Read decode error response: Decode error response received from slave device for read command 0 0 0x0 R/W E1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E1_SET ns_noc_io_spio_soc_ip.csr 123672 E1 1'b1: Read slave error response: Slave error response received from slave device for read command 1 1 0x0 R/W E2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E2_SET ns_noc_io_spio_soc_ip.csr 123685 E2 1'b1: [FATAL] Unknown read response destination: RID from read response produces a destination which is not present in the routing table 2 2 0x0 R/W E3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E3_SET ns_noc_io_spio_soc_ip.csr 123699 E3 1'b1: [FATAL] Interleaved read response: Interleaved read response. This can occur if interleaved read response is received from a slave device for which a de-interleaver was not specified 3 3 0x0 R/W E4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E4_SET ns_noc_io_spio_soc_ip.csr 123711 E4 1'b1: Read command modified: A read command which was marked as non-modifiable was modified by the slave bridge 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_UNSD_15_5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_UNSD_15_5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_UNSD_15_5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_UNSD_15_5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_UNSD_15_5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_UNSD_15_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_UNSD_15_5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 123722 UNSD_15_5 15 5 0x000 R E16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E16_SET ns_noc_io_spio_soc_ip.csr 123734 E16 1'b1: Write decode error response: Decode error response received from slave device for write command 16 16 0x0 R/W E17 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E17_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E17_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E17_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E17_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E17_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E17_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E17_SET ns_noc_io_spio_soc_ip.csr 123746 E17 1'b1: Write slave error response: Slave error response received from slave device for write command 17 17 0x0 R/W E18 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E18_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E18_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E18_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E18_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E18_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E18_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E18_SET ns_noc_io_spio_soc_ip.csr 123759 E18 1'b1: [FATAL] Unknown write response destination: BID from write response produces a destination which is not present in the routing table 18 18 0x0 R/W E19 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E19_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E19_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E19_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E19_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E19_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E19_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E19_SET ns_noc_io_spio_soc_ip.csr 123771 E19 1'b1: Write command modified: A write command which was marked as non-modifiable was modified by the slave bridge 19 19 0x0 R/W UNSD_31_20 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_UNSD_31_20_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_UNSD_31_20_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_UNSD_31_20_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_UNSD_31_20_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_UNSD_31_20_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_UNSD_31_20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_UNSD_31_20_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_UNSD_31_20_SET ns_noc_io_spio_soc_ip.csr 123782 UNSD_31_20 31 20 0x000 R E32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E32_SET ns_noc_io_spio_soc_ip.csr 123794 E32 1'b1: [FATAL] Traffic sent to a noc layer which is power gated 32 32 0x0 R/W E33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E33_SET ns_noc_io_spio_soc_ip.csr 123805 E33 1'b1: [FATAL] Parity error in config/status registers 33 33 0x0 R/W E34 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E34_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E34_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E34_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E34_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E34_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E34_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E34_SET ns_noc_io_spio_soc_ip.csr 123816 E34 1'b1: [FATAL] RDATA Parity error 34 34 0x0 R/W E35 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E35_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E35_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E35_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E35_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E35_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E35_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E35_SET ns_noc_io_spio_soc_ip.csr 123827 E35 1'b1: [FATAL] RRESP Parity error 35 35 0x0 R/W E36 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E36_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E36_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E36_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E36_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E36_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E36_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E36_SET ns_noc_io_spio_soc_ip.csr 123838 E36 1'b1: [FATAL] BRESP Parity error 36 36 0x0 R/W E37 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E37_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E37_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E37_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E37_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E37_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E37_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E37_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E37_SET ns_noc_io_spio_soc_ip.csr 123849 E37 1'b1: [FATAL] AC Parity error 37 37 0x0 R/W E38 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E38_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E38_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E38_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E38_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E38_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E38_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E38_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E38_SET ns_noc_io_spio_soc_ip.csr 123860 E38 1'b1: [FATAL] ACADDR Parity error 38 38 0x0 R/W E39 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E39_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E39_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E39_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E39_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E39_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E39_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E39_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E39_SET ns_noc_io_spio_soc_ip.csr 123872 E39 1'b1: [FATAL] R Ch Cmdtbl Parity Err 39 39 0x0 R E40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E40_SET ns_noc_io_spio_soc_ip.csr 123884 E40 1'b1: [FATAL] B Ch Cmdtbl Parity Err 40 40 0x0 R E41 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E41_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E41_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E41_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E41_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E41_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E41_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E41_SET ns_noc_io_spio_soc_ip.csr 123896 E41 1'b1: [FATAL] Rx Fifo Parity Err 41 41 0x0 R E42 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E42_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E42_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E42_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E42_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E42_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E42_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E42_SET ns_noc_io_spio_soc_ip.csr 123908 E42 1'b1: [FATAL] CRCD Ch Reorder Buffer Parity Err 42 42 0x0 R E43 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E43_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E43_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E43_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E43_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E43_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E43_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E43_SET ns_noc_io_spio_soc_ip.csr 123920 E43 1'b1: [FATAL] Ack Ch Wack Reorder Buffer Parity Err 43 43 0x0 R E44 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E44_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E44_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E44_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E44_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E44_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E44_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E44_SET ns_noc_io_spio_soc_ip.csr 123932 E44 1'b1: [FATAL] Ack Ch Rack Reorder Buffer Parity Err 44 44 0x0 R E45 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E45_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E45_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E45_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E45_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E45_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E45_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E45_SET ns_noc_io_spio_soc_ip.csr 123944 E45 1'b1: [FATAL] B Ch Drain Fifo Parity Err 45 45 0x0 R E46 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E46_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E46_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E46_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E46_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E46_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E46_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E46_SET ns_noc_io_spio_soc_ip.csr 123956 E46 1'b1: [FATAL] R Ch Flush Fifo Parity Err 46 46 0x0 R E47 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E47_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E47_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E47_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E47_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E47_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E47_SET ns_noc_io_spio_soc_ip.csr 123968 E47 1'b1: [FATAL] R Ch Deinterleaver Cmdtbl Parity Err 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_E48_SET ns_noc_io_spio_soc_ip.csr 123980 E48 1'b1: [FATAL] R Ch Deinterleaver Data Buffer Parity Err 48 48 0x0 R UNSD_63_49 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_UNSD_63_49_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_UNSD_63_49_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_UNSD_63_49_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_UNSD_63_49_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_UNSD_63_49_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_UNSD_63_49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_UNSD_63_49_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_ERR_UNSD_63_49_SET ns_noc_io_spio_soc_ip.csr 123991 UNSD_63_49 63 49 0x0000 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_intm bridge_spio_sp_main0_sp_main_pu_s_16_6_as_intm SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 124332 spio_sp_main0_sp_main_pu_s register as_intm 0x41E40 R/W 0x0000007d000b0013 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_as_intm Interrupt mask register.Individual bit positions match the error bit positions in AS_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M0_SET ns_noc_io_spio_soc_ip.csr 124013 M0 Mask interrupts for read channel 0 0 0x1 R/W M1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M1_SET ns_noc_io_spio_soc_ip.csr 124024 M1 Mask interrupts for read channel 1 1 0x1 R/W M2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M2_SET ns_noc_io_spio_soc_ip.csr 124035 M2 Mask interrupts for read channel 2 2 0x0 R/W M3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M3_SET ns_noc_io_spio_soc_ip.csr 124046 M3 Mask interrupts for read channel 3 3 0x0 R/W M4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M4_SET ns_noc_io_spio_soc_ip.csr 124057 M4 Mask interrupts for read channel 4 4 0x1 R/W UNSD_15_5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_UNSD_15_5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_UNSD_15_5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_UNSD_15_5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_UNSD_15_5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_UNSD_15_5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_UNSD_15_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_UNSD_15_5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 124068 UNSD_15_5 15 5 0x000 R M16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M16_SET ns_noc_io_spio_soc_ip.csr 124079 M16 Mask interrupts for write channel 16 16 0x1 R/W M17 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M17_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M17_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M17_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M17_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M17_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M17_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M17_SET ns_noc_io_spio_soc_ip.csr 124090 M17 Mask interrupts for write channel 17 17 0x1 R/W M18 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M18_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M18_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M18_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M18_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M18_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M18_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M18_SET ns_noc_io_spio_soc_ip.csr 124101 M18 Mask interrupts for write channel 18 18 0x0 R/W M19 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M19_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M19_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M19_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M19_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M19_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M19_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M19_SET ns_noc_io_spio_soc_ip.csr 124112 M19 Mask interrupts for write channel 19 19 0x1 R/W UNSD_31_20 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_UNSD_31_20_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_UNSD_31_20_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_UNSD_31_20_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_UNSD_31_20_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_UNSD_31_20_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_UNSD_31_20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_UNSD_31_20_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_UNSD_31_20_SET ns_noc_io_spio_soc_ip.csr 124123 UNSD_31_20 31 20 0x000 R M32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M32_SET ns_noc_io_spio_soc_ip.csr 124134 M32 Mask interrupt on traffic to PG layer 32 32 0x1 R/W M33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M33_SET ns_noc_io_spio_soc_ip.csr 124145 M33 Mask interrupt on csr parity errors 33 33 0x0 R/W M34 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M34_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M34_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M34_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M34_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M34_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M34_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M34_SET ns_noc_io_spio_soc_ip.csr 124156 M34 RDATA parity interrupt Mask 34 34 0x1 R/W M35 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M35_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M35_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M35_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M35_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M35_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M35_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M35_SET ns_noc_io_spio_soc_ip.csr 124167 M35 RRESP parity interrupt Mask 35 35 0x1 R/W M36 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M36_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M36_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M36_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M36_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M36_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M36_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M36_SET ns_noc_io_spio_soc_ip.csr 124178 M36 BRESP parity interrupt Mask 36 36 0x1 R/W M37 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M37_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M37_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M37_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M37_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M37_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M37_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M37_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M37_SET ns_noc_io_spio_soc_ip.csr 124189 M37 AC parity interrupt Mask 37 37 0x1 R/W M38 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M38_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M38_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M38_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M38_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M38_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M38_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M38_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_M38_SET ns_noc_io_spio_soc_ip.csr 124200 M38 ACADDR parity interrupt Mask 38 38 0x1 R/W E39 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E39_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E39_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E39_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E39_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E39_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E39_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E39_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E39_SET ns_noc_io_spio_soc_ip.csr 124212 E39 1'b1: R Ch Cmdtbl Parity Err Intr Mask 39 39 0x0 R E40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E40_SET ns_noc_io_spio_soc_ip.csr 124224 E40 1'b1: B Ch Cmdtbl Parity Err Intr Mask 40 40 0x0 R E41 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E41_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E41_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E41_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E41_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E41_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E41_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E41_SET ns_noc_io_spio_soc_ip.csr 124236 E41 1'b1: Rx Fifo Parity Err Intr Mask 41 41 0x0 R E42 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E42_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E42_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E42_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E42_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E42_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E42_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E42_SET ns_noc_io_spio_soc_ip.csr 124248 E42 1'b1: CRCD Ch Reorder Buffer Parity Err Intr Mask 42 42 0x0 R E43 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E43_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E43_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E43_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E43_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E43_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E43_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E43_SET ns_noc_io_spio_soc_ip.csr 124260 E43 1'b1: Ack Ch Wack Reorder Buffer Parity Err IntrMask 43 43 0x0 R E44 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E44_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E44_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E44_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E44_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E44_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E44_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E44_SET ns_noc_io_spio_soc_ip.csr 124272 E44 1'b1: Ack Ch Rack Reorder Buffer Parity Err Intr Mask 44 44 0x0 R E45 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E45_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E45_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E45_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E45_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E45_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E45_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E45_SET ns_noc_io_spio_soc_ip.csr 124284 E45 1'b1: B Ch Drain Fifo Parity Err Intr Mask 45 45 0x0 R E46 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E46_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E46_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E46_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E46_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E46_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E46_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E46_SET ns_noc_io_spio_soc_ip.csr 124296 E46 1'b1: R Ch Flush Fifo Parity Err Intr Mask 46 46 0x0 R E47 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E47_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E47_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E47_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E47_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E47_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E47_SET ns_noc_io_spio_soc_ip.csr 124308 E47 1'b1: R Ch Deinterleaver Cmdtbl Parity Err Intr Mask 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_E48_SET ns_noc_io_spio_soc_ip.csr 124320 E48 1'b1: R Ch Deinterleaver Data Buffer Parity Err Intr Mask 48 48 0x0 R UNSD_63_49 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_UNSD_63_49_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_UNSD_63_49_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_UNSD_63_49_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_UNSD_63_49_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_UNSD_63_49_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_UNSD_63_49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_UNSD_63_49_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_INTM_UNSD_63_49_SET ns_noc_io_spio_soc_ip.csr 124331 UNSD_63_49 63 49 0x0000 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_ccmd bridge_spio_sp_main0_sp_main_pu_s_16_6_as_ccmd SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 124407 spio_sp_main0_sp_main_pu_s register as_ccmd 0x41F00 R/W 0x0000000003000000 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_as_ccmd Not applicable for current release. false false false false UNSD_23_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_UNSD_23_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_UNSD_23_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_UNSD_23_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_UNSD_23_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_UNSD_23_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_UNSD_23_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_UNSD_23_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_UNSD_23_0_SET ns_noc_io_spio_soc_ip.csr 124350 UNSD_23_0 23 0 0x000000 R rdy SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_RDY_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_RDY_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_RDY_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_RDY_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_RDY_SET ns_noc_io_spio_soc_ip.csr 124361 rdy 1'b1: Ready 24 24 0x1 R/W val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_VAL_SET ns_noc_io_spio_soc_ip.csr 124372 val 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_UNSD_27_26_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_UNSD_27_26_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_UNSD_27_26_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_UNSD_27_26_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_UNSD_27_26_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_UNSD_27_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_UNSD_27_26_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_UNSD_27_26_SET ns_noc_io_spio_soc_ip.csr 124383 UNSD_27_26 27 26 0x0 R intfid SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_INTFID_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_INTFID_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_INTFID_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_INTFID_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_INTFID_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_INTFID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_INTFID_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_INTFID_SET ns_noc_io_spio_soc_ip.csr 124395 intfid 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_63_31 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_UNSD_63_31_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_UNSD_63_31_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_UNSD_63_31_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_UNSD_63_31_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_UNSD_63_31_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_UNSD_63_31_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_UNSD_63_31_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMD_UNSD_63_31_SET ns_noc_io_spio_soc_ip.csr 124406 UNSD_63_31 63 31 0x000000000 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_ccmdmsk bridge_spio_sp_main0_sp_main_pu_s_16_6_as_ccmdmsk SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 124459 spio_sp_main0_sp_main_pu_s register as_ccmdmsk 0x41F08 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_as_ccmdmsk Not applicable for current release. false false false false UNSD_23_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_UNSD_23_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_UNSD_23_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_UNSD_23_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_UNSD_23_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_UNSD_23_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_UNSD_23_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_UNSD_23_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_UNSD_23_0_SET ns_noc_io_spio_soc_ip.csr 124425 UNSD_23_0 23 0 0x000000 R rdy SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_RDY_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_RDY_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_RDY_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_RDY_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_RDY_SET ns_noc_io_spio_soc_ip.csr 124436 rdy 1'b1: Ready 24 24 0x0 R/W val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_VAL_SET ns_noc_io_spio_soc_ip.csr 124447 val 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_UNSD_63_26_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_UNSD_63_26_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_UNSD_63_26_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_UNSD_63_26_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_UNSD_63_26_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_UNSD_63_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_UNSD_63_26_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CCMDMSK_UNSD_63_26_SET ns_noc_io_spio_soc_ip.csr 124458 UNSD_63_26 63 26 0x0000000000 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_cntr bridge_spio_sp_main0_sp_main_pu_s_16_6_as_cntr SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CNTR_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CNTR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CNTR_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CNTR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 124489 spio_sp_main0_sp_main_pu_s register as_cntr 0x41F10 R 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_as_cntr Not applicable for current release. false false false false CNTR SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CNTR_CNTR_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CNTR_CNTR_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CNTR_CNTR_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CNTR_CNTR_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CNTR_CNTR_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CNTR_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CNTR_CNTR_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CNTR_CNTR_SET ns_noc_io_spio_soc_ip.csr 124478 CNTR Counter 31 0 0x00000000 R UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CNTR_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CNTR_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CNTR_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CNTR_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CNTR_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CNTR_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CNTR_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_CNTR_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 124488 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_arovrd bridge_spio_sp_main0_sp_main_pu_s_16_6_as_arovrd SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 124602 spio_sp_main0_sp_main_pu_s register as_arovrd 0x41F18 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_as_arovrd AR Overrides. false false false false arcache_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 124507 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 124520 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 124531 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 124542 UNSD_11_11 11 11 0x0 R arprot_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 124555 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 124566 UNSD_15_15 15 15 0x0 R arqos_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 124577 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_ARQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 124590 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AROVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 124601 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_as_awovrd bridge_spio_sp_main0_sp_main_pu_s_16_6_as_awovrd SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 124715 spio_sp_main0_sp_main_pu_s register as_awovrd 0x41F20 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_as_awovrd AW Overrides. false false false false awcache_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 124620 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 124633 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 124644 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 124655 UNSD_11_11 11 11 0x0 R awprot_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 124668 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 124679 UNSD_15_15 15 15 0x0 R awqos_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 124690 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_AWQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 124703 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_AS_AWOVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 124714 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_p_0 bridge_spio_sp_main0_sp_main_pu_s_16_6_p_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 124780 spio_sp_main0_sp_main_pu_s register p_0 0x43000 R/W 0x00000003 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_0_SET ns_noc_io_spio_soc_ip.csr 124743 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_1_SET ns_noc_io_spio_soc_ip.csr 124755 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_2_SET ns_noc_io_spio_soc_ip.csr 124767 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_0_WT_QOS_3_SET ns_noc_io_spio_soc_ip.csr 124779 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_p_1 bridge_spio_sp_main0_sp_main_pu_s_16_6_p_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 124846 spio_sp_main0_sp_main_pu_s register p_1 0x43008 R 0x00000000 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_4_SET ns_noc_io_spio_soc_ip.csr 124809 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_5_SET ns_noc_io_spio_soc_ip.csr 124821 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_6_SET ns_noc_io_spio_soc_ip.csr 124833 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_1_WT_QOS_7_SET ns_noc_io_spio_soc_ip.csr 124845 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_p_2 bridge_spio_sp_main0_sp_main_pu_s_16_6_p_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 124912 spio_sp_main0_sp_main_pu_s register p_2 0x43010 R 0x00000000 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_8_SET ns_noc_io_spio_soc_ip.csr 124875 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_9_SET ns_noc_io_spio_soc_ip.csr 124887 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_10_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_10_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_10_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_10_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_10_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_10_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_10_SET ns_noc_io_spio_soc_ip.csr 124899 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_2_WT_QOS_11_SET ns_noc_io_spio_soc_ip.csr 124911 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_p_3 bridge_spio_sp_main0_sp_main_pu_s_16_6_p_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 124978 spio_sp_main0_sp_main_pu_s register p_3 0x43018 R 0x00000000 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_12_SET ns_noc_io_spio_soc_ip.csr 124941 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_13_SET ns_noc_io_spio_soc_ip.csr 124953 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_14_SET ns_noc_io_spio_soc_ip.csr 124965 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_P_3_WT_QOS_15_SET ns_noc_io_spio_soc_ip.csr 124977 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_txe bridge_spio_sp_main0_sp_main_pu_s_16_6_txe SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 125124 spio_sp_main0_sp_main_pu_s register txe 0x43040 R/W 0x00000000 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_TRANS_WITHOUT_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_TRANS_WITHOUT_SOP_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_TRANS_WITHOUT_SOP_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_TRANS_WITHOUT_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_TRANS_WITHOUT_SOP_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_TRANS_WITHOUT_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_TRANS_WITHOUT_SOP_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_spio_soc_ip.csr 125005 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_SOP_AFTER_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_SOP_AFTER_SOP_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_SOP_AFTER_SOP_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_SOP_AFTER_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_SOP_AFTER_SOP_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_SOP_AFTER_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_SOP_AFTER_SOP_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_SOP_AFTER_SOP_SET ns_noc_io_spio_soc_ip.csr 125017 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 125032 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 125045 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_spio_soc_ip.csr 125059 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_spio_soc_ip.csr 125073 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_spio_soc_ip.csr 125087 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_spio_soc_ip.csr 125101 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 125112 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXE_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 125123 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_txem bridge_spio_sp_main0_sp_main_pu_s_16_6_txem SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 125203 spio_sp_main0_sp_main_pu_s register txem 0x43048 R/W 0x00000008 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_UNSD_1_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_UNSD_1_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_UNSD_1_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_UNSD_1_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_UNSD_1_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_UNSD_1_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_UNSD_1_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_UNSD_1_0_SET ns_noc_io_spio_soc_ip.csr 125147 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 125158 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 125169 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_UNSD_7_4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_UNSD_7_4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_UNSD_7_4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_UNSD_7_4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_UNSD_7_4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_UNSD_7_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_UNSD_7_4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_UNSD_7_4_SET ns_noc_io_spio_soc_ip.csr 125180 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 125191 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_TXEM_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 125202 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btus_0 bridge_spio_sp_main0_sp_main_pu_s_16_6_btus_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 125571 spio_sp_main0_sp_main_pu_s register btus_0 0x43058 R 0x00000000 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_A_SET ns_noc_io_spio_soc_ip.csr 125229 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_B_SET ns_noc_io_spio_soc_ip.csr 125240 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_C_SET ns_noc_io_spio_soc_ip.csr 125251 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L0_D_SET ns_noc_io_spio_soc_ip.csr 125262 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_A_SET ns_noc_io_spio_soc_ip.csr 125273 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_B_SET ns_noc_io_spio_soc_ip.csr 125284 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_C_SET ns_noc_io_spio_soc_ip.csr 125295 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L1_D_SET ns_noc_io_spio_soc_ip.csr 125306 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_A_SET ns_noc_io_spio_soc_ip.csr 125317 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_B_SET ns_noc_io_spio_soc_ip.csr 125328 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_C_SET ns_noc_io_spio_soc_ip.csr 125339 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L2_D_SET ns_noc_io_spio_soc_ip.csr 125350 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_A_SET ns_noc_io_spio_soc_ip.csr 125361 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_B_SET ns_noc_io_spio_soc_ip.csr 125372 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_C_SET ns_noc_io_spio_soc_ip.csr 125383 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L3_D_SET ns_noc_io_spio_soc_ip.csr 125394 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_A_SET ns_noc_io_spio_soc_ip.csr 125405 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_B_SET ns_noc_io_spio_soc_ip.csr 125416 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_C_SET ns_noc_io_spio_soc_ip.csr 125427 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L4_D_SET ns_noc_io_spio_soc_ip.csr 125438 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_A_SET ns_noc_io_spio_soc_ip.csr 125449 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_B_SET ns_noc_io_spio_soc_ip.csr 125460 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_C_SET ns_noc_io_spio_soc_ip.csr 125471 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L5_D_SET ns_noc_io_spio_soc_ip.csr 125482 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_A_SET ns_noc_io_spio_soc_ip.csr 125493 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_B_SET ns_noc_io_spio_soc_ip.csr 125504 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_C_SET ns_noc_io_spio_soc_ip.csr 125515 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L6_D_SET ns_noc_io_spio_soc_ip.csr 125526 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_A_SET ns_noc_io_spio_soc_ip.csr 125537 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_B_SET ns_noc_io_spio_soc_ip.csr 125548 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_C_SET ns_noc_io_spio_soc_ip.csr 125559 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_0_L7_D_SET ns_noc_io_spio_soc_ip.csr 125570 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btus_1 bridge_spio_sp_main0_sp_main_pu_s_16_6_btus_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 125939 spio_sp_main0_sp_main_pu_s register btus_1 0x43060 R 0x00000000 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_A_SET ns_noc_io_spio_soc_ip.csr 125597 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_B_SET ns_noc_io_spio_soc_ip.csr 125608 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_C_SET ns_noc_io_spio_soc_ip.csr 125619 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L8_D_SET ns_noc_io_spio_soc_ip.csr 125630 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_A_SET ns_noc_io_spio_soc_ip.csr 125641 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_B_SET ns_noc_io_spio_soc_ip.csr 125652 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_C_SET ns_noc_io_spio_soc_ip.csr 125663 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L9_D_SET ns_noc_io_spio_soc_ip.csr 125674 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_A_SET ns_noc_io_spio_soc_ip.csr 125685 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_B_SET ns_noc_io_spio_soc_ip.csr 125696 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_C_SET ns_noc_io_spio_soc_ip.csr 125707 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L10_D_SET ns_noc_io_spio_soc_ip.csr 125718 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_A_SET ns_noc_io_spio_soc_ip.csr 125729 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_B_SET ns_noc_io_spio_soc_ip.csr 125740 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_C_SET ns_noc_io_spio_soc_ip.csr 125751 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L11_D_SET ns_noc_io_spio_soc_ip.csr 125762 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_A_SET ns_noc_io_spio_soc_ip.csr 125773 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_B_SET ns_noc_io_spio_soc_ip.csr 125784 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_C_SET ns_noc_io_spio_soc_ip.csr 125795 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L12_D_SET ns_noc_io_spio_soc_ip.csr 125806 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_A_SET ns_noc_io_spio_soc_ip.csr 125817 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_B_SET ns_noc_io_spio_soc_ip.csr 125828 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_C_SET ns_noc_io_spio_soc_ip.csr 125839 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L13_D_SET ns_noc_io_spio_soc_ip.csr 125850 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_A_SET ns_noc_io_spio_soc_ip.csr 125861 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_B_SET ns_noc_io_spio_soc_ip.csr 125872 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_C_SET ns_noc_io_spio_soc_ip.csr 125883 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L14_D_SET ns_noc_io_spio_soc_ip.csr 125894 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_A_SET ns_noc_io_spio_soc_ip.csr 125905 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_B_SET ns_noc_io_spio_soc_ip.csr 125916 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_C_SET ns_noc_io_spio_soc_ip.csr 125927 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTUS_1_L15_D_SET ns_noc_io_spio_soc_ip.csr 125938 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btrl_0 bridge_spio_sp_main0_sp_main_pu_s_16_6_btrl_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 126015 spio_sp_main0_sp_main_pu_s register btrl_0 0x43080 R 0x00000000 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_WT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_WT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_WT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_WT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_WT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_WT_SET ns_noc_io_spio_soc_ip.csr 125963 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 125974 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_CNT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_CNT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_CNT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_CNT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_CNT_SET ns_noc_io_spio_soc_ip.csr 125989 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_EN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_EN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_EN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_EN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_EN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_EN_SET ns_noc_io_spio_soc_ip.csr 126003 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_0_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 126014 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btrl_1 bridge_spio_sp_main0_sp_main_pu_s_16_6_btrl_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 126091 spio_sp_main0_sp_main_pu_s register btrl_1 0x43088 R 0x00000000 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_WT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_WT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_WT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_WT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_WT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_WT_SET ns_noc_io_spio_soc_ip.csr 126039 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 126050 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_CNT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_CNT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_CNT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_CNT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_CNT_SET ns_noc_io_spio_soc_ip.csr 126065 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_EN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_EN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_EN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_EN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_EN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_EN_SET ns_noc_io_spio_soc_ip.csr 126079 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_1_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 126090 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btrl_2 bridge_spio_sp_main0_sp_main_pu_s_16_6_btrl_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 126167 spio_sp_main0_sp_main_pu_s register btrl_2 0x43090 R 0x00000000 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_WT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_WT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_WT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_WT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_WT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_WT_SET ns_noc_io_spio_soc_ip.csr 126115 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 126126 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_CNT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_CNT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_CNT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_CNT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_CNT_SET ns_noc_io_spio_soc_ip.csr 126141 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_EN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_EN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_EN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_EN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_EN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_EN_SET ns_noc_io_spio_soc_ip.csr 126155 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_2_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 126166 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btrl_3 bridge_spio_sp_main0_sp_main_pu_s_16_6_btrl_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 126243 spio_sp_main0_sp_main_pu_s register btrl_3 0x43098 R 0x00000000 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_WT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_WT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_WT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_WT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_WT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_WT_SET ns_noc_io_spio_soc_ip.csr 126191 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 126202 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_CNT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_CNT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_CNT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_CNT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_CNT_SET ns_noc_io_spio_soc_ip.csr 126217 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_EN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_EN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_EN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_EN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_EN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_EN_SET ns_noc_io_spio_soc_ip.csr 126231 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTRL_3_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 126242 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btperr bridge_spio_sp_main0_sp_main_pu_s_16_6_btperr SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 126445 spio_sp_main0_sp_main_pu_s register btperr 0x430A8 R/W 0x00000000 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L0_SET ns_noc_io_spio_soc_ip.csr 126268 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L1_SET ns_noc_io_spio_soc_ip.csr 126279 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L2_SET ns_noc_io_spio_soc_ip.csr 126290 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L3_SET ns_noc_io_spio_soc_ip.csr 126301 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L4_SET ns_noc_io_spio_soc_ip.csr 126312 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L5_SET ns_noc_io_spio_soc_ip.csr 126323 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L6_SET ns_noc_io_spio_soc_ip.csr 126334 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L7_SET ns_noc_io_spio_soc_ip.csr 126345 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L8_SET ns_noc_io_spio_soc_ip.csr 126356 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L9_SET ns_noc_io_spio_soc_ip.csr 126367 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L10_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L10_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L10_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L10_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L10_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L10_SET ns_noc_io_spio_soc_ip.csr 126378 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L11_SET ns_noc_io_spio_soc_ip.csr 126389 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L12_SET ns_noc_io_spio_soc_ip.csr 126400 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L13_SET ns_noc_io_spio_soc_ip.csr 126411 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L14_SET ns_noc_io_spio_soc_ip.csr 126422 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_L15_SET ns_noc_io_spio_soc_ip.csr 126433 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_UNSD_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERR_UNSD_SET ns_noc_io_spio_soc_ip.csr 126444 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_btperrm bridge_spio_sp_main0_sp_main_pu_s_16_6_btperrm SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 126645 spio_sp_main0_sp_main_pu_s register btperrm 0x430B0 R/W 0x00000000 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L0_SET ns_noc_io_spio_soc_ip.csr 126468 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L1_SET ns_noc_io_spio_soc_ip.csr 126479 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L2_SET ns_noc_io_spio_soc_ip.csr 126490 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L3_SET ns_noc_io_spio_soc_ip.csr 126501 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L4_SET ns_noc_io_spio_soc_ip.csr 126512 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L5_SET ns_noc_io_spio_soc_ip.csr 126523 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L6_SET ns_noc_io_spio_soc_ip.csr 126534 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L7_SET ns_noc_io_spio_soc_ip.csr 126545 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L8_SET ns_noc_io_spio_soc_ip.csr 126556 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L9_SET ns_noc_io_spio_soc_ip.csr 126567 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L10_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L10_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L10_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L10_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L10_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L10_SET ns_noc_io_spio_soc_ip.csr 126578 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L11_SET ns_noc_io_spio_soc_ip.csr 126589 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L12_SET ns_noc_io_spio_soc_ip.csr 126600 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L13_SET ns_noc_io_spio_soc_ip.csr 126611 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L14_SET ns_noc_io_spio_soc_ip.csr 126622 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_L15_SET ns_noc_io_spio_soc_ip.csr 126633 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_UNSD_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BTPERRM_UNSD_SET ns_noc_io_spio_soc_ip.csr 126644 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_rxe bridge_spio_sp_main0_sp_main_pu_s_16_6_rxe SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 126753 spio_sp_main0_sp_main_pu_s register rxe 0x43120 R/W 0x00000000 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_A_SET ns_noc_io_spio_soc_ip.csr 126673 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_B_SET ns_noc_io_spio_soc_ip.csr 126684 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_C_SET ns_noc_io_spio_soc_ip.csr 126695 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_CRC_OFLW_D_SET ns_noc_io_spio_soc_ip.csr 126706 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_EVC_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_EVC_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_EVC_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_EVC_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_EVC_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_EVC_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_EVC_OFLW_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_EVC_OFLW_SET ns_noc_io_spio_soc_ip.csr 126718 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 126729 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_EVC1_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_EVC1_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_EVC1_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_EVC1_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_EVC1_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_EVC1_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_EVC1_OFLW_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_EVC1_OFLW_SET ns_noc_io_spio_soc_ip.csr 126741 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXE_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 126752 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_rxem bridge_spio_sp_main0_sp_main_pu_s_16_6_rxem SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 126825 spio_sp_main0_sp_main_pu_s register rxem 0x43128 R/W 0x00000050 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_UNSD_3_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_UNSD_3_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_UNSD_3_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_UNSD_3_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_UNSD_3_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_UNSD_3_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_UNSD_3_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_UNSD_3_0_SET ns_noc_io_spio_soc_ip.csr 126774 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_EVC_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_EVC_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_EVC_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_EVC_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_EVC_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_EVC_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_EVC_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_EVC_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 126788 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 126799 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_EVC1_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_EVC1_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_EVC1_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_EVC1_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_EVC1_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_EVC1_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_EVC1_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 126813 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_RXEM_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 126824 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_brs_0 bridge_spio_sp_main0_sp_main_pu_s_16_6_brs_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 127099 spio_sp_main0_sp_main_pu_s register brs_0 0x43130 R 0x00000000 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 126849 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_0_SET ns_noc_io_spio_soc_ip.csr 126860 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_0_SET ns_noc_io_spio_soc_ip.csr 126871 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_0_SET ns_noc_io_spio_soc_ip.csr 126882 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_0_SET ns_noc_io_spio_soc_ip.csr 126893 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 126903 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 126914 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_1_SET ns_noc_io_spio_soc_ip.csr 126925 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_1_SET ns_noc_io_spio_soc_ip.csr 126936 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_1_SET ns_noc_io_spio_soc_ip.csr 126947 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_1_SET ns_noc_io_spio_soc_ip.csr 126958 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 126968 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 126979 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_2_SET ns_noc_io_spio_soc_ip.csr 126990 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_2_SET ns_noc_io_spio_soc_ip.csr 127001 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_2_SET ns_noc_io_spio_soc_ip.csr 127012 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_2_SET ns_noc_io_spio_soc_ip.csr 127023 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 127033 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 127044 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_V_3_SET ns_noc_io_spio_soc_ip.csr 127055 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_S_3_SET ns_noc_io_spio_soc_ip.csr 127066 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_B_3_SET ns_noc_io_spio_soc_ip.csr 127077 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_F_3_SET ns_noc_io_spio_soc_ip.csr 127088 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_0_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 127098 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_brs_1 bridge_spio_sp_main0_sp_main_pu_s_16_6_brs_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 127373 spio_sp_main0_sp_main_pu_s register brs_1 0x43138 R 0x00000000 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 127123 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_0_SET ns_noc_io_spio_soc_ip.csr 127134 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_0_SET ns_noc_io_spio_soc_ip.csr 127145 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_0_SET ns_noc_io_spio_soc_ip.csr 127156 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_0_SET ns_noc_io_spio_soc_ip.csr 127167 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 127177 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 127188 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_1_SET ns_noc_io_spio_soc_ip.csr 127199 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_1_SET ns_noc_io_spio_soc_ip.csr 127210 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_1_SET ns_noc_io_spio_soc_ip.csr 127221 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_1_SET ns_noc_io_spio_soc_ip.csr 127232 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 127242 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 127253 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_2_SET ns_noc_io_spio_soc_ip.csr 127264 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_2_SET ns_noc_io_spio_soc_ip.csr 127275 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_2_SET ns_noc_io_spio_soc_ip.csr 127286 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_2_SET ns_noc_io_spio_soc_ip.csr 127297 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 127307 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 127318 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_V_3_SET ns_noc_io_spio_soc_ip.csr 127329 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_S_3_SET ns_noc_io_spio_soc_ip.csr 127340 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_B_3_SET ns_noc_io_spio_soc_ip.csr 127351 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_F_3_SET ns_noc_io_spio_soc_ip.csr 127362 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRS_1_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 127372 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_brus bridge_spio_sp_main0_sp_main_pu_s_16_6_brus SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 127442 spio_sp_main0_sp_main_pu_s register brus 0x431B0 R 0x00000000 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_A_SET ns_noc_io_spio_soc_ip.csr 127398 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_B_SET ns_noc_io_spio_soc_ip.csr 127409 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_C_SET ns_noc_io_spio_soc_ip.csr 127420 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_V_D_SET ns_noc_io_spio_soc_ip.csr 127431 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_UNSD_31_4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_UNSD_31_4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_UNSD_31_4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_UNSD_31_4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_UNSD_31_4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_UNSD_31_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_UNSD_31_4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRUS_UNSD_31_4_SET ns_noc_io_spio_soc_ip.csr 127441 UNSD_31_4 31 4 0x0000000 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_brperr0 bridge_spio_sp_main0_sp_main_pu_s_16_6_brperr0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 127670 spio_sp_main0_sp_main_pu_s register brperr0 0x431D0 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_D0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_D0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_D0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_D0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_D0_SET ns_noc_io_spio_soc_ip.csr 127480 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_DC0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_DC0_SET ns_noc_io_spio_soc_ip.csr 127491 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SB0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SB0_SET ns_noc_io_spio_soc_ip.csr 127502 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SBC0_SET ns_noc_io_spio_soc_ip.csr 127514 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_PK0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_PK0_SET ns_noc_io_spio_soc_ip.csr 127525 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 127536 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_D1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_D1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_D1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_D1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_D1_SET ns_noc_io_spio_soc_ip.csr 127547 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_DC1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_DC1_SET ns_noc_io_spio_soc_ip.csr 127558 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SB1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SB1_SET ns_noc_io_spio_soc_ip.csr 127569 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_SBC1_SET ns_noc_io_spio_soc_ip.csr 127581 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_PK1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_PK1_SET ns_noc_io_spio_soc_ip.csr 127592 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 127603 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 127614 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 127625 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 127636 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 127647 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 127658 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 127669 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_brperr1 bridge_spio_sp_main0_sp_main_pu_s_16_6_brperr1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 127786 spio_sp_main0_sp_main_pu_s register brperr1 0x431D8 R 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 127708 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 127719 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 127730 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 127741 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 127752 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 127763 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 127774 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERR1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 127785 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_brperrm0 bridge_spio_sp_main0_sp_main_pu_s_16_6_brperrm0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 128007 spio_sp_main0_sp_main_pu_s register brperrm0 0x431E0 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_D0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_D0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_D0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_D0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_D0_SET ns_noc_io_spio_soc_ip.csr 127813 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_DC0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_DC0_SET ns_noc_io_spio_soc_ip.csr 127825 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SB0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SB0_SET ns_noc_io_spio_soc_ip.csr 127836 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SBC0_SET ns_noc_io_spio_soc_ip.csr 127848 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_PK0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_PK0_SET ns_noc_io_spio_soc_ip.csr 127860 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 127871 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_D1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_D1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_D1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_D1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_D1_SET ns_noc_io_spio_soc_ip.csr 127882 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_DC1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_DC1_SET ns_noc_io_spio_soc_ip.csr 127894 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SB1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SB1_SET ns_noc_io_spio_soc_ip.csr 127905 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_SBC1_SET ns_noc_io_spio_soc_ip.csr 127917 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_PK1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_PK1_SET ns_noc_io_spio_soc_ip.csr 127929 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 127940 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 127951 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 127962 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 127973 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 127984 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 127995 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 128006 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_sp_main0_sp_main_pu_s_16_6_brperrm1 bridge_spio_sp_main0_sp_main_pu_s_16_6_brperrm1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 128112 spio_sp_main0_sp_main_pu_s register brperrm1 0x431E8 R 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_sp_main_pu_s_16_6_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 128034 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 128045 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 128056 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 128067 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 128078 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 128089 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 128100 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SP_MAIN_PU_S_16_6_BRPERRM1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 128111 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 128228 spio_sp_main0_srvcproc_m register am_adbase_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 0x44000 R/W 0x0000000040100000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 128152 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 128163 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 128174 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 128186 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 128197 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 128209 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 128220 BASE_ADDRESS_0_33 Base address 39 6 0x001004000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 128227 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 128320 spio_sp_main0_srvcproc_m register am_admask_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 0x44008 R/W 0x000000fffff00000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_rbm_s_sr_rbm_s_map_r_1g_1m__1g_2m__1m_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 128245 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 128256 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 128267 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 128278 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 128290 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 128301 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 128312 MASK_0_33 Mask 39 6 0x3ffffc000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_RBM_S_SR_RBM_S_MAP_R_1G_1M__1G_2M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 128319 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 128436 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 0x44020 R/W 0x0000000056100000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 128360 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 128371 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 128382 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 128394 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 128405 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 128417 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 128428 BASE_ADDRESS_0_33 Base address 39 6 0x001584000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 128435 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 128528 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 0x44028 R/W 0x000000fffff00000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p00_axi_comm_s_sr_spio_p00_axi_comm_s_map_r_1g_353m__1g_354m__1m_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 128453 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 128464 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 128475 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 128486 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 128498 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 128509 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 128520 MASK_0_33 Mask 39 6 0x3ffffc000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_AXI_COMM_S_SR_SPIO_P00_AXI_COMM_S_MAP_R_1G_353M__1G_354M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 128527 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 128644 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 0x44040 R/W 0x0000000056000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 128568 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 128579 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 128590 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 128602 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 128613 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 128625 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 128636 BASE_ADDRESS_0_33 Base address 39 6 0x001580000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 128643 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 128736 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 0x44048 R/W 0x000000fffffff000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p00_dma_ahb0_s_sr_spio_p00_dma_ahb0_s_map_r_1g_352m__1g_352m_4k__4k_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 128661 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 128672 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 128683 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 128694 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 128706 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 128717 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 128728 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P00_DMA_AHB0_S_SR_SPIO_P00_DMA_AHB0_S_MAP_R_1G_352M__1G_352M_4K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 128735 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 128852 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 0x44060 R/W 0x0000000054000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 128776 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 128787 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 128798 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 128810 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 128821 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 128833 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 128844 BASE_ADDRESS_0_33 Base address 39 6 0x001500000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 128851 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 128944 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 0x44068 R/W 0x000000ffffff0000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m__1g_320m_64k__64k_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 128869 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 128880 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 128891 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 128902 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 128914 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 128925 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 128936 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M__1G_320M_64K__64K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 128943 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 129060 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 0x44080 R/W 0x0000000054010000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_SET ns_noc_io_spio_soc_ip.csr 128984 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 128995 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_SET ns_noc_io_spio_soc_ip.csr 129006 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 129018 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_DI_SET ns_noc_io_spio_soc_ip.csr 129029 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_LLC_SET ns_noc_io_spio_soc_ip.csr 129041 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 129052 BASE_ADDRESS_0_33 Base address 39 6 0x001500400 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 129059 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 129152 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 0x44088 R/W 0x000000ffffff0000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_64k__1g_320m_128k__64k_1_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_P_SET ns_noc_io_spio_soc_ip.csr 129077 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 129088 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_I_SET ns_noc_io_spio_soc_ip.csr 129099 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_VAL_SET ns_noc_io_spio_soc_ip.csr 129110 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_TM_SET ns_noc_io_spio_soc_ip.csr 129122 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_RSV_SET ns_noc_io_spio_soc_ip.csr 129133 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 129144 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_64K__1G_320M_128K__64K_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 129151 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 129268 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 0x440A0 R/W 0x0000000054020000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_SET ns_noc_io_spio_soc_ip.csr 129192 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 129203 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_SET ns_noc_io_spio_soc_ip.csr 129214 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 129226 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_DI_SET ns_noc_io_spio_soc_ip.csr 129237 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_LLC_SET ns_noc_io_spio_soc_ip.csr 129249 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 129260 BASE_ADDRESS_0_33 Base address 39 6 0x001500800 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 129267 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 129360 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 0x440A8 R/W 0x000000ffffff0000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_128k__1g_320m_192k__64k_2_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_P_SET ns_noc_io_spio_soc_ip.csr 129285 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 129296 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_I_SET ns_noc_io_spio_soc_ip.csr 129307 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_VAL_SET ns_noc_io_spio_soc_ip.csr 129318 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_TM_SET ns_noc_io_spio_soc_ip.csr 129330 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_RSV_SET ns_noc_io_spio_soc_ip.csr 129341 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 129352 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_128K__1G_320M_192K__64K_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 129359 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 129476 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 0x440C0 R/W 0x0000000054030000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_SET ns_noc_io_spio_soc_ip.csr 129400 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 129411 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_SET ns_noc_io_spio_soc_ip.csr 129422 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 129434 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_DI_SET ns_noc_io_spio_soc_ip.csr 129445 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_LLC_SET ns_noc_io_spio_soc_ip.csr 129457 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 129468 BASE_ADDRESS_0_33 Base address 39 6 0x001500c00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 129475 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 129568 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 0x440C8 R/W 0x000000ffffff0000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_192k__1g_320m_256k__64k_3_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_P_SET ns_noc_io_spio_soc_ip.csr 129493 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 129504 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_I_SET ns_noc_io_spio_soc_ip.csr 129515 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_VAL_SET ns_noc_io_spio_soc_ip.csr 129526 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_TM_SET ns_noc_io_spio_soc_ip.csr 129538 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_RSV_SET ns_noc_io_spio_soc_ip.csr 129549 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 129560 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_192K__1G_320M_256K__64K_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 129567 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 129684 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 0x440E0 R/W 0x0000000054040000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_SET ns_noc_io_spio_soc_ip.csr 129608 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 129619 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_SET ns_noc_io_spio_soc_ip.csr 129630 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 129642 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_DI_SET ns_noc_io_spio_soc_ip.csr 129653 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_LLC_SET ns_noc_io_spio_soc_ip.csr 129665 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 129676 BASE_ADDRESS_0_33 Base address 39 6 0x001501000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 129683 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 129776 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 0x440E8 R/W 0x000000ffffff0000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_256k__1g_320m_320k__64k_4_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_P_SET ns_noc_io_spio_soc_ip.csr 129701 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 129712 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_I_SET ns_noc_io_spio_soc_ip.csr 129723 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_VAL_SET ns_noc_io_spio_soc_ip.csr 129734 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_TM_SET ns_noc_io_spio_soc_ip.csr 129746 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_RSV_SET ns_noc_io_spio_soc_ip.csr 129757 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 129768 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_256K__1G_320M_320K__64K_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 129775 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 129892 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 0x44100 R/W 0x0000000054050000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_SET ns_noc_io_spio_soc_ip.csr 129816 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 129827 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_SET ns_noc_io_spio_soc_ip.csr 129838 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 129850 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_DI_SET ns_noc_io_spio_soc_ip.csr 129861 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_LLC_SET ns_noc_io_spio_soc_ip.csr 129873 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 129884 BASE_ADDRESS_0_33 Base address 39 6 0x001501400 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 129891 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 129984 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 0x44108 R/W 0x000000fffffff000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_320k__1g_320m_324k__4k_5_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_P_SET ns_noc_io_spio_soc_ip.csr 129909 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 129920 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_I_SET ns_noc_io_spio_soc_ip.csr 129931 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_VAL_SET ns_noc_io_spio_soc_ip.csr 129942 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_TM_SET ns_noc_io_spio_soc_ip.csr 129954 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_RSV_SET ns_noc_io_spio_soc_ip.csr 129965 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 129976 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_320K__1G_320M_324K__4K_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 129983 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 130100 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 0x44120 R/W 0x0000000054051000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_SET ns_noc_io_spio_soc_ip.csr 130024 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 130035 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_SET ns_noc_io_spio_soc_ip.csr 130046 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 130058 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_DI_SET ns_noc_io_spio_soc_ip.csr 130069 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_LLC_SET ns_noc_io_spio_soc_ip.csr 130081 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 130092 BASE_ADDRESS_0_33 Base address 39 6 0x001501440 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 130099 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 130192 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 0x44128 R/W 0x000000fffffff000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_324k__1g_320m_328k__4k_6_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_P_SET ns_noc_io_spio_soc_ip.csr 130117 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 130128 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_I_SET ns_noc_io_spio_soc_ip.csr 130139 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_VAL_SET ns_noc_io_spio_soc_ip.csr 130150 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_TM_SET ns_noc_io_spio_soc_ip.csr 130162 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_RSV_SET ns_noc_io_spio_soc_ip.csr 130173 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 130184 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_324K__1G_320M_328K__4K_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 130191 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 130308 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 0x44140 R/W 0x0000000054052000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_SET ns_noc_io_spio_soc_ip.csr 130232 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 130243 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_SET ns_noc_io_spio_soc_ip.csr 130254 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 130266 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_DI_SET ns_noc_io_spio_soc_ip.csr 130277 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_LLC_SET ns_noc_io_spio_soc_ip.csr 130289 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 130300 BASE_ADDRESS_0_33 Base address 39 6 0x001501480 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 130307 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 130400 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 0x44148 R/W 0x000000fffffff000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_328k__1g_320m_332k__4k_7_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_P_SET ns_noc_io_spio_soc_ip.csr 130325 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 130336 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_I_SET ns_noc_io_spio_soc_ip.csr 130347 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_VAL_SET ns_noc_io_spio_soc_ip.csr 130358 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_TM_SET ns_noc_io_spio_soc_ip.csr 130370 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_RSV_SET ns_noc_io_spio_soc_ip.csr 130381 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 130392 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_328K__1G_320M_332K__4K_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 130399 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 130516 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 0x44160 R/W 0x0000000054053000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_SET ns_noc_io_spio_soc_ip.csr 130440 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 130451 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_SET ns_noc_io_spio_soc_ip.csr 130462 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 130474 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_DI_SET ns_noc_io_spio_soc_ip.csr 130485 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_LLC_SET ns_noc_io_spio_soc_ip.csr 130497 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 130508 BASE_ADDRESS_0_33 Base address 39 6 0x0015014c0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 130515 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 130608 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 0x44168 R/W 0x000000fffffff000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_332k__1g_320m_336k__4k_8_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_P_SET ns_noc_io_spio_soc_ip.csr 130533 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 130544 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_I_SET ns_noc_io_spio_soc_ip.csr 130555 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_VAL_SET ns_noc_io_spio_soc_ip.csr 130566 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_TM_SET ns_noc_io_spio_soc_ip.csr 130578 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_RSV_SET ns_noc_io_spio_soc_ip.csr 130589 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 130600 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_332K__1G_320M_336K__4K_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 130607 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 130724 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 0x44180 R/W 0x0000000054054000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 130648 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 130659 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 130670 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 130682 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_DI_SET ns_noc_io_spio_soc_ip.csr 130693 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_LLC_SET ns_noc_io_spio_soc_ip.csr 130705 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 130716 BASE_ADDRESS_0_33 Base address 39 6 0x001501500 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 130723 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 130816 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 0x44188 R/W 0x000000fffffff000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_336k__1g_320m_340k__4k_9_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 130741 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 130752 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 130763 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_VAL_SET ns_noc_io_spio_soc_ip.csr 130774 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_TM_SET ns_noc_io_spio_soc_ip.csr 130786 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_RSV_SET ns_noc_io_spio_soc_ip.csr 130797 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 130808 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_336K__1G_320M_340K__4K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 130815 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 130932 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 0x441A0 R/W 0x0000000054055000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_SET ns_noc_io_spio_soc_ip.csr 130856 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_SET ns_noc_io_spio_soc_ip.csr 130867 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_SET ns_noc_io_spio_soc_ip.csr 130878 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 130890 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_DI_SET ns_noc_io_spio_soc_ip.csr 130901 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_LLC_SET ns_noc_io_spio_soc_ip.csr 130913 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 130924 BASE_ADDRESS_0_33 Base address 39 6 0x001501540 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 130931 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 131024 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 0x441A8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_340k__1g_320m_344k__4k_10_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_P_SET ns_noc_io_spio_soc_ip.csr 130949 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_NS_SET ns_noc_io_spio_soc_ip.csr 130960 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_I_SET ns_noc_io_spio_soc_ip.csr 130971 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_VAL_SET ns_noc_io_spio_soc_ip.csr 130982 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_TM_SET ns_noc_io_spio_soc_ip.csr 130994 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_RSV_SET ns_noc_io_spio_soc_ip.csr 131005 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 131016 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_340K__1G_320M_344K__4K_10_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 131023 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 131140 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 0x441C0 R/W 0x0000000054056000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_SET ns_noc_io_spio_soc_ip.csr 131064 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_SET ns_noc_io_spio_soc_ip.csr 131075 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_SET ns_noc_io_spio_soc_ip.csr 131086 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 131098 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_DI_SET ns_noc_io_spio_soc_ip.csr 131109 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_LLC_SET ns_noc_io_spio_soc_ip.csr 131121 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 131132 BASE_ADDRESS_0_33 Base address 39 6 0x001501580 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 131139 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 131232 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 0x441C8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_344k__1g_320m_348k__4k_11_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_P_SET ns_noc_io_spio_soc_ip.csr 131157 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_NS_SET ns_noc_io_spio_soc_ip.csr 131168 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_I_SET ns_noc_io_spio_soc_ip.csr 131179 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_VAL_SET ns_noc_io_spio_soc_ip.csr 131190 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_TM_SET ns_noc_io_spio_soc_ip.csr 131202 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_RSV_SET ns_noc_io_spio_soc_ip.csr 131213 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 131224 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_344K__1G_320M_348K__4K_11_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 131231 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 131348 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 0x441E0 R/W 0x0000000054057000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_SET ns_noc_io_spio_soc_ip.csr 131272 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_SET ns_noc_io_spio_soc_ip.csr 131283 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_SET ns_noc_io_spio_soc_ip.csr 131294 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 131306 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_DI_SET ns_noc_io_spio_soc_ip.csr 131317 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_LLC_SET ns_noc_io_spio_soc_ip.csr 131329 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 131340 BASE_ADDRESS_0_33 Base address 39 6 0x0015015c0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 131347 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 131440 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 0x441E8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb0_s_sr_spio_p10_apb0_s_map_r_1g_320m_348k__1g_320m_352k__4k_12_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_P_SET ns_noc_io_spio_soc_ip.csr 131365 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_NS_SET ns_noc_io_spio_soc_ip.csr 131376 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_I_SET ns_noc_io_spio_soc_ip.csr 131387 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_VAL_SET ns_noc_io_spio_soc_ip.csr 131398 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_TM_SET ns_noc_io_spio_soc_ip.csr 131410 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_RSV_SET ns_noc_io_spio_soc_ip.csr 131421 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 131432 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB0_S_SR_SPIO_P10_APB0_S_MAP_R_1G_320M_348K__1G_320M_352K__4K_12_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 131439 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 131556 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 0x44200 R/W 0x0000000050000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_SET ns_noc_io_spio_soc_ip.csr 131480 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_SET ns_noc_io_spio_soc_ip.csr 131491 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_SET ns_noc_io_spio_soc_ip.csr 131502 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 131514 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_DI_SET ns_noc_io_spio_soc_ip.csr 131525 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_LLC_SET ns_noc_io_spio_soc_ip.csr 131537 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 131548 BASE_ADDRESS_0_33 Base address 39 6 0x001400000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 131555 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 131648 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 0x44208 R/W 0x000000fffe000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_256m__1g_288m__32m_10_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_P_SET ns_noc_io_spio_soc_ip.csr 131573 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_NS_SET ns_noc_io_spio_soc_ip.csr 131584 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_I_SET ns_noc_io_spio_soc_ip.csr 131595 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_VAL_SET ns_noc_io_spio_soc_ip.csr 131606 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_TM_SET ns_noc_io_spio_soc_ip.csr 131618 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_RSV_SET ns_noc_io_spio_soc_ip.csr 131629 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 131640 MASK_0_33 Mask 39 6 0x3fff80000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_256M__1G_288M__32M_10_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 131647 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 131764 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 0x44220 R/W 0x0000000052000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 131688 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 131699 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 131710 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 131722 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_DI_SET ns_noc_io_spio_soc_ip.csr 131733 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_LLC_SET ns_noc_io_spio_soc_ip.csr 131745 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 131756 BASE_ADDRESS_0_33 Base address 39 6 0x001480000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 131763 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 131856 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 0x44228 R/W 0x000000fffffe0000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m__1g_288m_128k__128k_9_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 131781 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 131792 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 131803 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_VAL_SET ns_noc_io_spio_soc_ip.csr 131814 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_TM_SET ns_noc_io_spio_soc_ip.csr 131826 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_RSV_SET ns_noc_io_spio_soc_ip.csr 131837 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 131848 MASK_0_33 Mask 39 6 0x3fffff800 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M__1G_288M_128K__128K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 131855 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 131972 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 0x44240 R/W 0x0000000052020000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_SET ns_noc_io_spio_soc_ip.csr 131896 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 131907 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_SET ns_noc_io_spio_soc_ip.csr 131918 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 131930 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_DI_SET ns_noc_io_spio_soc_ip.csr 131941 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_LLC_SET ns_noc_io_spio_soc_ip.csr 131953 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 131964 BASE_ADDRESS_0_33 Base address 39 6 0x001480800 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 131971 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 132064 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 0x44248 R/W 0x000000fffffff000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_128k__1g_288m_132k__4k_1_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_P_SET ns_noc_io_spio_soc_ip.csr 131989 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 132000 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_I_SET ns_noc_io_spio_soc_ip.csr 132011 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_VAL_SET ns_noc_io_spio_soc_ip.csr 132022 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_TM_SET ns_noc_io_spio_soc_ip.csr 132034 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_RSV_SET ns_noc_io_spio_soc_ip.csr 132045 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 132056 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_128K__1G_288M_132K__4K_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 132063 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 132180 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 0x44260 R/W 0x0000000052021000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_SET ns_noc_io_spio_soc_ip.csr 132104 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 132115 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_SET ns_noc_io_spio_soc_ip.csr 132126 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 132138 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_DI_SET ns_noc_io_spio_soc_ip.csr 132149 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_LLC_SET ns_noc_io_spio_soc_ip.csr 132161 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 132172 BASE_ADDRESS_0_33 Base address 39 6 0x001480840 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 132179 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 132272 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 0x44268 R/W 0x000000fffffff000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_132k__1g_288m_136k__4k_2_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_P_SET ns_noc_io_spio_soc_ip.csr 132197 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 132208 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_I_SET ns_noc_io_spio_soc_ip.csr 132219 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_VAL_SET ns_noc_io_spio_soc_ip.csr 132230 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_TM_SET ns_noc_io_spio_soc_ip.csr 132242 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_RSV_SET ns_noc_io_spio_soc_ip.csr 132253 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 132264 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_132K__1G_288M_136K__4K_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 132271 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 132388 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 0x44280 R/W 0x0000000052022000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_SET ns_noc_io_spio_soc_ip.csr 132312 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 132323 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_SET ns_noc_io_spio_soc_ip.csr 132334 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 132346 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_DI_SET ns_noc_io_spio_soc_ip.csr 132357 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_LLC_SET ns_noc_io_spio_soc_ip.csr 132369 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 132380 BASE_ADDRESS_0_33 Base address 39 6 0x001480880 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 132387 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 132480 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 0x44288 R/W 0x000000fffffff000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_136k__1g_288m_140k__4k_3_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_P_SET ns_noc_io_spio_soc_ip.csr 132405 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 132416 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_I_SET ns_noc_io_spio_soc_ip.csr 132427 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_VAL_SET ns_noc_io_spio_soc_ip.csr 132438 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_TM_SET ns_noc_io_spio_soc_ip.csr 132450 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_RSV_SET ns_noc_io_spio_soc_ip.csr 132461 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 132472 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_136K__1G_288M_140K__4K_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 132479 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 132596 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 0x442A0 R/W 0x0000000052023000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 132520 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 132531 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 132542 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 132554 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 132565 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 132577 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 132588 BASE_ADDRESS_0_33 Base address 39 6 0x0014808c0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 132595 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 132688 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 0x442A8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_140k__1g_288m_144k__4k_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 132613 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 132624 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 132635 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 132646 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 132658 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 132669 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 132680 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_140K__1G_288M_144K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 132687 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 132804 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 0x442C0 R/W 0x0000000052024000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_SET ns_noc_io_spio_soc_ip.csr 132728 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 132739 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_SET ns_noc_io_spio_soc_ip.csr 132750 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 132762 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_DI_SET ns_noc_io_spio_soc_ip.csr 132773 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_LLC_SET ns_noc_io_spio_soc_ip.csr 132785 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 132796 BASE_ADDRESS_0_33 Base address 39 6 0x001480900 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 132803 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 132896 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 0x442C8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_144k__1g_288m_148k__4k_4_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_P_SET ns_noc_io_spio_soc_ip.csr 132821 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 132832 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_I_SET ns_noc_io_spio_soc_ip.csr 132843 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_VAL_SET ns_noc_io_spio_soc_ip.csr 132854 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_TM_SET ns_noc_io_spio_soc_ip.csr 132866 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_RSV_SET ns_noc_io_spio_soc_ip.csr 132877 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 132888 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_144K__1G_288M_148K__4K_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 132895 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 133012 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 0x442E0 R/W 0x0000000052025000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_SET ns_noc_io_spio_soc_ip.csr 132936 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 132947 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_SET ns_noc_io_spio_soc_ip.csr 132958 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 132970 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_DI_SET ns_noc_io_spio_soc_ip.csr 132981 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_LLC_SET ns_noc_io_spio_soc_ip.csr 132993 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 133004 BASE_ADDRESS_0_33 Base address 39 6 0x001480940 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 133011 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 133104 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 0x442E8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_148k__1g_288m_152k__4k_5_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_P_SET ns_noc_io_spio_soc_ip.csr 133029 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 133040 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_I_SET ns_noc_io_spio_soc_ip.csr 133051 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_VAL_SET ns_noc_io_spio_soc_ip.csr 133062 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_TM_SET ns_noc_io_spio_soc_ip.csr 133074 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_RSV_SET ns_noc_io_spio_soc_ip.csr 133085 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 133096 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_148K__1G_288M_152K__4K_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 133103 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 133220 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 0x44300 R/W 0x0000000052026000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_SET ns_noc_io_spio_soc_ip.csr 133144 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 133155 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_SET ns_noc_io_spio_soc_ip.csr 133166 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 133178 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_DI_SET ns_noc_io_spio_soc_ip.csr 133189 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_LLC_SET ns_noc_io_spio_soc_ip.csr 133201 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 133212 BASE_ADDRESS_0_33 Base address 39 6 0x001480980 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 133219 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 133312 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 0x44308 R/W 0x000000ffffffe000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_152k__1g_288m_160k__8k_6_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_P_SET ns_noc_io_spio_soc_ip.csr 133237 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 133248 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_I_SET ns_noc_io_spio_soc_ip.csr 133259 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_VAL_SET ns_noc_io_spio_soc_ip.csr 133270 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_TM_SET ns_noc_io_spio_soc_ip.csr 133282 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_RSV_SET ns_noc_io_spio_soc_ip.csr 133293 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 133304 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_152K__1G_288M_160K__8K_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 133311 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 133428 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 0x44320 R/W 0x0000000052028000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_SET ns_noc_io_spio_soc_ip.csr 133352 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 133363 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_SET ns_noc_io_spio_soc_ip.csr 133374 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 133386 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_DI_SET ns_noc_io_spio_soc_ip.csr 133397 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_LLC_SET ns_noc_io_spio_soc_ip.csr 133409 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 133420 BASE_ADDRESS_0_33 Base address 39 6 0x001480a00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 133427 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 133520 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 0x44328 R/W 0x000000fffffff000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_160k__1g_288m_164k__4k_7_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_P_SET ns_noc_io_spio_soc_ip.csr 133445 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 133456 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_I_SET ns_noc_io_spio_soc_ip.csr 133467 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_VAL_SET ns_noc_io_spio_soc_ip.csr 133478 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_TM_SET ns_noc_io_spio_soc_ip.csr 133490 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_RSV_SET ns_noc_io_spio_soc_ip.csr 133501 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 133512 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_160K__1G_288M_164K__4K_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 133519 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 133636 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 0x44340 R/W 0x0000000052029000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_SET ns_noc_io_spio_soc_ip.csr 133560 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 133571 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_SET ns_noc_io_spio_soc_ip.csr 133582 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 133594 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_DI_SET ns_noc_io_spio_soc_ip.csr 133605 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_LLC_SET ns_noc_io_spio_soc_ip.csr 133617 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 133628 BASE_ADDRESS_0_33 Base address 39 6 0x001480a40 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 133635 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 133728 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 0x44348 R/W 0x000000fffffff000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_288m_164k__1g_288m_168k__4k_8_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_P_SET ns_noc_io_spio_soc_ip.csr 133653 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 133664 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_I_SET ns_noc_io_spio_soc_ip.csr 133675 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_VAL_SET ns_noc_io_spio_soc_ip.csr 133686 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_TM_SET ns_noc_io_spio_soc_ip.csr 133698 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_RSV_SET ns_noc_io_spio_soc_ip.csr 133709 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 133720 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_288M_164K__1G_288M_168K__4K_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 133727 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 133844 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 0x44360 R/W 0x0000000054058000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_SET ns_noc_io_spio_soc_ip.csr 133768 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_SET ns_noc_io_spio_soc_ip.csr 133779 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_SET ns_noc_io_spio_soc_ip.csr 133790 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 133802 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_DI_SET ns_noc_io_spio_soc_ip.csr 133813 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_LLC_SET ns_noc_io_spio_soc_ip.csr 133825 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 133836 BASE_ADDRESS_0_33 Base address 39 6 0x001501600 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 133843 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 133936 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 0x44368 R/W 0x000000fffffff000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_apb1_s_sr_spio_p10_apb1_s_map_r_1g_320m_352k__1g_320m_356k__4k_11_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_P_SET ns_noc_io_spio_soc_ip.csr 133861 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_NS_SET ns_noc_io_spio_soc_ip.csr 133872 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_I_SET ns_noc_io_spio_soc_ip.csr 133883 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_VAL_SET ns_noc_io_spio_soc_ip.csr 133894 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_TM_SET ns_noc_io_spio_soc_ip.csr 133906 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_RSV_SET ns_noc_io_spio_soc_ip.csr 133917 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 133928 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_APB1_S_SR_SPIO_P10_APB1_S_MAP_R_1G_320M_352K__1G_320M_356K__4K_11_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 133935 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 134052 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 0x44380 R/W 0x0000000040300000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 133976 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 133987 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 133998 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 134010 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 134021 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 134033 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 134044 BASE_ADDRESS_0_33 Base address 39 6 0x00100c000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 134051 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 134144 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 0x44388 R/W 0x000000fffff00000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_rbm_s_sr_spio_p10_pcie_rbm_s_map_r_1g_3m__1g_4m__1m_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 134069 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 134080 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 134091 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 134102 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 134114 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 134125 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 134136 MASK_0_33 Mask 39 6 0x3ffffc000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_RBM_S_SR_SPIO_P10_PCIE_RBM_S_MAP_R_1G_3M__1G_4M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 134143 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 134260 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 0x443A0 R/W 0x0000000058200000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 134184 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 134195 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 134206 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 134218 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 134229 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 134241 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 134252 BASE_ADDRESS_0_33 Base address 39 6 0x001608000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 134259 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 134352 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 0x443A8 R/W 0x000000ffffffe000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_386m__1g_386m_8k__8k_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 134277 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 134288 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 134299 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 134310 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 134322 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 134333 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 134344 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_386M__1G_386M_8K__8K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 134351 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 134468 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 0x443C0 R/W 0x0000000058400000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_SET ns_noc_io_spio_soc_ip.csr 134392 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 134403 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_SET ns_noc_io_spio_soc_ip.csr 134414 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 134426 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_DI_SET ns_noc_io_spio_soc_ip.csr 134437 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_LLC_SET ns_noc_io_spio_soc_ip.csr 134449 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 134460 BASE_ADDRESS_0_33 Base address 39 6 0x001610000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 134467 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 134560 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 0x443C8 R/W 0x000000ffffe00000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_1g_388m__1g_390m__2m_1_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_P_SET ns_noc_io_spio_soc_ip.csr 134485 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 134496 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_I_SET ns_noc_io_spio_soc_ip.csr 134507 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_VAL_SET ns_noc_io_spio_soc_ip.csr 134518 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_TM_SET ns_noc_io_spio_soc_ip.csr 134530 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_RSV_SET ns_noc_io_spio_soc_ip.csr 134541 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 134552 MASK_0_33 Mask 39 6 0x3ffff8000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_1G_388M__1G_390M__2M_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 134559 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 134676 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 0x443E0 R/W 0x0000004000000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_SET ns_noc_io_spio_soc_ip.csr 134600 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 134611 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_SET ns_noc_io_spio_soc_ip.csr 134622 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 134634 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_DI_SET ns_noc_io_spio_soc_ip.csr 134645 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_LLC_SET ns_noc_io_spio_soc_ip.csr 134657 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 134668 BASE_ADDRESS_0_33 Base address 39 6 0x100000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 134675 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 134768 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 0x443E8 R/W 0x000000e000000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_256g__384g__128g_2_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_P_SET ns_noc_io_spio_soc_ip.csr 134693 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 134704 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_I_SET ns_noc_io_spio_soc_ip.csr 134715 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_VAL_SET ns_noc_io_spio_soc_ip.csr 134726 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_TM_SET ns_noc_io_spio_soc_ip.csr 134738 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_RSV_SET ns_noc_io_spio_soc_ip.csr 134749 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 134760 MASK_0_33 Mask 39 6 0x380000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_256G__384G__128G_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 134767 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 134884 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 0x44400 R/W 0x0000006000000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_SET ns_noc_io_spio_soc_ip.csr 134808 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 134819 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_SET ns_noc_io_spio_soc_ip.csr 134830 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 134842 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_DI_SET ns_noc_io_spio_soc_ip.csr 134853 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_LLC_SET ns_noc_io_spio_soc_ip.csr 134865 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 134876 BASE_ADDRESS_0_33 Base address 39 6 0x180000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 134883 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 134976 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 0x44408 R/W 0x000000f000000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_384g__448g__64g_3_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_P_SET ns_noc_io_spio_soc_ip.csr 134901 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 134912 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_I_SET ns_noc_io_spio_soc_ip.csr 134923 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_VAL_SET ns_noc_io_spio_soc_ip.csr 134934 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_TM_SET ns_noc_io_spio_soc_ip.csr 134946 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_RSV_SET ns_noc_io_spio_soc_ip.csr 134957 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 134968 MASK_0_33 Mask 39 6 0x3c0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_384G__448G__64G_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 134975 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 135092 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 0x44420 R/W 0x0000007000000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_SET ns_noc_io_spio_soc_ip.csr 135016 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 135027 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_SET ns_noc_io_spio_soc_ip.csr 135038 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 135050 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_DI_SET ns_noc_io_spio_soc_ip.csr 135061 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_LLC_SET ns_noc_io_spio_soc_ip.csr 135073 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 135084 BASE_ADDRESS_0_33 Base address 39 6 0x1c0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 135091 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 135184 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 0x44428 R/W 0x000000f800000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_448g__480g__32g_4_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_P_SET ns_noc_io_spio_soc_ip.csr 135109 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 135120 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_I_SET ns_noc_io_spio_soc_ip.csr 135131 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_VAL_SET ns_noc_io_spio_soc_ip.csr 135142 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_TM_SET ns_noc_io_spio_soc_ip.csr 135154 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_RSV_SET ns_noc_io_spio_soc_ip.csr 135165 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 135176 MASK_0_33 Mask 39 6 0x3e0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_448G__480G__32G_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 135183 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 135300 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 0x44440 R/W 0x0000007800000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_SET ns_noc_io_spio_soc_ip.csr 135224 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 135235 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_SET ns_noc_io_spio_soc_ip.csr 135246 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 135258 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_DI_SET ns_noc_io_spio_soc_ip.csr 135269 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_LLC_SET ns_noc_io_spio_soc_ip.csr 135281 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 135292 BASE_ADDRESS_0_33 Base address 39 6 0x1e0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 135299 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 135392 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 0x44448 R/W 0x000000fc00000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_480g__496g__16g_5_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_P_SET ns_noc_io_spio_soc_ip.csr 135317 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 135328 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_I_SET ns_noc_io_spio_soc_ip.csr 135339 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_VAL_SET ns_noc_io_spio_soc_ip.csr 135350 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_TM_SET ns_noc_io_spio_soc_ip.csr 135362 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_RSV_SET ns_noc_io_spio_soc_ip.csr 135373 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 135384 MASK_0_33 Mask 39 6 0x3f0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_480G__496G__16G_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 135391 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 135508 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 0x44460 R/W 0x0000007c00000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_SET ns_noc_io_spio_soc_ip.csr 135432 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 135443 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_SET ns_noc_io_spio_soc_ip.csr 135454 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 135466 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_DI_SET ns_noc_io_spio_soc_ip.csr 135477 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_LLC_SET ns_noc_io_spio_soc_ip.csr 135489 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 135500 BASE_ADDRESS_0_33 Base address 39 6 0x1f0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 135507 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 135600 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 0x44468 R/W 0x000000fe00000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_496g__504g__8g_6_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_P_SET ns_noc_io_spio_soc_ip.csr 135525 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 135536 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_I_SET ns_noc_io_spio_soc_ip.csr 135547 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_VAL_SET ns_noc_io_spio_soc_ip.csr 135558 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_TM_SET ns_noc_io_spio_soc_ip.csr 135570 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_RSV_SET ns_noc_io_spio_soc_ip.csr 135581 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 135592 MASK_0_33 Mask 39 6 0x3f8000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_496G__504G__8G_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 135599 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 135716 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 0x44480 R/W 0x0000007e00000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_SET ns_noc_io_spio_soc_ip.csr 135640 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 135651 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_SET ns_noc_io_spio_soc_ip.csr 135662 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 135674 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_DI_SET ns_noc_io_spio_soc_ip.csr 135685 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_LLC_SET ns_noc_io_spio_soc_ip.csr 135697 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 135708 BASE_ADDRESS_0_33 Base address 39 6 0x1f8000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 135715 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 135808 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 0x44488 R/W 0x000000ff00000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_504g__508g__4g_7_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_P_SET ns_noc_io_spio_soc_ip.csr 135733 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 135744 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_I_SET ns_noc_io_spio_soc_ip.csr 135755 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_VAL_SET ns_noc_io_spio_soc_ip.csr 135766 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_TM_SET ns_noc_io_spio_soc_ip.csr 135778 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_RSV_SET ns_noc_io_spio_soc_ip.csr 135789 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 135800 MASK_0_33 Mask 39 6 0x3fc000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_504G__508G__4G_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 135807 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 135924 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 0x444A0 R/W 0x0000007f00000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_SET ns_noc_io_spio_soc_ip.csr 135848 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 135859 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_SET ns_noc_io_spio_soc_ip.csr 135870 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 135882 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_DI_SET ns_noc_io_spio_soc_ip.csr 135893 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_LLC_SET ns_noc_io_spio_soc_ip.csr 135905 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 135916 BASE_ADDRESS_0_33 Base address 39 6 0x1fc000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 135923 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 136016 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 0x444A8 R/W 0x000000ff80000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_508g__510g__2g_8_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_P_SET ns_noc_io_spio_soc_ip.csr 135941 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 135952 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_I_SET ns_noc_io_spio_soc_ip.csr 135963 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_VAL_SET ns_noc_io_spio_soc_ip.csr 135974 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_TM_SET ns_noc_io_spio_soc_ip.csr 135986 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_RSV_SET ns_noc_io_spio_soc_ip.csr 135997 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 136008 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_508G__510G__2G_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 136015 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 136132 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 0x444C0 R/W 0x0000007f80000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 136056 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 136067 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 136078 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 136090 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_DI_SET ns_noc_io_spio_soc_ip.csr 136101 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_LLC_SET ns_noc_io_spio_soc_ip.csr 136113 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 136124 BASE_ADDRESS_0_33 Base address 39 6 0x1fe000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 136131 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 136224 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 0x444C8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_pcie_s_sr_spio_p10_pcie_s_map_r_510g__510g_4k__4k_9_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 136149 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 136160 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 136171 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_VAL_SET ns_noc_io_spio_soc_ip.csr 136182 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_TM_SET ns_noc_io_spio_soc_ip.csr 136194 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_RSV_SET ns_noc_io_spio_soc_ip.csr 136205 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 136216 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_PCIE_S_SR_SPIO_P10_PCIE_S_MAP_R_510G__510G_4K__4K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 136223 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 136340 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 0x444E0 R/W 0x0000000052100000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 136264 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 136275 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 136286 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 136298 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 136309 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 136321 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 136332 BASE_ADDRESS_0_33 Base address 39 6 0x001484000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 136339 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 136432 spio_sp_main0_srvcproc_m register am_admask_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 0x444E8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_p10_rvt_ahb0_s_sr_spio_p10_rvt_ahb0_s_map_r_1g_289m__1g_289m_4k__4k_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 136357 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 136368 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 136379 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 136390 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 136402 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 136413 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 136424 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_P10_RVT_AHB0_S_SR_SPIO_P10_RVT_AHB0_S_MAP_R_1G_289M__1G_289M_4K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 136431 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 136548 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 0x44500 R/W 0x0000000042000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 136472 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 136483 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 136494 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 136506 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 136517 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 136529 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 136540 BASE_ADDRESS_0_33 Base address 39 6 0x001080000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 136547 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 136640 spio_sp_main0_srvcproc_m register am_admask_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 0x44508 R/W 0x000000fffe000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_main_noc_rbm_s_sr_spio_sp_main0_main_noc_rbm_s_map_r_1g_32m__1g_64m__32m_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 136565 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 136576 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 136587 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 136598 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 136610 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 136621 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 136632 MASK_0_33 Mask 39 6 0x3fff80000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_SR_SPIO_SP_MAIN0_MAIN_NOC_RBM_S_MAP_R_1G_32M__1G_64M__32M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 136639 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 136756 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 0x44520 R/W 0x0000000040200000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 136680 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 136691 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 136702 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 136714 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 136725 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 136737 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 136748 BASE_ADDRESS_0_33 Base address 39 6 0x001008000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 136755 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 136848 spio_sp_main0_srvcproc_m register am_admask_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 0x44528 R/W 0x000000fffff00000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_pu_rbm_s_sr_spio_sp_main0_pu_rbm_s_map_r_1g_2m__1g_3m__1m_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 136773 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 136784 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 136795 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 136806 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 136818 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 136829 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 136840 MASK_0_33 Mask 39 6 0x3ffffc000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_PU_RBM_S_SR_SPIO_SP_MAIN0_PU_RBM_S_MAP_R_1G_2M__1G_3M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 136847 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 136964 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 0x44540 R/W 0x0000000040400000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 136888 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 136899 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 136910 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 136922 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 136933 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 136945 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 136956 BASE_ADDRESS_0_33 Base address 39 6 0x001010000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 136963 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 137056 spio_sp_main0_srvcproc_m register am_admask_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 0x44548 R/W 0x000000fffff00000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_ram_s_sr_spio_sp_main0_ram_s_map_r_1g_4m__1g_5m__1m_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_P_SET ns_noc_io_spio_soc_ip.csr 136981 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 136992 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_I_SET ns_noc_io_spio_soc_ip.csr 137003 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 137014 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 137026 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 137037 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 137048 MASK_0_33 Mask 39 6 0x3ffffc000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_RAM_S_SR_SPIO_SP_MAIN0_RAM_S_MAP_R_1G_4M__1G_5M__1M_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 137055 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 137172 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 0x44560 R/W 0x0000000040000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 137096 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 137107 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 137118 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 137130 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 137141 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 137153 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 137164 BASE_ADDRESS_0_33 Base address 39 6 0x001000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 137171 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 137264 spio_sp_main0_srvcproc_m register am_admask_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 0x44568 R/W 0x000000ffffff0000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_rom_s_sr_spio_sp_main0_rom_s_map_r_1g__1g_64k__64k_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 137189 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 137200 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 137211 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 137222 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 137234 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 137245 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 137256 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_ROM_S_SR_SPIO_SP_MAIN0_ROM_S_MAP_R_1G__1G_64K__64K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 137263 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 137380 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 0x44580 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 137304 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 137315 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 137326 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 137338 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_DI_SET ns_noc_io_spio_soc_ip.csr 137349 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_LLC_SET ns_noc_io_spio_soc_ip.csr 137361 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 137372 BASE_ADDRESS_0_33 Base address 39 6 0x000000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 137379 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 137472 spio_sp_main0_srvcproc_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 0x44588 R/W 0x000000fffffff000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_0k__4k__4k_0_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_P_SET ns_noc_io_spio_soc_ip.csr 137397 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_NS_SET ns_noc_io_spio_soc_ip.csr 137408 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_I_SET ns_noc_io_spio_soc_ip.csr 137419 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_VAL_SET ns_noc_io_spio_soc_ip.csr 137430 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_TM_SET ns_noc_io_spio_soc_ip.csr 137442 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_RSV_SET ns_noc_io_spio_soc_ip.csr 137453 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 137464 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_0K__4K__4K_0_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 137471 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 137588 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 0x445A0 R/W 0x0000000000003000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_SET ns_noc_io_spio_soc_ip.csr 137512 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 137523 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_SET ns_noc_io_spio_soc_ip.csr 137534 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 137546 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_DI_SET ns_noc_io_spio_soc_ip.csr 137557 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_LLC_SET ns_noc_io_spio_soc_ip.csr 137569 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 137580 BASE_ADDRESS_0_33 Base address 39 6 0x0000000c0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 137587 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 137680 spio_sp_main0_srvcproc_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 0x445A8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_12k__16k__4k_1_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_P_SET ns_noc_io_spio_soc_ip.csr 137605 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_NS_SET ns_noc_io_spio_soc_ip.csr 137616 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_I_SET ns_noc_io_spio_soc_ip.csr 137627 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_VAL_SET ns_noc_io_spio_soc_ip.csr 137638 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_TM_SET ns_noc_io_spio_soc_ip.csr 137650 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_RSV_SET ns_noc_io_spio_soc_ip.csr 137661 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 137672 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_12K__16K__4K_1_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 137679 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 137796 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 0x445C0 R/W 0x0000000000010000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_SET ns_noc_io_spio_soc_ip.csr 137720 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 137731 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_SET ns_noc_io_spio_soc_ip.csr 137742 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 137754 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_DI_SET ns_noc_io_spio_soc_ip.csr 137765 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_LLC_SET ns_noc_io_spio_soc_ip.csr 137777 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 137788 BASE_ADDRESS_0_33 Base address 39 6 0x000000400 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 137795 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 137888 spio_sp_main0_srvcproc_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 0x445C8 R/W 0x000000ffffffe000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_64k__72k__8k_2_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_P_SET ns_noc_io_spio_soc_ip.csr 137813 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_NS_SET ns_noc_io_spio_soc_ip.csr 137824 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_I_SET ns_noc_io_spio_soc_ip.csr 137835 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_VAL_SET ns_noc_io_spio_soc_ip.csr 137846 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_TM_SET ns_noc_io_spio_soc_ip.csr 137858 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_RSV_SET ns_noc_io_spio_soc_ip.csr 137869 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 137880 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_64K__72K__8K_2_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 137887 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 138004 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 0x445E0 R/W 0x0000000000100000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_SET ns_noc_io_spio_soc_ip.csr 137928 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 137939 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_SET ns_noc_io_spio_soc_ip.csr 137950 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 137962 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_DI_SET ns_noc_io_spio_soc_ip.csr 137973 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_LLC_SET ns_noc_io_spio_soc_ip.csr 137985 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 137996 BASE_ADDRESS_0_33 Base address 39 6 0x000004000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 138003 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 138096 spio_sp_main0_srvcproc_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 0x445E8 R/W 0x000000ffffff8000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1m__1m_32k__32k_3_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_P_SET ns_noc_io_spio_soc_ip.csr 138021 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_NS_SET ns_noc_io_spio_soc_ip.csr 138032 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_I_SET ns_noc_io_spio_soc_ip.csr 138043 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_VAL_SET ns_noc_io_spio_soc_ip.csr 138054 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_TM_SET ns_noc_io_spio_soc_ip.csr 138066 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_RSV_SET ns_noc_io_spio_soc_ip.csr 138077 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 138088 MASK_0_33 Mask 39 6 0x3fffffe00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1M__1M_32K__32K_3_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 138095 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 138212 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 0x44600 R/W 0x0000000000200000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_SET ns_noc_io_spio_soc_ip.csr 138136 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 138147 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_SET ns_noc_io_spio_soc_ip.csr 138158 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 138170 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_DI_SET ns_noc_io_spio_soc_ip.csr 138181 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_LLC_SET ns_noc_io_spio_soc_ip.csr 138193 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 138204 BASE_ADDRESS_0_33 Base address 39 6 0x000008000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 138211 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 138304 spio_sp_main0_srvcproc_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 0x44608 R/W 0x000000ffffffc000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2m__2m_16k__16k_4_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_P_SET ns_noc_io_spio_soc_ip.csr 138229 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_NS_SET ns_noc_io_spio_soc_ip.csr 138240 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_I_SET ns_noc_io_spio_soc_ip.csr 138251 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_VAL_SET ns_noc_io_spio_soc_ip.csr 138262 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_TM_SET ns_noc_io_spio_soc_ip.csr 138274 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_RSV_SET ns_noc_io_spio_soc_ip.csr 138285 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 138296 MASK_0_33 Mask 39 6 0x3ffffff00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2M__2M_16K__16K_4_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 138303 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 138420 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 0x44620 R/W 0x0000000000300000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_SET ns_noc_io_spio_soc_ip.csr 138344 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 138355 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_SET ns_noc_io_spio_soc_ip.csr 138366 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 138378 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_DI_SET ns_noc_io_spio_soc_ip.csr 138389 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_LLC_SET ns_noc_io_spio_soc_ip.csr 138401 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 138412 BASE_ADDRESS_0_33 Base address 39 6 0x00000c000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 138419 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 138512 spio_sp_main0_srvcproc_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 0x44628 R/W 0x000000ffffffc000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_3m__3m_16k__16k_5_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_P_SET ns_noc_io_spio_soc_ip.csr 138437 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_NS_SET ns_noc_io_spio_soc_ip.csr 138448 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_I_SET ns_noc_io_spio_soc_ip.csr 138459 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_VAL_SET ns_noc_io_spio_soc_ip.csr 138470 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_TM_SET ns_noc_io_spio_soc_ip.csr 138482 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_RSV_SET ns_noc_io_spio_soc_ip.csr 138493 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 138504 MASK_0_33 Mask 39 6 0x3ffffff00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_3M__3M_16K__16K_5_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 138511 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 138628 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 0x44640 R/W 0x0000000002000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_SET ns_noc_io_spio_soc_ip.csr 138552 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 138563 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_SET ns_noc_io_spio_soc_ip.csr 138574 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 138586 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_DI_SET ns_noc_io_spio_soc_ip.csr 138597 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_LLC_SET ns_noc_io_spio_soc_ip.csr 138609 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 138620 BASE_ADDRESS_0_33 Base address 39 6 0x000080000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 138627 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 138720 spio_sp_main0_srvcproc_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 0x44648 R/W 0x000000ffffff0000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_32m__32m_64k__64k_6_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_P_SET ns_noc_io_spio_soc_ip.csr 138645 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_NS_SET ns_noc_io_spio_soc_ip.csr 138656 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_I_SET ns_noc_io_spio_soc_ip.csr 138667 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_VAL_SET ns_noc_io_spio_soc_ip.csr 138678 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_TM_SET ns_noc_io_spio_soc_ip.csr 138690 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_RSV_SET ns_noc_io_spio_soc_ip.csr 138701 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 138712 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_32M__32M_64K__64K_6_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 138719 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 138836 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 0x44660 R/W 0x0000000010000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_SET ns_noc_io_spio_soc_ip.csr 138760 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 138771 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_SET ns_noc_io_spio_soc_ip.csr 138782 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 138794 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_DI_SET ns_noc_io_spio_soc_ip.csr 138805 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_LLC_SET ns_noc_io_spio_soc_ip.csr 138817 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 138828 BASE_ADDRESS_0_33 Base address 39 6 0x000400000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 138835 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 138928 spio_sp_main0_srvcproc_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 0x44668 R/W 0x000000fffe000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_256m__288m__32m_7_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_P_SET ns_noc_io_spio_soc_ip.csr 138853 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_NS_SET ns_noc_io_spio_soc_ip.csr 138864 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_I_SET ns_noc_io_spio_soc_ip.csr 138875 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_VAL_SET ns_noc_io_spio_soc_ip.csr 138886 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_TM_SET ns_noc_io_spio_soc_ip.csr 138898 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_RSV_SET ns_noc_io_spio_soc_ip.csr 138909 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 138920 MASK_0_33 Mask 39 6 0x3fff80000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_256M__288M__32M_7_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 138927 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 139044 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 0x44680 R/W 0x0000000012000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_SET ns_noc_io_spio_soc_ip.csr 138968 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 138979 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_SET ns_noc_io_spio_soc_ip.csr 138990 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 139002 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_DI_SET ns_noc_io_spio_soc_ip.csr 139013 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_LLC_SET ns_noc_io_spio_soc_ip.csr 139025 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 139036 BASE_ADDRESS_0_33 Base address 39 6 0x000480000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 139043 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 139136 spio_sp_main0_srvcproc_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 0x44688 R/W 0x000000ffffff8000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m__288m_32k__32k_8_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_P_SET ns_noc_io_spio_soc_ip.csr 139061 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_NS_SET ns_noc_io_spio_soc_ip.csr 139072 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_I_SET ns_noc_io_spio_soc_ip.csr 139083 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_VAL_SET ns_noc_io_spio_soc_ip.csr 139094 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_TM_SET ns_noc_io_spio_soc_ip.csr 139106 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_RSV_SET ns_noc_io_spio_soc_ip.csr 139117 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 139128 MASK_0_33 Mask 39 6 0x3fffffe00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M__288M_32K__32K_8_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 139135 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 139252 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 0x446A0 R/W 0x0000000012008000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 139176 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 139187 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 139198 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 139210 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_DI_SET ns_noc_io_spio_soc_ip.csr 139221 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_LLC_SET ns_noc_io_spio_soc_ip.csr 139233 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 139244 BASE_ADDRESS_0_33 Base address 39 6 0x000480200 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 139251 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 139344 spio_sp_main0_srvcproc_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 0x446A8 R/W 0x000000ffffffe000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_32k__288m_40k__8k_9_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_P_SET ns_noc_io_spio_soc_ip.csr 139269 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_NS_SET ns_noc_io_spio_soc_ip.csr 139280 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_I_SET ns_noc_io_spio_soc_ip.csr 139291 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_VAL_SET ns_noc_io_spio_soc_ip.csr 139302 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_TM_SET ns_noc_io_spio_soc_ip.csr 139314 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_RSV_SET ns_noc_io_spio_soc_ip.csr 139325 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 139336 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_32K__288M_40K__8K_9_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 139343 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 139460 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 0x446C0 R/W 0x000000001200a000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_SET ns_noc_io_spio_soc_ip.csr 139384 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_SET ns_noc_io_spio_soc_ip.csr 139395 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_SET ns_noc_io_spio_soc_ip.csr 139406 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 139418 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_DI_SET ns_noc_io_spio_soc_ip.csr 139429 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_LLC_SET ns_noc_io_spio_soc_ip.csr 139441 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 139452 BASE_ADDRESS_0_33 Base address 39 6 0x000480280 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 139459 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 139552 spio_sp_main0_srvcproc_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 0x446C8 R/W 0x000000fffffff000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_288m_40k__288m_44k__4k_10_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_P_SET ns_noc_io_spio_soc_ip.csr 139477 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_NS_SET ns_noc_io_spio_soc_ip.csr 139488 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_I_SET ns_noc_io_spio_soc_ip.csr 139499 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_VAL_SET ns_noc_io_spio_soc_ip.csr 139510 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_TM_SET ns_noc_io_spio_soc_ip.csr 139522 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_RSV_SET ns_noc_io_spio_soc_ip.csr 139533 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 139544 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_288M_40K__288M_44K__4K_10_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 139551 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 139668 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 0x446E0 R/W 0x0000000014000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_SET ns_noc_io_spio_soc_ip.csr 139592 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_SET ns_noc_io_spio_soc_ip.csr 139603 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_SET ns_noc_io_spio_soc_ip.csr 139614 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 139626 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_DI_SET ns_noc_io_spio_soc_ip.csr 139637 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_LLC_SET ns_noc_io_spio_soc_ip.csr 139649 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 139660 BASE_ADDRESS_0_33 Base address 39 6 0x000500000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 139667 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 139760 spio_sp_main0_srvcproc_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 0x446E8 R/W 0x000000fffffc0000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_320m__320m_256k__256k_11_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_P_SET ns_noc_io_spio_soc_ip.csr 139685 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_NS_SET ns_noc_io_spio_soc_ip.csr 139696 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_I_SET ns_noc_io_spio_soc_ip.csr 139707 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_VAL_SET ns_noc_io_spio_soc_ip.csr 139718 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_TM_SET ns_noc_io_spio_soc_ip.csr 139730 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_RSV_SET ns_noc_io_spio_soc_ip.csr 139741 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 139752 MASK_0_33 Mask 39 6 0x3fffff000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_320M__320M_256K__256K_11_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 139759 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 139876 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 0x44700 R/W 0x0000000018000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_SET ns_noc_io_spio_soc_ip.csr 139800 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_SET ns_noc_io_spio_soc_ip.csr 139811 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_SET ns_noc_io_spio_soc_ip.csr 139822 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 139834 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_DI_SET ns_noc_io_spio_soc_ip.csr 139845 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_LLC_SET ns_noc_io_spio_soc_ip.csr 139857 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 139868 BASE_ADDRESS_0_33 Base address 39 6 0x000600000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 139875 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 139968 spio_sp_main0_srvcproc_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 0x44708 R/W 0x000000fffff80000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m__384m_512k__512k_12_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_P_SET ns_noc_io_spio_soc_ip.csr 139893 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_NS_SET ns_noc_io_spio_soc_ip.csr 139904 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_I_SET ns_noc_io_spio_soc_ip.csr 139915 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_VAL_SET ns_noc_io_spio_soc_ip.csr 139926 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_TM_SET ns_noc_io_spio_soc_ip.csr 139938 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_RSV_SET ns_noc_io_spio_soc_ip.csr 139949 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 139960 MASK_0_33 Mask 39 6 0x3ffffe000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M__384M_512K__512K_12_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 139967 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 140084 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 0x44720 R/W 0x0000000018080000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_SET ns_noc_io_spio_soc_ip.csr 140008 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_SET ns_noc_io_spio_soc_ip.csr 140019 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_SET ns_noc_io_spio_soc_ip.csr 140030 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 140042 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_DI_SET ns_noc_io_spio_soc_ip.csr 140053 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_LLC_SET ns_noc_io_spio_soc_ip.csr 140065 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 140076 BASE_ADDRESS_0_33 Base address 39 6 0x000602000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 140083 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 140176 spio_sp_main0_srvcproc_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 0x44728 R/W 0x000000ffffffe000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_512k__384m_520k__8k_13_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_P_SET ns_noc_io_spio_soc_ip.csr 140101 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_NS_SET ns_noc_io_spio_soc_ip.csr 140112 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_I_SET ns_noc_io_spio_soc_ip.csr 140123 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_VAL_SET ns_noc_io_spio_soc_ip.csr 140134 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_TM_SET ns_noc_io_spio_soc_ip.csr 140146 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_RSV_SET ns_noc_io_spio_soc_ip.csr 140157 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 140168 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_512K__384M_520K__8K_13_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 140175 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 140292 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 0x44740 R/W 0x0000000018082000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_SET ns_noc_io_spio_soc_ip.csr 140216 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_SET ns_noc_io_spio_soc_ip.csr 140227 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_SET ns_noc_io_spio_soc_ip.csr 140238 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 140250 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_DI_SET ns_noc_io_spio_soc_ip.csr 140261 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_LLC_SET ns_noc_io_spio_soc_ip.csr 140273 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 140284 BASE_ADDRESS_0_33 Base address 39 6 0x000602080 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 140291 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 140384 spio_sp_main0_srvcproc_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 0x44748 R/W 0x000000fffffff000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_384m_520k__384m_524k__4k_14_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_P_SET ns_noc_io_spio_soc_ip.csr 140309 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_NS_SET ns_noc_io_spio_soc_ip.csr 140320 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_I_SET ns_noc_io_spio_soc_ip.csr 140331 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_VAL_SET ns_noc_io_spio_soc_ip.csr 140342 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_TM_SET ns_noc_io_spio_soc_ip.csr 140354 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_RSV_SET ns_noc_io_spio_soc_ip.csr 140365 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 140376 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_384M_520K__384M_524K__4K_14_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 140383 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 140500 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 0x44760 R/W 0x0000000020000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_SET ns_noc_io_spio_soc_ip.csr 140424 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_SET ns_noc_io_spio_soc_ip.csr 140435 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_SET ns_noc_io_spio_soc_ip.csr 140446 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 140458 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_DI_SET ns_noc_io_spio_soc_ip.csr 140469 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_LLC_SET ns_noc_io_spio_soc_ip.csr 140481 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 140492 BASE_ADDRESS_0_33 Base address 39 6 0x000800000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 140499 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 140592 spio_sp_main0_srvcproc_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 0x44768 R/W 0x000000fffffc0000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512m__512m_256k__256k_15_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_P_SET ns_noc_io_spio_soc_ip.csr 140517 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_NS_SET ns_noc_io_spio_soc_ip.csr 140528 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_I_SET ns_noc_io_spio_soc_ip.csr 140539 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_VAL_SET ns_noc_io_spio_soc_ip.csr 140550 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_TM_SET ns_noc_io_spio_soc_ip.csr 140562 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_RSV_SET ns_noc_io_spio_soc_ip.csr 140573 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 140584 MASK_0_33 Mask 39 6 0x3fffff000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512M__512M_256K__256K_15_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 140591 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 140708 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 0x44780 R/W 0x0000000030000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_SET ns_noc_io_spio_soc_ip.csr 140632 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_SET ns_noc_io_spio_soc_ip.csr 140643 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_SET ns_noc_io_spio_soc_ip.csr 140654 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 140666 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_DI_SET ns_noc_io_spio_soc_ip.csr 140677 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_LLC_SET ns_noc_io_spio_soc_ip.csr 140689 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 140700 BASE_ADDRESS_0_33 Base address 39 6 0x000c00000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 140707 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 140800 spio_sp_main0_srvcproc_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 0x44788 R/W 0x000000ffffff8000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m__768m_32k__32k_16_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_P_SET ns_noc_io_spio_soc_ip.csr 140725 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_NS_SET ns_noc_io_spio_soc_ip.csr 140736 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_I_SET ns_noc_io_spio_soc_ip.csr 140747 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_VAL_SET ns_noc_io_spio_soc_ip.csr 140758 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_TM_SET ns_noc_io_spio_soc_ip.csr 140770 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_RSV_SET ns_noc_io_spio_soc_ip.csr 140781 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 140792 MASK_0_33 Mask 39 6 0x3fffffe00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M__768M_32K__32K_16_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 140799 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 140916 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 0x447A0 R/W 0x0000000030008000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_SET ns_noc_io_spio_soc_ip.csr 140840 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_SET ns_noc_io_spio_soc_ip.csr 140851 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_SET ns_noc_io_spio_soc_ip.csr 140862 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 140874 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_DI_SET ns_noc_io_spio_soc_ip.csr 140885 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_LLC_SET ns_noc_io_spio_soc_ip.csr 140897 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 140908 BASE_ADDRESS_0_33 Base address 39 6 0x000c00200 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 140915 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 141008 spio_sp_main0_srvcproc_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 0x447A8 R/W 0x000000ffffffc000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768m_32k__768m_48k__16k_17_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_P_SET ns_noc_io_spio_soc_ip.csr 140933 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_NS_SET ns_noc_io_spio_soc_ip.csr 140944 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_I_SET ns_noc_io_spio_soc_ip.csr 140955 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_VAL_SET ns_noc_io_spio_soc_ip.csr 140966 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_TM_SET ns_noc_io_spio_soc_ip.csr 140978 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_RSV_SET ns_noc_io_spio_soc_ip.csr 140989 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 141000 MASK_0_33 Mask 39 6 0x3ffffff00 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768M_32K__768M_48K__16K_17_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 141007 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 141124 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 0x447C0 R/W 0x0000000040080000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_SET ns_noc_io_spio_soc_ip.csr 141048 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_SET ns_noc_io_spio_soc_ip.csr 141059 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_SET ns_noc_io_spio_soc_ip.csr 141070 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 141082 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_DI_SET ns_noc_io_spio_soc_ip.csr 141093 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_LLC_SET ns_noc_io_spio_soc_ip.csr 141105 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 141116 BASE_ADDRESS_0_33 Base address 39 6 0x001002000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 141123 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 141216 spio_sp_main0_srvcproc_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 0x447C8 R/W 0x000000ffffffe000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512k__1g_520k__8k_18_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_P_SET ns_noc_io_spio_soc_ip.csr 141141 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_NS_SET ns_noc_io_spio_soc_ip.csr 141152 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_I_SET ns_noc_io_spio_soc_ip.csr 141163 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_VAL_SET ns_noc_io_spio_soc_ip.csr 141174 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_TM_SET ns_noc_io_spio_soc_ip.csr 141186 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_RSV_SET ns_noc_io_spio_soc_ip.csr 141197 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 141208 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512K__1G_520K__8K_18_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 141215 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 141332 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 0x447E0 R/W 0x0000000058000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_SET ns_noc_io_spio_soc_ip.csr 141256 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_SET ns_noc_io_spio_soc_ip.csr 141267 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_SET ns_noc_io_spio_soc_ip.csr 141278 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 141290 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_DI_SET ns_noc_io_spio_soc_ip.csr 141301 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_LLC_SET ns_noc_io_spio_soc_ip.csr 141313 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 141324 BASE_ADDRESS_0_33 Base address 39 6 0x001600000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 141331 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 141424 spio_sp_main0_srvcproc_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 0x447E8 R/W 0x000000ffffffe000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_384m__1g_384m_8k__8k_19_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_P_SET ns_noc_io_spio_soc_ip.csr 141349 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_NS_SET ns_noc_io_spio_soc_ip.csr 141360 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_I_SET ns_noc_io_spio_soc_ip.csr 141371 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_VAL_SET ns_noc_io_spio_soc_ip.csr 141382 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_TM_SET ns_noc_io_spio_soc_ip.csr 141394 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_RSV_SET ns_noc_io_spio_soc_ip.csr 141405 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 141416 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_384M__1G_384M_8K__8K_19_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 141423 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 141540 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 0x44800 R/W 0x0000000060000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_SET ns_noc_io_spio_soc_ip.csr 141464 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_SET ns_noc_io_spio_soc_ip.csr 141475 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_SET ns_noc_io_spio_soc_ip.csr 141486 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 141498 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_DI_SET ns_noc_io_spio_soc_ip.csr 141509 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_LLC_SET ns_noc_io_spio_soc_ip.csr 141521 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 141532 BASE_ADDRESS_0_33 Base address 39 6 0x001800000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 141539 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 141632 spio_sp_main0_srvcproc_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 0x44808 R/W 0x000000ffe0000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_1g_512m__2g__512m_20_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_P_SET ns_noc_io_spio_soc_ip.csr 141557 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_NS_SET ns_noc_io_spio_soc_ip.csr 141568 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_I_SET ns_noc_io_spio_soc_ip.csr 141579 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_VAL_SET ns_noc_io_spio_soc_ip.csr 141590 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_TM_SET ns_noc_io_spio_soc_ip.csr 141602 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_RSV_SET ns_noc_io_spio_soc_ip.csr 141613 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 141624 MASK_0_33 Mask 39 6 0x3ff800000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_1G_512M__2G__512M_20_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 141631 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 141748 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 0x44820 R/W 0x0000000080000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_SET ns_noc_io_spio_soc_ip.csr 141672 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_SET ns_noc_io_spio_soc_ip.csr 141683 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_SET ns_noc_io_spio_soc_ip.csr 141694 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 141706 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_DI_SET ns_noc_io_spio_soc_ip.csr 141717 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_LLC_SET ns_noc_io_spio_soc_ip.csr 141729 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 141740 BASE_ADDRESS_0_33 Base address 39 6 0x002000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 141747 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 141840 spio_sp_main0_srvcproc_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 0x44828 R/W 0x000000ff80000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_2g__4g__2g_21_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_P_SET ns_noc_io_spio_soc_ip.csr 141765 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_NS_SET ns_noc_io_spio_soc_ip.csr 141776 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_I_SET ns_noc_io_spio_soc_ip.csr 141787 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_VAL_SET ns_noc_io_spio_soc_ip.csr 141798 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_TM_SET ns_noc_io_spio_soc_ip.csr 141810 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_RSV_SET ns_noc_io_spio_soc_ip.csr 141821 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 141832 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_2G__4G__2G_21_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 141839 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 141956 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 0x44840 R/W 0x0000000100000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_SET ns_noc_io_spio_soc_ip.csr 141880 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_SET ns_noc_io_spio_soc_ip.csr 141891 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_SET ns_noc_io_spio_soc_ip.csr 141902 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 141914 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_DI_SET ns_noc_io_spio_soc_ip.csr 141925 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_LLC_SET ns_noc_io_spio_soc_ip.csr 141937 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 141948 BASE_ADDRESS_0_33 Base address 39 6 0x004000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 141955 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 142048 spio_sp_main0_srvcproc_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 0x44848 R/W 0x000000ff00000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_4g__8g__4g_22_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_P_SET ns_noc_io_spio_soc_ip.csr 141973 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_NS_SET ns_noc_io_spio_soc_ip.csr 141984 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_I_SET ns_noc_io_spio_soc_ip.csr 141995 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_VAL_SET ns_noc_io_spio_soc_ip.csr 142006 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_TM_SET ns_noc_io_spio_soc_ip.csr 142018 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_RSV_SET ns_noc_io_spio_soc_ip.csr 142029 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 142040 MASK_0_33 Mask 39 6 0x3fc000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_4G__8G__4G_22_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 142047 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 142164 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 0x44860 R/W 0x0000008000000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_SET ns_noc_io_spio_soc_ip.csr 142088 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_SET ns_noc_io_spio_soc_ip.csr 142099 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_SET ns_noc_io_spio_soc_ip.csr 142110 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 142122 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_DI_SET ns_noc_io_spio_soc_ip.csr 142133 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_LLC_SET ns_noc_io_spio_soc_ip.csr 142145 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 142156 BASE_ADDRESS_0_33 Base address 39 6 0x200000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 142163 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 142256 spio_sp_main0_srvcproc_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 0x44868 R/W 0x000000f800000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_512g__544g__32g_23_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_P_SET ns_noc_io_spio_soc_ip.csr 142181 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_NS_SET ns_noc_io_spio_soc_ip.csr 142192 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_I_SET ns_noc_io_spio_soc_ip.csr 142203 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_VAL_SET ns_noc_io_spio_soc_ip.csr 142214 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_TM_SET ns_noc_io_spio_soc_ip.csr 142226 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_RSV_SET ns_noc_io_spio_soc_ip.csr 142237 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 142248 MASK_0_33 Mask 39 6 0x3e0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_512G__544G__32G_23_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 142255 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 142372 spio_sp_main0_srvcproc_m register am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 0x44880 R/W 0x000000c000000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_adbase_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_SET ns_noc_io_spio_soc_ip.csr 142296 P 1'b1: Privileged 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_SET ns_noc_io_spio_soc_ip.csr 142307 NS 1'b1: Non-secure 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_SET ns_noc_io_spio_soc_ip.csr 142318 I 1'b1: Instruction 2 2 0x0 R/W R_Wn SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_R_WN_SET ns_noc_io_spio_soc_ip.csr 142330 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_DI_SET ns_noc_io_spio_soc_ip.csr 142341 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_LLC_SET ns_noc_io_spio_soc_ip.csr 142353 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BASE_ADDRESS_0_33_SET ns_noc_io_spio_soc_ip.csr 142364 BASE_ADDRESS_0_33 Base address 39 6 0x300000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADBASE_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 142371 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 142464 spio_sp_main0_srvcproc_m register am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 0x44888 R/W 0x000000f800000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_admask_mem_spio_sp_main0_sp_main_pu_s_sr_spio_sp_main0_sp_main_pu_s_map_r_768g__800g__32g_24_0 See AM_ADBASE. false false false false P SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_P_SET ns_noc_io_spio_soc_ip.csr 142389 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_NS_SET ns_noc_io_spio_soc_ip.csr 142400 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_I_SET ns_noc_io_spio_soc_ip.csr 142411 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_VAL_SET ns_noc_io_spio_soc_ip.csr 142422 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_TM_SET ns_noc_io_spio_soc_ip.csr 142434 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_RSV_SET ns_noc_io_spio_soc_ip.csr 142445 RSV Reserved 5 5 0x0 R/W MASK_0_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_MASK_0_33_SET ns_noc_io_spio_soc_ip.csr 142456 MASK_0_33 Mask 39 6 0x3e0000000 R/W UNSD_34_57 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ADMASK_MEM_SPIO_SP_MAIN0_SP_MAIN_PU_S_SR_SPIO_SP_MAIN0_SP_MAIN_PU_S_MAP_R_768G__800G__32G_24_0_UNSD_34_57_SET ns_noc_io_spio_soc_ip.csr 142463 UNSD_34_57 63 40 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_p_0 bridge_spio_sp_main0_srvcproc_m_3_6_p_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 142529 spio_sp_main0_srvcproc_m register p_0 0x47000 R/W 0x00000003 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_0_SET ns_noc_io_spio_soc_ip.csr 142492 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_1_SET ns_noc_io_spio_soc_ip.csr 142504 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_2_SET ns_noc_io_spio_soc_ip.csr 142516 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_0_WT_QOS_3_SET ns_noc_io_spio_soc_ip.csr 142528 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_p_1 bridge_spio_sp_main0_srvcproc_m_3_6_p_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 142595 spio_sp_main0_srvcproc_m register p_1 0x47008 R 0x00000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_4_SET ns_noc_io_spio_soc_ip.csr 142558 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_5_SET ns_noc_io_spio_soc_ip.csr 142570 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_6_SET ns_noc_io_spio_soc_ip.csr 142582 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_1_WT_QOS_7_SET ns_noc_io_spio_soc_ip.csr 142594 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_p_2 bridge_spio_sp_main0_srvcproc_m_3_6_p_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 142661 spio_sp_main0_srvcproc_m register p_2 0x47010 R 0x00000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_8_SET ns_noc_io_spio_soc_ip.csr 142624 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_9_SET ns_noc_io_spio_soc_ip.csr 142636 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_10_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_10_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_10_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_10_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_10_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_10_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_10_SET ns_noc_io_spio_soc_ip.csr 142648 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_2_WT_QOS_11_SET ns_noc_io_spio_soc_ip.csr 142660 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_p_3 bridge_spio_sp_main0_srvcproc_m_3_6_p_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 142727 spio_sp_main0_srvcproc_m register p_3 0x47018 R 0x00000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_12_SET ns_noc_io_spio_soc_ip.csr 142690 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_13_SET ns_noc_io_spio_soc_ip.csr 142702 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_14_SET ns_noc_io_spio_soc_ip.csr 142714 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_P_3_WT_QOS_15_SET ns_noc_io_spio_soc_ip.csr 142726 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_txe bridge_spio_sp_main0_srvcproc_m_3_6_txe SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 142873 spio_sp_main0_srvcproc_m register txe 0x47040 R/W 0x00000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_TRANS_WITHOUT_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_TRANS_WITHOUT_SOP_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_TRANS_WITHOUT_SOP_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_TRANS_WITHOUT_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_TRANS_WITHOUT_SOP_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_TRANS_WITHOUT_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_TRANS_WITHOUT_SOP_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_spio_soc_ip.csr 142754 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_SOP_AFTER_SOP_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_SOP_AFTER_SOP_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_SOP_AFTER_SOP_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_SOP_AFTER_SOP_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_SOP_AFTER_SOP_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_SOP_AFTER_SOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_SOP_AFTER_SOP_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_SOP_AFTER_SOP_SET ns_noc_io_spio_soc_ip.csr 142766 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 142781 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 142794 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_spio_soc_ip.csr 142808 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_spio_soc_ip.csr 142822 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_spio_soc_ip.csr 142836 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_spio_soc_ip.csr 142850 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 142861 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXE_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 142872 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_txem bridge_spio_sp_main0_srvcproc_m_3_6_txem SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 142952 spio_sp_main0_srvcproc_m register txem 0x47048 R/W 0x00000008 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_UNSD_1_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_UNSD_1_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_UNSD_1_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_UNSD_1_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_UNSD_1_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_UNSD_1_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_UNSD_1_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_UNSD_1_0_SET ns_noc_io_spio_soc_ip.csr 142896 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_TRANS_ILLEGAL_DEST_QOS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_spio_soc_ip.csr 142907 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_EVENT_CNTR_OVERFLOW_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_EVENT_CNTR_OVERFLOW_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_EVENT_CNTR_OVERFLOW_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_EVENT_CNTR_OVERFLOW_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_EVENT_CNTR_OVERFLOW_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_EVENT_CNTR_OVERFLOW_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_spio_soc_ip.csr 142918 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_UNSD_7_4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_UNSD_7_4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_UNSD_7_4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_UNSD_7_4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_UNSD_7_4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_UNSD_7_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_UNSD_7_4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_UNSD_7_4_SET ns_noc_io_spio_soc_ip.csr 142929 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 142940 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_UNSD_31_9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_UNSD_31_9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_UNSD_31_9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_UNSD_31_9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_UNSD_31_9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_UNSD_31_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_UNSD_31_9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_TXEM_UNSD_31_9_SET ns_noc_io_spio_soc_ip.csr 142951 UNSD_31_9 31 9 0x000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btus_0 bridge_spio_sp_main0_srvcproc_m_3_6_btus_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 143320 spio_sp_main0_srvcproc_m register btus_0 0x47058 R 0x00000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_A_SET ns_noc_io_spio_soc_ip.csr 142978 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_B_SET ns_noc_io_spio_soc_ip.csr 142989 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_C_SET ns_noc_io_spio_soc_ip.csr 143000 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L0_D_SET ns_noc_io_spio_soc_ip.csr 143011 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_A_SET ns_noc_io_spio_soc_ip.csr 143022 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_B_SET ns_noc_io_spio_soc_ip.csr 143033 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_C_SET ns_noc_io_spio_soc_ip.csr 143044 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L1_D_SET ns_noc_io_spio_soc_ip.csr 143055 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_A_SET ns_noc_io_spio_soc_ip.csr 143066 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_B_SET ns_noc_io_spio_soc_ip.csr 143077 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_C_SET ns_noc_io_spio_soc_ip.csr 143088 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L2_D_SET ns_noc_io_spio_soc_ip.csr 143099 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_A_SET ns_noc_io_spio_soc_ip.csr 143110 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_B_SET ns_noc_io_spio_soc_ip.csr 143121 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_C_SET ns_noc_io_spio_soc_ip.csr 143132 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L3_D_SET ns_noc_io_spio_soc_ip.csr 143143 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_A_SET ns_noc_io_spio_soc_ip.csr 143154 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_B_SET ns_noc_io_spio_soc_ip.csr 143165 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_C_SET ns_noc_io_spio_soc_ip.csr 143176 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L4_D_SET ns_noc_io_spio_soc_ip.csr 143187 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_A_SET ns_noc_io_spio_soc_ip.csr 143198 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_B_SET ns_noc_io_spio_soc_ip.csr 143209 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_C_SET ns_noc_io_spio_soc_ip.csr 143220 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L5_D_SET ns_noc_io_spio_soc_ip.csr 143231 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_A_SET ns_noc_io_spio_soc_ip.csr 143242 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_B_SET ns_noc_io_spio_soc_ip.csr 143253 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_C_SET ns_noc_io_spio_soc_ip.csr 143264 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L6_D_SET ns_noc_io_spio_soc_ip.csr 143275 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_A_SET ns_noc_io_spio_soc_ip.csr 143286 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_B_SET ns_noc_io_spio_soc_ip.csr 143297 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_C_SET ns_noc_io_spio_soc_ip.csr 143308 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_0_L7_D_SET ns_noc_io_spio_soc_ip.csr 143319 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btus_1 bridge_spio_sp_main0_srvcproc_m_3_6_btus_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 143688 spio_sp_main0_srvcproc_m register btus_1 0x47060 R 0x00000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_A_SET ns_noc_io_spio_soc_ip.csr 143346 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_B_SET ns_noc_io_spio_soc_ip.csr 143357 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_C_SET ns_noc_io_spio_soc_ip.csr 143368 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L8_D_SET ns_noc_io_spio_soc_ip.csr 143379 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_A_SET ns_noc_io_spio_soc_ip.csr 143390 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_B_SET ns_noc_io_spio_soc_ip.csr 143401 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_C_SET ns_noc_io_spio_soc_ip.csr 143412 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L9_D_SET ns_noc_io_spio_soc_ip.csr 143423 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_A_SET ns_noc_io_spio_soc_ip.csr 143434 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_B_SET ns_noc_io_spio_soc_ip.csr 143445 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_C_SET ns_noc_io_spio_soc_ip.csr 143456 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L10_D_SET ns_noc_io_spio_soc_ip.csr 143467 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_A_SET ns_noc_io_spio_soc_ip.csr 143478 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_B_SET ns_noc_io_spio_soc_ip.csr 143489 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_C_SET ns_noc_io_spio_soc_ip.csr 143500 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L11_D_SET ns_noc_io_spio_soc_ip.csr 143511 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_A_SET ns_noc_io_spio_soc_ip.csr 143522 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_B_SET ns_noc_io_spio_soc_ip.csr 143533 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_C_SET ns_noc_io_spio_soc_ip.csr 143544 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L12_D_SET ns_noc_io_spio_soc_ip.csr 143555 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_A_SET ns_noc_io_spio_soc_ip.csr 143566 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_B_SET ns_noc_io_spio_soc_ip.csr 143577 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_C_SET ns_noc_io_spio_soc_ip.csr 143588 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L13_D_SET ns_noc_io_spio_soc_ip.csr 143599 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_A_SET ns_noc_io_spio_soc_ip.csr 143610 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_B_SET ns_noc_io_spio_soc_ip.csr 143621 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_C_SET ns_noc_io_spio_soc_ip.csr 143632 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L14_D_SET ns_noc_io_spio_soc_ip.csr 143643 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_A_SET ns_noc_io_spio_soc_ip.csr 143654 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_B_SET ns_noc_io_spio_soc_ip.csr 143665 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_C_SET ns_noc_io_spio_soc_ip.csr 143676 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTUS_1_L15_D_SET ns_noc_io_spio_soc_ip.csr 143687 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btrl_0 bridge_spio_sp_main0_srvcproc_m_3_6_btrl_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 143764 spio_sp_main0_srvcproc_m register btrl_0 0x47080 R 0x00000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_WT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_WT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_WT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_WT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_WT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_WT_SET ns_noc_io_spio_soc_ip.csr 143712 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 143723 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_CNT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_CNT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_CNT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_CNT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_CNT_SET ns_noc_io_spio_soc_ip.csr 143738 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_EN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_EN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_EN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_EN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_EN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_EN_SET ns_noc_io_spio_soc_ip.csr 143752 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_0_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 143763 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btrl_1 bridge_spio_sp_main0_srvcproc_m_3_6_btrl_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 143840 spio_sp_main0_srvcproc_m register btrl_1 0x47088 R 0x00000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_WT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_WT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_WT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_WT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_WT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_WT_SET ns_noc_io_spio_soc_ip.csr 143788 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 143799 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_CNT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_CNT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_CNT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_CNT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_CNT_SET ns_noc_io_spio_soc_ip.csr 143814 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_EN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_EN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_EN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_EN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_EN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_EN_SET ns_noc_io_spio_soc_ip.csr 143828 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_1_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 143839 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btrl_2 bridge_spio_sp_main0_srvcproc_m_3_6_btrl_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 143916 spio_sp_main0_srvcproc_m register btrl_2 0x47090 R 0x00000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_WT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_WT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_WT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_WT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_WT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_WT_SET ns_noc_io_spio_soc_ip.csr 143864 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 143875 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_CNT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_CNT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_CNT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_CNT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_CNT_SET ns_noc_io_spio_soc_ip.csr 143890 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_EN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_EN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_EN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_EN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_EN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_EN_SET ns_noc_io_spio_soc_ip.csr 143904 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_2_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 143915 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btrl_3 bridge_spio_sp_main0_srvcproc_m_3_6_btrl_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 143992 spio_sp_main0_srvcproc_m register btrl_3 0x47098 R 0x00000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_WT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_WT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_WT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_WT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_WT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_WT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_WT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_WT_SET ns_noc_io_spio_soc_ip.csr 143940 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_RESV_15_12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_RESV_15_12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_RESV_15_12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_RESV_15_12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_RESV_15_12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_RESV_15_12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_RESV_15_12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_RESV_15_12_SET ns_noc_io_spio_soc_ip.csr 143951 RESV_15_12 15 12 0x0 R CNT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_CNT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_CNT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_CNT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_CNT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_CNT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_CNT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_CNT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_CNT_SET ns_noc_io_spio_soc_ip.csr 143966 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_EN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_EN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_EN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_EN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_EN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_EN_SET ns_noc_io_spio_soc_ip.csr 143980 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_UNSD_31_21_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_UNSD_31_21_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_UNSD_31_21_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_UNSD_31_21_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_UNSD_31_21_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_UNSD_31_21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_UNSD_31_21_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTRL_3_UNSD_31_21_SET ns_noc_io_spio_soc_ip.csr 143991 UNSD_31_21 31 21 0x000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btperr bridge_spio_sp_main0_srvcproc_m_3_6_btperr SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 144194 spio_sp_main0_srvcproc_m register btperr 0x470A8 R/W 0x00000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L0_SET ns_noc_io_spio_soc_ip.csr 144017 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L1_SET ns_noc_io_spio_soc_ip.csr 144028 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L2_SET ns_noc_io_spio_soc_ip.csr 144039 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L3_SET ns_noc_io_spio_soc_ip.csr 144050 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L4_SET ns_noc_io_spio_soc_ip.csr 144061 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L5_SET ns_noc_io_spio_soc_ip.csr 144072 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L6_SET ns_noc_io_spio_soc_ip.csr 144083 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L7_SET ns_noc_io_spio_soc_ip.csr 144094 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L8_SET ns_noc_io_spio_soc_ip.csr 144105 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L9_SET ns_noc_io_spio_soc_ip.csr 144116 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L10_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L10_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L10_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L10_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L10_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L10_SET ns_noc_io_spio_soc_ip.csr 144127 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L11_SET ns_noc_io_spio_soc_ip.csr 144138 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L12_SET ns_noc_io_spio_soc_ip.csr 144149 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L13_SET ns_noc_io_spio_soc_ip.csr 144160 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L14_SET ns_noc_io_spio_soc_ip.csr 144171 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_L15_SET ns_noc_io_spio_soc_ip.csr 144182 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_UNSD_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERR_UNSD_SET ns_noc_io_spio_soc_ip.csr 144193 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_btperrm bridge_spio_sp_main0_srvcproc_m_3_6_btperrm SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 144394 spio_sp_main0_srvcproc_m register btperrm 0x470B0 R/W 0x00000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L0_SET ns_noc_io_spio_soc_ip.csr 144217 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L1_SET ns_noc_io_spio_soc_ip.csr 144228 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L2_SET ns_noc_io_spio_soc_ip.csr 144239 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L3_SET ns_noc_io_spio_soc_ip.csr 144250 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L4_SET ns_noc_io_spio_soc_ip.csr 144261 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L5_SET ns_noc_io_spio_soc_ip.csr 144272 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L6_SET ns_noc_io_spio_soc_ip.csr 144283 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L7_SET ns_noc_io_spio_soc_ip.csr 144294 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L8_SET ns_noc_io_spio_soc_ip.csr 144305 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L9_SET ns_noc_io_spio_soc_ip.csr 144316 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L10_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L10_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L10_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L10_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L10_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L10_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L10_SET ns_noc_io_spio_soc_ip.csr 144327 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L11_SET ns_noc_io_spio_soc_ip.csr 144338 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L12_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L12_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L12_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L12_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L12_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L12_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L12_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L12_SET ns_noc_io_spio_soc_ip.csr 144349 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L13_SET ns_noc_io_spio_soc_ip.csr 144360 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L14_SET ns_noc_io_spio_soc_ip.csr 144371 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_L15_SET ns_noc_io_spio_soc_ip.csr 144382 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_UNSD_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_UNSD_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_UNSD_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_UNSD_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_UNSD_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_UNSD_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_UNSD_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BTPERRM_UNSD_SET ns_noc_io_spio_soc_ip.csr 144393 UNSD 31 16 0x0000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_rxe bridge_spio_sp_main0_srvcproc_m_3_6_rxe SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 144502 spio_sp_main0_srvcproc_m register rxe 0x47120 R/W 0x00000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_A_SET ns_noc_io_spio_soc_ip.csr 144422 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_B_SET ns_noc_io_spio_soc_ip.csr 144433 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_C_SET ns_noc_io_spio_soc_ip.csr 144444 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_CRC_OFLW_D_SET ns_noc_io_spio_soc_ip.csr 144455 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_EVC_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_EVC_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_EVC_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_EVC_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_EVC_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_EVC_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_EVC_OFLW_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_EVC_OFLW_SET ns_noc_io_spio_soc_ip.csr 144467 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_PARITY_ERR_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_PARITY_ERR_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_PARITY_ERR_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_PARITY_ERR_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_PARITY_ERR_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_PARITY_ERR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_PARITY_ERR_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_PARITY_ERR_SET ns_noc_io_spio_soc_ip.csr 144478 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_EVC1_OFLW_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_EVC1_OFLW_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_EVC1_OFLW_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_EVC1_OFLW_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_EVC1_OFLW_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_EVC1_OFLW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_EVC1_OFLW_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_EVC1_OFLW_SET ns_noc_io_spio_soc_ip.csr 144490 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXE_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 144501 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_rxem bridge_spio_sp_main0_srvcproc_m_3_6_rxem SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 144574 spio_sp_main0_srvcproc_m register rxem 0x47128 R/W 0x00000050 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_UNSD_3_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_UNSD_3_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_UNSD_3_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_UNSD_3_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_UNSD_3_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_UNSD_3_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_UNSD_3_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_UNSD_3_0_SET ns_noc_io_spio_soc_ip.csr 144523 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_EVC_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_EVC_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_EVC_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_EVC_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_EVC_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_EVC_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_EVC_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_EVC_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 144537 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_PARITY_ERR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_PARITY_ERR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_PARITY_ERR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_PARITY_ERR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_PARITY_ERR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_PARITY_ERR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_PARITY_ERR_MASK_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_PARITY_ERR_MASK_SET ns_noc_io_spio_soc_ip.csr 144548 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_EVC1_OFLW_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_EVC1_OFLW_MASK_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_EVC1_OFLW_MASK_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_EVC1_OFLW_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_EVC1_OFLW_MASK_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_EVC1_OFLW_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_EVC1_OFLW_MASK_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_spio_soc_ip.csr 144562 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_UNSD_31_7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_UNSD_31_7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_UNSD_31_7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_UNSD_31_7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_UNSD_31_7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_UNSD_31_7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_UNSD_31_7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_RXEM_UNSD_31_7_SET ns_noc_io_spio_soc_ip.csr 144573 UNSD_31_7 31 7 0x0000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_brs_0 bridge_spio_sp_main0_srvcproc_m_3_6_brs_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 144848 spio_sp_main0_srvcproc_m register brs_0 0x47130 R 0x00000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 144598 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_0_SET ns_noc_io_spio_soc_ip.csr 144609 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_0_SET ns_noc_io_spio_soc_ip.csr 144620 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_0_SET ns_noc_io_spio_soc_ip.csr 144631 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_0_SET ns_noc_io_spio_soc_ip.csr 144642 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 144652 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 144663 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_1_SET ns_noc_io_spio_soc_ip.csr 144674 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_1_SET ns_noc_io_spio_soc_ip.csr 144685 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_1_SET ns_noc_io_spio_soc_ip.csr 144696 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_1_SET ns_noc_io_spio_soc_ip.csr 144707 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 144717 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 144728 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_2_SET ns_noc_io_spio_soc_ip.csr 144739 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_2_SET ns_noc_io_spio_soc_ip.csr 144750 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_2_SET ns_noc_io_spio_soc_ip.csr 144761 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_2_SET ns_noc_io_spio_soc_ip.csr 144772 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 144782 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 144793 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_V_3_SET ns_noc_io_spio_soc_ip.csr 144804 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_S_3_SET ns_noc_io_spio_soc_ip.csr 144815 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_B_3_SET ns_noc_io_spio_soc_ip.csr 144826 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_F_3_SET ns_noc_io_spio_soc_ip.csr 144837 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_0_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 144847 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_brs_1 bridge_spio_sp_main0_srvcproc_m_3_6_brs_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 145122 spio_sp_main0_srvcproc_m register brs_1 0x47138 R 0x00000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_0_SET ns_noc_io_spio_soc_ip.csr 144872 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_0_SET ns_noc_io_spio_soc_ip.csr 144883 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_0_SET ns_noc_io_spio_soc_ip.csr 144894 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_0_SET ns_noc_io_spio_soc_ip.csr 144905 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_0_SET ns_noc_io_spio_soc_ip.csr 144916 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 144926 UNSD_7_6 7 6 0x0 R OUTI_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_1_SET ns_noc_io_spio_soc_ip.csr 144937 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_1_SET ns_noc_io_spio_soc_ip.csr 144948 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_1_SET ns_noc_io_spio_soc_ip.csr 144959 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_1_SET ns_noc_io_spio_soc_ip.csr 144970 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_1_SET ns_noc_io_spio_soc_ip.csr 144981 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_15_14_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_15_14_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_15_14_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_15_14_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_15_14_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_15_14_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_15_14_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_15_14_SET ns_noc_io_spio_soc_ip.csr 144991 UNSD_15_14 15 14 0x0 R OUTI_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_2_SET ns_noc_io_spio_soc_ip.csr 145002 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_2_SET ns_noc_io_spio_soc_ip.csr 145013 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_2_SET ns_noc_io_spio_soc_ip.csr 145024 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_2_SET ns_noc_io_spio_soc_ip.csr 145035 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_2_SET ns_noc_io_spio_soc_ip.csr 145046 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_23_22_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_23_22_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_23_22_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_23_22_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_23_22_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_23_22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_23_22_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_23_22_SET ns_noc_io_spio_soc_ip.csr 145056 UNSD_23_22 23 22 0x0 R OUTI_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_OUTI_3_SET ns_noc_io_spio_soc_ip.csr 145067 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_V_3_SET ns_noc_io_spio_soc_ip.csr 145078 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_S_3_SET ns_noc_io_spio_soc_ip.csr 145089 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_B_3_SET ns_noc_io_spio_soc_ip.csr 145100 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_F_3_SET ns_noc_io_spio_soc_ip.csr 145111 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_31_30_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_31_30_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_31_30_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_31_30_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_31_30_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_31_30_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_31_30_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRS_1_UNSD_31_30_SET ns_noc_io_spio_soc_ip.csr 145121 UNSD_31_30 31 30 0x0 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_brus bridge_spio_sp_main0_srvcproc_m_3_6_brus SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 145191 spio_sp_main0_srvcproc_m register brus 0x471B0 R 0x00000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_A_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_A_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_A_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_A_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_A_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_A_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_A_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_A_SET ns_noc_io_spio_soc_ip.csr 145147 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_B_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_B_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_B_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_B_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_B_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_B_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_B_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_B_SET ns_noc_io_spio_soc_ip.csr 145158 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_C_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_C_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_C_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_C_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_C_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_C_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_C_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_C_SET ns_noc_io_spio_soc_ip.csr 145169 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_D_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_D_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_D_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_D_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_D_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_D_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_D_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_V_D_SET ns_noc_io_spio_soc_ip.csr 145180 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_UNSD_31_4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_UNSD_31_4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_UNSD_31_4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_UNSD_31_4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_UNSD_31_4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_UNSD_31_4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_UNSD_31_4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRUS_UNSD_31_4_SET ns_noc_io_spio_soc_ip.csr 145190 UNSD_31_4 31 4 0x0000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_brperr0 bridge_spio_sp_main0_srvcproc_m_3_6_brperr0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 145419 spio_sp_main0_srvcproc_m register brperr0 0x471D0 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_D0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_D0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_D0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_D0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_D0_SET ns_noc_io_spio_soc_ip.csr 145229 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_DC0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_DC0_SET ns_noc_io_spio_soc_ip.csr 145240 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SB0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SB0_SET ns_noc_io_spio_soc_ip.csr 145251 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SBC0_SET ns_noc_io_spio_soc_ip.csr 145263 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_PK0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_PK0_SET ns_noc_io_spio_soc_ip.csr 145274 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 145285 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_D1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_D1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_D1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_D1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_D1_SET ns_noc_io_spio_soc_ip.csr 145296 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_DC1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_DC1_SET ns_noc_io_spio_soc_ip.csr 145307 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SB1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SB1_SET ns_noc_io_spio_soc_ip.csr 145318 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_SBC1_SET ns_noc_io_spio_soc_ip.csr 145330 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_PK1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_PK1_SET ns_noc_io_spio_soc_ip.csr 145341 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 145352 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 145363 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 145374 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 145385 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 145396 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 145407 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 145418 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_brperr1 bridge_spio_sp_main0_srvcproc_m_3_6_brperr1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 145535 spio_sp_main0_srvcproc_m register brperr1 0x471D8 R 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 145457 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 145468 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 145479 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 145490 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 145501 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 145512 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 145523 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERR1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 145534 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_brperrm0 bridge_spio_sp_main0_srvcproc_m_3_6_brperrm0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 145756 spio_sp_main0_srvcproc_m register brperrm0 0x471E0 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_D0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_D0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_D0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_D0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_D0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_D0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_D0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_D0_SET ns_noc_io_spio_soc_ip.csr 145562 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_DC0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_DC0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_DC0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_DC0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_DC0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_DC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_DC0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_DC0_SET ns_noc_io_spio_soc_ip.csr 145574 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SB0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SB0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SB0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SB0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SB0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SB0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SB0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SB0_SET ns_noc_io_spio_soc_ip.csr 145585 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SBC0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SBC0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SBC0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SBC0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SBC0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SBC0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SBC0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SBC0_SET ns_noc_io_spio_soc_ip.csr 145597 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_PK0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_PK0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_PK0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_PK0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_PK0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_PK0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_PK0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_PK0_SET ns_noc_io_spio_soc_ip.csr 145609 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_7_5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_7_5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_7_5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_7_5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_7_5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_7_5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_7_5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_7_5_SET ns_noc_io_spio_soc_ip.csr 145620 UNSD_7_5 7 5 0x0 R D1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_D1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_D1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_D1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_D1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_D1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_D1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_D1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_D1_SET ns_noc_io_spio_soc_ip.csr 145631 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_DC1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_DC1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_DC1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_DC1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_DC1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_DC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_DC1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_DC1_SET ns_noc_io_spio_soc_ip.csr 145643 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SB1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SB1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SB1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SB1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SB1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SB1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SB1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SB1_SET ns_noc_io_spio_soc_ip.csr 145654 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SBC1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SBC1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SBC1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SBC1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SBC1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SBC1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SBC1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_SBC1_SET ns_noc_io_spio_soc_ip.csr 145666 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_PK1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_PK1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_PK1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_PK1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_PK1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_PK1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_PK1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_PK1_SET ns_noc_io_spio_soc_ip.csr 145678 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_15_13_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_15_13_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_15_13_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_15_13_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_15_13_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_15_13_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_15_13_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_15_13_SET ns_noc_io_spio_soc_ip.csr 145689 UNSD_15_13 15 13 0x0 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 145700 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 145711 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 145722 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 145733 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 145744 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM0_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 145755 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_brperrm1 bridge_spio_sp_main0_srvcproc_m_3_6_brperrm1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 145861 spio_sp_main0_srvcproc_m register brperrm1 0x471E8 R 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_7_0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_7_0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_7_0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_7_0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_7_0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_7_0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_7_0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_7_0_SET ns_noc_io_spio_soc_ip.csr 145783 UNSD_7_0 7 0 0x00 R UNSD_15_8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_15_8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_15_8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_15_8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_15_8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_15_8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_15_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_15_8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_15_8_SET ns_noc_io_spio_soc_ip.csr 145794 UNSD_15_8 15 8 0x00 R UNSD_23_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_23_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_23_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_23_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_23_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_23_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_23_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_23_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_23_16_SET ns_noc_io_spio_soc_ip.csr 145805 UNSD_23_16 23 16 0x00 R UNSD_31_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_31_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_31_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_31_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_31_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_31_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_31_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_31_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_31_24_SET ns_noc_io_spio_soc_ip.csr 145816 UNSD_31_24 31 24 0x00 R UNSD_39_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_39_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_39_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_39_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_39_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_39_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_39_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_39_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_39_32_SET ns_noc_io_spio_soc_ip.csr 145827 UNSD_39_32 39 32 0x00 R UNSD_47_40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_47_40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_47_40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_47_40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_47_40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_47_40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_47_40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_47_40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_47_40_SET ns_noc_io_spio_soc_ip.csr 145838 UNSD_47_40 47 40 0x00 R UNSD_55_48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_55_48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_55_48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_55_48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_55_48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_55_48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_55_48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_55_48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_55_48_SET ns_noc_io_spio_soc_ip.csr 145849 UNSD_55_48 55 48 0x00 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_BRPERRM1_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 145860 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_tocfg bridge_spio_sp_main0_srvcproc_m_3_6_am_tocfg SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 145935 spio_sp_main0_srvcproc_m register am_tocfg 0x47C00 R/W 0x000000000000001f Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_tocfg This register is used to configure response timeouts. AM_TOCFG[8] (En) needs to be set for timeout tracking to be enabled. When this bit is 1'b0, no timestamps are recorded to generate timeout interrupts. A 64-bit free running counter is used to time the response interval. AM_TOCFG[5:0] (TI) specifies the lower bit index into this counter, from where 2-bits are picked up and recorded as the arrival time stamp of every incoming AR and AW command. If response for a command does not return before the current time stamp rolls to arrival time stamp minus 1, the response is assumed to have timedout and an interrupt is raised along with the slave ID to which the timed out request was sent. When changing the TI field, first write to the register with the En field cleared, then write a second time with the TI field to its new value, then a 3rd write to restore the En field to Enabled. During this update while the En field is cleared, existing timers will cancelled, and new timer starts will be inhibited. false false false false TI SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_TI_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_TI_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_TI_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_TI_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_TI_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_TI_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_TI_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_TI_SET ns_noc_io_spio_soc_ip.csr 145898 TI Timer index, index of a 64-bit counter from where timestamp is picked. The register value has to be 'd62 or smaller. 5 0 0x1f R/W UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 145909 UNSD_7_6 7 6 0x0 R EN SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_EN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_EN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_EN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_EN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_EN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_EN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_EN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_EN_SET ns_noc_io_spio_soc_ip.csr 145923 EN 1'b1: Enabled timeout tracking, a 64-bit free running counter is used to time the response interval. 1'b0: No timestamps are recorded to generate timeout interrupts 8 8 0x0 R/W UNSD_63_9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_UNSD_63_9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_UNSD_63_9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_UNSD_63_9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_UNSD_63_9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_UNSD_63_9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_UNSD_63_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_UNSD_63_9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOCFG_UNSD_63_9_SET ns_noc_io_spio_soc_ip.csr 145934 UNSD_63_9 63 9 0x00000000000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_osslv bridge_spio_sp_main0_srvcproc_m_3_6_am_osslv SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_OSSLV_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_OSSLV_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_OSSLV_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_OSSLV_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 145970 spio_sp_main0_srvcproc_m register am_osslv 0x47C08 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_osslv This register is used to check if there are any outstanding read/write commands to a slave specified by field slvid. NocStudio provides a table of slvids corresponding to the slave ports accessible from a master bridge. Outstanding status is reflected in AM_STS. false false false false SLVID SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_OSSLV_SLVID_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_OSSLV_SLVID_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_OSSLV_SLVID_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_OSSLV_SLVID_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_OSSLV_SLVID_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_OSSLV_SLVID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_OSSLV_SLVID_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_OSSLV_SLVID_SET ns_noc_io_spio_soc_ip.csr 145958 SLVID A slave ID associated with the current master for command outstanding status 15 0 0x0000 R/W UNSD_63_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_OSSLV_UNSD_63_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_OSSLV_UNSD_63_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_OSSLV_UNSD_63_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_OSSLV_UNSD_63_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_OSSLV_UNSD_63_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_OSSLV_UNSD_63_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_OSSLV_UNSD_63_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_OSSLV_UNSD_63_16_SET ns_noc_io_spio_soc_ip.csr 145969 UNSD_63_16 63 16 0x000000000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_cgc bridge_spio_sp_main0_srvcproc_m_3_6_am_cgc SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGC_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGC_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGC_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 146007 spio_sp_main0_srvcproc_m register am_cgc 0x47C10 R/W 0x0000000000000064 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_cgc Programmable interval used by coarse clock gating logic in master bridge.This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGC_HYSTERESIS_COUNTER_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGC_HYSTERESIS_COUNTER_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGC_HYSTERESIS_COUNTER_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGC_HYSTERESIS_COUNTER_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGC_HYSTERESIS_COUNTER_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGC_HYSTERESIS_COUNTER_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGC_HYSTERESIS_COUNTER_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_spio_soc_ip.csr 145995 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGC_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGC_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGC_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGC_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGC_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGC_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGC_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGC_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 146006 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_cgo bridge_spio_sp_main0_srvcproc_m_3_6_am_cgo SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGO_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGO_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGO_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGO_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 146042 spio_sp_main0_srvcproc_m register am_cgo 0x47C18 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the master bridge. false false false false FPO SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGO_FPO_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGO_FPO_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGO_FPO_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGO_FPO_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGO_FPO_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGO_FPO_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGO_FPO_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGO_FPO_SET ns_noc_io_spio_soc_ip.csr 146030 FPO 1'b1: Clock gating override is enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGO_UNSD_63_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGO_UNSD_63_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGO_UNSD_63_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGO_UNSD_63_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGO_UNSD_63_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGO_UNSD_63_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGO_UNSD_63_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CGO_UNSD_63_1_SET ns_noc_io_spio_soc_ip.csr 146041 UNSD_63_1 63 1 0x0000000000000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_cfg bridge_spio_sp_main0_srvcproc_m_3_6_am_cfg SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CFG_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CFG_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CFG_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CFG_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 146079 spio_sp_main0_srvcproc_m register am_cfg 0x47C20 R/W 0x0000000000000001 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_cfg Configures the master bridge's support for autowake of power domains. When set, master bridge halts a request and issues wakeup requests for power domains that need to powered up to complete the transaction. The power domains should support auto wake. When reset, master bridge issues DECERR for any transaction which has dependent power domains in sleep state. false false false false AW SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CFG_AW_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CFG_AW_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CFG_AW_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CFG_AW_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CFG_AW_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CFG_AW_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CFG_AW_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CFG_AW_SET ns_noc_io_spio_soc_ip.csr 146067 AW 1'b1: Autowake enabled 1'b0: Autowake disabled 0 0 0x1 R/W UNSD_63_1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CFG_UNSD_63_1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CFG_UNSD_63_1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CFG_UNSD_63_1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CFG_UNSD_63_1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CFG_UNSD_63_1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CFG_UNSD_63_1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CFG_UNSD_63_1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CFG_UNSD_63_1_SET ns_noc_io_spio_soc_ip.csr 146078 UNSD_63_1 63 1 0x0000000000000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_sts bridge_spio_sp_main0_srvcproc_m_3_6_am_sts SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 146207 spio_sp_main0_srvcproc_m register am_sts 0x47D00 R 0x000000000000000c Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_sts When reordering is disabled on the master bridge, hazard stall occurs if the master tries to access a new slave device while response from a different slave is outstanding on the same AID. This is because the responses can arrive out of order and the bridge is not equipped to correct the order. Without re-order buffers, hazard stalls also occur if a new large command needs to be split while there are older commands outstanding, or a large command just finished sending all its split segments but all responses have not returned yet. When reordering is enabled, stall due to hazard occurs if a new command arrives, whose NoC QoS is different from the NoC QoS of commands outstanding on that AID. false false false false ROF SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ROF_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ROF_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ROF_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ROF_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ROF_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ROF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ROF_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ROF_SET ns_noc_io_spio_soc_ip.csr 146112 ROF 1'b1: Maximum supported number of read commands are outstanding waiting for response and no more requests can be accepted 1'b0: Master bridge can accept more read requests 0 0 0x0 R WOF SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_WOF_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_WOF_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_WOF_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_WOF_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_WOF_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_WOF_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_WOF_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_WOF_SET ns_noc_io_spio_soc_ip.csr 146126 WOF 1'b1: Maximum supported number of write commands are outstanding waiting for response and no more requests can be accepted 1'b0: Master bridge can accept more write requests 1 1 0x0 R ROE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ROE_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ROE_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ROE_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ROE_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ROE_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ROE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ROE_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ROE_SET ns_noc_io_spio_soc_ip.csr 146138 ROE 1'b1: There are no read commands outstanding from the attached master device 2 2 0x1 R WOE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_WOE_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_WOE_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_WOE_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_WOE_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_WOE_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_WOE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_WOE_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_WOE_SET ns_noc_io_spio_soc_ip.csr 146150 WOE 1'b1: There are no write commands outstanding from the attached master device 3 3 0x1 R ARS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ARS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ARS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ARS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ARS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ARS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ARS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ARS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ARS_SET ns_noc_io_spio_soc_ip.csr 146161 ARS 1'b1: AR channel is stalled on hazard 4 4 0x0 R AWS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_AWS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_AWS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_AWS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_AWS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_AWS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_AWS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_AWS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_AWS_SET ns_noc_io_spio_soc_ip.csr 146172 AWS 1'b1: AW channel is stalled on hazard 5 5 0x0 R ARO SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ARO_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ARO_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ARO_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ARO_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ARO_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ARO_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ARO_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_ARO_SET ns_noc_io_spio_soc_ip.csr 146184 ARO 1'b1: Read commands are outstanding to the slave specified in OSSLV register 6 6 0x0 R AWO SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_AWO_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_AWO_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_AWO_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_AWO_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_AWO_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_AWO_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_AWO_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_AWO_SET ns_noc_io_spio_soc_ip.csr 146196 AWO 1'b1: Write commands are outstanding to the slave specified in OSSLV register 7 7 0x0 R UNSD_63_8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_UNSD_63_8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_UNSD_63_8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_UNSD_63_8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_UNSD_63_8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_UNSD_63_8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_UNSD_63_8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_UNSD_63_8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_STS_UNSD_63_8_SET ns_noc_io_spio_soc_ip.csr 146206 UNSD_63_8 63 8 0x00000000000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_bridge_id bridge_spio_sp_main0_srvcproc_m_3_6_am_bridge_id SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_BRIDGE_ID_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_BRIDGE_ID_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_BRIDGE_ID_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_BRIDGE_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 146237 spio_sp_main0_srvcproc_m register am_bridge_id 0x47D08 R 0x0000000000000003 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_bridge_id Unique identifier assigned to the master bridge. false false false false ID SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_BRIDGE_ID_ID_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_BRIDGE_ID_ID_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_BRIDGE_ID_ID_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_BRIDGE_ID_ID_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_BRIDGE_ID_ID_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_BRIDGE_ID_ID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_BRIDGE_ID_ID_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_BRIDGE_ID_ID_SET ns_noc_io_spio_soc_ip.csr 146226 ID Unique bridge ID 15 0 0x0003 R UNSD_63_16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_BRIDGE_ID_UNSD_63_16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_BRIDGE_ID_UNSD_63_16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_BRIDGE_ID_UNSD_63_16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_BRIDGE_ID_UNSD_63_16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_BRIDGE_ID_UNSD_63_16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_BRIDGE_ID_UNSD_63_16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_BRIDGE_ID_UNSD_63_16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_spio_soc_ip.csr 146236 UNSD_63_16 63 16 0x000000000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_err bridge_spio_sp_main0_srvcproc_m_3_6_am_err SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 146733 spio_sp_main0_srvcproc_m register am_err 0x47E00 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E0_SET ns_noc_io_spio_soc_ip.csr 146259 E0 1'b1: Local read address decode error: ARADDR did not find a match in the master bridges address table and a decode error was issued 0 0 0x0 R/W E1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E1_SET ns_noc_io_spio_soc_ip.csr 146271 E1 1'b1: Read address decode error from slave: A decode error response was received from a slave device 1 1 0x0 R/W E2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E2_SET ns_noc_io_spio_soc_ip.csr 146283 E2 1'b1: Read slave error: A slave error response was received from a slave device 2 2 0x0 R/W E3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E3_SET ns_noc_io_spio_soc_ip.csr 146295 E3 1'b1: Non modifiable WRAP: A WRAP command marked as non-modifiable (ARCACHE[0]=0) was detected 3 3 0x0 R/W E4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E4_SET ns_noc_io_spio_soc_ip.csr 146307 E4 1'b1: [FATAL] Read exclusive split: An AR command of FIXED burst type was detected 4 4 0x0 R/W E5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E5_SET ns_noc_io_spio_soc_ip.csr 146319 E5 1'b1: [FATAL] Read address multi-hit: An AR command matched against multiple entries in the address table 5 5 0x0 R/W E6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E6_SET ns_noc_io_spio_soc_ip.csr 146332 E6 1'b1: Read response timeout: Read response timeout occurred. With timeout enabled, a response wasn't received within the expected interval 6 6 0x0 R/W E7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E7_SET ns_noc_io_spio_soc_ip.csr 146345 E7 1'b1: [FATAL] Read WRAP not equal to supported cacheline size: A WRAP command of unupported cache line size was detected 7 7 0x0 R/W E8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E8_SET ns_noc_io_spio_soc_ip.csr 146356 E8 1'b1: [FATAL] Unexpected narrow read detected 8 8 0x0 R/W UNSD_15_9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_15_9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_15_9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_15_9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_15_9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_15_9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_15_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_15_9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_15_9_SET ns_noc_io_spio_soc_ip.csr 146367 UNSD_15_9 15 9 0x00 R E16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E16_SET ns_noc_io_spio_soc_ip.csr 146378 E16 1'b1: Local write address decode error 16 16 0x0 R/W E17 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E17_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E17_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E17_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E17_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E17_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E17_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E17_SET ns_noc_io_spio_soc_ip.csr 146389 E17 1'b1: Write address decode error from slave 17 17 0x0 R/W E18 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E18_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E18_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E18_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E18_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E18_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E18_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E18_SET ns_noc_io_spio_soc_ip.csr 146400 E18 1'b1: Write slave error 18 18 0x0 R/W E19 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E19_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E19_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E19_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E19_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E19_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E19_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E19_SET ns_noc_io_spio_soc_ip.csr 146411 E19 1'b1: Non modifiable WRAP 19 19 0x0 R/W E20 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E20_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E20_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E20_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E20_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E20_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E20_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E20_SET ns_noc_io_spio_soc_ip.csr 146422 E20 1'b1: [FATAL] Write exclusive split 20 20 0x0 R/W E21 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E21_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E21_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E21_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E21_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E21_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E21_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E21_SET ns_noc_io_spio_soc_ip.csr 146433 E21 1'b1: [FATAL] Write address multi-hit 21 21 0x0 R/W E22 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E22_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E22_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E22_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E22_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E22_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E22_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E22_SET ns_noc_io_spio_soc_ip.csr 146444 E22 1'b1: Write respone timeout 22 22 0x0 R/W E23 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E23_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E23_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E23_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E23_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E23_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E23_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E23_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E23_SET ns_noc_io_spio_soc_ip.csr 146456 E23 1'b1: [FATAL] Write WRAP not equal to supported cacheline size 23 23 0x0 R/W E24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E24_SET ns_noc_io_spio_soc_ip.csr 146467 E24 1'b1: [FATAL] Unexpected narrow write detected 24 24 0x0 R/W UNSD_31_25 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_31_25_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_31_25_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_31_25_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_31_25_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_31_25_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_31_25_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_31_25_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_31_25_SET ns_noc_io_spio_soc_ip.csr 146478 UNSD_31_25 31 25 0x00 R E32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E32_SET ns_noc_io_spio_soc_ip.csr 146489 E32 1'b1: Capture counter0 overflow 32 32 0x0 R/W E33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E33_SET ns_noc_io_spio_soc_ip.csr 146500 E33 1'b1: Capture counter1 overflow 33 33 0x0 R/W E34 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E34_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E34_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E34_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E34_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E34_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E34_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E34_SET ns_noc_io_spio_soc_ip.csr 146512 E34 1'b1: [FATAL] Traffic sent to a noc layer which is power gate 34 34 0x0 R/W E35 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E35_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E35_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E35_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E35_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E35_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E35_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E35_SET ns_noc_io_spio_soc_ip.csr 146524 E35 1'b1: [FATAL] Parity error in configuration/status registers 35 35 0x0 R/W UNSD_39_36 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_39_36_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_39_36_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_39_36_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_39_36_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_39_36_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_39_36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_39_36_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_39_36_SET ns_noc_io_spio_soc_ip.csr 146535 UNSD_39_36 39 36 0x0 R E40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E40_SET ns_noc_io_spio_soc_ip.csr 146547 E40 1'b1: [FATAL] Indicates that portcheck detected error (SIB mode only) 40 40 0x0 R/W E41 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E41_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E41_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E41_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E41_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E41_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E41_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E41_SET ns_noc_io_spio_soc_ip.csr 146558 E41 1'b1: [FATAL] AR Parity Err 41 41 0x0 R/W E42 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E42_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E42_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E42_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E42_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E42_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E42_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E42_SET ns_noc_io_spio_soc_ip.csr 146569 E42 1'b1: [FATAL] ARADDR Parity Err 42 42 0x0 R/W E43 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E43_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E43_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E43_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E43_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E43_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E43_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E43_SET ns_noc_io_spio_soc_ip.csr 146580 E43 1'b1: [FATAL] AW Parity Err 43 43 0x0 R/W E44 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E44_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E44_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E44_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E44_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E44_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E44_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E44_SET ns_noc_io_spio_soc_ip.csr 146591 E44 1'b1: [FATAL] AWADDR Parity Err 44 44 0x0 R/W E45 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E45_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E45_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E45_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E45_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E45_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E45_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E45_SET ns_noc_io_spio_soc_ip.csr 146602 E45 1'b1: [FATAL] WDATA Parity Err 45 45 0x0 R/W E46 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E46_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E46_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E46_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E46_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E46_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E46_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E46_SET ns_noc_io_spio_soc_ip.csr 146613 E46 1'b1: [FATAL] CDDATA Parity Err 46 46 0x0 R/W E47 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E47_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E47_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E47_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E47_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E47_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E47_SET ns_noc_io_spio_soc_ip.csr 146625 E47 1'b1: [FATAL] Ridtbl Entry Parity Err 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E48_SET ns_noc_io_spio_soc_ip.csr 146637 E48 1'b1: [FATAL] Widtbl Entry Parity Err 48 48 0x0 R E49 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E49_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E49_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E49_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E49_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E49_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E49_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E49_SET ns_noc_io_spio_soc_ip.csr 146649 E49 1'b1: [FATAL] Read Reorder Buffer Parity Err 49 49 0x0 R E50 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E50_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E50_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E50_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E50_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E50_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E50_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E50_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E50_SET ns_noc_io_spio_soc_ip.csr 146661 E50 1'b1: [FATAL] Write Reorder Buffer Parity Err 50 50 0x0 R E51 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E51_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E51_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E51_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E51_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E51_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E51_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E51_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E51_SET ns_noc_io_spio_soc_ip.csr 146673 E51 1'b1: [FATAL] Rx Fifo Parity Err 51 51 0x0 R E52 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E52_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E52_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E52_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E52_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E52_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E52_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E52_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E52_SET ns_noc_io_spio_soc_ip.csr 146685 E52 1'b1: [FATAL] Ack Channel Wack Fifo Parity Error 52 52 0x0 R E53 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E53_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E53_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E53_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E53_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E53_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E53_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E53_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E53_SET ns_noc_io_spio_soc_ip.csr 146697 E53 1'b1: [FATAL] Ack Channel Rack Fifo Parity Error 53 53 0x0 R E54 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E54_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E54_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E54_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E54_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E54_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E54_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E54_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E54_SET ns_noc_io_spio_soc_ip.csr 146709 E54 1'b1: [FATAL] CRCD Channel Crid Fifo Parity Error 54 54 0x0 R E55 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E55_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E55_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E55_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E55_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E55_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E55_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E55_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_E55_SET ns_noc_io_spio_soc_ip.csr 146721 E55 1'b1: [FATAL] R Channel Cpkt Fifo Parity Error 55 55 0x0 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERR_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 146732 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_toslvid bridge_spio_sp_main0_srvcproc_m_3_6_am_toslvid SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOSLVID_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOSLVID_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOSLVID_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOSLVID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 146778 spio_sp_main0_srvcproc_m register am_toslvid 0x47E08 R 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_toslvid AR slvid and AW slvid fields indicate slave IDs to which a read, write response timeout was detected. Note that slvid encoding is not same as the bridge ID of the slave. NocStudio provides a table mapping the slvids to the actual slave ports accessible from the master bridge. false false false false AR_SLVID SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOSLVID_AR_SLVID_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOSLVID_AR_SLVID_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOSLVID_AR_SLVID_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOSLVID_AR_SLVID_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOSLVID_AR_SLVID_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOSLVID_AR_SLVID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOSLVID_AR_SLVID_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOSLVID_AR_SLVID_SET ns_noc_io_spio_soc_ip.csr 146756 AR_SLVID Slave ID of timed out AR request 15 0 0x0000 R AW_SLVID SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOSLVID_AW_SLVID_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOSLVID_AW_SLVID_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOSLVID_AW_SLVID_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOSLVID_AW_SLVID_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOSLVID_AW_SLVID_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOSLVID_AW_SLVID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOSLVID_AW_SLVID_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOSLVID_AW_SLVID_SET ns_noc_io_spio_soc_ip.csr 146767 AW_SLVID Slave ID of timed out AW request 31 16 0x0000 R UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOSLVID_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOSLVID_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOSLVID_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOSLVID_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOSLVID_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOSLVID_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOSLVID_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_TOSLVID_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 146777 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_era bridge_spio_sp_main0_srvcproc_m_3_6_am_era SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERA_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERA_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERA_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERA_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 146800 spio_sp_main0_srvcproc_m register am_era 0x47E10 R 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_era This is the address on AR channel for which a decode error was detected. This corresponds to the status register bit e0 in AM_ERR. false false false false READ_DECERR_ADDRS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERA_READ_DECERR_ADDRS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERA_READ_DECERR_ADDRS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERA_READ_DECERR_ADDRS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERA_READ_DECERR_ADDRS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERA_READ_DECERR_ADDRS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERA_READ_DECERR_ADDRS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERA_READ_DECERR_ADDRS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_ERA_READ_DECERR_ADDRS_SET ns_noc_io_spio_soc_ip.csr 146799 READ_DECERR_ADDRS Read decerr address 63 0 0x0000000000000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_ewa bridge_spio_sp_main0_srvcproc_m_3_6_am_ewa SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_EWA_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_EWA_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_EWA_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_EWA_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 146822 spio_sp_main0_srvcproc_m register am_ewa 0x47E18 R 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_ewa This is the address on AW channel for which a decode error was detected. This corresponds to the status register bit e16 in AM_ERR. false false false false WRITE_DECERR_ADDRS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_EWA_WRITE_DECERR_ADDRS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_EWA_WRITE_DECERR_ADDRS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_EWA_WRITE_DECERR_ADDRS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_EWA_WRITE_DECERR_ADDRS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_EWA_WRITE_DECERR_ADDRS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_EWA_WRITE_DECERR_ADDRS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_EWA_WRITE_DECERR_ADDRS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_EWA_WRITE_DECERR_ADDRS_SET ns_noc_io_spio_soc_ip.csr 146821 WRITE_DECERR_ADDRS Write decerr address 63 0 0x0000000000000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_intm bridge_spio_sp_main0_srvcproc_m_3_6_am_intm SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 147306 spio_sp_main0_srvcproc_m register am_intm 0x47E40 R/W 0x00007e07004f004f Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_intm Interrupt mask register. Individual bit position matches the error bit positions in AM_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M0_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M0_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M0_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M0_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M0_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M0_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M0_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M0_SET ns_noc_io_spio_soc_ip.csr 146844 M0 1'b1: Mask interrupt for read channel 0 0 0x1 R/W M1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M1_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M1_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M1_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M1_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M1_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M1_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M1_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M1_SET ns_noc_io_spio_soc_ip.csr 146855 M1 1'b1: Mask interrupt for read channel 1 1 0x1 R/W M2 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M2_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M2_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M2_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M2_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M2_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M2_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M2_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M2_SET ns_noc_io_spio_soc_ip.csr 146866 M2 1'b1: Mask interrupt for read channel 2 2 0x1 R/W M3 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M3_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M3_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M3_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M3_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M3_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M3_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M3_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M3_SET ns_noc_io_spio_soc_ip.csr 146877 M3 1'b1: Mask interrupt for read channel 3 3 0x1 R/W M4 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M4_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M4_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M4_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M4_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M4_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M4_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M4_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M4_SET ns_noc_io_spio_soc_ip.csr 146888 M4 1'b1: Mask interrupt for read channel 4 4 0x0 R/W M5 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M5_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M5_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M5_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M5_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M5_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M5_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M5_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M5_SET ns_noc_io_spio_soc_ip.csr 146899 M5 1'b1: Mask interrupt for read channel 5 5 0x0 R/W M6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M6_SET ns_noc_io_spio_soc_ip.csr 146910 M6 1'b1: Mask interrupt for read channel 6 6 0x1 R/W M7 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M7_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M7_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M7_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M7_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M7_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M7_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M7_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M7_SET ns_noc_io_spio_soc_ip.csr 146921 M7 1'b1: Mask interrupt for read channel 7 7 0x0 R/W M8 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M8_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M8_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M8_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M8_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M8_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M8_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M8_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M8_SET ns_noc_io_spio_soc_ip.csr 146932 M8 1'b1: Mask interrupt for read channel 8 8 0x0 R/W UNSD_15_9 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_15_9_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_15_9_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_15_9_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_15_9_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_15_9_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_15_9_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_15_9_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_15_9_SET ns_noc_io_spio_soc_ip.csr 146943 UNSD_15_9 15 9 0x00 R M16 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M16_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M16_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M16_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M16_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M16_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M16_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M16_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M16_SET ns_noc_io_spio_soc_ip.csr 146954 M16 1'b1: Mask interrupt for write channel 16 16 0x1 R/W M17 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M17_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M17_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M17_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M17_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M17_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M17_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M17_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M17_SET ns_noc_io_spio_soc_ip.csr 146965 M17 1'b1: Mask interrupt for write channel 17 17 0x1 R/W M18 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M18_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M18_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M18_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M18_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M18_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M18_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M18_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M18_SET ns_noc_io_spio_soc_ip.csr 146976 M18 1'b1: Mask interrupt for write channel 18 18 0x1 R/W M19 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M19_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M19_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M19_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M19_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M19_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M19_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M19_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M19_SET ns_noc_io_spio_soc_ip.csr 146987 M19 1'b1: Mask interrupt for write channel 19 19 0x1 R/W M20 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M20_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M20_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M20_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M20_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M20_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M20_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M20_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M20_SET ns_noc_io_spio_soc_ip.csr 146998 M20 1'b1: Mask interrupt for write channel 20 20 0x0 R/W M21 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M21_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M21_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M21_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M21_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M21_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M21_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M21_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M21_SET ns_noc_io_spio_soc_ip.csr 147009 M21 1'b1: Mask interrupt for write channel 21 21 0x0 R/W M22 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M22_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M22_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M22_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M22_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M22_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M22_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M22_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M22_SET ns_noc_io_spio_soc_ip.csr 147020 M22 1'b1: Mask interrupt for write channel 22 22 0x1 R/W M23 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M23_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M23_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M23_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M23_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M23_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M23_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M23_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M23_SET ns_noc_io_spio_soc_ip.csr 147031 M23 1'b1: Mask interrupt for write channel 23 23 0x0 R/W M24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M24_SET ns_noc_io_spio_soc_ip.csr 147042 M24 1'b1: Mask interrupt for write channel 24 24 0x0 R/W UNSD_31_25 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_31_25_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_31_25_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_31_25_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_31_25_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_31_25_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_31_25_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_31_25_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_31_25_SET ns_noc_io_spio_soc_ip.csr 147053 UNSD_31_25 31 25 0x00 R M32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M32_SET ns_noc_io_spio_soc_ip.csr 147064 M32 1'b1: Counter 0 overflow interrupt mask 32 32 0x1 R/W M33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M33_SET ns_noc_io_spio_soc_ip.csr 147075 M33 1'b1: Counter 1 overflow interrupt mask 33 33 0x1 R/W M34 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M34_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M34_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M34_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M34_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M34_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M34_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M34_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M34_SET ns_noc_io_spio_soc_ip.csr 147086 M34 1'b1: Mask interrupt on traffic to PG layer 34 34 0x1 R/W M35 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M35_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M35_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M35_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M35_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M35_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M35_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M35_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M35_SET ns_noc_io_spio_soc_ip.csr 147097 M35 1'b1: Mask interrupt on csr parity errors 35 35 0x0 R/W UNSD_39_36 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_39_36_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_39_36_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_39_36_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_39_36_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_39_36_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_39_36_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_39_36_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_39_36_SET ns_noc_io_spio_soc_ip.csr 147108 UNSD_39_36 39 36 0x0 R M40 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M40_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M40_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M40_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M40_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M40_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M40_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M40_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M40_SET ns_noc_io_spio_soc_ip.csr 147120 M40 1'b1: Mask interrupt for SIB portcheck error (SIB mode only) 40 40 0x0 R/W M41 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M41_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M41_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M41_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M41_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M41_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M41_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M41_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M41_SET ns_noc_io_spio_soc_ip.csr 147131 M41 1'b1: AR Parity Intr Mask 41 41 0x1 R/W M42 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M42_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M42_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M42_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M42_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M42_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M42_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M42_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M42_SET ns_noc_io_spio_soc_ip.csr 147142 M42 1'b1: ARADDR Parity Intr Mask 42 42 0x1 R/W M43 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M43_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M43_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M43_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M43_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M43_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M43_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M43_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M43_SET ns_noc_io_spio_soc_ip.csr 147153 M43 1'b1: AW Parity Intr Mask 43 43 0x1 R/W M44 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M44_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M44_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M44_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M44_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M44_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M44_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M44_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M44_SET ns_noc_io_spio_soc_ip.csr 147164 M44 1'b1: AWADDR Parity Intr Mask 44 44 0x1 R/W M45 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M45_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M45_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M45_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M45_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M45_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M45_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M45_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M45_SET ns_noc_io_spio_soc_ip.csr 147175 M45 1'b1: WDATA Parity Intr Mask 45 45 0x1 R/W M46 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M46_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M46_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M46_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M46_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M46_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M46_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M46_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_M46_SET ns_noc_io_spio_soc_ip.csr 147186 M46 1'b1: CDDATA Parity Intr Mask 46 46 0x1 R/W E47 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E47_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E47_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E47_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E47_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E47_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E47_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E47_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E47_SET ns_noc_io_spio_soc_ip.csr 147198 E47 1'b1: Ridtbl Parity Intr Mask 47 47 0x0 R E48 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E48_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E48_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E48_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E48_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E48_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E48_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E48_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E48_SET ns_noc_io_spio_soc_ip.csr 147210 E48 1'b1: Widtbl Parity Intr Mask 48 48 0x0 R E49 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E49_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E49_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E49_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E49_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E49_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E49_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E49_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E49_SET ns_noc_io_spio_soc_ip.csr 147222 E49 1'b1: Read Reorder Buffer Parity Intr Mask 49 49 0x0 R E50 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E50_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E50_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E50_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E50_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E50_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E50_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E50_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E50_SET ns_noc_io_spio_soc_ip.csr 147234 E50 1'b1: Write Reorder Buffer Parity Intr Mask 50 50 0x0 R E51 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E51_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E51_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E51_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E51_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E51_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E51_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E51_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E51_SET ns_noc_io_spio_soc_ip.csr 147246 E51 1'b1: Rx Fifo Parity Intr Mask 51 51 0x0 R E52 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E52_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E52_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E52_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E52_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E52_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E52_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E52_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E52_SET ns_noc_io_spio_soc_ip.csr 147258 E52 1'b1: Ack Channel Wack Fifo Parity Intr Mask 52 52 0x0 R E53 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E53_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E53_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E53_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E53_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E53_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E53_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E53_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E53_SET ns_noc_io_spio_soc_ip.csr 147270 E53 1'b1: Ack Channel Rack Fifo Parity Intr Mask 53 53 0x0 R E54 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E54_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E54_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E54_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E54_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E54_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E54_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E54_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E54_SET ns_noc_io_spio_soc_ip.csr 147282 E54 1'b1: CRCD Channel Crid Fifo Parity Intr Mask 54 54 0x0 R E55 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E55_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E55_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E55_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E55_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E55_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E55_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E55_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_E55_SET ns_noc_io_spio_soc_ip.csr 147294 E55 1'b1: R Channel Cpkt Fifo Parity Intr Mask 55 55 0x0 R UNSD_63_56 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_63_56_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_63_56_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_63_56_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_63_56_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_63_56_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_63_56_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_63_56_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_INTM_UNSD_63_56_SET ns_noc_io_spio_soc_ip.csr 147305 UNSD_63_56 63 56 0x00 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_caddr bridge_spio_sp_main0_srvcproc_m_3_6_am_caddr SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CADDR_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CADDR_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CADDR_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CADDR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 147328 spio_sp_main0_srvcproc_m register am_caddr 0x47F00 R/W 0xffffffffffffffff Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_caddr This register is part of statistics gathering on the AR and AW command channels. This is the address value which is checked against AR, AW command channels in conjunction with the mask below to filter commands for statistics gathering. false false false false CAPTURE_ADDR SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CADDR_CAPTURE_ADDR_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CADDR_CAPTURE_ADDR_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CADDR_CAPTURE_ADDR_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CADDR_CAPTURE_ADDR_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CADDR_CAPTURE_ADDR_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CADDR_CAPTURE_ADDR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CADDR_CAPTURE_ADDR_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CADDR_CAPTURE_ADDR_SET ns_noc_io_spio_soc_ip.csr 147327 CAPTURE_ADDR Capture address 63 0 0xffffffffffffffff R/W register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_caddrmsk bridge_spio_sp_main0_srvcproc_m_3_6_am_caddrmsk SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CADDRMSK_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CADDRMSK_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CADDRMSK_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CADDRMSK_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 147351 spio_sp_main0_srvcproc_m register am_caddrmsk 0x47F08 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_caddrmsk If command address on the AR, AW channel logically ANDed with this mask is equal to the value specified in AM_CADDR, then an address match has occurred. Note that only lowest significant bits equal to the master's address width are used in the comparison. false false false false CAPTURE_ADDR_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_SET ns_noc_io_spio_soc_ip.csr 147350 CAPTURE_ADDR_MASK Capture address mask 63 0 0x0000000000000000 R/W register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_ccmd0 bridge_spio_sp_main0_srvcproc_m_3_6_am_ccmd0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 147541 spio_sp_main0_srvcproc_m register am_ccmd0 0x47F10 R/W 0x0000000003fff33f Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_ccmd0 Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands. false false false false SNOOP SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_SNOOP_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_SNOOP_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_SNOOP_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_SNOOP_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_SNOOP_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_SNOOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_SNOOP_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_SNOOP_SET ns_noc_io_spio_soc_ip.csr 147373 SNOOP Snoop 3 0 0xf R/W DOMAIN SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_DOMAIN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_DOMAIN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_DOMAIN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_DOMAIN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_DOMAIN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_DOMAIN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_DOMAIN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_DOMAIN_SET ns_noc_io_spio_soc_ip.csr 147384 DOMAIN Domain 5 4 0x3 R/W UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 147395 UNSD_7_6 7 6 0x0 R BAR SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_BAR_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_BAR_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_BAR_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_BAR_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_BAR_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_BAR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_BAR_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_BAR_SET ns_noc_io_spio_soc_ip.csr 147406 BAR Bar 9 8 0x3 R/W UNSD_11_10 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_11_10_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_11_10_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_11_10_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_11_10_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_11_10_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_11_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_11_10_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_11_10_SET ns_noc_io_spio_soc_ip.csr 147417 UNSD_11_10 11 10 0x0 R CACHE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_CACHE_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_CACHE_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_CACHE_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_CACHE_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_CACHE_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_CACHE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_CACHE_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_CACHE_SET ns_noc_io_spio_soc_ip.csr 147428 CACHE Cache 15 12 0xf R/W QOS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_QOS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_QOS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_QOS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_QOS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_QOS_SET ns_noc_io_spio_soc_ip.csr 147439 QOS QoS 19 16 0xf R/W PROT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_PROT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_PROT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_PROT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_PROT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_PROT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_PROT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_PROT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_PROT_SET ns_noc_io_spio_soc_ip.csr 147450 PROT Prot 22 20 0x7 R/W LOC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_LOC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_LOC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_LOC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_LOC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_LOC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_LOC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_LOC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_LOC_SET ns_noc_io_spio_soc_ip.csr 147461 LOC 1'b1: Lock 23 23 0x1 R/W RDY SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_RDY_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_RDY_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_RDY_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_RDY_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_RDY_SET ns_noc_io_spio_soc_ip.csr 147472 RDY 1'b1: Ready 24 24 0x1 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_VAL_SET ns_noc_io_spio_soc_ip.csr 147483 VAL 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_27_26_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_27_26_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_27_26_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_27_26_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_27_26_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_27_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_27_26_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_27_26_SET ns_noc_io_spio_soc_ip.csr 147494 UNSD_27_26 27 26 0x0 R INTFID SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_INTFID_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_INTFID_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_INTFID_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_INTFID_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_INTFID_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_INTFID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_INTFID_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_INTFID_SET ns_noc_io_spio_soc_ip.csr 147506 INTFID 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_31_31 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_31_31_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_31_31_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_31_31_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_31_31_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_31_31_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_31_31_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_31_31_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_31_31_SET ns_noc_io_spio_soc_ip.csr 147517 UNSD_31_31 31 31 0x0 R TYP SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_TYP_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_TYP_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_TYP_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_TYP_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_TYP_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_TYP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_TYP_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_TYP_SET ns_noc_io_spio_soc_ip.csr 147529 TYP 1'b1: Count response latency of captured command 1'b0: Count captured command 32 32 0x0 R/W UNSD_63_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_63_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_63_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_63_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_63_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_63_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_63_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_63_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD0_UNSD_63_33_SET ns_noc_io_spio_soc_ip.csr 147540 UNSD_63_33 63 33 0x00000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_ccmdmsk0 bridge_spio_sp_main0_srvcproc_m_3_6_am_ccmdmsk0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 147685 spio_sp_main0_srvcproc_m register am_ccmdmsk0 0x47F18 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_ccmdmsk0 If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters. false false false false SNOOP SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_SNOOP_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_SNOOP_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_SNOOP_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_SNOOP_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_SNOOP_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_SNOOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_SNOOP_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_SNOOP_SET ns_noc_io_spio_soc_ip.csr 147563 SNOOP Snoop 3 0 0x0 R/W DOMAIN SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_DOMAIN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_DOMAIN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_DOMAIN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_DOMAIN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_DOMAIN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_DOMAIN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_DOMAIN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_DOMAIN_SET ns_noc_io_spio_soc_ip.csr 147574 DOMAIN Domain 5 4 0x0 R/W UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 147585 UNSD_7_6 7 6 0x0 R BAR SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_BAR_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_BAR_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_BAR_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_BAR_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_BAR_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_BAR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_BAR_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_BAR_SET ns_noc_io_spio_soc_ip.csr 147596 BAR Bar 9 8 0x0 R/W UNSD_11_10 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_UNSD_11_10_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_UNSD_11_10_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_UNSD_11_10_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_UNSD_11_10_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_UNSD_11_10_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_UNSD_11_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_UNSD_11_10_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_UNSD_11_10_SET ns_noc_io_spio_soc_ip.csr 147607 UNSD_11_10 11 10 0x0 R CACHE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_CACHE_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_CACHE_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_CACHE_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_CACHE_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_CACHE_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_CACHE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_CACHE_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_CACHE_SET ns_noc_io_spio_soc_ip.csr 147618 CACHE Cache 15 12 0x0 R/W QOS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_QOS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_QOS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_QOS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_QOS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_QOS_SET ns_noc_io_spio_soc_ip.csr 147629 QOS QoS 19 16 0x0 R/W PROT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_PROT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_PROT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_PROT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_PROT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_PROT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_PROT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_PROT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_PROT_SET ns_noc_io_spio_soc_ip.csr 147640 PROT Prot 22 20 0x0 R/W LOC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_LOC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_LOC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_LOC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_LOC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_LOC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_LOC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_LOC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_LOC_SET ns_noc_io_spio_soc_ip.csr 147651 LOC 1'b1: Lock 23 23 0x0 R/W RDY SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_RDY_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_RDY_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_RDY_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_RDY_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_RDY_SET ns_noc_io_spio_soc_ip.csr 147662 RDY 1'b1: Ready 24 24 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_VAL_SET ns_noc_io_spio_soc_ip.csr 147673 VAL 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_UNSD_63_26_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_UNSD_63_26_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_UNSD_63_26_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_UNSD_63_26_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_UNSD_63_26_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_UNSD_63_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_UNSD_63_26_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK0_UNSD_63_26_SET ns_noc_io_spio_soc_ip.csr 147684 UNSD_63_26 63 26 0x0000000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_cntr0 bridge_spio_sp_main0_srvcproc_m_3_6_am_cntr0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 147720 spio_sp_main0_srvcproc_m register am_cntr0 0x47F20 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_cntr0 32-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured. false false false false CNTR SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR0_CNTR_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR0_CNTR_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR0_CNTR_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR0_CNTR_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR0_CNTR_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR0_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR0_CNTR_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR0_CNTR_SET ns_noc_io_spio_soc_ip.csr 147708 CNTR Counter 31 0 0x00000000 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR0_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR0_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR0_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR0_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR0_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR0_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR0_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR0_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 147719 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_latnum0 bridge_spio_sp_main0_srvcproc_m_3_6_am_latnum0 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM0_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM0_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM0_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM0_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 147759 spio_sp_main0_srvcproc_m register am_latnum0 0x47F28 R/W 0x0000000000000007 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_latnum0 This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using: Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0 There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set. false false false false CNTR SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM0_CNTR_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM0_CNTR_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM0_CNTR_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM0_CNTR_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM0_CNTR_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM0_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM0_CNTR_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM0_CNTR_SET ns_noc_io_spio_soc_ip.csr 147747 CNTR Counter 31 0 0x00000007 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM0_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM0_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM0_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM0_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM0_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM0_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM0_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM0_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 147758 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_ccmd1 bridge_spio_sp_main0_srvcproc_m_3_6_am_ccmd1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 147949 spio_sp_main0_srvcproc_m register am_ccmd1 0x47F30 R/W 0x0000000003fff33f Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_ccmd1 Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands. false false false false SNOOP SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_SNOOP_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_SNOOP_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_SNOOP_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_SNOOP_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_SNOOP_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_SNOOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_SNOOP_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_SNOOP_SET ns_noc_io_spio_soc_ip.csr 147781 SNOOP Snoop 3 0 0xf R/W DOMAIN SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_DOMAIN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_DOMAIN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_DOMAIN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_DOMAIN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_DOMAIN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_DOMAIN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_DOMAIN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_DOMAIN_SET ns_noc_io_spio_soc_ip.csr 147792 DOMAIN Domain 5 4 0x3 R/W UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 147803 UNSD_7_6 7 6 0x0 R BAR SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_BAR_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_BAR_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_BAR_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_BAR_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_BAR_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_BAR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_BAR_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_BAR_SET ns_noc_io_spio_soc_ip.csr 147814 BAR Bar 9 8 0x3 R/W UNSD_11_10 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_11_10_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_11_10_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_11_10_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_11_10_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_11_10_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_11_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_11_10_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_11_10_SET ns_noc_io_spio_soc_ip.csr 147825 UNSD_11_10 11 10 0x0 R CACHE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_CACHE_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_CACHE_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_CACHE_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_CACHE_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_CACHE_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_CACHE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_CACHE_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_CACHE_SET ns_noc_io_spio_soc_ip.csr 147836 CACHE Cache 15 12 0xf R/W QOS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_QOS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_QOS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_QOS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_QOS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_QOS_SET ns_noc_io_spio_soc_ip.csr 147847 QOS QoS 19 16 0xf R/W PROT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_PROT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_PROT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_PROT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_PROT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_PROT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_PROT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_PROT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_PROT_SET ns_noc_io_spio_soc_ip.csr 147858 PROT Prot 22 20 0x7 R/W LOC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_LOC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_LOC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_LOC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_LOC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_LOC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_LOC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_LOC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_LOC_SET ns_noc_io_spio_soc_ip.csr 147869 LOC 1'b1: Lock 23 23 0x1 R/W RDY SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_RDY_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_RDY_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_RDY_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_RDY_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_RDY_SET ns_noc_io_spio_soc_ip.csr 147880 RDY 1'b1: Ready 24 24 0x1 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_VAL_SET ns_noc_io_spio_soc_ip.csr 147891 VAL 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_27_26_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_27_26_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_27_26_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_27_26_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_27_26_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_27_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_27_26_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_27_26_SET ns_noc_io_spio_soc_ip.csr 147902 UNSD_27_26 27 26 0x0 R INTFID SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_INTFID_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_INTFID_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_INTFID_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_INTFID_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_INTFID_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_INTFID_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_INTFID_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_INTFID_SET ns_noc_io_spio_soc_ip.csr 147914 INTFID 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_31_31 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_31_31_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_31_31_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_31_31_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_31_31_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_31_31_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_31_31_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_31_31_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_31_31_SET ns_noc_io_spio_soc_ip.csr 147925 UNSD_31_31 31 31 0x0 R TYP SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_TYP_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_TYP_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_TYP_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_TYP_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_TYP_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_TYP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_TYP_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_TYP_SET ns_noc_io_spio_soc_ip.csr 147937 TYP 1'b1: Count response latency of captured command 1'b0: Count captured command 32 32 0x0 R/W UNSD_63_33 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_63_33_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_63_33_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_63_33_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_63_33_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_63_33_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_63_33_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_63_33_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMD1_UNSD_63_33_SET ns_noc_io_spio_soc_ip.csr 147948 UNSD_63_33 63 33 0x00000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_ccmdmsk1 bridge_spio_sp_main0_srvcproc_m_3_6_am_ccmdmsk1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 148093 spio_sp_main0_srvcproc_m register am_ccmdmsk1 0x47F38 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_ccmdmsk1 If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters. false false false false SNOOP SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_SNOOP_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_SNOOP_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_SNOOP_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_SNOOP_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_SNOOP_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_SNOOP_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_SNOOP_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_SNOOP_SET ns_noc_io_spio_soc_ip.csr 147971 SNOOP Snoop 3 0 0x0 R/W DOMAIN SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_DOMAIN_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_DOMAIN_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_DOMAIN_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_DOMAIN_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_DOMAIN_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_DOMAIN_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_DOMAIN_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_DOMAIN_SET ns_noc_io_spio_soc_ip.csr 147982 DOMAIN Domain 5 4 0x0 R/W UNSD_7_6 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_UNSD_7_6_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_UNSD_7_6_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_UNSD_7_6_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_UNSD_7_6_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_UNSD_7_6_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_UNSD_7_6_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_UNSD_7_6_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_UNSD_7_6_SET ns_noc_io_spio_soc_ip.csr 147993 UNSD_7_6 7 6 0x0 R BAR SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_BAR_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_BAR_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_BAR_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_BAR_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_BAR_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_BAR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_BAR_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_BAR_SET ns_noc_io_spio_soc_ip.csr 148004 BAR Bar 9 8 0x0 R/W UNSD_11_10 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_UNSD_11_10_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_UNSD_11_10_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_UNSD_11_10_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_UNSD_11_10_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_UNSD_11_10_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_UNSD_11_10_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_UNSD_11_10_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_UNSD_11_10_SET ns_noc_io_spio_soc_ip.csr 148015 UNSD_11_10 11 10 0x0 R CACHE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_CACHE_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_CACHE_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_CACHE_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_CACHE_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_CACHE_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_CACHE_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_CACHE_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_CACHE_SET ns_noc_io_spio_soc_ip.csr 148026 CACHE Cache 15 12 0x0 R/W QOS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_QOS_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_QOS_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_QOS_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_QOS_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_QOS_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_QOS_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_QOS_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_QOS_SET ns_noc_io_spio_soc_ip.csr 148037 QOS QoS 19 16 0x0 R/W PROT SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_PROT_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_PROT_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_PROT_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_PROT_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_PROT_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_PROT_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_PROT_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_PROT_SET ns_noc_io_spio_soc_ip.csr 148048 PROT Prot 22 20 0x0 R/W LOC SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_LOC_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_LOC_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_LOC_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_LOC_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_LOC_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_LOC_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_LOC_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_LOC_SET ns_noc_io_spio_soc_ip.csr 148059 LOC 1'b1: Lock 23 23 0x0 R/W RDY SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_RDY_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_RDY_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_RDY_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_RDY_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_RDY_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_RDY_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_RDY_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_RDY_SET ns_noc_io_spio_soc_ip.csr 148070 RDY 1'b1: Ready 24 24 0x0 R/W VAL SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_VAL_SET ns_noc_io_spio_soc_ip.csr 148081 VAL 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_UNSD_63_26_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_UNSD_63_26_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_UNSD_63_26_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_UNSD_63_26_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_UNSD_63_26_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_UNSD_63_26_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_UNSD_63_26_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CCMDMSK1_UNSD_63_26_SET ns_noc_io_spio_soc_ip.csr 148092 UNSD_63_26 63 26 0x0000000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_cntr1 bridge_spio_sp_main0_srvcproc_m_3_6_am_cntr1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 148128 spio_sp_main0_srvcproc_m register am_cntr1 0x47F40 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_cntr1 32-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured. false false false false CNTR SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR1_CNTR_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR1_CNTR_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR1_CNTR_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR1_CNTR_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR1_CNTR_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR1_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR1_CNTR_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR1_CNTR_SET ns_noc_io_spio_soc_ip.csr 148116 CNTR Counter 31 0 0x00000000 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR1_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR1_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR1_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR1_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR1_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR1_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR1_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_CNTR1_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 148127 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_latnum1 bridge_spio_sp_main0_srvcproc_m_3_6_am_latnum1 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM1_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM1_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM1_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM1_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 148167 spio_sp_main0_srvcproc_m register am_latnum1 0x47F48 R/W 0x0000000000000007 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_latnum1 This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using: Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0 There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set. false false false false CNTR SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM1_CNTR_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM1_CNTR_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM1_CNTR_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM1_CNTR_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM1_CNTR_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM1_CNTR_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM1_CNTR_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM1_CNTR_SET ns_noc_io_spio_soc_ip.csr 148155 CNTR Counter 31 0 0x00000007 R/W UNSD_63_32 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM1_UNSD_63_32_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM1_UNSD_63_32_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM1_UNSD_63_32_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM1_UNSD_63_32_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM1_UNSD_63_32_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM1_UNSD_63_32_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM1_UNSD_63_32_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_LATNUM1_UNSD_63_32_SET ns_noc_io_spio_soc_ip.csr 148166 UNSD_63_32 63 32 0x00000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_arovrd bridge_spio_sp_main0_srvcproc_m_3_6_am_arovrd SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 148280 spio_sp_main0_srvcproc_m register am_arovrd 0x47F60 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_arovrd AR override. false false false false arcache_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 148185 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 148198 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 148209 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 148220 UNSD_11_11 11 11 0x0 R arprot_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 148233 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 148244 UNSD_15_15 15 15 0x0 R arqos_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 148255 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_ARQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 148268 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AROVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 148279 UNSD_63_24 63 24 0x0000000000 R register spio_noc.bridge_spio_sp_main0_srvcproc_m_3_6_am_awovrd bridge_spio_sp_main0_srvcproc_m_3_6_am_awovrd SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_BYTE_ADDRESS SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_OFFSET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 148393 spio_sp_main0_srvcproc_m register am_awovrd 0x47F68 R/W 0x0000000000000000 Spio_noc_bridge_spio_sp_main0_srvcproc_m_3_6_am_awovrd AW override. false false false false awcache_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWCACHE_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWCACHE_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWCACHE_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWCACHE_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWCACHE_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWCACHE_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWCACHE_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWCACHE_VAL_SET ns_noc_io_spio_soc_ip.csr 148298 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWCACHE_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWCACHE_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWCACHE_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWCACHE_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWCACHE_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWCACHE_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWCACHE_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWCACHE_ENB_SET ns_noc_io_spio_soc_ip.csr 148311 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWPROT_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWPROT_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWPROT_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWPROT_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWPROT_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWPROT_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWPROT_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWPROT_VAL_SET ns_noc_io_spio_soc_ip.csr 148322 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_UNSD_11_11_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_UNSD_11_11_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_UNSD_11_11_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_UNSD_11_11_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_UNSD_11_11_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_UNSD_11_11_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_UNSD_11_11_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_UNSD_11_11_SET ns_noc_io_spio_soc_ip.csr 148333 UNSD_11_11 11 11 0x0 R awprot_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWPROT_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWPROT_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWPROT_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWPROT_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWPROT_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWPROT_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWPROT_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWPROT_ENB_SET ns_noc_io_spio_soc_ip.csr 148346 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_UNSD_15_15_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_UNSD_15_15_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_UNSD_15_15_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_UNSD_15_15_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_UNSD_15_15_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_UNSD_15_15_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_UNSD_15_15_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_UNSD_15_15_SET ns_noc_io_spio_soc_ip.csr 148357 UNSD_15_15 15 15 0x0 R awqos_val SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWQOS_VAL_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWQOS_VAL_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWQOS_VAL_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWQOS_VAL_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWQOS_VAL_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWQOS_VAL_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWQOS_VAL_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWQOS_VAL_SET ns_noc_io_spio_soc_ip.csr 148368 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWQOS_ENB_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWQOS_ENB_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWQOS_ENB_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWQOS_ENB_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWQOS_ENB_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWQOS_ENB_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWQOS_ENB_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_AWQOS_ENB_SET ns_noc_io_spio_soc_ip.csr 148381 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_UNSD_63_24_WIDTH SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_UNSD_63_24_MSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_UNSD_63_24_LSB SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_UNSD_63_24_RANGE SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_UNSD_63_24_RESET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_UNSD_63_24_FIELD_MASK SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_UNSD_63_24_GET SPIO_NOC_BRIDGE_SPIO_SP_MAIN0_SRVCPROC_M_3_6_AM_AWOVRD_UNSD_63_24_SET ns_noc_io_spio_soc_ip.csr 148392 UNSD_63_24 63 24 0x0000000000 R register spio_noc.router_0_6_6_rivcs_h router_0_6_6_rivcs_h SPIO_NOC_ROUTER_0_6_6_RIVCS_H_ADDRESS SPIO_NOC_ROUTER_0_6_6_RIVCS_H_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OFFSET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 148722 R0_6 register rivcs_h 0x48000 R 0x00000000 Spio_noc_router_0_6_6_rivcs_h This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 148418 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_0_SET ns_noc_io_spio_soc_ip.csr 148432 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_0_SET ns_noc_io_spio_soc_ip.csr 148448 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_0_SET ns_noc_io_spio_soc_ip.csr 148462 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_0_SET ns_noc_io_spio_soc_ip.csr 148473 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_0_SET ns_noc_io_spio_soc_ip.csr 148484 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 148497 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_1_SET ns_noc_io_spio_soc_ip.csr 148511 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_1_SET ns_noc_io_spio_soc_ip.csr 148527 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_1_SET ns_noc_io_spio_soc_ip.csr 148541 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_1_SET ns_noc_io_spio_soc_ip.csr 148552 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_1_SET ns_noc_io_spio_soc_ip.csr 148563 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 148576 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_2_SET ns_noc_io_spio_soc_ip.csr 148590 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_2_SET ns_noc_io_spio_soc_ip.csr 148606 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_2_SET ns_noc_io_spio_soc_ip.csr 148620 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_2_SET ns_noc_io_spio_soc_ip.csr 148631 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_2_SET ns_noc_io_spio_soc_ip.csr 148642 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 148655 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_UP_3_SET ns_noc_io_spio_soc_ip.csr 148669 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_S_3_SET ns_noc_io_spio_soc_ip.csr 148685 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_B_3_SET ns_noc_io_spio_soc_ip.csr 148699 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_F_3_SET ns_noc_io_spio_soc_ip.csr 148710 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_H_V_3_SET ns_noc_io_spio_soc_ip.csr 148721 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_0_6_6_rivcs_e router_0_6_6_rivcs_e SPIO_NOC_ROUTER_0_6_6_RIVCS_E_ADDRESS SPIO_NOC_ROUTER_0_6_6_RIVCS_E_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OFFSET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 149051 R0_6 register rivcs_e 0x48008 R 0x00000000 Spio_noc_router_0_6_6_rivcs_e This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 148747 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_0_SET ns_noc_io_spio_soc_ip.csr 148761 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_0_SET ns_noc_io_spio_soc_ip.csr 148777 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_0_SET ns_noc_io_spio_soc_ip.csr 148791 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_0_SET ns_noc_io_spio_soc_ip.csr 148802 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_0_SET ns_noc_io_spio_soc_ip.csr 148813 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 148826 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_1_SET ns_noc_io_spio_soc_ip.csr 148840 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_1_SET ns_noc_io_spio_soc_ip.csr 148856 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_1_SET ns_noc_io_spio_soc_ip.csr 148870 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_1_SET ns_noc_io_spio_soc_ip.csr 148881 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_1_SET ns_noc_io_spio_soc_ip.csr 148892 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 148905 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_2_SET ns_noc_io_spio_soc_ip.csr 148919 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_2_SET ns_noc_io_spio_soc_ip.csr 148935 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_2_SET ns_noc_io_spio_soc_ip.csr 148949 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_2_SET ns_noc_io_spio_soc_ip.csr 148960 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_2_SET ns_noc_io_spio_soc_ip.csr 148971 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 148984 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_UP_3_SET ns_noc_io_spio_soc_ip.csr 148998 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_S_3_SET ns_noc_io_spio_soc_ip.csr 149014 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_B_3_SET ns_noc_io_spio_soc_ip.csr 149028 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_F_3_SET ns_noc_io_spio_soc_ip.csr 149039 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_E_V_3_SET ns_noc_io_spio_soc_ip.csr 149050 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_0_6_6_rivcs_s router_0_6_6_rivcs_s SPIO_NOC_ROUTER_0_6_6_RIVCS_S_ADDRESS SPIO_NOC_ROUTER_0_6_6_RIVCS_S_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OFFSET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 149380 R0_6 register rivcs_s 0x48010 R 0x00000000 Spio_noc_router_0_6_6_rivcs_s This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 149076 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_0_SET ns_noc_io_spio_soc_ip.csr 149090 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_0_SET ns_noc_io_spio_soc_ip.csr 149106 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_0_SET ns_noc_io_spio_soc_ip.csr 149120 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_0_SET ns_noc_io_spio_soc_ip.csr 149131 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_0_SET ns_noc_io_spio_soc_ip.csr 149142 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 149155 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_1_SET ns_noc_io_spio_soc_ip.csr 149169 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_1_SET ns_noc_io_spio_soc_ip.csr 149185 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_1_SET ns_noc_io_spio_soc_ip.csr 149199 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_1_SET ns_noc_io_spio_soc_ip.csr 149210 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_1_SET ns_noc_io_spio_soc_ip.csr 149221 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 149234 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_2_SET ns_noc_io_spio_soc_ip.csr 149248 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_2_SET ns_noc_io_spio_soc_ip.csr 149264 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_2_SET ns_noc_io_spio_soc_ip.csr 149278 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_2_SET ns_noc_io_spio_soc_ip.csr 149289 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_2_SET ns_noc_io_spio_soc_ip.csr 149300 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 149313 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_UP_3_SET ns_noc_io_spio_soc_ip.csr 149327 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_S_3_SET ns_noc_io_spio_soc_ip.csr 149343 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_B_3_SET ns_noc_io_spio_soc_ip.csr 149357 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_F_3_SET ns_noc_io_spio_soc_ip.csr 149368 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_S_V_3_SET ns_noc_io_spio_soc_ip.csr 149379 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_0_6_6_rivcs_w router_0_6_6_rivcs_w SPIO_NOC_ROUTER_0_6_6_RIVCS_W_ADDRESS SPIO_NOC_ROUTER_0_6_6_RIVCS_W_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OFFSET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 149709 R0_6 register rivcs_w 0x48018 R 0x00000000 Spio_noc_router_0_6_6_rivcs_w This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 149405 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_0_SET ns_noc_io_spio_soc_ip.csr 149419 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_0_SET ns_noc_io_spio_soc_ip.csr 149435 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_0_SET ns_noc_io_spio_soc_ip.csr 149449 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_0_SET ns_noc_io_spio_soc_ip.csr 149460 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_0_SET ns_noc_io_spio_soc_ip.csr 149471 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 149484 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_1_SET ns_noc_io_spio_soc_ip.csr 149498 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_1_SET ns_noc_io_spio_soc_ip.csr 149514 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_1_SET ns_noc_io_spio_soc_ip.csr 149528 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_1_SET ns_noc_io_spio_soc_ip.csr 149539 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_1_SET ns_noc_io_spio_soc_ip.csr 149550 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 149563 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_2_SET ns_noc_io_spio_soc_ip.csr 149577 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_2_SET ns_noc_io_spio_soc_ip.csr 149593 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_2_SET ns_noc_io_spio_soc_ip.csr 149607 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_2_SET ns_noc_io_spio_soc_ip.csr 149618 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_2_SET ns_noc_io_spio_soc_ip.csr 149629 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 149642 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_UP_3_SET ns_noc_io_spio_soc_ip.csr 149656 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_S_3_SET ns_noc_io_spio_soc_ip.csr 149672 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_B_3_SET ns_noc_io_spio_soc_ip.csr 149686 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_F_3_SET ns_noc_io_spio_soc_ip.csr 149697 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_W_V_3_SET ns_noc_io_spio_soc_ip.csr 149708 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_0_6_6_rivcs_n router_0_6_6_rivcs_n SPIO_NOC_ROUTER_0_6_6_RIVCS_N_ADDRESS SPIO_NOC_ROUTER_0_6_6_RIVCS_N_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OFFSET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 150038 R0_6 register rivcs_n 0x48020 R 0x00000000 Spio_noc_router_0_6_6_rivcs_n This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 149734 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_0_SET ns_noc_io_spio_soc_ip.csr 149748 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_0_SET ns_noc_io_spio_soc_ip.csr 149764 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_0_SET ns_noc_io_spio_soc_ip.csr 149778 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_0_SET ns_noc_io_spio_soc_ip.csr 149789 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_0_SET ns_noc_io_spio_soc_ip.csr 149800 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 149813 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_1_SET ns_noc_io_spio_soc_ip.csr 149827 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_1_SET ns_noc_io_spio_soc_ip.csr 149843 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_1_SET ns_noc_io_spio_soc_ip.csr 149857 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_1_SET ns_noc_io_spio_soc_ip.csr 149868 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_1_SET ns_noc_io_spio_soc_ip.csr 149879 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 149892 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_2_SET ns_noc_io_spio_soc_ip.csr 149906 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_2_SET ns_noc_io_spio_soc_ip.csr 149922 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_2_SET ns_noc_io_spio_soc_ip.csr 149936 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_2_SET ns_noc_io_spio_soc_ip.csr 149947 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_2_SET ns_noc_io_spio_soc_ip.csr 149958 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 149971 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_UP_3_SET ns_noc_io_spio_soc_ip.csr 149985 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_S_3_SET ns_noc_io_spio_soc_ip.csr 150001 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_B_3_SET ns_noc_io_spio_soc_ip.csr 150015 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_F_3_SET ns_noc_io_spio_soc_ip.csr 150026 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_N_V_3_SET ns_noc_io_spio_soc_ip.csr 150037 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_0_6_6_rivcs_i router_0_6_6_rivcs_i SPIO_NOC_ROUTER_0_6_6_RIVCS_I_ADDRESS SPIO_NOC_ROUTER_0_6_6_RIVCS_I_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OFFSET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 150367 R0_6 register rivcs_i 0x48028 R 0x00000000 Spio_noc_router_0_6_6_rivcs_i This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 150063 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_0_SET ns_noc_io_spio_soc_ip.csr 150077 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_0_SET ns_noc_io_spio_soc_ip.csr 150093 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_0_SET ns_noc_io_spio_soc_ip.csr 150107 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_0_SET ns_noc_io_spio_soc_ip.csr 150118 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_0_SET ns_noc_io_spio_soc_ip.csr 150129 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 150142 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_1_SET ns_noc_io_spio_soc_ip.csr 150156 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_1_SET ns_noc_io_spio_soc_ip.csr 150172 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_1_SET ns_noc_io_spio_soc_ip.csr 150186 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_1_SET ns_noc_io_spio_soc_ip.csr 150197 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_1_SET ns_noc_io_spio_soc_ip.csr 150208 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 150221 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_2_SET ns_noc_io_spio_soc_ip.csr 150235 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_2_SET ns_noc_io_spio_soc_ip.csr 150251 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_2_SET ns_noc_io_spio_soc_ip.csr 150265 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_2_SET ns_noc_io_spio_soc_ip.csr 150276 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_2_SET ns_noc_io_spio_soc_ip.csr 150287 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 150300 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_UP_3_SET ns_noc_io_spio_soc_ip.csr 150314 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_S_3_SET ns_noc_io_spio_soc_ip.csr 150330 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_B_3_SET ns_noc_io_spio_soc_ip.csr 150344 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_F_3_SET ns_noc_io_spio_soc_ip.csr 150355 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_I_V_3_SET ns_noc_io_spio_soc_ip.csr 150366 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_0_6_6_rivcs_j router_0_6_6_rivcs_j SPIO_NOC_ROUTER_0_6_6_RIVCS_J_ADDRESS SPIO_NOC_ROUTER_0_6_6_RIVCS_J_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OFFSET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 150696 R0_6 register rivcs_j 0x48030 R 0x00000000 Spio_noc_router_0_6_6_rivcs_j This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 150392 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_0_SET ns_noc_io_spio_soc_ip.csr 150406 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_0_SET ns_noc_io_spio_soc_ip.csr 150422 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_0_SET ns_noc_io_spio_soc_ip.csr 150436 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_0_SET ns_noc_io_spio_soc_ip.csr 150447 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_0_SET ns_noc_io_spio_soc_ip.csr 150458 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 150471 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_1_SET ns_noc_io_spio_soc_ip.csr 150485 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_1_SET ns_noc_io_spio_soc_ip.csr 150501 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_1_SET ns_noc_io_spio_soc_ip.csr 150515 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_1_SET ns_noc_io_spio_soc_ip.csr 150526 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_1_SET ns_noc_io_spio_soc_ip.csr 150537 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 150550 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_2_SET ns_noc_io_spio_soc_ip.csr 150564 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_2_SET ns_noc_io_spio_soc_ip.csr 150580 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_2_SET ns_noc_io_spio_soc_ip.csr 150594 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_2_SET ns_noc_io_spio_soc_ip.csr 150605 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_2_SET ns_noc_io_spio_soc_ip.csr 150616 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 150629 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_UP_3_SET ns_noc_io_spio_soc_ip.csr 150643 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_S_3_SET ns_noc_io_spio_soc_ip.csr 150659 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_B_3_SET ns_noc_io_spio_soc_ip.csr 150673 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_F_3_SET ns_noc_io_spio_soc_ip.csr 150684 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_J_V_3_SET ns_noc_io_spio_soc_ip.csr 150695 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_0_6_6_rivcs_k router_0_6_6_rivcs_k SPIO_NOC_ROUTER_0_6_6_RIVCS_K_ADDRESS SPIO_NOC_ROUTER_0_6_6_RIVCS_K_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OFFSET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 151025 R0_6 register rivcs_k 0x48038 R 0x00000000 Spio_noc_router_0_6_6_rivcs_k This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 150721 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_0_SET ns_noc_io_spio_soc_ip.csr 150735 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_0_SET ns_noc_io_spio_soc_ip.csr 150751 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_0_SET ns_noc_io_spio_soc_ip.csr 150765 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_0_SET ns_noc_io_spio_soc_ip.csr 150776 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_0_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_0_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_0_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_0_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_0_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_0_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_0_SET ns_noc_io_spio_soc_ip.csr 150787 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 150800 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_1_SET ns_noc_io_spio_soc_ip.csr 150814 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_1_SET ns_noc_io_spio_soc_ip.csr 150830 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_1_SET ns_noc_io_spio_soc_ip.csr 150844 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_1_SET ns_noc_io_spio_soc_ip.csr 150855 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_1_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_1_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_1_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_1_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_1_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_1_SET ns_noc_io_spio_soc_ip.csr 150866 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 150879 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_2_SET ns_noc_io_spio_soc_ip.csr 150893 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_2_SET ns_noc_io_spio_soc_ip.csr 150909 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_2_SET ns_noc_io_spio_soc_ip.csr 150923 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_2_SET ns_noc_io_spio_soc_ip.csr 150934 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_2_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_2_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_2_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_2_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_2_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_2_SET ns_noc_io_spio_soc_ip.csr 150945 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 150958 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_UP_3_SET ns_noc_io_spio_soc_ip.csr 150972 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_S_3_SET ns_noc_io_spio_soc_ip.csr 150988 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_B_3_SET ns_noc_io_spio_soc_ip.csr 151002 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_F_3_SET ns_noc_io_spio_soc_ip.csr 151013 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_3_MSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_3_LSB SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_3_RANGE SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_3_RESET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_3_GET SPIO_NOC_ROUTER_0_6_6_RIVCS_K_V_3_SET ns_noc_io_spio_soc_ip.csr 151024 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_0_6_6_rovcs_h router_0_6_6_rovcs_h SPIO_NOC_ROUTER_0_6_6_ROVCS_H_ADDRESS SPIO_NOC_ROUTER_0_6_6_ROVCS_H_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_ROVCS_H_OFFSET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 151286 R0_6 register rovcs_h 0x48040 R 0x00000001 Spio_noc_router_0_6_6_rovcs_h This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_0_SET ns_noc_io_spio_soc_ip.csr 151049 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_0_SET ns_noc_io_spio_soc_ip.csr 151063 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_0_SET ns_noc_io_spio_soc_ip.csr 151078 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_0_SET ns_noc_io_spio_soc_ip.csr 151089 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 151099 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_1_SET ns_noc_io_spio_soc_ip.csr 151111 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_1_SET ns_noc_io_spio_soc_ip.csr 151125 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_1_SET ns_noc_io_spio_soc_ip.csr 151140 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_1_SET ns_noc_io_spio_soc_ip.csr 151151 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 151161 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_2_SET ns_noc_io_spio_soc_ip.csr 151173 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_2_SET ns_noc_io_spio_soc_ip.csr 151187 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_2_SET ns_noc_io_spio_soc_ip.csr 151202 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_2_SET ns_noc_io_spio_soc_ip.csr 151213 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 151223 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CF_3_SET ns_noc_io_spio_soc_ip.csr 151235 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_CE_3_SET ns_noc_io_spio_soc_ip.csr 151249 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_VB_3_SET ns_noc_io_spio_soc_ip.csr 151264 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_RSV_3_SET ns_noc_io_spio_soc_ip.csr 151275 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 151285 UNSD_3 31 28 0x0 R register spio_noc.router_0_6_6_rovcs_e router_0_6_6_rovcs_e SPIO_NOC_ROUTER_0_6_6_ROVCS_E_ADDRESS SPIO_NOC_ROUTER_0_6_6_ROVCS_E_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_ROVCS_E_OFFSET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 151547 R0_6 register rovcs_e 0x48048 R 0x00000101 Spio_noc_router_0_6_6_rovcs_e This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_0_SET ns_noc_io_spio_soc_ip.csr 151310 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_0_SET ns_noc_io_spio_soc_ip.csr 151324 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_0_SET ns_noc_io_spio_soc_ip.csr 151339 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_0_SET ns_noc_io_spio_soc_ip.csr 151350 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 151360 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_1_SET ns_noc_io_spio_soc_ip.csr 151372 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x1 R CE_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_1_SET ns_noc_io_spio_soc_ip.csr 151386 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_1_SET ns_noc_io_spio_soc_ip.csr 151401 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_1_SET ns_noc_io_spio_soc_ip.csr 151412 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 151422 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_2_SET ns_noc_io_spio_soc_ip.csr 151434 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_2_SET ns_noc_io_spio_soc_ip.csr 151448 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_2_SET ns_noc_io_spio_soc_ip.csr 151463 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_2_SET ns_noc_io_spio_soc_ip.csr 151474 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 151484 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CF_3_SET ns_noc_io_spio_soc_ip.csr 151496 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_CE_3_SET ns_noc_io_spio_soc_ip.csr 151510 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_VB_3_SET ns_noc_io_spio_soc_ip.csr 151525 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_RSV_3_SET ns_noc_io_spio_soc_ip.csr 151536 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 151546 UNSD_3 31 28 0x0 R register spio_noc.router_0_6_6_rovcs_s router_0_6_6_rovcs_s SPIO_NOC_ROUTER_0_6_6_ROVCS_S_ADDRESS SPIO_NOC_ROUTER_0_6_6_ROVCS_S_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_ROVCS_S_OFFSET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 151808 R0_6 register rovcs_s 0x48050 R 0x00000001 Spio_noc_router_0_6_6_rovcs_s This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_0_SET ns_noc_io_spio_soc_ip.csr 151571 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_0_SET ns_noc_io_spio_soc_ip.csr 151585 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_0_SET ns_noc_io_spio_soc_ip.csr 151600 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_0_SET ns_noc_io_spio_soc_ip.csr 151611 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 151621 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_1_SET ns_noc_io_spio_soc_ip.csr 151633 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_1_SET ns_noc_io_spio_soc_ip.csr 151647 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_1_SET ns_noc_io_spio_soc_ip.csr 151662 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_1_SET ns_noc_io_spio_soc_ip.csr 151673 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 151683 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_2_SET ns_noc_io_spio_soc_ip.csr 151695 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_2_SET ns_noc_io_spio_soc_ip.csr 151709 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_2_SET ns_noc_io_spio_soc_ip.csr 151724 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_2_SET ns_noc_io_spio_soc_ip.csr 151735 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 151745 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CF_3_SET ns_noc_io_spio_soc_ip.csr 151757 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_CE_3_SET ns_noc_io_spio_soc_ip.csr 151771 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_VB_3_SET ns_noc_io_spio_soc_ip.csr 151786 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_RSV_3_SET ns_noc_io_spio_soc_ip.csr 151797 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 151807 UNSD_3 31 28 0x0 R register spio_noc.router_0_6_6_rovcs_w router_0_6_6_rovcs_w SPIO_NOC_ROUTER_0_6_6_ROVCS_W_ADDRESS SPIO_NOC_ROUTER_0_6_6_ROVCS_W_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_ROVCS_W_OFFSET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 152069 R0_6 register rovcs_w 0x48058 R 0x00000001 Spio_noc_router_0_6_6_rovcs_w This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_0_SET ns_noc_io_spio_soc_ip.csr 151832 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_0_SET ns_noc_io_spio_soc_ip.csr 151846 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_0_SET ns_noc_io_spio_soc_ip.csr 151861 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_0_SET ns_noc_io_spio_soc_ip.csr 151872 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 151882 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_1_SET ns_noc_io_spio_soc_ip.csr 151894 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_1_SET ns_noc_io_spio_soc_ip.csr 151908 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_1_SET ns_noc_io_spio_soc_ip.csr 151923 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_1_SET ns_noc_io_spio_soc_ip.csr 151934 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 151944 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_2_SET ns_noc_io_spio_soc_ip.csr 151956 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_2_SET ns_noc_io_spio_soc_ip.csr 151970 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_2_SET ns_noc_io_spio_soc_ip.csr 151985 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_2_SET ns_noc_io_spio_soc_ip.csr 151996 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 152006 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CF_3_SET ns_noc_io_spio_soc_ip.csr 152018 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_CE_3_SET ns_noc_io_spio_soc_ip.csr 152032 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_VB_3_SET ns_noc_io_spio_soc_ip.csr 152047 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_RSV_3_SET ns_noc_io_spio_soc_ip.csr 152058 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 152068 UNSD_3 31 28 0x0 R register spio_noc.router_0_6_6_rovcs_n router_0_6_6_rovcs_n SPIO_NOC_ROUTER_0_6_6_ROVCS_N_ADDRESS SPIO_NOC_ROUTER_0_6_6_ROVCS_N_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_ROVCS_N_OFFSET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 152330 R0_6 register rovcs_n 0x48060 R 0x00000001 Spio_noc_router_0_6_6_rovcs_n This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_0_SET ns_noc_io_spio_soc_ip.csr 152093 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_0_SET ns_noc_io_spio_soc_ip.csr 152107 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_0_SET ns_noc_io_spio_soc_ip.csr 152122 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_0_SET ns_noc_io_spio_soc_ip.csr 152133 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 152143 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_1_SET ns_noc_io_spio_soc_ip.csr 152155 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_1_SET ns_noc_io_spio_soc_ip.csr 152169 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_1_SET ns_noc_io_spio_soc_ip.csr 152184 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_1_SET ns_noc_io_spio_soc_ip.csr 152195 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 152205 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_2_SET ns_noc_io_spio_soc_ip.csr 152217 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_2_SET ns_noc_io_spio_soc_ip.csr 152231 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_2_SET ns_noc_io_spio_soc_ip.csr 152246 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_2_SET ns_noc_io_spio_soc_ip.csr 152257 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 152267 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CF_3_SET ns_noc_io_spio_soc_ip.csr 152279 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_CE_3_SET ns_noc_io_spio_soc_ip.csr 152293 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_VB_3_SET ns_noc_io_spio_soc_ip.csr 152308 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_RSV_3_SET ns_noc_io_spio_soc_ip.csr 152319 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 152329 UNSD_3 31 28 0x0 R register spio_noc.router_0_6_6_rovcs_i router_0_6_6_rovcs_i SPIO_NOC_ROUTER_0_6_6_ROVCS_I_ADDRESS SPIO_NOC_ROUTER_0_6_6_ROVCS_I_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_ROVCS_I_OFFSET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 152591 R0_6 register rovcs_i 0x48068 R 0x00000001 Spio_noc_router_0_6_6_rovcs_i This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_0_SET ns_noc_io_spio_soc_ip.csr 152354 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_0_SET ns_noc_io_spio_soc_ip.csr 152368 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_0_SET ns_noc_io_spio_soc_ip.csr 152383 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_0_SET ns_noc_io_spio_soc_ip.csr 152394 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 152404 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_1_SET ns_noc_io_spio_soc_ip.csr 152416 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_1_SET ns_noc_io_spio_soc_ip.csr 152430 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_1_SET ns_noc_io_spio_soc_ip.csr 152445 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_1_SET ns_noc_io_spio_soc_ip.csr 152456 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 152466 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_2_SET ns_noc_io_spio_soc_ip.csr 152478 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_2_SET ns_noc_io_spio_soc_ip.csr 152492 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_2_SET ns_noc_io_spio_soc_ip.csr 152507 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_2_SET ns_noc_io_spio_soc_ip.csr 152518 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 152528 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CF_3_SET ns_noc_io_spio_soc_ip.csr 152540 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_CE_3_SET ns_noc_io_spio_soc_ip.csr 152554 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_VB_3_SET ns_noc_io_spio_soc_ip.csr 152569 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_RSV_3_SET ns_noc_io_spio_soc_ip.csr 152580 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 152590 UNSD_3 31 28 0x0 R register spio_noc.router_0_6_6_rovcs_j router_0_6_6_rovcs_j SPIO_NOC_ROUTER_0_6_6_ROVCS_J_ADDRESS SPIO_NOC_ROUTER_0_6_6_ROVCS_J_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_ROVCS_J_OFFSET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 152852 R0_6 register rovcs_j 0x48070 R 0x00000001 Spio_noc_router_0_6_6_rovcs_j This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_0_SET ns_noc_io_spio_soc_ip.csr 152615 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_0_SET ns_noc_io_spio_soc_ip.csr 152629 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_0_SET ns_noc_io_spio_soc_ip.csr 152644 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_0_SET ns_noc_io_spio_soc_ip.csr 152655 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 152665 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_1_SET ns_noc_io_spio_soc_ip.csr 152677 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_1_SET ns_noc_io_spio_soc_ip.csr 152691 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_1_SET ns_noc_io_spio_soc_ip.csr 152706 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_1_SET ns_noc_io_spio_soc_ip.csr 152717 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 152727 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_2_SET ns_noc_io_spio_soc_ip.csr 152739 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_2_SET ns_noc_io_spio_soc_ip.csr 152753 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_2_SET ns_noc_io_spio_soc_ip.csr 152768 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_2_SET ns_noc_io_spio_soc_ip.csr 152779 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 152789 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CF_3_SET ns_noc_io_spio_soc_ip.csr 152801 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_CE_3_SET ns_noc_io_spio_soc_ip.csr 152815 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_VB_3_SET ns_noc_io_spio_soc_ip.csr 152830 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_RSV_3_SET ns_noc_io_spio_soc_ip.csr 152841 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 152851 UNSD_3 31 28 0x0 R register spio_noc.router_0_6_6_rovcs_k router_0_6_6_rovcs_k SPIO_NOC_ROUTER_0_6_6_ROVCS_K_ADDRESS SPIO_NOC_ROUTER_0_6_6_ROVCS_K_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_ROVCS_K_OFFSET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 153113 R0_6 register rovcs_k 0x48078 R 0x00000001 Spio_noc_router_0_6_6_rovcs_k This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_0_SET ns_noc_io_spio_soc_ip.csr 152876 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_0_SET ns_noc_io_spio_soc_ip.csr 152890 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_0_SET ns_noc_io_spio_soc_ip.csr 152905 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_0_SET ns_noc_io_spio_soc_ip.csr 152916 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_0_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_0_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_0_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_0_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_0_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_0_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 152926 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_1_SET ns_noc_io_spio_soc_ip.csr 152938 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_1_SET ns_noc_io_spio_soc_ip.csr 152952 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_1_SET ns_noc_io_spio_soc_ip.csr 152967 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_1_SET ns_noc_io_spio_soc_ip.csr 152978 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_1_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_1_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_1_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_1_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_1_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_1_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 152988 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_2_SET ns_noc_io_spio_soc_ip.csr 153000 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_2_SET ns_noc_io_spio_soc_ip.csr 153014 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_2_SET ns_noc_io_spio_soc_ip.csr 153029 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_2_SET ns_noc_io_spio_soc_ip.csr 153040 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_2_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_2_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_2_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_2_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_2_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_2_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 153050 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CF_3_SET ns_noc_io_spio_soc_ip.csr 153062 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_CE_3_SET ns_noc_io_spio_soc_ip.csr 153076 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_VB_3_SET ns_noc_io_spio_soc_ip.csr 153091 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_RSV_3_SET ns_noc_io_spio_soc_ip.csr 153102 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_3_WIDTH SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_3_MSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_3_LSB SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_3_RANGE SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_3_RESET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_3_GET SPIO_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 153112 UNSD_3 31 28 0x0 R register spio_noc.router_0_6_6_re router_0_6_6_re SPIO_NOC_ROUTER_0_6_6_RE_ADDRESS SPIO_NOC_ROUTER_0_6_6_RE_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_RE_OFFSET SPIO_NOC_ROUTER_0_6_6_RE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 153287 R0_6 register re 0x48080 R/W 0x00000000 Spio_noc_router_0_6_6_re This register tracks the interrupt or error events that can occur in the router. The only interrupt event is the event counter overflow. This register is readable, and can be cleared by performing a write with the write data bits set to 0 for the bits that should be cleared. false false false false OVFI SPIO_NOC_ROUTER_0_6_6_RE_OVFI_WIDTH SPIO_NOC_ROUTER_0_6_6_RE_OVFI_MSB SPIO_NOC_ROUTER_0_6_6_RE_OVFI_LSB SPIO_NOC_ROUTER_0_6_6_RE_OVFI_RANGE SPIO_NOC_ROUTER_0_6_6_RE_OVFI_RESET SPIO_NOC_ROUTER_0_6_6_RE_OVFI_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RE_OVFI_GET SPIO_NOC_ROUTER_0_6_6_RE_OVFI_SET ns_noc_io_spio_soc_ip.csr 153139 OVFI 1'b1: In this status bit indicates that the router input event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 0 0 0x0 R/W CSR_PARERR SPIO_NOC_ROUTER_0_6_6_RE_CSR_PARERR_WIDTH SPIO_NOC_ROUTER_0_6_6_RE_CSR_PARERR_MSB SPIO_NOC_ROUTER_0_6_6_RE_CSR_PARERR_LSB SPIO_NOC_ROUTER_0_6_6_RE_CSR_PARERR_RANGE SPIO_NOC_ROUTER_0_6_6_RE_CSR_PARERR_RESET SPIO_NOC_ROUTER_0_6_6_RE_CSR_PARERR_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RE_CSR_PARERR_GET SPIO_NOC_ROUTER_0_6_6_RE_CSR_PARERR_SET ns_noc_io_spio_soc_ip.csr 153150 CSR_PARERR 1'b1: Parity error in config/status registers 1 1 0x0 R/W OVFO SPIO_NOC_ROUTER_0_6_6_RE_OVFO_WIDTH SPIO_NOC_ROUTER_0_6_6_RE_OVFO_MSB SPIO_NOC_ROUTER_0_6_6_RE_OVFO_LSB SPIO_NOC_ROUTER_0_6_6_RE_OVFO_RANGE SPIO_NOC_ROUTER_0_6_6_RE_OVFO_RESET SPIO_NOC_ROUTER_0_6_6_RE_OVFO_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RE_OVFO_GET SPIO_NOC_ROUTER_0_6_6_RE_OVFO_SET ns_noc_io_spio_soc_ip.csr 153164 OVFO 1'b1: In this status bit indicates that the router output event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 2 2 0x0 R/W UNSD_7_3 SPIO_NOC_ROUTER_0_6_6_RE_UNSD_7_3_WIDTH SPIO_NOC_ROUTER_0_6_6_RE_UNSD_7_3_MSB SPIO_NOC_ROUTER_0_6_6_RE_UNSD_7_3_LSB SPIO_NOC_ROUTER_0_6_6_RE_UNSD_7_3_RANGE SPIO_NOC_ROUTER_0_6_6_RE_UNSD_7_3_RESET SPIO_NOC_ROUTER_0_6_6_RE_UNSD_7_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RE_UNSD_7_3_GET SPIO_NOC_ROUTER_0_6_6_RE_UNSD_7_3_SET ns_noc_io_spio_soc_ip.csr 153175 UNSD_7_3 7 3 0x00 R PGE SPIO_NOC_ROUTER_0_6_6_RE_PGE_WIDTH SPIO_NOC_ROUTER_0_6_6_RE_PGE_MSB SPIO_NOC_ROUTER_0_6_6_RE_PGE_LSB SPIO_NOC_ROUTER_0_6_6_RE_PGE_RANGE SPIO_NOC_ROUTER_0_6_6_RE_PGE_RESET SPIO_NOC_ROUTER_0_6_6_RE_PGE_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RE_PGE_GET SPIO_NOC_ROUTER_0_6_6_RE_PGE_SET ns_noc_io_spio_soc_ip.csr 153187 PGE 1'b1: Power gating error, traffic received after router commited to power down 8 8 0x0 R/W NLU SPIO_NOC_ROUTER_0_6_6_RE_NLU_WIDTH SPIO_NOC_ROUTER_0_6_6_RE_NLU_MSB SPIO_NOC_ROUTER_0_6_6_RE_NLU_LSB SPIO_NOC_ROUTER_0_6_6_RE_NLU_RANGE SPIO_NOC_ROUTER_0_6_6_RE_NLU_RESET SPIO_NOC_ROUTER_0_6_6_RE_NLU_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RE_NLU_GET SPIO_NOC_ROUTER_0_6_6_RE_NLU_SET ns_noc_io_spio_soc_ip.csr 153198 NLU 1'b1: Traffic destined for North link which is unavailable 9 9 0x0 R/W ELU SPIO_NOC_ROUTER_0_6_6_RE_ELU_WIDTH SPIO_NOC_ROUTER_0_6_6_RE_ELU_MSB SPIO_NOC_ROUTER_0_6_6_RE_ELU_LSB SPIO_NOC_ROUTER_0_6_6_RE_ELU_RANGE SPIO_NOC_ROUTER_0_6_6_RE_ELU_RESET SPIO_NOC_ROUTER_0_6_6_RE_ELU_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RE_ELU_GET SPIO_NOC_ROUTER_0_6_6_RE_ELU_SET ns_noc_io_spio_soc_ip.csr 153209 ELU 1'b1: Traffic destined for East link which is unavailable 10 10 0x0 R/W WLU SPIO_NOC_ROUTER_0_6_6_RE_WLU_WIDTH SPIO_NOC_ROUTER_0_6_6_RE_WLU_MSB SPIO_NOC_ROUTER_0_6_6_RE_WLU_LSB SPIO_NOC_ROUTER_0_6_6_RE_WLU_RANGE SPIO_NOC_ROUTER_0_6_6_RE_WLU_RESET SPIO_NOC_ROUTER_0_6_6_RE_WLU_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RE_WLU_GET SPIO_NOC_ROUTER_0_6_6_RE_WLU_SET ns_noc_io_spio_soc_ip.csr 153220 WLU 1'b1: Traffic destined for West link which is unavailable 11 11 0x0 R/W SLU SPIO_NOC_ROUTER_0_6_6_RE_SLU_WIDTH SPIO_NOC_ROUTER_0_6_6_RE_SLU_MSB SPIO_NOC_ROUTER_0_6_6_RE_SLU_LSB SPIO_NOC_ROUTER_0_6_6_RE_SLU_RANGE SPIO_NOC_ROUTER_0_6_6_RE_SLU_RESET SPIO_NOC_ROUTER_0_6_6_RE_SLU_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RE_SLU_GET SPIO_NOC_ROUTER_0_6_6_RE_SLU_SET ns_noc_io_spio_soc_ip.csr 153231 SLU 1'b1: Traffic destined for South link which is unavailable 12 12 0x0 R/W HLU SPIO_NOC_ROUTER_0_6_6_RE_HLU_WIDTH SPIO_NOC_ROUTER_0_6_6_RE_HLU_MSB SPIO_NOC_ROUTER_0_6_6_RE_HLU_LSB SPIO_NOC_ROUTER_0_6_6_RE_HLU_RANGE SPIO_NOC_ROUTER_0_6_6_RE_HLU_RESET SPIO_NOC_ROUTER_0_6_6_RE_HLU_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RE_HLU_GET SPIO_NOC_ROUTER_0_6_6_RE_HLU_SET ns_noc_io_spio_soc_ip.csr 153242 HLU 1'b1: Traffic destined for H link which is unavailable 13 13 0x0 R/W ILU SPIO_NOC_ROUTER_0_6_6_RE_ILU_WIDTH SPIO_NOC_ROUTER_0_6_6_RE_ILU_MSB SPIO_NOC_ROUTER_0_6_6_RE_ILU_LSB SPIO_NOC_ROUTER_0_6_6_RE_ILU_RANGE SPIO_NOC_ROUTER_0_6_6_RE_ILU_RESET SPIO_NOC_ROUTER_0_6_6_RE_ILU_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RE_ILU_GET SPIO_NOC_ROUTER_0_6_6_RE_ILU_SET ns_noc_io_spio_soc_ip.csr 153253 ILU 1'b1: Traffic destined for I link which is unavailable 14 14 0x0 R/W JLU SPIO_NOC_ROUTER_0_6_6_RE_JLU_WIDTH SPIO_NOC_ROUTER_0_6_6_RE_JLU_MSB SPIO_NOC_ROUTER_0_6_6_RE_JLU_LSB SPIO_NOC_ROUTER_0_6_6_RE_JLU_RANGE SPIO_NOC_ROUTER_0_6_6_RE_JLU_RESET SPIO_NOC_ROUTER_0_6_6_RE_JLU_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RE_JLU_GET SPIO_NOC_ROUTER_0_6_6_RE_JLU_SET ns_noc_io_spio_soc_ip.csr 153264 JLU 1'b1: Traffic destined for J link which is unavailable 15 15 0x0 R/W KLU SPIO_NOC_ROUTER_0_6_6_RE_KLU_WIDTH SPIO_NOC_ROUTER_0_6_6_RE_KLU_MSB SPIO_NOC_ROUTER_0_6_6_RE_KLU_LSB SPIO_NOC_ROUTER_0_6_6_RE_KLU_RANGE SPIO_NOC_ROUTER_0_6_6_RE_KLU_RESET SPIO_NOC_ROUTER_0_6_6_RE_KLU_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RE_KLU_GET SPIO_NOC_ROUTER_0_6_6_RE_KLU_SET ns_noc_io_spio_soc_ip.csr 153275 KLU 1'b1: Traffic destined for K link which is unavailable 16 16 0x0 R/W UNSD_31_14 SPIO_NOC_ROUTER_0_6_6_RE_UNSD_31_14_WIDTH SPIO_NOC_ROUTER_0_6_6_RE_UNSD_31_14_MSB SPIO_NOC_ROUTER_0_6_6_RE_UNSD_31_14_LSB SPIO_NOC_ROUTER_0_6_6_RE_UNSD_31_14_RANGE SPIO_NOC_ROUTER_0_6_6_RE_UNSD_31_14_RESET SPIO_NOC_ROUTER_0_6_6_RE_UNSD_31_14_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RE_UNSD_31_14_GET SPIO_NOC_ROUTER_0_6_6_RE_UNSD_31_14_SET ns_noc_io_spio_soc_ip.csr 153286 UNSD_31_14 31 17 0x0000 R register spio_noc.router_0_6_6_rem router_0_6_6_rem SPIO_NOC_ROUTER_0_6_6_REM_ADDRESS SPIO_NOC_ROUTER_0_6_6_REM_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_REM_OFFSET SPIO_NOC_ROUTER_0_6_6_REM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 153460 R0_6 register rem 0x48088 R/W 0x0001fe00 Spio_noc_router_0_6_6_rem This register is used to select whether the interrupt events in the Router Event Interrupt Status register should send an interrupt when asserted. If the corresponding bit is set to 1, an interrupt will not be sent. This register can be read and written to. false false false false OVFIM SPIO_NOC_ROUTER_0_6_6_REM_OVFIM_WIDTH SPIO_NOC_ROUTER_0_6_6_REM_OVFIM_MSB SPIO_NOC_ROUTER_0_6_6_REM_OVFIM_LSB SPIO_NOC_ROUTER_0_6_6_REM_OVFIM_RANGE SPIO_NOC_ROUTER_0_6_6_REM_OVFIM_RESET SPIO_NOC_ROUTER_0_6_6_REM_OVFIM_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_REM_OVFIM_GET SPIO_NOC_ROUTER_0_6_6_REM_OVFIM_SET ns_noc_io_spio_soc_ip.csr 153313 OVFIM 1'b1: Masks or disables an interrupt from being generated by the input event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 0 0 0x0 R/W CSR_PARERRM SPIO_NOC_ROUTER_0_6_6_REM_CSR_PARERRM_WIDTH SPIO_NOC_ROUTER_0_6_6_REM_CSR_PARERRM_MSB SPIO_NOC_ROUTER_0_6_6_REM_CSR_PARERRM_LSB SPIO_NOC_ROUTER_0_6_6_REM_CSR_PARERRM_RANGE SPIO_NOC_ROUTER_0_6_6_REM_CSR_PARERRM_RESET SPIO_NOC_ROUTER_0_6_6_REM_CSR_PARERRM_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_REM_CSR_PARERRM_GET SPIO_NOC_ROUTER_0_6_6_REM_CSR_PARERRM_SET ns_noc_io_spio_soc_ip.csr 153324 CSR_PARERRM 1'b1: Mask CSR parity error interrupt 1 1 0x0 R/W OVFOM SPIO_NOC_ROUTER_0_6_6_REM_OVFOM_WIDTH SPIO_NOC_ROUTER_0_6_6_REM_OVFOM_MSB SPIO_NOC_ROUTER_0_6_6_REM_OVFOM_LSB SPIO_NOC_ROUTER_0_6_6_REM_OVFOM_RANGE SPIO_NOC_ROUTER_0_6_6_REM_OVFOM_RESET SPIO_NOC_ROUTER_0_6_6_REM_OVFOM_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_REM_OVFOM_GET SPIO_NOC_ROUTER_0_6_6_REM_OVFOM_SET ns_noc_io_spio_soc_ip.csr 153338 OVFOM 1'b1: Masks or disables an interrupt from being generated by the output event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 2 2 0x0 R/W UNSD_7_3 SPIO_NOC_ROUTER_0_6_6_REM_UNSD_7_3_WIDTH SPIO_NOC_ROUTER_0_6_6_REM_UNSD_7_3_MSB SPIO_NOC_ROUTER_0_6_6_REM_UNSD_7_3_LSB SPIO_NOC_ROUTER_0_6_6_REM_UNSD_7_3_RANGE SPIO_NOC_ROUTER_0_6_6_REM_UNSD_7_3_RESET SPIO_NOC_ROUTER_0_6_6_REM_UNSD_7_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_REM_UNSD_7_3_GET SPIO_NOC_ROUTER_0_6_6_REM_UNSD_7_3_SET ns_noc_io_spio_soc_ip.csr 153349 UNSD_7_3 7 3 0x00 R PGM SPIO_NOC_ROUTER_0_6_6_REM_PGM_WIDTH SPIO_NOC_ROUTER_0_6_6_REM_PGM_MSB SPIO_NOC_ROUTER_0_6_6_REM_PGM_LSB SPIO_NOC_ROUTER_0_6_6_REM_PGM_RANGE SPIO_NOC_ROUTER_0_6_6_REM_PGM_RESET SPIO_NOC_ROUTER_0_6_6_REM_PGM_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_REM_PGM_GET SPIO_NOC_ROUTER_0_6_6_REM_PGM_SET ns_noc_io_spio_soc_ip.csr 153360 PGM 1'b1: Mask PGE error interrupt 8 8 0x0 R/W MN SPIO_NOC_ROUTER_0_6_6_REM_MN_WIDTH SPIO_NOC_ROUTER_0_6_6_REM_MN_MSB SPIO_NOC_ROUTER_0_6_6_REM_MN_LSB SPIO_NOC_ROUTER_0_6_6_REM_MN_RANGE SPIO_NOC_ROUTER_0_6_6_REM_MN_RESET SPIO_NOC_ROUTER_0_6_6_REM_MN_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_REM_MN_GET SPIO_NOC_ROUTER_0_6_6_REM_MN_SET ns_noc_io_spio_soc_ip.csr 153371 MN 1'b1: Mask NLU error interrupt 9 9 0x1 R/W ME SPIO_NOC_ROUTER_0_6_6_REM_ME_WIDTH SPIO_NOC_ROUTER_0_6_6_REM_ME_MSB SPIO_NOC_ROUTER_0_6_6_REM_ME_LSB SPIO_NOC_ROUTER_0_6_6_REM_ME_RANGE SPIO_NOC_ROUTER_0_6_6_REM_ME_RESET SPIO_NOC_ROUTER_0_6_6_REM_ME_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_REM_ME_GET SPIO_NOC_ROUTER_0_6_6_REM_ME_SET ns_noc_io_spio_soc_ip.csr 153382 ME 1'b1: Mask ELU error interrupt 10 10 0x1 R/W MW SPIO_NOC_ROUTER_0_6_6_REM_MW_WIDTH SPIO_NOC_ROUTER_0_6_6_REM_MW_MSB SPIO_NOC_ROUTER_0_6_6_REM_MW_LSB SPIO_NOC_ROUTER_0_6_6_REM_MW_RANGE SPIO_NOC_ROUTER_0_6_6_REM_MW_RESET SPIO_NOC_ROUTER_0_6_6_REM_MW_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_REM_MW_GET SPIO_NOC_ROUTER_0_6_6_REM_MW_SET ns_noc_io_spio_soc_ip.csr 153393 MW 1'b1: Mask WLU error interrupt 11 11 0x1 R/W MS SPIO_NOC_ROUTER_0_6_6_REM_MS_WIDTH SPIO_NOC_ROUTER_0_6_6_REM_MS_MSB SPIO_NOC_ROUTER_0_6_6_REM_MS_LSB SPIO_NOC_ROUTER_0_6_6_REM_MS_RANGE SPIO_NOC_ROUTER_0_6_6_REM_MS_RESET SPIO_NOC_ROUTER_0_6_6_REM_MS_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_REM_MS_GET SPIO_NOC_ROUTER_0_6_6_REM_MS_SET ns_noc_io_spio_soc_ip.csr 153404 MS 1'b1: Mask SLU error interrupt 12 12 0x1 R/W MH SPIO_NOC_ROUTER_0_6_6_REM_MH_WIDTH SPIO_NOC_ROUTER_0_6_6_REM_MH_MSB SPIO_NOC_ROUTER_0_6_6_REM_MH_LSB SPIO_NOC_ROUTER_0_6_6_REM_MH_RANGE SPIO_NOC_ROUTER_0_6_6_REM_MH_RESET SPIO_NOC_ROUTER_0_6_6_REM_MH_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_REM_MH_GET SPIO_NOC_ROUTER_0_6_6_REM_MH_SET ns_noc_io_spio_soc_ip.csr 153415 MH 1'b1: Mask HLU error interrupt 13 13 0x1 R/W MI SPIO_NOC_ROUTER_0_6_6_REM_MI_WIDTH SPIO_NOC_ROUTER_0_6_6_REM_MI_MSB SPIO_NOC_ROUTER_0_6_6_REM_MI_LSB SPIO_NOC_ROUTER_0_6_6_REM_MI_RANGE SPIO_NOC_ROUTER_0_6_6_REM_MI_RESET SPIO_NOC_ROUTER_0_6_6_REM_MI_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_REM_MI_GET SPIO_NOC_ROUTER_0_6_6_REM_MI_SET ns_noc_io_spio_soc_ip.csr 153426 MI 1'b1: Mask ILU error interrupt 14 14 0x1 R/W MJ SPIO_NOC_ROUTER_0_6_6_REM_MJ_WIDTH SPIO_NOC_ROUTER_0_6_6_REM_MJ_MSB SPIO_NOC_ROUTER_0_6_6_REM_MJ_LSB SPIO_NOC_ROUTER_0_6_6_REM_MJ_RANGE SPIO_NOC_ROUTER_0_6_6_REM_MJ_RESET SPIO_NOC_ROUTER_0_6_6_REM_MJ_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_REM_MJ_GET SPIO_NOC_ROUTER_0_6_6_REM_MJ_SET ns_noc_io_spio_soc_ip.csr 153437 MJ 1'b1: Mask JLU error interrupt 15 15 0x1 R/W MK SPIO_NOC_ROUTER_0_6_6_REM_MK_WIDTH SPIO_NOC_ROUTER_0_6_6_REM_MK_MSB SPIO_NOC_ROUTER_0_6_6_REM_MK_LSB SPIO_NOC_ROUTER_0_6_6_REM_MK_RANGE SPIO_NOC_ROUTER_0_6_6_REM_MK_RESET SPIO_NOC_ROUTER_0_6_6_REM_MK_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_REM_MK_GET SPIO_NOC_ROUTER_0_6_6_REM_MK_SET ns_noc_io_spio_soc_ip.csr 153448 MK 1'b1: Mask KLU error interrupt 16 16 0x1 R/W UNSD_31_14 SPIO_NOC_ROUTER_0_6_6_REM_UNSD_31_14_WIDTH SPIO_NOC_ROUTER_0_6_6_REM_UNSD_31_14_MSB SPIO_NOC_ROUTER_0_6_6_REM_UNSD_31_14_LSB SPIO_NOC_ROUTER_0_6_6_REM_UNSD_31_14_RANGE SPIO_NOC_ROUTER_0_6_6_REM_UNSD_31_14_RESET SPIO_NOC_ROUTER_0_6_6_REM_UNSD_31_14_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_REM_UNSD_31_14_GET SPIO_NOC_ROUTER_0_6_6_REM_UNSD_31_14_SET ns_noc_io_spio_soc_ip.csr 153459 UNSD_31_14 31 17 0x0000 R register spio_noc.router_0_6_6_recc router_0_6_6_recc SPIO_NOC_ROUTER_0_6_6_RECC_ADDRESS SPIO_NOC_ROUTER_0_6_6_RECC_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_RECC_OFFSET SPIO_NOC_ROUTER_0_6_6_RECC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 153545 R0_6 register recc 0x48090 R/W 0x00000000 Spio_noc_router_0_6_6_recc This register is used to select which hardware events will increment the event counter. false false false false IVC SPIO_NOC_ROUTER_0_6_6_RECC_IVC_WIDTH SPIO_NOC_ROUTER_0_6_6_RECC_IVC_MSB SPIO_NOC_ROUTER_0_6_6_RECC_IVC_LSB SPIO_NOC_ROUTER_0_6_6_RECC_IVC_RANGE SPIO_NOC_ROUTER_0_6_6_RECC_IVC_RESET SPIO_NOC_ROUTER_0_6_6_RECC_IVC_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RECC_IVC_GET SPIO_NOC_ROUTER_0_6_6_RECC_IVC_SET ns_noc_io_spio_soc_ip.csr 153481 IVC 11: Input VC 3 10: Input VC 2 01: Input VC 1 00: Input VC 0 1 0 0x0 R/W UNSD_3_2 SPIO_NOC_ROUTER_0_6_6_RECC_UNSD_3_2_WIDTH SPIO_NOC_ROUTER_0_6_6_RECC_UNSD_3_2_MSB SPIO_NOC_ROUTER_0_6_6_RECC_UNSD_3_2_LSB SPIO_NOC_ROUTER_0_6_6_RECC_UNSD_3_2_RANGE SPIO_NOC_ROUTER_0_6_6_RECC_UNSD_3_2_RESET SPIO_NOC_ROUTER_0_6_6_RECC_UNSD_3_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RECC_UNSD_3_2_GET SPIO_NOC_ROUTER_0_6_6_RECC_UNSD_3_2_SET ns_noc_io_spio_soc_ip.csr 153492 UNSD_3_2 3 2 0x0 R INP SPIO_NOC_ROUTER_0_6_6_RECC_INP_WIDTH SPIO_NOC_ROUTER_0_6_6_RECC_INP_MSB SPIO_NOC_ROUTER_0_6_6_RECC_INP_LSB SPIO_NOC_ROUTER_0_6_6_RECC_INP_RANGE SPIO_NOC_ROUTER_0_6_6_RECC_INP_RESET SPIO_NOC_ROUTER_0_6_6_RECC_INP_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RECC_INP_GET SPIO_NOC_ROUTER_0_6_6_RECC_INP_SET ns_noc_io_spio_soc_ip.csr 153503 INP Input port on which the event is captured 6 4 0x0 R/W UNSD_7_7 SPIO_NOC_ROUTER_0_6_6_RECC_UNSD_7_7_WIDTH SPIO_NOC_ROUTER_0_6_6_RECC_UNSD_7_7_MSB SPIO_NOC_ROUTER_0_6_6_RECC_UNSD_7_7_LSB SPIO_NOC_ROUTER_0_6_6_RECC_UNSD_7_7_RANGE SPIO_NOC_ROUTER_0_6_6_RECC_UNSD_7_7_RESET SPIO_NOC_ROUTER_0_6_6_RECC_UNSD_7_7_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RECC_UNSD_7_7_GET SPIO_NOC_ROUTER_0_6_6_RECC_UNSD_7_7_SET ns_noc_io_spio_soc_ip.csr 153514 UNSD_7_7 7 7 0x0 R EVT SPIO_NOC_ROUTER_0_6_6_RECC_EVT_WIDTH SPIO_NOC_ROUTER_0_6_6_RECC_EVT_MSB SPIO_NOC_ROUTER_0_6_6_RECC_EVT_LSB SPIO_NOC_ROUTER_0_6_6_RECC_EVT_RANGE SPIO_NOC_ROUTER_0_6_6_RECC_EVT_RESET SPIO_NOC_ROUTER_0_6_6_RECC_EVT_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RECC_EVT_GET SPIO_NOC_ROUTER_0_6_6_RECC_EVT_SET ns_noc_io_spio_soc_ip.csr 153533 EVT 11: Generates count event when VC has valid data, but is stalled 10: Generates count event on every flit received for the selected input port and selected input VCs, this can be used to count total flits received on a router input port 01: Generates count event on every EOP received for the selected input port and selected input VCs, this can be used to count packets received on a router input port 00: Disable 9 8 0x0 R/W UNSD_31_10 SPIO_NOC_ROUTER_0_6_6_RECC_UNSD_31_10_WIDTH SPIO_NOC_ROUTER_0_6_6_RECC_UNSD_31_10_MSB SPIO_NOC_ROUTER_0_6_6_RECC_UNSD_31_10_LSB SPIO_NOC_ROUTER_0_6_6_RECC_UNSD_31_10_RANGE SPIO_NOC_ROUTER_0_6_6_RECC_UNSD_31_10_RESET SPIO_NOC_ROUTER_0_6_6_RECC_UNSD_31_10_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RECC_UNSD_31_10_GET SPIO_NOC_ROUTER_0_6_6_RECC_UNSD_31_10_SET ns_noc_io_spio_soc_ip.csr 153544 UNSD_31_10 31 10 0x000000 R register spio_noc.router_0_6_6_rec router_0_6_6_rec SPIO_NOC_ROUTER_0_6_6_REC_ADDRESS SPIO_NOC_ROUTER_0_6_6_REC_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_REC_OFFSET SPIO_NOC_ROUTER_0_6_6_REC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 153570 R0_6 register rec 0x48098 R/W 0x00000000 Spio_noc_router_0_6_6_rec This register holds the event counter. The value can be read to determine the current count value. The value can be written to initialize the counter. When events trigger a count, the counter will increment. When the counter increments at its highest value, it will roll over to zero and the overflow will mark the Router Event Interrupt Status register, which could trigger an interrupt. false false false false EVENT_CNTR SPIO_NOC_ROUTER_0_6_6_REC_EVENT_CNTR_WIDTH SPIO_NOC_ROUTER_0_6_6_REC_EVENT_CNTR_MSB SPIO_NOC_ROUTER_0_6_6_REC_EVENT_CNTR_LSB SPIO_NOC_ROUTER_0_6_6_REC_EVENT_CNTR_RANGE SPIO_NOC_ROUTER_0_6_6_REC_EVENT_CNTR_RESET SPIO_NOC_ROUTER_0_6_6_REC_EVENT_CNTR_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_REC_EVENT_CNTR_GET SPIO_NOC_ROUTER_0_6_6_REC_EVENT_CNTR_SET ns_noc_io_spio_soc_ip.csr 153569 EVENT_CNTR 32'bit event incrementing counter. Rollover from 32'hFFFFF -> 32'd0 sets the rollover status bit RE 31 0 0x00000000 R/W register spio_noc.router_0_6_6_id router_0_6_6_id SPIO_NOC_ROUTER_0_6_6_ID_ADDRESS SPIO_NOC_ROUTER_0_6_6_ID_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_ID_OFFSET SPIO_NOC_ROUTER_0_6_6_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 153639 R0_6 register id 0x480A0 R 0x010000a0 Spio_noc_router_0_6_6_id This register holds layer and position information for the router. It is a read-only register. It can be used for debugging software access to the NoC elements by confirming that a read has successfully targeted the correct NoC element. false false false false LAYER SPIO_NOC_ROUTER_0_6_6_ID_LAYER_WIDTH SPIO_NOC_ROUTER_0_6_6_ID_LAYER_MSB SPIO_NOC_ROUTER_0_6_6_ID_LAYER_LSB SPIO_NOC_ROUTER_0_6_6_ID_LAYER_RANGE SPIO_NOC_ROUTER_0_6_6_ID_LAYER_RESET SPIO_NOC_ROUTER_0_6_6_ID_LAYER_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ID_LAYER_GET SPIO_NOC_ROUTER_0_6_6_ID_LAYER_SET ns_noc_io_spio_soc_ip.csr 153595 LAYER 5-bit identifier of the NoC layer on which this router is located 4 0 0x00 R POS SPIO_NOC_ROUTER_0_6_6_ID_POS_WIDTH SPIO_NOC_ROUTER_0_6_6_ID_POS_MSB SPIO_NOC_ROUTER_0_6_6_ID_POS_LSB SPIO_NOC_ROUTER_0_6_6_ID_POS_RANGE SPIO_NOC_ROUTER_0_6_6_ID_POS_RESET SPIO_NOC_ROUTER_0_6_6_ID_POS_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ID_POS_GET SPIO_NOC_ROUTER_0_6_6_ID_POS_SET ns_noc_io_spio_soc_ip.csr 153606 POS 16-bit position ID of this router in the NoC 20 5 0x0005 R ZERO SPIO_NOC_ROUTER_0_6_6_ID_ZERO_WIDTH SPIO_NOC_ROUTER_0_6_6_ID_ZERO_MSB SPIO_NOC_ROUTER_0_6_6_ID_ZERO_LSB SPIO_NOC_ROUTER_0_6_6_ID_ZERO_RANGE SPIO_NOC_ROUTER_0_6_6_ID_ZERO_RESET SPIO_NOC_ROUTER_0_6_6_ID_ZERO_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ID_ZERO_GET SPIO_NOC_ROUTER_0_6_6_ID_ZERO_SET ns_noc_io_spio_soc_ip.csr 153617 ZERO Zeroes 23 21 0x0 R ONE SPIO_NOC_ROUTER_0_6_6_ID_ONE_WIDTH SPIO_NOC_ROUTER_0_6_6_ID_ONE_MSB SPIO_NOC_ROUTER_0_6_6_ID_ONE_LSB SPIO_NOC_ROUTER_0_6_6_ID_ONE_RANGE SPIO_NOC_ROUTER_0_6_6_ID_ONE_RESET SPIO_NOC_ROUTER_0_6_6_ID_ONE_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ID_ONE_GET SPIO_NOC_ROUTER_0_6_6_ID_ONE_SET ns_noc_io_spio_soc_ip.csr 153628 ONE One 24 24 0x1 R UNSD_31_25 SPIO_NOC_ROUTER_0_6_6_ID_UNSD_31_25_WIDTH SPIO_NOC_ROUTER_0_6_6_ID_UNSD_31_25_MSB SPIO_NOC_ROUTER_0_6_6_ID_UNSD_31_25_LSB SPIO_NOC_ROUTER_0_6_6_ID_UNSD_31_25_RANGE SPIO_NOC_ROUTER_0_6_6_ID_UNSD_31_25_RESET SPIO_NOC_ROUTER_0_6_6_ID_UNSD_31_25_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ID_UNSD_31_25_GET SPIO_NOC_ROUTER_0_6_6_ID_UNSD_31_25_SET ns_noc_io_spio_soc_ip.csr 153638 UNSD_31_25 31 25 0x00 R register spio_noc.router_0_6_6_rcgc router_0_6_6_rcgc SPIO_NOC_ROUTER_0_6_6_RCGC_ADDRESS SPIO_NOC_ROUTER_0_6_6_RCGC_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_RCGC_OFFSET SPIO_NOC_ROUTER_0_6_6_RCGC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 153665 R0_6 register rcgc 0x480A8 R/W 0x00000064 Spio_noc_router_0_6_6_rcgc Programmable interval used by coarse clock gating logic in routers.This count determines the consecutive number of idle cycle after which a router output port initiates coarse clock gating of the local port clock and de-asserts the 'busy' signal to the downstream router. This signal indicates inactivity to the downstream router and allows it to initiate coarse clock gating of its corresponding input port. false false false false HYSTERESIS_COUNTER SPIO_NOC_ROUTER_0_6_6_RCGC_HYSTERESIS_COUNTER_WIDTH SPIO_NOC_ROUTER_0_6_6_RCGC_HYSTERESIS_COUNTER_MSB SPIO_NOC_ROUTER_0_6_6_RCGC_HYSTERESIS_COUNTER_LSB SPIO_NOC_ROUTER_0_6_6_RCGC_HYSTERESIS_COUNTER_RANGE SPIO_NOC_ROUTER_0_6_6_RCGC_HYSTERESIS_COUNTER_RESET SPIO_NOC_ROUTER_0_6_6_RCGC_HYSTERESIS_COUNTER_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RCGC_HYSTERESIS_COUNTER_GET SPIO_NOC_ROUTER_0_6_6_RCGC_HYSTERESIS_COUNTER_SET ns_noc_io_spio_soc_ip.csr 153664 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W register spio_noc.router_0_6_6_rcgo router_0_6_6_rcgo SPIO_NOC_ROUTER_0_6_6_RCGO_ADDRESS SPIO_NOC_ROUTER_0_6_6_RCGO_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_RCGO_OFFSET SPIO_NOC_ROUTER_0_6_6_RCGO_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 153704 R0_6 register rcgo 0x480B0 R/W 0x00000000 Spio_noc_router_0_6_6_rcgo This register is used by coarse grained clock gating logic. This register can be set to override coarse clock gating for the entire router. Coarse clock gating for selective routers can be overridden by locally setting this register, if the user does not want incur and aggregate coarse clock gating cycle penalty over a "fast path/critical path" through the NoC. false false false false FPO SPIO_NOC_ROUTER_0_6_6_RCGO_FPO_WIDTH SPIO_NOC_ROUTER_0_6_6_RCGO_FPO_MSB SPIO_NOC_ROUTER_0_6_6_RCGO_FPO_LSB SPIO_NOC_ROUTER_0_6_6_RCGO_FPO_RANGE SPIO_NOC_ROUTER_0_6_6_RCGO_FPO_RESET SPIO_NOC_ROUTER_0_6_6_RCGO_FPO_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RCGO_FPO_GET SPIO_NOC_ROUTER_0_6_6_RCGO_FPO_SET ns_noc_io_spio_soc_ip.csr 153692 FPO 1'b1: Coarse clock gating is locally disabled (for fast path) 1'b0: Coarse clock gating is locally enabled 0 0 0x0 R/W UNSD_31_1 SPIO_NOC_ROUTER_0_6_6_RCGO_UNSD_31_1_WIDTH SPIO_NOC_ROUTER_0_6_6_RCGO_UNSD_31_1_MSB SPIO_NOC_ROUTER_0_6_6_RCGO_UNSD_31_1_LSB SPIO_NOC_ROUTER_0_6_6_RCGO_UNSD_31_1_RANGE SPIO_NOC_ROUTER_0_6_6_RCGO_UNSD_31_1_RESET SPIO_NOC_ROUTER_0_6_6_RCGO_UNSD_31_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_RCGO_UNSD_31_1_GET SPIO_NOC_ROUTER_0_6_6_RCGO_UNSD_31_1_SET ns_noc_io_spio_soc_ip.csr 153703 UNSD_31_1 31 1 0x00000000 R register spio_noc.router_0_6_6_p0_rperr router_0_6_6_p0_rperr SPIO_NOC_ROUTER_0_6_6_P0_RPERR_ADDRESS SPIO_NOC_ROUTER_0_6_6_P0_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_P0_RPERR_OFFSET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 153995 R0_6 register p0_rperr 0x480B8 R/W 0x00000000 Spio_noc_router_0_6_6_p0_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 153747 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 153758 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 153769 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 153780 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_6_6_P0_RPERR_CR_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERR_CR_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_CR_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_CR_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERR_CR_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERR_CR_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 153791 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_6_6_P0_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 153802 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_0_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_0_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_0_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_0_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_0_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 153813 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_0_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_0_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_0_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_0_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 153824 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_0_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_0_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_0_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_0_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 153836 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_0_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_0_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_0_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_0_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 153847 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_1_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_1_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_1_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_1_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_1_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 153859 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_1_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_1_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_1_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_1_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 153871 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_1_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_1_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_1_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_1_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 153884 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_1_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_1_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_1_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_1_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 153896 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_2_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_2_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_2_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_2_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_2_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 153908 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_2_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_2_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_2_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_2_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 153920 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_2_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_2_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_2_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_2_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 153933 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_2_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_2_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_2_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_2_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 153945 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_3_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_3_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_3_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_3_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_3_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 153957 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_3_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_3_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_3_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_3_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 153969 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_3_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_3_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_3_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_3_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 153982 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_3_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_3_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_3_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_3_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 153994 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_0_6_6_p1_rperr router_0_6_6_p1_rperr SPIO_NOC_ROUTER_0_6_6_P1_RPERR_ADDRESS SPIO_NOC_ROUTER_0_6_6_P1_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_P1_RPERR_OFFSET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 154286 R0_6 register p1_rperr 0x480C0 R/W 0x00000000 Spio_noc_router_0_6_6_p1_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 154038 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 154049 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 154060 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 154071 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_6_6_P1_RPERR_CR_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERR_CR_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_CR_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_CR_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERR_CR_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERR_CR_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 154082 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_6_6_P1_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 154093 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_0_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_0_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_0_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_0_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_0_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 154104 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_0_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_0_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_0_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_0_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 154115 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_0_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_0_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_0_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_0_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 154127 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_0_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_0_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_0_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_0_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 154138 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_1_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_1_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_1_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_1_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_1_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 154150 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_1_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_1_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_1_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_1_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 154162 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_1_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_1_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_1_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_1_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 154175 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_1_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_1_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_1_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_1_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 154187 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_2_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_2_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_2_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_2_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_2_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 154199 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_2_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_2_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_2_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_2_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 154211 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_2_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_2_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_2_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_2_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 154224 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_2_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_2_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_2_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_2_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 154236 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_3_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_3_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_3_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_3_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_3_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 154248 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_3_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_3_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_3_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_3_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 154260 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_3_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_3_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_3_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_3_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 154273 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_3_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_3_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_3_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_3_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 154285 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_0_6_6_p2_rperr router_0_6_6_p2_rperr SPIO_NOC_ROUTER_0_6_6_P2_RPERR_ADDRESS SPIO_NOC_ROUTER_0_6_6_P2_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_P2_RPERR_OFFSET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 154577 R0_6 register p2_rperr 0x480C8 R/W 0x00000000 Spio_noc_router_0_6_6_p2_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 154329 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 154340 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 154351 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 154362 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_6_6_P2_RPERR_CR_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERR_CR_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_CR_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_CR_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERR_CR_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERR_CR_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 154373 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_6_6_P2_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 154384 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_0_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_0_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_0_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_0_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_0_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 154395 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_0_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_0_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_0_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_0_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 154406 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_0_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_0_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_0_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_0_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 154418 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_0_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_0_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_0_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_0_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 154429 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_1_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_1_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_1_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_1_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_1_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 154441 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_1_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_1_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_1_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_1_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 154453 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_1_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_1_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_1_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_1_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 154466 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_1_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_1_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_1_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_1_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 154478 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_2_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_2_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_2_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_2_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_2_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 154490 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_2_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_2_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_2_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_2_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 154502 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_2_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_2_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_2_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_2_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 154515 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_2_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_2_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_2_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_2_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 154527 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_3_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_3_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_3_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_3_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_3_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 154539 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_3_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_3_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_3_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_3_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 154551 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_3_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_3_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_3_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_3_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 154564 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_3_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_3_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_3_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_3_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 154576 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_0_6_6_p3_rperr router_0_6_6_p3_rperr SPIO_NOC_ROUTER_0_6_6_P3_RPERR_ADDRESS SPIO_NOC_ROUTER_0_6_6_P3_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_P3_RPERR_OFFSET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 154868 R0_6 register p3_rperr 0x480D0 R/W 0x00000000 Spio_noc_router_0_6_6_p3_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 154620 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 154631 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 154642 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 154653 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_6_6_P3_RPERR_CR_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERR_CR_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_CR_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_CR_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERR_CR_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERR_CR_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 154664 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_6_6_P3_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 154675 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_0_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_0_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_0_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_0_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_0_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 154686 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_0_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_0_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_0_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_0_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 154697 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_0_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_0_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_0_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_0_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 154709 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_0_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_0_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_0_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_0_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 154720 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_1_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_1_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_1_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_1_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_1_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 154732 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_1_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_1_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_1_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_1_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 154744 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_1_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_1_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_1_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_1_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 154757 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_1_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_1_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_1_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_1_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 154769 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_2_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_2_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_2_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_2_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_2_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 154781 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_2_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_2_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_2_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_2_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 154793 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_2_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_2_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_2_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_2_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 154806 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_2_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_2_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_2_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_2_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 154818 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_3_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_3_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_3_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_3_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_3_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 154830 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_3_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_3_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_3_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_3_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 154842 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_3_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_3_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_3_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_3_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 154855 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_3_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_3_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_3_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_3_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 154867 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_0_6_6_p4_rperr router_0_6_6_p4_rperr SPIO_NOC_ROUTER_0_6_6_P4_RPERR_ADDRESS SPIO_NOC_ROUTER_0_6_6_P4_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_P4_RPERR_OFFSET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 155159 R0_6 register p4_rperr 0x480D8 R/W 0x00000000 Spio_noc_router_0_6_6_p4_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 154911 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 154922 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 154933 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 154944 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_6_6_P4_RPERR_CR_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERR_CR_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_CR_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_CR_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERR_CR_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERR_CR_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 154955 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_6_6_P4_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 154966 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_0_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_0_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_0_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_0_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_0_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 154977 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_0_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_0_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_0_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_0_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 154988 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_0_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_0_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_0_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_0_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 155000 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_0_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_0_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_0_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_0_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 155011 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_1_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_1_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_1_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_1_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_1_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 155023 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_1_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_1_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_1_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_1_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 155035 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_1_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_1_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_1_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_1_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 155048 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_1_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_1_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_1_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_1_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 155060 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_2_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_2_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_2_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_2_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_2_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 155072 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_2_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_2_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_2_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_2_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 155084 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_2_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_2_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_2_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_2_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 155097 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_2_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_2_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_2_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_2_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 155109 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_3_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_3_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_3_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_3_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_3_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 155121 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_3_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_3_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_3_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_3_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 155133 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_3_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_3_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_3_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_3_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 155146 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_3_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_3_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_3_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_3_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 155158 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_0_6_6_p5_rperr router_0_6_6_p5_rperr SPIO_NOC_ROUTER_0_6_6_P5_RPERR_ADDRESS SPIO_NOC_ROUTER_0_6_6_P5_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_P5_RPERR_OFFSET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 155446 R0_6 register p5_rperr 0x480E0 R/W 0x00000000 Spio_noc_router_0_6_6_p5_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 155202 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 155213 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 155224 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 155235 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_6_6_P5_RPERR_CR_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERR_CR_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_CR_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_CR_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERR_CR_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERR_CR_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 155246 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_6_6_P5_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 155257 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_0_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_0_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_0_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_0_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_0_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 155268 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_0_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_0_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_0_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_0_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 155279 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_0_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_0_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_0_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_0_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 155291 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_0_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_0_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_0_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_0_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 155302 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_1_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_1_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_1_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_1_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_1_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 155313 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_1_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_1_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_1_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_1_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 155324 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_1_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_1_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_1_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_1_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 155336 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_1_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_1_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_1_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_1_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 155347 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_2_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_2_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_2_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_2_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_2_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 155359 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_2_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_2_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_2_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_2_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 155371 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_2_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_2_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_2_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_2_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 155384 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_2_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_2_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_2_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_2_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 155396 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_3_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_3_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_3_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_3_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_3_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 155408 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_3_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_3_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_3_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_3_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 155420 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_3_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_3_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_3_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_3_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 155433 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_3_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_3_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_3_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_3_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 155445 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_0_6_6_p6_rperr router_0_6_6_p6_rperr SPIO_NOC_ROUTER_0_6_6_P6_RPERR_ADDRESS SPIO_NOC_ROUTER_0_6_6_P6_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_P6_RPERR_OFFSET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 155737 R0_6 register p6_rperr 0x480E8 R/W 0x00000000 Spio_noc_router_0_6_6_p6_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 155489 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 155500 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 155511 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 155522 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_6_6_P6_RPERR_CR_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERR_CR_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_CR_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_CR_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERR_CR_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERR_CR_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 155533 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_6_6_P6_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 155544 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_0_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_0_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_0_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_0_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_0_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 155555 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_0_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_0_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_0_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_0_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 155566 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_0_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_0_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_0_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_0_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 155578 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_0_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_0_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_0_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_0_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 155589 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_1_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_1_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_1_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_1_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_1_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 155601 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_1_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_1_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_1_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_1_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 155613 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_1_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_1_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_1_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_1_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 155626 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_1_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_1_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_1_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_1_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 155638 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_2_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_2_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_2_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_2_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_2_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 155650 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_2_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_2_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_2_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_2_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 155662 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_2_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_2_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_2_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_2_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 155675 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_2_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_2_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_2_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_2_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 155687 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_3_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_3_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_3_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_3_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_3_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 155699 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_3_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_3_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_3_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_3_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 155711 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_3_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_3_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_3_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_3_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 155724 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_3_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_3_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_3_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_3_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 155736 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_0_6_6_p7_rperr router_0_6_6_p7_rperr SPIO_NOC_ROUTER_0_6_6_P7_RPERR_ADDRESS SPIO_NOC_ROUTER_0_6_6_P7_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_P7_RPERR_OFFSET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 156028 R0_6 register p7_rperr 0x480F0 R/W 0x00000000 Spio_noc_router_0_6_6_p7_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 155780 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 155791 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 155802 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 155813 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_6_6_P7_RPERR_CR_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERR_CR_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_CR_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_CR_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERR_CR_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERR_CR_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 155824 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_6_6_P7_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 155835 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_0_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_0_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_0_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_0_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_0_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 155846 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_0_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_0_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_0_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_0_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 155857 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_0_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_0_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_0_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_0_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 155869 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_0_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_0_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_0_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_0_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 155880 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_1_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_1_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_1_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_1_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_1_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 155892 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_1_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_1_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_1_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_1_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 155904 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_1_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_1_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_1_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_1_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 155917 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_1_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_1_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_1_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_1_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 155929 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_2_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_2_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_2_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_2_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_2_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 155941 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_2_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_2_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_2_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_2_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 155953 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_2_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_2_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_2_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_2_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 155966 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_2_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_2_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_2_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_2_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 155978 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_3_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_3_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_3_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_3_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_3_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 155990 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_3_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_3_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_3_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_3_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 156002 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_3_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_3_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_3_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_3_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 156015 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_3_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_3_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_3_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_3_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 156027 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_0_6_6_p0_rperrm router_0_6_6_p0_rperrm SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_ADDRESS SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_OFFSET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 156286 R0_6 register p0_rperrm 0x480F8 R/W 0x00000000 Spio_noc_router_0_6_6_p0_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 156050 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 156061 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 156072 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 156083 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_CR_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_CR_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_CR_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_CR_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_CR_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 156094 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 156105 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_0_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_0_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_0_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_0_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 156116 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_0_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 156127 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_0_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 156139 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_0_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 156150 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_1_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_1_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_1_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_1_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 156161 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_1_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 156172 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_1_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 156184 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_1_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 156195 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_2_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_2_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_2_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_2_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 156206 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_2_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 156217 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_2_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 156229 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_2_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 156240 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_3_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_3_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_3_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_3_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 156251 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_3_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 156262 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_3_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 156274 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_3_GET SPIO_NOC_ROUTER_0_6_6_P0_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 156285 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_0_6_6_p1_rperrm router_0_6_6_p1_rperrm SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_ADDRESS SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_OFFSET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 156544 R0_6 register p1_rperrm 0x48100 R/W 0x00000000 Spio_noc_router_0_6_6_p1_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 156308 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 156319 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 156330 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 156341 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_CR_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_CR_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_CR_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_CR_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_CR_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 156352 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 156363 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_0_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_0_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_0_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_0_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 156374 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_0_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 156385 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_0_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 156397 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_0_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 156408 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_1_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_1_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_1_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_1_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 156419 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_1_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 156430 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_1_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 156442 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_1_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 156453 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_2_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_2_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_2_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_2_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 156464 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_2_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 156475 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_2_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 156487 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_2_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 156498 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_3_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_3_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_3_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_3_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 156509 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_3_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 156520 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_3_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 156532 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_3_GET SPIO_NOC_ROUTER_0_6_6_P1_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 156543 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_0_6_6_p2_rperrm router_0_6_6_p2_rperrm SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_ADDRESS SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_OFFSET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 156802 R0_6 register p2_rperrm 0x48108 R/W 0x00000000 Spio_noc_router_0_6_6_p2_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 156566 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 156577 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 156588 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 156599 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_CR_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_CR_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_CR_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_CR_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_CR_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 156610 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 156621 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_0_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_0_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_0_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_0_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 156632 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_0_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 156643 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_0_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 156655 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_0_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 156666 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_1_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_1_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_1_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_1_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 156677 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_1_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 156688 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_1_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 156700 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_1_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 156711 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_2_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_2_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_2_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_2_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 156722 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_2_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 156733 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_2_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 156745 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_2_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 156756 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_3_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_3_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_3_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_3_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 156767 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_3_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 156778 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_3_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 156790 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_3_GET SPIO_NOC_ROUTER_0_6_6_P2_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 156801 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_0_6_6_p3_rperrm router_0_6_6_p3_rperrm SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_ADDRESS SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_OFFSET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 157060 R0_6 register p3_rperrm 0x48110 R/W 0x00000000 Spio_noc_router_0_6_6_p3_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 156824 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 156835 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 156846 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 156857 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_CR_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_CR_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_CR_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_CR_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_CR_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 156868 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 156879 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_0_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_0_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_0_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_0_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 156890 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_0_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 156901 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_0_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 156913 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_0_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 156924 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_1_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_1_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_1_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_1_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 156935 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_1_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 156946 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_1_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 156958 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_1_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 156969 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_2_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_2_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_2_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_2_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 156980 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_2_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 156991 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_2_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 157003 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_2_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 157014 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_3_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_3_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_3_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_3_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 157025 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_3_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 157036 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_3_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 157048 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_3_GET SPIO_NOC_ROUTER_0_6_6_P3_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 157059 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_0_6_6_p4_rperrm router_0_6_6_p4_rperrm SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_ADDRESS SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_OFFSET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 157318 R0_6 register p4_rperrm 0x48118 R/W 0x00000000 Spio_noc_router_0_6_6_p4_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 157082 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 157093 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 157104 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 157115 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_CR_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_CR_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_CR_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_CR_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_CR_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 157126 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 157137 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_0_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_0_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_0_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_0_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 157148 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_0_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 157159 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_0_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 157171 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_0_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 157182 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_1_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_1_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_1_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_1_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 157193 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_1_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 157204 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_1_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 157216 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_1_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 157227 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_2_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_2_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_2_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_2_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 157238 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_2_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 157249 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_2_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 157261 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_2_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 157272 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_3_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_3_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_3_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_3_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 157283 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_3_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 157294 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_3_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 157306 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_3_GET SPIO_NOC_ROUTER_0_6_6_P4_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 157317 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_0_6_6_p5_rperrm router_0_6_6_p5_rperrm SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_ADDRESS SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_OFFSET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 157576 R0_6 register p5_rperrm 0x48120 R/W 0x00000000 Spio_noc_router_0_6_6_p5_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 157340 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 157351 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 157362 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 157373 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_CR_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_CR_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_CR_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_CR_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_CR_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 157384 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 157395 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_0_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_0_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_0_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_0_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 157406 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_0_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 157417 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_0_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 157429 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_0_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 157440 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_1_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_1_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_1_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_1_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 157451 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_1_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 157462 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_1_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 157474 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_1_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 157485 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_2_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_2_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_2_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_2_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 157496 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_2_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 157507 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_2_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 157519 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_2_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 157530 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_3_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_3_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_3_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_3_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 157541 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_3_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 157552 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_3_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 157564 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_3_GET SPIO_NOC_ROUTER_0_6_6_P5_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 157575 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_0_6_6_p6_rperrm router_0_6_6_p6_rperrm SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_ADDRESS SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_OFFSET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 157834 R0_6 register p6_rperrm 0x48128 R/W 0x00000000 Spio_noc_router_0_6_6_p6_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 157598 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 157609 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 157620 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 157631 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_CR_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_CR_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_CR_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_CR_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_CR_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 157642 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 157653 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_0_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_0_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_0_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_0_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 157664 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_0_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 157675 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_0_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 157687 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_0_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 157698 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_1_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_1_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_1_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_1_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 157709 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_1_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 157720 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_1_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 157732 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_1_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 157743 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_2_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_2_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_2_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_2_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 157754 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_2_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 157765 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_2_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 157777 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_2_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 157788 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_3_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_3_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_3_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_3_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 157799 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_3_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 157810 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_3_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 157822 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_3_GET SPIO_NOC_ROUTER_0_6_6_P6_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 157833 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_0_6_6_p7_rperrm router_0_6_6_p7_rperrm SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_ADDRESS SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_OFFSET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 158092 R0_6 register p7_rperrm 0x48130 R/W 0x00000000 Spio_noc_router_0_6_6_p7_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 157856 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 157867 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 157878 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 157889 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_CR_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_CR_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_CR_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_CR_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_CR_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 157900 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 157911 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_0_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_0_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_0_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_0_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 157922 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_0_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 157933 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_0_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 157945 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_0_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 157956 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_1_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_1_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_1_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_1_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 157967 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_1_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 157978 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_1_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 157990 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_1_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 158001 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_2_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_2_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_2_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_2_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 158012 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_2_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 158023 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_2_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 158035 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_2_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 158046 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_3_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_3_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_3_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_3_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 158057 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_3_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 158068 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_3_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 158080 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_3_GET SPIO_NOC_ROUTER_0_6_6_P7_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 158091 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_0_6_6_roecc router_0_6_6_roecc SPIO_NOC_ROUTER_0_6_6_ROECC_ADDRESS SPIO_NOC_ROUTER_0_6_6_ROECC_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_ROECC_OFFSET SPIO_NOC_ROUTER_0_6_6_ROECC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 158165 R0_6 register roecc 0x48138 R/W 0x00000000 Spio_noc_router_0_6_6_roecc This register is used to select which hardware events will increment the output event counter. false false false false OVC SPIO_NOC_ROUTER_0_6_6_ROECC_OVC_WIDTH SPIO_NOC_ROUTER_0_6_6_ROECC_OVC_MSB SPIO_NOC_ROUTER_0_6_6_ROECC_OVC_LSB SPIO_NOC_ROUTER_0_6_6_ROECC_OVC_RANGE SPIO_NOC_ROUTER_0_6_6_ROECC_OVC_RESET SPIO_NOC_ROUTER_0_6_6_ROECC_OVC_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROECC_OVC_GET SPIO_NOC_ROUTER_0_6_6_ROECC_OVC_SET ns_noc_io_spio_soc_ip.csr 158110 OVC Bit map to select output VCs to monitor events on 3 0 0x0 R/W OP SPIO_NOC_ROUTER_0_6_6_ROECC_OP_WIDTH SPIO_NOC_ROUTER_0_6_6_ROECC_OP_MSB SPIO_NOC_ROUTER_0_6_6_ROECC_OP_LSB SPIO_NOC_ROUTER_0_6_6_ROECC_OP_RANGE SPIO_NOC_ROUTER_0_6_6_ROECC_OP_RESET SPIO_NOC_ROUTER_0_6_6_ROECC_OP_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROECC_OP_GET SPIO_NOC_ROUTER_0_6_6_ROECC_OP_SET ns_noc_io_spio_soc_ip.csr 158121 OP Output port on which the event is captured 6 4 0x0 R/W UNSD_7_7 SPIO_NOC_ROUTER_0_6_6_ROECC_UNSD_7_7_WIDTH SPIO_NOC_ROUTER_0_6_6_ROECC_UNSD_7_7_MSB SPIO_NOC_ROUTER_0_6_6_ROECC_UNSD_7_7_LSB SPIO_NOC_ROUTER_0_6_6_ROECC_UNSD_7_7_RANGE SPIO_NOC_ROUTER_0_6_6_ROECC_UNSD_7_7_RESET SPIO_NOC_ROUTER_0_6_6_ROECC_UNSD_7_7_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROECC_UNSD_7_7_GET SPIO_NOC_ROUTER_0_6_6_ROECC_UNSD_7_7_SET ns_noc_io_spio_soc_ip.csr 158132 UNSD_7_7 7 7 0x0 R EVT SPIO_NOC_ROUTER_0_6_6_ROECC_EVT_WIDTH SPIO_NOC_ROUTER_0_6_6_ROECC_EVT_MSB SPIO_NOC_ROUTER_0_6_6_ROECC_EVT_LSB SPIO_NOC_ROUTER_0_6_6_ROECC_EVT_RANGE SPIO_NOC_ROUTER_0_6_6_ROECC_EVT_RESET SPIO_NOC_ROUTER_0_6_6_ROECC_EVT_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROECC_EVT_GET SPIO_NOC_ROUTER_0_6_6_ROECC_EVT_SET ns_noc_io_spio_soc_ip.csr 158153 EVT 100: Port stalled. Input flits are available for the port, but no output VC has credit 011: Generates count event when flits are available to be sent to output VC, but the VC has no credit 010: Generates count event on every flit sent on the selected output port and selected outpt VCs, this can be used to count total flits sent on a router output port 001: Generates count event on every EOP sent on the selected output port and selected output VCs, this can be used to count packets sent on a router output port 000: Disable 10 8 0x0 R/W UNSD_31_11 SPIO_NOC_ROUTER_0_6_6_ROECC_UNSD_31_11_WIDTH SPIO_NOC_ROUTER_0_6_6_ROECC_UNSD_31_11_MSB SPIO_NOC_ROUTER_0_6_6_ROECC_UNSD_31_11_LSB SPIO_NOC_ROUTER_0_6_6_ROECC_UNSD_31_11_RANGE SPIO_NOC_ROUTER_0_6_6_ROECC_UNSD_31_11_RESET SPIO_NOC_ROUTER_0_6_6_ROECC_UNSD_31_11_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROECC_UNSD_31_11_GET SPIO_NOC_ROUTER_0_6_6_ROECC_UNSD_31_11_SET ns_noc_io_spio_soc_ip.csr 158164 UNSD_31_11 31 11 0x000000 R register spio_noc.router_0_6_6_roec router_0_6_6_roec SPIO_NOC_ROUTER_0_6_6_ROEC_ADDRESS SPIO_NOC_ROUTER_0_6_6_ROEC_BYTE_ADDRESS SPIO_NOC_ROUTER_0_6_6_ROEC_OFFSET SPIO_NOC_ROUTER_0_6_6_ROEC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 158190 R0_6 register roec 0x48140 R/W 0x00000000 Spio_noc_router_0_6_6_roec This register holds the output event counter. The value can be read to determine the current count value. The value can be written to initialize the counter. When events trigger a count, the counter will increment. When the counter increments at its highest value, it will roll over to zero and the overflow will mark the Router output Event Interrupt Status register, which could trigger an interrupt. false false false false EVENT_CNTR SPIO_NOC_ROUTER_0_6_6_ROEC_EVENT_CNTR_WIDTH SPIO_NOC_ROUTER_0_6_6_ROEC_EVENT_CNTR_MSB SPIO_NOC_ROUTER_0_6_6_ROEC_EVENT_CNTR_LSB SPIO_NOC_ROUTER_0_6_6_ROEC_EVENT_CNTR_RANGE SPIO_NOC_ROUTER_0_6_6_ROEC_EVENT_CNTR_RESET SPIO_NOC_ROUTER_0_6_6_ROEC_EVENT_CNTR_FIELD_MASK SPIO_NOC_ROUTER_0_6_6_ROEC_EVENT_CNTR_GET SPIO_NOC_ROUTER_0_6_6_ROEC_EVENT_CNTR_SET ns_noc_io_spio_soc_ip.csr 158189 EVENT_CNTR 32'bit event incrementing counter. Rollover from 32'hFFFFF -> 32'd0 sets the rollover status bit RE 31 0 0x00000000 R/W register spio_noc.router_0_7_7_rivcs_h router_0_7_7_rivcs_h SPIO_NOC_ROUTER_0_7_7_RIVCS_H_ADDRESS SPIO_NOC_ROUTER_0_7_7_RIVCS_H_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OFFSET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 158519 R0_7 register rivcs_h 0x4C000 R 0x00000000 Spio_noc_router_0_7_7_rivcs_h This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 158215 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_0_SET ns_noc_io_spio_soc_ip.csr 158229 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_0_SET ns_noc_io_spio_soc_ip.csr 158245 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_0_SET ns_noc_io_spio_soc_ip.csr 158259 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_0_SET ns_noc_io_spio_soc_ip.csr 158270 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_0_SET ns_noc_io_spio_soc_ip.csr 158281 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 158294 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_1_SET ns_noc_io_spio_soc_ip.csr 158308 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_1_SET ns_noc_io_spio_soc_ip.csr 158324 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_1_SET ns_noc_io_spio_soc_ip.csr 158338 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_1_SET ns_noc_io_spio_soc_ip.csr 158349 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_1_SET ns_noc_io_spio_soc_ip.csr 158360 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 158373 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_2_SET ns_noc_io_spio_soc_ip.csr 158387 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_2_SET ns_noc_io_spio_soc_ip.csr 158403 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_2_SET ns_noc_io_spio_soc_ip.csr 158417 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_2_SET ns_noc_io_spio_soc_ip.csr 158428 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_2_SET ns_noc_io_spio_soc_ip.csr 158439 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 158452 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_UP_3_SET ns_noc_io_spio_soc_ip.csr 158466 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_S_3_SET ns_noc_io_spio_soc_ip.csr 158482 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_B_3_SET ns_noc_io_spio_soc_ip.csr 158496 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_F_3_SET ns_noc_io_spio_soc_ip.csr 158507 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_H_V_3_SET ns_noc_io_spio_soc_ip.csr 158518 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_0_7_7_rivcs_e router_0_7_7_rivcs_e SPIO_NOC_ROUTER_0_7_7_RIVCS_E_ADDRESS SPIO_NOC_ROUTER_0_7_7_RIVCS_E_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OFFSET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 158848 R0_7 register rivcs_e 0x4C008 R 0x00000000 Spio_noc_router_0_7_7_rivcs_e This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 158544 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_0_SET ns_noc_io_spio_soc_ip.csr 158558 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_0_SET ns_noc_io_spio_soc_ip.csr 158574 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_0_SET ns_noc_io_spio_soc_ip.csr 158588 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_0_SET ns_noc_io_spio_soc_ip.csr 158599 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_0_SET ns_noc_io_spio_soc_ip.csr 158610 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 158623 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_1_SET ns_noc_io_spio_soc_ip.csr 158637 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_1_SET ns_noc_io_spio_soc_ip.csr 158653 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_1_SET ns_noc_io_spio_soc_ip.csr 158667 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_1_SET ns_noc_io_spio_soc_ip.csr 158678 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_1_SET ns_noc_io_spio_soc_ip.csr 158689 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 158702 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_2_SET ns_noc_io_spio_soc_ip.csr 158716 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_2_SET ns_noc_io_spio_soc_ip.csr 158732 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_2_SET ns_noc_io_spio_soc_ip.csr 158746 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_2_SET ns_noc_io_spio_soc_ip.csr 158757 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_2_SET ns_noc_io_spio_soc_ip.csr 158768 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 158781 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_UP_3_SET ns_noc_io_spio_soc_ip.csr 158795 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_S_3_SET ns_noc_io_spio_soc_ip.csr 158811 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_B_3_SET ns_noc_io_spio_soc_ip.csr 158825 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_F_3_SET ns_noc_io_spio_soc_ip.csr 158836 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_E_V_3_SET ns_noc_io_spio_soc_ip.csr 158847 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_0_7_7_rivcs_w router_0_7_7_rivcs_w SPIO_NOC_ROUTER_0_7_7_RIVCS_W_ADDRESS SPIO_NOC_ROUTER_0_7_7_RIVCS_W_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OFFSET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 159177 R0_7 register rivcs_w 0x4C018 R 0x00000000 Spio_noc_router_0_7_7_rivcs_w This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 158873 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_0_SET ns_noc_io_spio_soc_ip.csr 158887 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_0_SET ns_noc_io_spio_soc_ip.csr 158903 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_0_SET ns_noc_io_spio_soc_ip.csr 158917 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_0_SET ns_noc_io_spio_soc_ip.csr 158928 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_0_SET ns_noc_io_spio_soc_ip.csr 158939 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 158952 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_1_SET ns_noc_io_spio_soc_ip.csr 158966 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_1_SET ns_noc_io_spio_soc_ip.csr 158982 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_1_SET ns_noc_io_spio_soc_ip.csr 158996 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_1_SET ns_noc_io_spio_soc_ip.csr 159007 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_1_SET ns_noc_io_spio_soc_ip.csr 159018 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 159031 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_2_SET ns_noc_io_spio_soc_ip.csr 159045 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_2_SET ns_noc_io_spio_soc_ip.csr 159061 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_2_SET ns_noc_io_spio_soc_ip.csr 159075 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_2_SET ns_noc_io_spio_soc_ip.csr 159086 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_2_SET ns_noc_io_spio_soc_ip.csr 159097 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 159110 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_UP_3_SET ns_noc_io_spio_soc_ip.csr 159124 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_S_3_SET ns_noc_io_spio_soc_ip.csr 159140 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_B_3_SET ns_noc_io_spio_soc_ip.csr 159154 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_F_3_SET ns_noc_io_spio_soc_ip.csr 159165 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_W_V_3_SET ns_noc_io_spio_soc_ip.csr 159176 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_0_7_7_rivcs_n router_0_7_7_rivcs_n SPIO_NOC_ROUTER_0_7_7_RIVCS_N_ADDRESS SPIO_NOC_ROUTER_0_7_7_RIVCS_N_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OFFSET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 159506 R0_7 register rivcs_n 0x4C020 R 0x00000000 Spio_noc_router_0_7_7_rivcs_n This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 159202 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_0_SET ns_noc_io_spio_soc_ip.csr 159216 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_0_SET ns_noc_io_spio_soc_ip.csr 159232 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_0_SET ns_noc_io_spio_soc_ip.csr 159246 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_0_SET ns_noc_io_spio_soc_ip.csr 159257 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_0_SET ns_noc_io_spio_soc_ip.csr 159268 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 159281 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_1_SET ns_noc_io_spio_soc_ip.csr 159295 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_1_SET ns_noc_io_spio_soc_ip.csr 159311 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_1_SET ns_noc_io_spio_soc_ip.csr 159325 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_1_SET ns_noc_io_spio_soc_ip.csr 159336 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_1_SET ns_noc_io_spio_soc_ip.csr 159347 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 159360 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_2_SET ns_noc_io_spio_soc_ip.csr 159374 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_2_SET ns_noc_io_spio_soc_ip.csr 159390 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_2_SET ns_noc_io_spio_soc_ip.csr 159404 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_2_SET ns_noc_io_spio_soc_ip.csr 159415 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_2_SET ns_noc_io_spio_soc_ip.csr 159426 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 159439 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_UP_3_SET ns_noc_io_spio_soc_ip.csr 159453 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_S_3_SET ns_noc_io_spio_soc_ip.csr 159469 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_B_3_SET ns_noc_io_spio_soc_ip.csr 159483 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_F_3_SET ns_noc_io_spio_soc_ip.csr 159494 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_N_V_3_SET ns_noc_io_spio_soc_ip.csr 159505 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_0_7_7_rivcs_i router_0_7_7_rivcs_i SPIO_NOC_ROUTER_0_7_7_RIVCS_I_ADDRESS SPIO_NOC_ROUTER_0_7_7_RIVCS_I_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OFFSET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 159835 R0_7 register rivcs_i 0x4C028 R 0x00000000 Spio_noc_router_0_7_7_rivcs_i This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 159531 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_0_SET ns_noc_io_spio_soc_ip.csr 159545 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_0_SET ns_noc_io_spio_soc_ip.csr 159561 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_0_SET ns_noc_io_spio_soc_ip.csr 159575 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_0_SET ns_noc_io_spio_soc_ip.csr 159586 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_0_SET ns_noc_io_spio_soc_ip.csr 159597 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 159610 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_1_SET ns_noc_io_spio_soc_ip.csr 159624 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_1_SET ns_noc_io_spio_soc_ip.csr 159640 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_1_SET ns_noc_io_spio_soc_ip.csr 159654 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_1_SET ns_noc_io_spio_soc_ip.csr 159665 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_1_SET ns_noc_io_spio_soc_ip.csr 159676 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 159689 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_2_SET ns_noc_io_spio_soc_ip.csr 159703 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_2_SET ns_noc_io_spio_soc_ip.csr 159719 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_2_SET ns_noc_io_spio_soc_ip.csr 159733 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_2_SET ns_noc_io_spio_soc_ip.csr 159744 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_2_SET ns_noc_io_spio_soc_ip.csr 159755 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 159768 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_UP_3_SET ns_noc_io_spio_soc_ip.csr 159782 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_S_3_SET ns_noc_io_spio_soc_ip.csr 159798 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_B_3_SET ns_noc_io_spio_soc_ip.csr 159812 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_F_3_SET ns_noc_io_spio_soc_ip.csr 159823 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_I_V_3_SET ns_noc_io_spio_soc_ip.csr 159834 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_0_7_7_rivcs_j router_0_7_7_rivcs_j SPIO_NOC_ROUTER_0_7_7_RIVCS_J_ADDRESS SPIO_NOC_ROUTER_0_7_7_RIVCS_J_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OFFSET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 160164 R0_7 register rivcs_j 0x4C030 R 0x00000000 Spio_noc_router_0_7_7_rivcs_j This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 159860 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_0_SET ns_noc_io_spio_soc_ip.csr 159874 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_0_SET ns_noc_io_spio_soc_ip.csr 159890 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_0_SET ns_noc_io_spio_soc_ip.csr 159904 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_0_SET ns_noc_io_spio_soc_ip.csr 159915 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_0_SET ns_noc_io_spio_soc_ip.csr 159926 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 159939 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_1_SET ns_noc_io_spio_soc_ip.csr 159953 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_1_SET ns_noc_io_spio_soc_ip.csr 159969 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_1_SET ns_noc_io_spio_soc_ip.csr 159983 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_1_SET ns_noc_io_spio_soc_ip.csr 159994 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_1_SET ns_noc_io_spio_soc_ip.csr 160005 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 160018 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_2_SET ns_noc_io_spio_soc_ip.csr 160032 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_2_SET ns_noc_io_spio_soc_ip.csr 160048 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_2_SET ns_noc_io_spio_soc_ip.csr 160062 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_2_SET ns_noc_io_spio_soc_ip.csr 160073 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_2_SET ns_noc_io_spio_soc_ip.csr 160084 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 160097 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_UP_3_SET ns_noc_io_spio_soc_ip.csr 160111 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_S_3_SET ns_noc_io_spio_soc_ip.csr 160127 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_B_3_SET ns_noc_io_spio_soc_ip.csr 160141 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_F_3_SET ns_noc_io_spio_soc_ip.csr 160152 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_J_V_3_SET ns_noc_io_spio_soc_ip.csr 160163 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_0_7_7_rivcs_k router_0_7_7_rivcs_k SPIO_NOC_ROUTER_0_7_7_RIVCS_K_ADDRESS SPIO_NOC_ROUTER_0_7_7_RIVCS_K_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OFFSET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 160493 R0_7 register rivcs_k 0x4C038 R 0x00000000 Spio_noc_router_0_7_7_rivcs_k This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 160189 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_0_SET ns_noc_io_spio_soc_ip.csr 160203 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_0_SET ns_noc_io_spio_soc_ip.csr 160219 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_0_SET ns_noc_io_spio_soc_ip.csr 160233 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_0_SET ns_noc_io_spio_soc_ip.csr 160244 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_0_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_0_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_0_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_0_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_0_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_0_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_0_SET ns_noc_io_spio_soc_ip.csr 160255 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 160268 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_1_SET ns_noc_io_spio_soc_ip.csr 160282 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_1_SET ns_noc_io_spio_soc_ip.csr 160298 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_1_SET ns_noc_io_spio_soc_ip.csr 160312 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_1_SET ns_noc_io_spio_soc_ip.csr 160323 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_1_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_1_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_1_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_1_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_1_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_1_SET ns_noc_io_spio_soc_ip.csr 160334 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 160347 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_2_SET ns_noc_io_spio_soc_ip.csr 160361 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_2_SET ns_noc_io_spio_soc_ip.csr 160377 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_2_SET ns_noc_io_spio_soc_ip.csr 160391 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_2_SET ns_noc_io_spio_soc_ip.csr 160402 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_2_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_2_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_2_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_2_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_2_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_2_SET ns_noc_io_spio_soc_ip.csr 160413 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 160426 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_UP_3_SET ns_noc_io_spio_soc_ip.csr 160440 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_S_3_SET ns_noc_io_spio_soc_ip.csr 160456 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_B_3_SET ns_noc_io_spio_soc_ip.csr 160470 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_F_3_SET ns_noc_io_spio_soc_ip.csr 160481 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_3_MSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_3_LSB SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_3_RANGE SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_3_RESET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_3_GET SPIO_NOC_ROUTER_0_7_7_RIVCS_K_V_3_SET ns_noc_io_spio_soc_ip.csr 160492 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_0_7_7_rovcs_h router_0_7_7_rovcs_h SPIO_NOC_ROUTER_0_7_7_ROVCS_H_ADDRESS SPIO_NOC_ROUTER_0_7_7_ROVCS_H_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_ROVCS_H_OFFSET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 160754 R0_7 register rovcs_h 0x4C040 R 0x00000001 Spio_noc_router_0_7_7_rovcs_h This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_0_SET ns_noc_io_spio_soc_ip.csr 160517 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_0_SET ns_noc_io_spio_soc_ip.csr 160531 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_0_SET ns_noc_io_spio_soc_ip.csr 160546 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_0_SET ns_noc_io_spio_soc_ip.csr 160557 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 160567 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_1_SET ns_noc_io_spio_soc_ip.csr 160579 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_1_SET ns_noc_io_spio_soc_ip.csr 160593 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_1_SET ns_noc_io_spio_soc_ip.csr 160608 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_1_SET ns_noc_io_spio_soc_ip.csr 160619 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 160629 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_2_SET ns_noc_io_spio_soc_ip.csr 160641 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_2_SET ns_noc_io_spio_soc_ip.csr 160655 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_2_SET ns_noc_io_spio_soc_ip.csr 160670 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_2_SET ns_noc_io_spio_soc_ip.csr 160681 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 160691 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CF_3_SET ns_noc_io_spio_soc_ip.csr 160703 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_CE_3_SET ns_noc_io_spio_soc_ip.csr 160717 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_VB_3_SET ns_noc_io_spio_soc_ip.csr 160732 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_RSV_3_SET ns_noc_io_spio_soc_ip.csr 160743 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_H_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 160753 UNSD_3 31 28 0x0 R register spio_noc.router_0_7_7_rovcs_e router_0_7_7_rovcs_e SPIO_NOC_ROUTER_0_7_7_ROVCS_E_ADDRESS SPIO_NOC_ROUTER_0_7_7_ROVCS_E_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_ROVCS_E_OFFSET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 161015 R0_7 register rovcs_e 0x4C048 R 0x00000101 Spio_noc_router_0_7_7_rovcs_e This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_0_SET ns_noc_io_spio_soc_ip.csr 160778 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_0_SET ns_noc_io_spio_soc_ip.csr 160792 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_0_SET ns_noc_io_spio_soc_ip.csr 160807 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_0_SET ns_noc_io_spio_soc_ip.csr 160818 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 160828 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_1_SET ns_noc_io_spio_soc_ip.csr 160840 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x1 R CE_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_1_SET ns_noc_io_spio_soc_ip.csr 160854 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_1_SET ns_noc_io_spio_soc_ip.csr 160869 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_1_SET ns_noc_io_spio_soc_ip.csr 160880 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 160890 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_2_SET ns_noc_io_spio_soc_ip.csr 160902 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_2_SET ns_noc_io_spio_soc_ip.csr 160916 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_2_SET ns_noc_io_spio_soc_ip.csr 160931 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_2_SET ns_noc_io_spio_soc_ip.csr 160942 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 160952 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CF_3_SET ns_noc_io_spio_soc_ip.csr 160964 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_CE_3_SET ns_noc_io_spio_soc_ip.csr 160978 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_VB_3_SET ns_noc_io_spio_soc_ip.csr 160993 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_RSV_3_SET ns_noc_io_spio_soc_ip.csr 161004 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_E_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 161014 UNSD_3 31 28 0x0 R register spio_noc.router_0_7_7_rovcs_w router_0_7_7_rovcs_w SPIO_NOC_ROUTER_0_7_7_ROVCS_W_ADDRESS SPIO_NOC_ROUTER_0_7_7_ROVCS_W_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_ROVCS_W_OFFSET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 161276 R0_7 register rovcs_w 0x4C058 R 0x00000001 Spio_noc_router_0_7_7_rovcs_w This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_0_SET ns_noc_io_spio_soc_ip.csr 161039 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_0_SET ns_noc_io_spio_soc_ip.csr 161053 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_0_SET ns_noc_io_spio_soc_ip.csr 161068 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_0_SET ns_noc_io_spio_soc_ip.csr 161079 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 161089 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_1_SET ns_noc_io_spio_soc_ip.csr 161101 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_1_SET ns_noc_io_spio_soc_ip.csr 161115 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_1_SET ns_noc_io_spio_soc_ip.csr 161130 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_1_SET ns_noc_io_spio_soc_ip.csr 161141 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 161151 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_2_SET ns_noc_io_spio_soc_ip.csr 161163 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_2_SET ns_noc_io_spio_soc_ip.csr 161177 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_2_SET ns_noc_io_spio_soc_ip.csr 161192 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_2_SET ns_noc_io_spio_soc_ip.csr 161203 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 161213 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CF_3_SET ns_noc_io_spio_soc_ip.csr 161225 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_CE_3_SET ns_noc_io_spio_soc_ip.csr 161239 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_VB_3_SET ns_noc_io_spio_soc_ip.csr 161254 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_RSV_3_SET ns_noc_io_spio_soc_ip.csr 161265 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_W_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 161275 UNSD_3 31 28 0x0 R register spio_noc.router_0_7_7_rovcs_n router_0_7_7_rovcs_n SPIO_NOC_ROUTER_0_7_7_ROVCS_N_ADDRESS SPIO_NOC_ROUTER_0_7_7_ROVCS_N_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_ROVCS_N_OFFSET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 161537 R0_7 register rovcs_n 0x4C060 R 0x00000101 Spio_noc_router_0_7_7_rovcs_n This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_0_SET ns_noc_io_spio_soc_ip.csr 161300 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_0_SET ns_noc_io_spio_soc_ip.csr 161314 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_0_SET ns_noc_io_spio_soc_ip.csr 161329 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_0_SET ns_noc_io_spio_soc_ip.csr 161340 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 161350 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_1_SET ns_noc_io_spio_soc_ip.csr 161362 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x1 R CE_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_1_SET ns_noc_io_spio_soc_ip.csr 161376 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_1_SET ns_noc_io_spio_soc_ip.csr 161391 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_1_SET ns_noc_io_spio_soc_ip.csr 161402 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 161412 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_2_SET ns_noc_io_spio_soc_ip.csr 161424 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_2_SET ns_noc_io_spio_soc_ip.csr 161438 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_2_SET ns_noc_io_spio_soc_ip.csr 161453 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_2_SET ns_noc_io_spio_soc_ip.csr 161464 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 161474 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CF_3_SET ns_noc_io_spio_soc_ip.csr 161486 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_CE_3_SET ns_noc_io_spio_soc_ip.csr 161500 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_VB_3_SET ns_noc_io_spio_soc_ip.csr 161515 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_RSV_3_SET ns_noc_io_spio_soc_ip.csr 161526 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_N_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 161536 UNSD_3 31 28 0x0 R register spio_noc.router_0_7_7_rovcs_i router_0_7_7_rovcs_i SPIO_NOC_ROUTER_0_7_7_ROVCS_I_ADDRESS SPIO_NOC_ROUTER_0_7_7_ROVCS_I_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_ROVCS_I_OFFSET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 161798 R0_7 register rovcs_i 0x4C068 R 0x00000101 Spio_noc_router_0_7_7_rovcs_i This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_0_SET ns_noc_io_spio_soc_ip.csr 161561 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_0_SET ns_noc_io_spio_soc_ip.csr 161575 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_0_SET ns_noc_io_spio_soc_ip.csr 161590 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_0_SET ns_noc_io_spio_soc_ip.csr 161601 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 161611 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_1_SET ns_noc_io_spio_soc_ip.csr 161623 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x1 R CE_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_1_SET ns_noc_io_spio_soc_ip.csr 161637 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_1_SET ns_noc_io_spio_soc_ip.csr 161652 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_1_SET ns_noc_io_spio_soc_ip.csr 161663 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 161673 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_2_SET ns_noc_io_spio_soc_ip.csr 161685 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_2_SET ns_noc_io_spio_soc_ip.csr 161699 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_2_SET ns_noc_io_spio_soc_ip.csr 161714 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_2_SET ns_noc_io_spio_soc_ip.csr 161725 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 161735 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CF_3_SET ns_noc_io_spio_soc_ip.csr 161747 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_CE_3_SET ns_noc_io_spio_soc_ip.csr 161761 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_VB_3_SET ns_noc_io_spio_soc_ip.csr 161776 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_RSV_3_SET ns_noc_io_spio_soc_ip.csr 161787 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_I_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 161797 UNSD_3 31 28 0x0 R register spio_noc.router_0_7_7_rovcs_j router_0_7_7_rovcs_j SPIO_NOC_ROUTER_0_7_7_ROVCS_J_ADDRESS SPIO_NOC_ROUTER_0_7_7_ROVCS_J_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_ROVCS_J_OFFSET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 162059 R0_7 register rovcs_j 0x4C070 R 0x00000001 Spio_noc_router_0_7_7_rovcs_j This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_0_SET ns_noc_io_spio_soc_ip.csr 161822 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_0_SET ns_noc_io_spio_soc_ip.csr 161836 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_0_SET ns_noc_io_spio_soc_ip.csr 161851 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_0_SET ns_noc_io_spio_soc_ip.csr 161862 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 161872 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_1_SET ns_noc_io_spio_soc_ip.csr 161884 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_1_SET ns_noc_io_spio_soc_ip.csr 161898 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_1_SET ns_noc_io_spio_soc_ip.csr 161913 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_1_SET ns_noc_io_spio_soc_ip.csr 161924 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 161934 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_2_SET ns_noc_io_spio_soc_ip.csr 161946 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_2_SET ns_noc_io_spio_soc_ip.csr 161960 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_2_SET ns_noc_io_spio_soc_ip.csr 161975 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_2_SET ns_noc_io_spio_soc_ip.csr 161986 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 161996 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CF_3_SET ns_noc_io_spio_soc_ip.csr 162008 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_CE_3_SET ns_noc_io_spio_soc_ip.csr 162022 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_VB_3_SET ns_noc_io_spio_soc_ip.csr 162037 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_RSV_3_SET ns_noc_io_spio_soc_ip.csr 162048 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_J_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 162058 UNSD_3 31 28 0x0 R register spio_noc.router_0_7_7_rovcs_k router_0_7_7_rovcs_k SPIO_NOC_ROUTER_0_7_7_ROVCS_K_ADDRESS SPIO_NOC_ROUTER_0_7_7_ROVCS_K_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_ROVCS_K_OFFSET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 162320 R0_7 register rovcs_k 0x4C078 R 0x00000001 Spio_noc_router_0_7_7_rovcs_k This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_0_SET ns_noc_io_spio_soc_ip.csr 162083 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_0_SET ns_noc_io_spio_soc_ip.csr 162097 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_0_SET ns_noc_io_spio_soc_ip.csr 162112 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_0_SET ns_noc_io_spio_soc_ip.csr 162123 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_0_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_0_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_0_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_0_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_0_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_0_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 162133 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_1_SET ns_noc_io_spio_soc_ip.csr 162145 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_1_SET ns_noc_io_spio_soc_ip.csr 162159 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_1_SET ns_noc_io_spio_soc_ip.csr 162174 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_1_SET ns_noc_io_spio_soc_ip.csr 162185 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_1_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_1_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_1_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_1_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_1_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_1_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 162195 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_2_SET ns_noc_io_spio_soc_ip.csr 162207 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_2_SET ns_noc_io_spio_soc_ip.csr 162221 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_2_SET ns_noc_io_spio_soc_ip.csr 162236 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_2_SET ns_noc_io_spio_soc_ip.csr 162247 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_2_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_2_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_2_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_2_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_2_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_2_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 162257 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CF_3_SET ns_noc_io_spio_soc_ip.csr 162269 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_CE_3_SET ns_noc_io_spio_soc_ip.csr 162283 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_VB_3_SET ns_noc_io_spio_soc_ip.csr 162298 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_RSV_3_SET ns_noc_io_spio_soc_ip.csr 162309 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_3_WIDTH SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_3_MSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_3_LSB SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_3_RANGE SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_3_RESET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_3_GET SPIO_NOC_ROUTER_0_7_7_ROVCS_K_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 162319 UNSD_3 31 28 0x0 R register spio_noc.router_0_7_7_re router_0_7_7_re SPIO_NOC_ROUTER_0_7_7_RE_ADDRESS SPIO_NOC_ROUTER_0_7_7_RE_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_RE_OFFSET SPIO_NOC_ROUTER_0_7_7_RE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 162494 R0_7 register re 0x4C080 R/W 0x00000000 Spio_noc_router_0_7_7_re This register tracks the interrupt or error events that can occur in the router. The only interrupt event is the event counter overflow. This register is readable, and can be cleared by performing a write with the write data bits set to 0 for the bits that should be cleared. false false false false OVFI SPIO_NOC_ROUTER_0_7_7_RE_OVFI_WIDTH SPIO_NOC_ROUTER_0_7_7_RE_OVFI_MSB SPIO_NOC_ROUTER_0_7_7_RE_OVFI_LSB SPIO_NOC_ROUTER_0_7_7_RE_OVFI_RANGE SPIO_NOC_ROUTER_0_7_7_RE_OVFI_RESET SPIO_NOC_ROUTER_0_7_7_RE_OVFI_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RE_OVFI_GET SPIO_NOC_ROUTER_0_7_7_RE_OVFI_SET ns_noc_io_spio_soc_ip.csr 162346 OVFI 1'b1: In this status bit indicates that the router input event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 0 0 0x0 R/W CSR_PARERR SPIO_NOC_ROUTER_0_7_7_RE_CSR_PARERR_WIDTH SPIO_NOC_ROUTER_0_7_7_RE_CSR_PARERR_MSB SPIO_NOC_ROUTER_0_7_7_RE_CSR_PARERR_LSB SPIO_NOC_ROUTER_0_7_7_RE_CSR_PARERR_RANGE SPIO_NOC_ROUTER_0_7_7_RE_CSR_PARERR_RESET SPIO_NOC_ROUTER_0_7_7_RE_CSR_PARERR_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RE_CSR_PARERR_GET SPIO_NOC_ROUTER_0_7_7_RE_CSR_PARERR_SET ns_noc_io_spio_soc_ip.csr 162357 CSR_PARERR 1'b1: Parity error in config/status registers 1 1 0x0 R/W OVFO SPIO_NOC_ROUTER_0_7_7_RE_OVFO_WIDTH SPIO_NOC_ROUTER_0_7_7_RE_OVFO_MSB SPIO_NOC_ROUTER_0_7_7_RE_OVFO_LSB SPIO_NOC_ROUTER_0_7_7_RE_OVFO_RANGE SPIO_NOC_ROUTER_0_7_7_RE_OVFO_RESET SPIO_NOC_ROUTER_0_7_7_RE_OVFO_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RE_OVFO_GET SPIO_NOC_ROUTER_0_7_7_RE_OVFO_SET ns_noc_io_spio_soc_ip.csr 162371 OVFO 1'b1: In this status bit indicates that the router output event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 2 2 0x0 R/W UNSD_7_3 SPIO_NOC_ROUTER_0_7_7_RE_UNSD_7_3_WIDTH SPIO_NOC_ROUTER_0_7_7_RE_UNSD_7_3_MSB SPIO_NOC_ROUTER_0_7_7_RE_UNSD_7_3_LSB SPIO_NOC_ROUTER_0_7_7_RE_UNSD_7_3_RANGE SPIO_NOC_ROUTER_0_7_7_RE_UNSD_7_3_RESET SPIO_NOC_ROUTER_0_7_7_RE_UNSD_7_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RE_UNSD_7_3_GET SPIO_NOC_ROUTER_0_7_7_RE_UNSD_7_3_SET ns_noc_io_spio_soc_ip.csr 162382 UNSD_7_3 7 3 0x00 R PGE SPIO_NOC_ROUTER_0_7_7_RE_PGE_WIDTH SPIO_NOC_ROUTER_0_7_7_RE_PGE_MSB SPIO_NOC_ROUTER_0_7_7_RE_PGE_LSB SPIO_NOC_ROUTER_0_7_7_RE_PGE_RANGE SPIO_NOC_ROUTER_0_7_7_RE_PGE_RESET SPIO_NOC_ROUTER_0_7_7_RE_PGE_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RE_PGE_GET SPIO_NOC_ROUTER_0_7_7_RE_PGE_SET ns_noc_io_spio_soc_ip.csr 162394 PGE 1'b1: Power gating error, traffic received after router commited to power down 8 8 0x0 R/W NLU SPIO_NOC_ROUTER_0_7_7_RE_NLU_WIDTH SPIO_NOC_ROUTER_0_7_7_RE_NLU_MSB SPIO_NOC_ROUTER_0_7_7_RE_NLU_LSB SPIO_NOC_ROUTER_0_7_7_RE_NLU_RANGE SPIO_NOC_ROUTER_0_7_7_RE_NLU_RESET SPIO_NOC_ROUTER_0_7_7_RE_NLU_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RE_NLU_GET SPIO_NOC_ROUTER_0_7_7_RE_NLU_SET ns_noc_io_spio_soc_ip.csr 162405 NLU 1'b1: Traffic destined for North link which is unavailable 9 9 0x0 R/W ELU SPIO_NOC_ROUTER_0_7_7_RE_ELU_WIDTH SPIO_NOC_ROUTER_0_7_7_RE_ELU_MSB SPIO_NOC_ROUTER_0_7_7_RE_ELU_LSB SPIO_NOC_ROUTER_0_7_7_RE_ELU_RANGE SPIO_NOC_ROUTER_0_7_7_RE_ELU_RESET SPIO_NOC_ROUTER_0_7_7_RE_ELU_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RE_ELU_GET SPIO_NOC_ROUTER_0_7_7_RE_ELU_SET ns_noc_io_spio_soc_ip.csr 162416 ELU 1'b1: Traffic destined for East link which is unavailable 10 10 0x0 R/W WLU SPIO_NOC_ROUTER_0_7_7_RE_WLU_WIDTH SPIO_NOC_ROUTER_0_7_7_RE_WLU_MSB SPIO_NOC_ROUTER_0_7_7_RE_WLU_LSB SPIO_NOC_ROUTER_0_7_7_RE_WLU_RANGE SPIO_NOC_ROUTER_0_7_7_RE_WLU_RESET SPIO_NOC_ROUTER_0_7_7_RE_WLU_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RE_WLU_GET SPIO_NOC_ROUTER_0_7_7_RE_WLU_SET ns_noc_io_spio_soc_ip.csr 162427 WLU 1'b1: Traffic destined for West link which is unavailable 11 11 0x0 R/W SLU SPIO_NOC_ROUTER_0_7_7_RE_SLU_WIDTH SPIO_NOC_ROUTER_0_7_7_RE_SLU_MSB SPIO_NOC_ROUTER_0_7_7_RE_SLU_LSB SPIO_NOC_ROUTER_0_7_7_RE_SLU_RANGE SPIO_NOC_ROUTER_0_7_7_RE_SLU_RESET SPIO_NOC_ROUTER_0_7_7_RE_SLU_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RE_SLU_GET SPIO_NOC_ROUTER_0_7_7_RE_SLU_SET ns_noc_io_spio_soc_ip.csr 162438 SLU 1'b1: Traffic destined for South link which is unavailable 12 12 0x0 R/W HLU SPIO_NOC_ROUTER_0_7_7_RE_HLU_WIDTH SPIO_NOC_ROUTER_0_7_7_RE_HLU_MSB SPIO_NOC_ROUTER_0_7_7_RE_HLU_LSB SPIO_NOC_ROUTER_0_7_7_RE_HLU_RANGE SPIO_NOC_ROUTER_0_7_7_RE_HLU_RESET SPIO_NOC_ROUTER_0_7_7_RE_HLU_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RE_HLU_GET SPIO_NOC_ROUTER_0_7_7_RE_HLU_SET ns_noc_io_spio_soc_ip.csr 162449 HLU 1'b1: Traffic destined for H link which is unavailable 13 13 0x0 R/W ILU SPIO_NOC_ROUTER_0_7_7_RE_ILU_WIDTH SPIO_NOC_ROUTER_0_7_7_RE_ILU_MSB SPIO_NOC_ROUTER_0_7_7_RE_ILU_LSB SPIO_NOC_ROUTER_0_7_7_RE_ILU_RANGE SPIO_NOC_ROUTER_0_7_7_RE_ILU_RESET SPIO_NOC_ROUTER_0_7_7_RE_ILU_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RE_ILU_GET SPIO_NOC_ROUTER_0_7_7_RE_ILU_SET ns_noc_io_spio_soc_ip.csr 162460 ILU 1'b1: Traffic destined for I link which is unavailable 14 14 0x0 R/W JLU SPIO_NOC_ROUTER_0_7_7_RE_JLU_WIDTH SPIO_NOC_ROUTER_0_7_7_RE_JLU_MSB SPIO_NOC_ROUTER_0_7_7_RE_JLU_LSB SPIO_NOC_ROUTER_0_7_7_RE_JLU_RANGE SPIO_NOC_ROUTER_0_7_7_RE_JLU_RESET SPIO_NOC_ROUTER_0_7_7_RE_JLU_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RE_JLU_GET SPIO_NOC_ROUTER_0_7_7_RE_JLU_SET ns_noc_io_spio_soc_ip.csr 162471 JLU 1'b1: Traffic destined for J link which is unavailable 15 15 0x0 R/W KLU SPIO_NOC_ROUTER_0_7_7_RE_KLU_WIDTH SPIO_NOC_ROUTER_0_7_7_RE_KLU_MSB SPIO_NOC_ROUTER_0_7_7_RE_KLU_LSB SPIO_NOC_ROUTER_0_7_7_RE_KLU_RANGE SPIO_NOC_ROUTER_0_7_7_RE_KLU_RESET SPIO_NOC_ROUTER_0_7_7_RE_KLU_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RE_KLU_GET SPIO_NOC_ROUTER_0_7_7_RE_KLU_SET ns_noc_io_spio_soc_ip.csr 162482 KLU 1'b1: Traffic destined for K link which is unavailable 16 16 0x0 R/W UNSD_31_14 SPIO_NOC_ROUTER_0_7_7_RE_UNSD_31_14_WIDTH SPIO_NOC_ROUTER_0_7_7_RE_UNSD_31_14_MSB SPIO_NOC_ROUTER_0_7_7_RE_UNSD_31_14_LSB SPIO_NOC_ROUTER_0_7_7_RE_UNSD_31_14_RANGE SPIO_NOC_ROUTER_0_7_7_RE_UNSD_31_14_RESET SPIO_NOC_ROUTER_0_7_7_RE_UNSD_31_14_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RE_UNSD_31_14_GET SPIO_NOC_ROUTER_0_7_7_RE_UNSD_31_14_SET ns_noc_io_spio_soc_ip.csr 162493 UNSD_31_14 31 17 0x0000 R register spio_noc.router_0_7_7_rem router_0_7_7_rem SPIO_NOC_ROUTER_0_7_7_REM_ADDRESS SPIO_NOC_ROUTER_0_7_7_REM_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_REM_OFFSET SPIO_NOC_ROUTER_0_7_7_REM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 162667 R0_7 register rem 0x4C088 R/W 0x0001fe00 Spio_noc_router_0_7_7_rem This register is used to select whether the interrupt events in the Router Event Interrupt Status register should send an interrupt when asserted. If the corresponding bit is set to 1, an interrupt will not be sent. This register can be read and written to. false false false false OVFIM SPIO_NOC_ROUTER_0_7_7_REM_OVFIM_WIDTH SPIO_NOC_ROUTER_0_7_7_REM_OVFIM_MSB SPIO_NOC_ROUTER_0_7_7_REM_OVFIM_LSB SPIO_NOC_ROUTER_0_7_7_REM_OVFIM_RANGE SPIO_NOC_ROUTER_0_7_7_REM_OVFIM_RESET SPIO_NOC_ROUTER_0_7_7_REM_OVFIM_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_REM_OVFIM_GET SPIO_NOC_ROUTER_0_7_7_REM_OVFIM_SET ns_noc_io_spio_soc_ip.csr 162520 OVFIM 1'b1: Masks or disables an interrupt from being generated by the input event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 0 0 0x0 R/W CSR_PARERRM SPIO_NOC_ROUTER_0_7_7_REM_CSR_PARERRM_WIDTH SPIO_NOC_ROUTER_0_7_7_REM_CSR_PARERRM_MSB SPIO_NOC_ROUTER_0_7_7_REM_CSR_PARERRM_LSB SPIO_NOC_ROUTER_0_7_7_REM_CSR_PARERRM_RANGE SPIO_NOC_ROUTER_0_7_7_REM_CSR_PARERRM_RESET SPIO_NOC_ROUTER_0_7_7_REM_CSR_PARERRM_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_REM_CSR_PARERRM_GET SPIO_NOC_ROUTER_0_7_7_REM_CSR_PARERRM_SET ns_noc_io_spio_soc_ip.csr 162531 CSR_PARERRM 1'b1: Mask CSR parity error interrupt 1 1 0x0 R/W OVFOM SPIO_NOC_ROUTER_0_7_7_REM_OVFOM_WIDTH SPIO_NOC_ROUTER_0_7_7_REM_OVFOM_MSB SPIO_NOC_ROUTER_0_7_7_REM_OVFOM_LSB SPIO_NOC_ROUTER_0_7_7_REM_OVFOM_RANGE SPIO_NOC_ROUTER_0_7_7_REM_OVFOM_RESET SPIO_NOC_ROUTER_0_7_7_REM_OVFOM_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_REM_OVFOM_GET SPIO_NOC_ROUTER_0_7_7_REM_OVFOM_SET ns_noc_io_spio_soc_ip.csr 162545 OVFOM 1'b1: Masks or disables an interrupt from being generated by the output event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 2 2 0x0 R/W UNSD_7_3 SPIO_NOC_ROUTER_0_7_7_REM_UNSD_7_3_WIDTH SPIO_NOC_ROUTER_0_7_7_REM_UNSD_7_3_MSB SPIO_NOC_ROUTER_0_7_7_REM_UNSD_7_3_LSB SPIO_NOC_ROUTER_0_7_7_REM_UNSD_7_3_RANGE SPIO_NOC_ROUTER_0_7_7_REM_UNSD_7_3_RESET SPIO_NOC_ROUTER_0_7_7_REM_UNSD_7_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_REM_UNSD_7_3_GET SPIO_NOC_ROUTER_0_7_7_REM_UNSD_7_3_SET ns_noc_io_spio_soc_ip.csr 162556 UNSD_7_3 7 3 0x00 R PGM SPIO_NOC_ROUTER_0_7_7_REM_PGM_WIDTH SPIO_NOC_ROUTER_0_7_7_REM_PGM_MSB SPIO_NOC_ROUTER_0_7_7_REM_PGM_LSB SPIO_NOC_ROUTER_0_7_7_REM_PGM_RANGE SPIO_NOC_ROUTER_0_7_7_REM_PGM_RESET SPIO_NOC_ROUTER_0_7_7_REM_PGM_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_REM_PGM_GET SPIO_NOC_ROUTER_0_7_7_REM_PGM_SET ns_noc_io_spio_soc_ip.csr 162567 PGM 1'b1: Mask PGE error interrupt 8 8 0x0 R/W MN SPIO_NOC_ROUTER_0_7_7_REM_MN_WIDTH SPIO_NOC_ROUTER_0_7_7_REM_MN_MSB SPIO_NOC_ROUTER_0_7_7_REM_MN_LSB SPIO_NOC_ROUTER_0_7_7_REM_MN_RANGE SPIO_NOC_ROUTER_0_7_7_REM_MN_RESET SPIO_NOC_ROUTER_0_7_7_REM_MN_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_REM_MN_GET SPIO_NOC_ROUTER_0_7_7_REM_MN_SET ns_noc_io_spio_soc_ip.csr 162578 MN 1'b1: Mask NLU error interrupt 9 9 0x1 R/W ME SPIO_NOC_ROUTER_0_7_7_REM_ME_WIDTH SPIO_NOC_ROUTER_0_7_7_REM_ME_MSB SPIO_NOC_ROUTER_0_7_7_REM_ME_LSB SPIO_NOC_ROUTER_0_7_7_REM_ME_RANGE SPIO_NOC_ROUTER_0_7_7_REM_ME_RESET SPIO_NOC_ROUTER_0_7_7_REM_ME_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_REM_ME_GET SPIO_NOC_ROUTER_0_7_7_REM_ME_SET ns_noc_io_spio_soc_ip.csr 162589 ME 1'b1: Mask ELU error interrupt 10 10 0x1 R/W MW SPIO_NOC_ROUTER_0_7_7_REM_MW_WIDTH SPIO_NOC_ROUTER_0_7_7_REM_MW_MSB SPIO_NOC_ROUTER_0_7_7_REM_MW_LSB SPIO_NOC_ROUTER_0_7_7_REM_MW_RANGE SPIO_NOC_ROUTER_0_7_7_REM_MW_RESET SPIO_NOC_ROUTER_0_7_7_REM_MW_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_REM_MW_GET SPIO_NOC_ROUTER_0_7_7_REM_MW_SET ns_noc_io_spio_soc_ip.csr 162600 MW 1'b1: Mask WLU error interrupt 11 11 0x1 R/W MS SPIO_NOC_ROUTER_0_7_7_REM_MS_WIDTH SPIO_NOC_ROUTER_0_7_7_REM_MS_MSB SPIO_NOC_ROUTER_0_7_7_REM_MS_LSB SPIO_NOC_ROUTER_0_7_7_REM_MS_RANGE SPIO_NOC_ROUTER_0_7_7_REM_MS_RESET SPIO_NOC_ROUTER_0_7_7_REM_MS_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_REM_MS_GET SPIO_NOC_ROUTER_0_7_7_REM_MS_SET ns_noc_io_spio_soc_ip.csr 162611 MS 1'b1: Mask SLU error interrupt 12 12 0x1 R/W MH SPIO_NOC_ROUTER_0_7_7_REM_MH_WIDTH SPIO_NOC_ROUTER_0_7_7_REM_MH_MSB SPIO_NOC_ROUTER_0_7_7_REM_MH_LSB SPIO_NOC_ROUTER_0_7_7_REM_MH_RANGE SPIO_NOC_ROUTER_0_7_7_REM_MH_RESET SPIO_NOC_ROUTER_0_7_7_REM_MH_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_REM_MH_GET SPIO_NOC_ROUTER_0_7_7_REM_MH_SET ns_noc_io_spio_soc_ip.csr 162622 MH 1'b1: Mask HLU error interrupt 13 13 0x1 R/W MI SPIO_NOC_ROUTER_0_7_7_REM_MI_WIDTH SPIO_NOC_ROUTER_0_7_7_REM_MI_MSB SPIO_NOC_ROUTER_0_7_7_REM_MI_LSB SPIO_NOC_ROUTER_0_7_7_REM_MI_RANGE SPIO_NOC_ROUTER_0_7_7_REM_MI_RESET SPIO_NOC_ROUTER_0_7_7_REM_MI_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_REM_MI_GET SPIO_NOC_ROUTER_0_7_7_REM_MI_SET ns_noc_io_spio_soc_ip.csr 162633 MI 1'b1: Mask ILU error interrupt 14 14 0x1 R/W MJ SPIO_NOC_ROUTER_0_7_7_REM_MJ_WIDTH SPIO_NOC_ROUTER_0_7_7_REM_MJ_MSB SPIO_NOC_ROUTER_0_7_7_REM_MJ_LSB SPIO_NOC_ROUTER_0_7_7_REM_MJ_RANGE SPIO_NOC_ROUTER_0_7_7_REM_MJ_RESET SPIO_NOC_ROUTER_0_7_7_REM_MJ_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_REM_MJ_GET SPIO_NOC_ROUTER_0_7_7_REM_MJ_SET ns_noc_io_spio_soc_ip.csr 162644 MJ 1'b1: Mask JLU error interrupt 15 15 0x1 R/W MK SPIO_NOC_ROUTER_0_7_7_REM_MK_WIDTH SPIO_NOC_ROUTER_0_7_7_REM_MK_MSB SPIO_NOC_ROUTER_0_7_7_REM_MK_LSB SPIO_NOC_ROUTER_0_7_7_REM_MK_RANGE SPIO_NOC_ROUTER_0_7_7_REM_MK_RESET SPIO_NOC_ROUTER_0_7_7_REM_MK_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_REM_MK_GET SPIO_NOC_ROUTER_0_7_7_REM_MK_SET ns_noc_io_spio_soc_ip.csr 162655 MK 1'b1: Mask KLU error interrupt 16 16 0x1 R/W UNSD_31_14 SPIO_NOC_ROUTER_0_7_7_REM_UNSD_31_14_WIDTH SPIO_NOC_ROUTER_0_7_7_REM_UNSD_31_14_MSB SPIO_NOC_ROUTER_0_7_7_REM_UNSD_31_14_LSB SPIO_NOC_ROUTER_0_7_7_REM_UNSD_31_14_RANGE SPIO_NOC_ROUTER_0_7_7_REM_UNSD_31_14_RESET SPIO_NOC_ROUTER_0_7_7_REM_UNSD_31_14_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_REM_UNSD_31_14_GET SPIO_NOC_ROUTER_0_7_7_REM_UNSD_31_14_SET ns_noc_io_spio_soc_ip.csr 162666 UNSD_31_14 31 17 0x0000 R register spio_noc.router_0_7_7_recc router_0_7_7_recc SPIO_NOC_ROUTER_0_7_7_RECC_ADDRESS SPIO_NOC_ROUTER_0_7_7_RECC_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_RECC_OFFSET SPIO_NOC_ROUTER_0_7_7_RECC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 162752 R0_7 register recc 0x4C090 R/W 0x00000000 Spio_noc_router_0_7_7_recc This register is used to select which hardware events will increment the event counter. false false false false IVC SPIO_NOC_ROUTER_0_7_7_RECC_IVC_WIDTH SPIO_NOC_ROUTER_0_7_7_RECC_IVC_MSB SPIO_NOC_ROUTER_0_7_7_RECC_IVC_LSB SPIO_NOC_ROUTER_0_7_7_RECC_IVC_RANGE SPIO_NOC_ROUTER_0_7_7_RECC_IVC_RESET SPIO_NOC_ROUTER_0_7_7_RECC_IVC_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RECC_IVC_GET SPIO_NOC_ROUTER_0_7_7_RECC_IVC_SET ns_noc_io_spio_soc_ip.csr 162688 IVC 11: Input VC 3 10: Input VC 2 01: Input VC 1 00: Input VC 0 1 0 0x0 R/W UNSD_3_2 SPIO_NOC_ROUTER_0_7_7_RECC_UNSD_3_2_WIDTH SPIO_NOC_ROUTER_0_7_7_RECC_UNSD_3_2_MSB SPIO_NOC_ROUTER_0_7_7_RECC_UNSD_3_2_LSB SPIO_NOC_ROUTER_0_7_7_RECC_UNSD_3_2_RANGE SPIO_NOC_ROUTER_0_7_7_RECC_UNSD_3_2_RESET SPIO_NOC_ROUTER_0_7_7_RECC_UNSD_3_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RECC_UNSD_3_2_GET SPIO_NOC_ROUTER_0_7_7_RECC_UNSD_3_2_SET ns_noc_io_spio_soc_ip.csr 162699 UNSD_3_2 3 2 0x0 R INP SPIO_NOC_ROUTER_0_7_7_RECC_INP_WIDTH SPIO_NOC_ROUTER_0_7_7_RECC_INP_MSB SPIO_NOC_ROUTER_0_7_7_RECC_INP_LSB SPIO_NOC_ROUTER_0_7_7_RECC_INP_RANGE SPIO_NOC_ROUTER_0_7_7_RECC_INP_RESET SPIO_NOC_ROUTER_0_7_7_RECC_INP_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RECC_INP_GET SPIO_NOC_ROUTER_0_7_7_RECC_INP_SET ns_noc_io_spio_soc_ip.csr 162710 INP Input port on which the event is captured 6 4 0x0 R/W UNSD_7_7 SPIO_NOC_ROUTER_0_7_7_RECC_UNSD_7_7_WIDTH SPIO_NOC_ROUTER_0_7_7_RECC_UNSD_7_7_MSB SPIO_NOC_ROUTER_0_7_7_RECC_UNSD_7_7_LSB SPIO_NOC_ROUTER_0_7_7_RECC_UNSD_7_7_RANGE SPIO_NOC_ROUTER_0_7_7_RECC_UNSD_7_7_RESET SPIO_NOC_ROUTER_0_7_7_RECC_UNSD_7_7_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RECC_UNSD_7_7_GET SPIO_NOC_ROUTER_0_7_7_RECC_UNSD_7_7_SET ns_noc_io_spio_soc_ip.csr 162721 UNSD_7_7 7 7 0x0 R EVT SPIO_NOC_ROUTER_0_7_7_RECC_EVT_WIDTH SPIO_NOC_ROUTER_0_7_7_RECC_EVT_MSB SPIO_NOC_ROUTER_0_7_7_RECC_EVT_LSB SPIO_NOC_ROUTER_0_7_7_RECC_EVT_RANGE SPIO_NOC_ROUTER_0_7_7_RECC_EVT_RESET SPIO_NOC_ROUTER_0_7_7_RECC_EVT_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RECC_EVT_GET SPIO_NOC_ROUTER_0_7_7_RECC_EVT_SET ns_noc_io_spio_soc_ip.csr 162740 EVT 11: Generates count event when VC has valid data, but is stalled 10: Generates count event on every flit received for the selected input port and selected input VCs, this can be used to count total flits received on a router input port 01: Generates count event on every EOP received for the selected input port and selected input VCs, this can be used to count packets received on a router input port 00: Disable 9 8 0x0 R/W UNSD_31_10 SPIO_NOC_ROUTER_0_7_7_RECC_UNSD_31_10_WIDTH SPIO_NOC_ROUTER_0_7_7_RECC_UNSD_31_10_MSB SPIO_NOC_ROUTER_0_7_7_RECC_UNSD_31_10_LSB SPIO_NOC_ROUTER_0_7_7_RECC_UNSD_31_10_RANGE SPIO_NOC_ROUTER_0_7_7_RECC_UNSD_31_10_RESET SPIO_NOC_ROUTER_0_7_7_RECC_UNSD_31_10_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RECC_UNSD_31_10_GET SPIO_NOC_ROUTER_0_7_7_RECC_UNSD_31_10_SET ns_noc_io_spio_soc_ip.csr 162751 UNSD_31_10 31 10 0x000000 R register spio_noc.router_0_7_7_rec router_0_7_7_rec SPIO_NOC_ROUTER_0_7_7_REC_ADDRESS SPIO_NOC_ROUTER_0_7_7_REC_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_REC_OFFSET SPIO_NOC_ROUTER_0_7_7_REC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 162777 R0_7 register rec 0x4C098 R/W 0x00000000 Spio_noc_router_0_7_7_rec This register holds the event counter. The value can be read to determine the current count value. The value can be written to initialize the counter. When events trigger a count, the counter will increment. When the counter increments at its highest value, it will roll over to zero and the overflow will mark the Router Event Interrupt Status register, which could trigger an interrupt. false false false false EVENT_CNTR SPIO_NOC_ROUTER_0_7_7_REC_EVENT_CNTR_WIDTH SPIO_NOC_ROUTER_0_7_7_REC_EVENT_CNTR_MSB SPIO_NOC_ROUTER_0_7_7_REC_EVENT_CNTR_LSB SPIO_NOC_ROUTER_0_7_7_REC_EVENT_CNTR_RANGE SPIO_NOC_ROUTER_0_7_7_REC_EVENT_CNTR_RESET SPIO_NOC_ROUTER_0_7_7_REC_EVENT_CNTR_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_REC_EVENT_CNTR_GET SPIO_NOC_ROUTER_0_7_7_REC_EVENT_CNTR_SET ns_noc_io_spio_soc_ip.csr 162776 EVENT_CNTR 32'bit event incrementing counter. Rollover from 32'hFFFFF -> 32'd0 sets the rollover status bit RE 31 0 0x00000000 R/W register spio_noc.router_0_7_7_id router_0_7_7_id SPIO_NOC_ROUTER_0_7_7_ID_ADDRESS SPIO_NOC_ROUTER_0_7_7_ID_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_ID_OFFSET SPIO_NOC_ROUTER_0_7_7_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 162846 R0_7 register id 0x4C0A0 R 0x010000c0 Spio_noc_router_0_7_7_id This register holds layer and position information for the router. It is a read-only register. It can be used for debugging software access to the NoC elements by confirming that a read has successfully targeted the correct NoC element. false false false false LAYER SPIO_NOC_ROUTER_0_7_7_ID_LAYER_WIDTH SPIO_NOC_ROUTER_0_7_7_ID_LAYER_MSB SPIO_NOC_ROUTER_0_7_7_ID_LAYER_LSB SPIO_NOC_ROUTER_0_7_7_ID_LAYER_RANGE SPIO_NOC_ROUTER_0_7_7_ID_LAYER_RESET SPIO_NOC_ROUTER_0_7_7_ID_LAYER_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ID_LAYER_GET SPIO_NOC_ROUTER_0_7_7_ID_LAYER_SET ns_noc_io_spio_soc_ip.csr 162802 LAYER 5-bit identifier of the NoC layer on which this router is located 4 0 0x00 R POS SPIO_NOC_ROUTER_0_7_7_ID_POS_WIDTH SPIO_NOC_ROUTER_0_7_7_ID_POS_MSB SPIO_NOC_ROUTER_0_7_7_ID_POS_LSB SPIO_NOC_ROUTER_0_7_7_ID_POS_RANGE SPIO_NOC_ROUTER_0_7_7_ID_POS_RESET SPIO_NOC_ROUTER_0_7_7_ID_POS_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ID_POS_GET SPIO_NOC_ROUTER_0_7_7_ID_POS_SET ns_noc_io_spio_soc_ip.csr 162813 POS 16-bit position ID of this router in the NoC 20 5 0x0006 R ZERO SPIO_NOC_ROUTER_0_7_7_ID_ZERO_WIDTH SPIO_NOC_ROUTER_0_7_7_ID_ZERO_MSB SPIO_NOC_ROUTER_0_7_7_ID_ZERO_LSB SPIO_NOC_ROUTER_0_7_7_ID_ZERO_RANGE SPIO_NOC_ROUTER_0_7_7_ID_ZERO_RESET SPIO_NOC_ROUTER_0_7_7_ID_ZERO_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ID_ZERO_GET SPIO_NOC_ROUTER_0_7_7_ID_ZERO_SET ns_noc_io_spio_soc_ip.csr 162824 ZERO Zeroes 23 21 0x0 R ONE SPIO_NOC_ROUTER_0_7_7_ID_ONE_WIDTH SPIO_NOC_ROUTER_0_7_7_ID_ONE_MSB SPIO_NOC_ROUTER_0_7_7_ID_ONE_LSB SPIO_NOC_ROUTER_0_7_7_ID_ONE_RANGE SPIO_NOC_ROUTER_0_7_7_ID_ONE_RESET SPIO_NOC_ROUTER_0_7_7_ID_ONE_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ID_ONE_GET SPIO_NOC_ROUTER_0_7_7_ID_ONE_SET ns_noc_io_spio_soc_ip.csr 162835 ONE One 24 24 0x1 R UNSD_31_25 SPIO_NOC_ROUTER_0_7_7_ID_UNSD_31_25_WIDTH SPIO_NOC_ROUTER_0_7_7_ID_UNSD_31_25_MSB SPIO_NOC_ROUTER_0_7_7_ID_UNSD_31_25_LSB SPIO_NOC_ROUTER_0_7_7_ID_UNSD_31_25_RANGE SPIO_NOC_ROUTER_0_7_7_ID_UNSD_31_25_RESET SPIO_NOC_ROUTER_0_7_7_ID_UNSD_31_25_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ID_UNSD_31_25_GET SPIO_NOC_ROUTER_0_7_7_ID_UNSD_31_25_SET ns_noc_io_spio_soc_ip.csr 162845 UNSD_31_25 31 25 0x00 R register spio_noc.router_0_7_7_rcgc router_0_7_7_rcgc SPIO_NOC_ROUTER_0_7_7_RCGC_ADDRESS SPIO_NOC_ROUTER_0_7_7_RCGC_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_RCGC_OFFSET SPIO_NOC_ROUTER_0_7_7_RCGC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 162872 R0_7 register rcgc 0x4C0A8 R/W 0x00000064 Spio_noc_router_0_7_7_rcgc Programmable interval used by coarse clock gating logic in routers.This count determines the consecutive number of idle cycle after which a router output port initiates coarse clock gating of the local port clock and de-asserts the 'busy' signal to the downstream router. This signal indicates inactivity to the downstream router and allows it to initiate coarse clock gating of its corresponding input port. false false false false HYSTERESIS_COUNTER SPIO_NOC_ROUTER_0_7_7_RCGC_HYSTERESIS_COUNTER_WIDTH SPIO_NOC_ROUTER_0_7_7_RCGC_HYSTERESIS_COUNTER_MSB SPIO_NOC_ROUTER_0_7_7_RCGC_HYSTERESIS_COUNTER_LSB SPIO_NOC_ROUTER_0_7_7_RCGC_HYSTERESIS_COUNTER_RANGE SPIO_NOC_ROUTER_0_7_7_RCGC_HYSTERESIS_COUNTER_RESET SPIO_NOC_ROUTER_0_7_7_RCGC_HYSTERESIS_COUNTER_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RCGC_HYSTERESIS_COUNTER_GET SPIO_NOC_ROUTER_0_7_7_RCGC_HYSTERESIS_COUNTER_SET ns_noc_io_spio_soc_ip.csr 162871 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W register spio_noc.router_0_7_7_rcgo router_0_7_7_rcgo SPIO_NOC_ROUTER_0_7_7_RCGO_ADDRESS SPIO_NOC_ROUTER_0_7_7_RCGO_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_RCGO_OFFSET SPIO_NOC_ROUTER_0_7_7_RCGO_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 162911 R0_7 register rcgo 0x4C0B0 R/W 0x00000000 Spio_noc_router_0_7_7_rcgo This register is used by coarse grained clock gating logic. This register can be set to override coarse clock gating for the entire router. Coarse clock gating for selective routers can be overridden by locally setting this register, if the user does not want incur and aggregate coarse clock gating cycle penalty over a "fast path/critical path" through the NoC. false false false false FPO SPIO_NOC_ROUTER_0_7_7_RCGO_FPO_WIDTH SPIO_NOC_ROUTER_0_7_7_RCGO_FPO_MSB SPIO_NOC_ROUTER_0_7_7_RCGO_FPO_LSB SPIO_NOC_ROUTER_0_7_7_RCGO_FPO_RANGE SPIO_NOC_ROUTER_0_7_7_RCGO_FPO_RESET SPIO_NOC_ROUTER_0_7_7_RCGO_FPO_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RCGO_FPO_GET SPIO_NOC_ROUTER_0_7_7_RCGO_FPO_SET ns_noc_io_spio_soc_ip.csr 162899 FPO 1'b1: Coarse clock gating is locally disabled (for fast path) 1'b0: Coarse clock gating is locally enabled 0 0 0x0 R/W UNSD_31_1 SPIO_NOC_ROUTER_0_7_7_RCGO_UNSD_31_1_WIDTH SPIO_NOC_ROUTER_0_7_7_RCGO_UNSD_31_1_MSB SPIO_NOC_ROUTER_0_7_7_RCGO_UNSD_31_1_LSB SPIO_NOC_ROUTER_0_7_7_RCGO_UNSD_31_1_RANGE SPIO_NOC_ROUTER_0_7_7_RCGO_UNSD_31_1_RESET SPIO_NOC_ROUTER_0_7_7_RCGO_UNSD_31_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_RCGO_UNSD_31_1_GET SPIO_NOC_ROUTER_0_7_7_RCGO_UNSD_31_1_SET ns_noc_io_spio_soc_ip.csr 162910 UNSD_31_1 31 1 0x00000000 R register spio_noc.router_0_7_7_p0_rperr router_0_7_7_p0_rperr SPIO_NOC_ROUTER_0_7_7_P0_RPERR_ADDRESS SPIO_NOC_ROUTER_0_7_7_P0_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_P0_RPERR_OFFSET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 163202 R0_7 register p0_rperr 0x4C0B8 R/W 0x00000000 Spio_noc_router_0_7_7_p0_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 162954 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 162965 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 162976 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 162987 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_7_7_P0_RPERR_CR_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERR_CR_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_CR_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_CR_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERR_CR_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERR_CR_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 162998 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_7_7_P0_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 163009 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_0_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_0_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_0_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_0_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_0_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 163020 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_0_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_0_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_0_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_0_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 163031 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_0_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_0_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_0_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_0_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 163043 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_0_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_0_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_0_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_0_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 163054 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_1_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_1_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_1_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_1_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_1_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 163066 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_1_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_1_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_1_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_1_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 163078 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_1_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_1_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_1_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_1_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 163091 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_1_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_1_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_1_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_1_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 163103 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_2_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_2_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_2_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_2_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_2_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 163115 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_2_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_2_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_2_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_2_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 163127 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_2_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_2_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_2_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_2_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 163140 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_2_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_2_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_2_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_2_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 163152 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_3_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_3_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_3_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_3_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_3_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 163164 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_3_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_3_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_3_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_3_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 163176 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_3_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_3_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_3_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_3_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 163189 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_3_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_3_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_3_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_3_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 163201 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_0_7_7_p1_rperr router_0_7_7_p1_rperr SPIO_NOC_ROUTER_0_7_7_P1_RPERR_ADDRESS SPIO_NOC_ROUTER_0_7_7_P1_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_P1_RPERR_OFFSET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 163493 R0_7 register p1_rperr 0x4C0C0 R/W 0x00000000 Spio_noc_router_0_7_7_p1_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 163245 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 163256 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 163267 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 163278 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_7_7_P1_RPERR_CR_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERR_CR_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_CR_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_CR_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERR_CR_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERR_CR_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 163289 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_7_7_P1_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 163300 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_0_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_0_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_0_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_0_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_0_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 163311 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_0_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_0_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_0_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_0_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 163322 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_0_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_0_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_0_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_0_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 163334 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_0_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_0_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_0_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_0_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 163345 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_1_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_1_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_1_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_1_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_1_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 163357 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_1_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_1_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_1_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_1_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 163369 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_1_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_1_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_1_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_1_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 163382 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_1_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_1_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_1_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_1_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 163394 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_2_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_2_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_2_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_2_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_2_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 163406 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_2_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_2_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_2_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_2_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 163418 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_2_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_2_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_2_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_2_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 163431 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_2_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_2_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_2_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_2_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 163443 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_3_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_3_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_3_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_3_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_3_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 163455 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_3_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_3_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_3_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_3_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 163467 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_3_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_3_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_3_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_3_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 163480 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_3_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_3_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_3_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_3_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 163492 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_0_7_7_p2_rperr router_0_7_7_p2_rperr SPIO_NOC_ROUTER_0_7_7_P2_RPERR_ADDRESS SPIO_NOC_ROUTER_0_7_7_P2_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_P2_RPERR_OFFSET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 163780 R0_7 register p2_rperr 0x4C0C8 R/W 0x00000000 Spio_noc_router_0_7_7_p2_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 163536 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 163547 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 163558 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 163569 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_7_7_P2_RPERR_CR_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERR_CR_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_CR_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_CR_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERR_CR_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERR_CR_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 163580 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_7_7_P2_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 163591 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_0_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_0_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_0_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_0_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_0_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 163602 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_0_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_0_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_0_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_0_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 163613 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_0_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_0_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_0_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_0_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 163625 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_0_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_0_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_0_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_0_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 163636 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_1_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_1_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_1_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_1_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_1_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 163647 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_1_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_1_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_1_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_1_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 163658 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_1_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_1_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_1_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_1_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 163670 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_1_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_1_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_1_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_1_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 163681 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_2_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_2_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_2_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_2_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_2_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 163693 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_2_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_2_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_2_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_2_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 163705 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_2_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_2_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_2_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_2_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 163718 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_2_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_2_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_2_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_2_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 163730 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_3_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_3_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_3_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_3_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_3_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 163742 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_3_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_3_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_3_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_3_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 163754 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_3_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_3_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_3_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_3_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 163767 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_3_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_3_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_3_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_3_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 163779 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_0_7_7_p4_rperr router_0_7_7_p4_rperr SPIO_NOC_ROUTER_0_7_7_P4_RPERR_ADDRESS SPIO_NOC_ROUTER_0_7_7_P4_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_P4_RPERR_OFFSET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 164071 R0_7 register p4_rperr 0x4C0D8 R/W 0x00000000 Spio_noc_router_0_7_7_p4_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 163823 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 163834 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 163845 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 163856 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_7_7_P4_RPERR_CR_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERR_CR_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_CR_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_CR_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERR_CR_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERR_CR_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 163867 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_7_7_P4_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 163878 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_0_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_0_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_0_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_0_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_0_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 163889 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_0_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_0_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_0_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_0_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 163900 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_0_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_0_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_0_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_0_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 163912 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_0_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_0_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_0_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_0_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 163923 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_1_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_1_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_1_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_1_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_1_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 163935 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_1_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_1_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_1_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_1_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 163947 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_1_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_1_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_1_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_1_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 163960 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_1_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_1_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_1_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_1_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 163972 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_2_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_2_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_2_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_2_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_2_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 163984 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_2_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_2_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_2_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_2_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 163996 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_2_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_2_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_2_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_2_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 164009 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_2_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_2_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_2_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_2_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 164021 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_3_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_3_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_3_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_3_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_3_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 164033 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_3_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_3_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_3_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_3_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 164045 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_3_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_3_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_3_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_3_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 164058 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_3_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_3_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_3_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_3_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 164070 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_0_7_7_p5_rperr router_0_7_7_p5_rperr SPIO_NOC_ROUTER_0_7_7_P5_RPERR_ADDRESS SPIO_NOC_ROUTER_0_7_7_P5_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_P5_RPERR_OFFSET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 164362 R0_7 register p5_rperr 0x4C0E0 R/W 0x00000000 Spio_noc_router_0_7_7_p5_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 164114 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 164125 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 164136 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 164147 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_7_7_P5_RPERR_CR_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERR_CR_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_CR_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_CR_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERR_CR_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERR_CR_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 164158 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_7_7_P5_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 164169 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_0_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_0_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_0_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_0_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_0_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 164180 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_0_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_0_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_0_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_0_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 164191 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_0_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_0_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_0_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_0_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 164203 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_0_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_0_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_0_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_0_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 164214 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_1_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_1_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_1_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_1_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_1_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 164226 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_1_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_1_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_1_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_1_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 164238 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_1_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_1_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_1_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_1_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 164251 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_1_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_1_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_1_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_1_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 164263 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_2_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_2_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_2_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_2_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_2_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 164275 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_2_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_2_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_2_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_2_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 164287 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_2_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_2_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_2_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_2_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 164300 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_2_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_2_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_2_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_2_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 164312 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_3_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_3_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_3_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_3_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_3_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 164324 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_3_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_3_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_3_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_3_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 164336 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_3_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_3_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_3_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_3_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 164349 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_3_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_3_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_3_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_3_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 164361 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_0_7_7_p6_rperr router_0_7_7_p6_rperr SPIO_NOC_ROUTER_0_7_7_P6_RPERR_ADDRESS SPIO_NOC_ROUTER_0_7_7_P6_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_P6_RPERR_OFFSET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 164653 R0_7 register p6_rperr 0x4C0E8 R/W 0x00000000 Spio_noc_router_0_7_7_p6_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 164405 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 164416 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 164427 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 164438 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_7_7_P6_RPERR_CR_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERR_CR_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_CR_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_CR_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERR_CR_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERR_CR_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 164449 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_7_7_P6_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 164460 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_0_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_0_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_0_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_0_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_0_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 164471 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_0_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_0_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_0_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_0_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 164482 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_0_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_0_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_0_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_0_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 164494 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_0_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_0_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_0_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_0_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 164505 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_1_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_1_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_1_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_1_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_1_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 164517 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_1_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_1_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_1_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_1_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 164529 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_1_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_1_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_1_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_1_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 164542 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_1_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_1_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_1_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_1_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 164554 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_2_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_2_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_2_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_2_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_2_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 164566 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_2_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_2_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_2_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_2_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 164578 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_2_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_2_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_2_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_2_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 164591 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_2_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_2_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_2_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_2_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 164603 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_3_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_3_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_3_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_3_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_3_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 164615 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_3_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_3_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_3_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_3_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 164627 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_3_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_3_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_3_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_3_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 164640 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_3_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_3_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_3_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_3_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 164652 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_0_7_7_p7_rperr router_0_7_7_p7_rperr SPIO_NOC_ROUTER_0_7_7_P7_RPERR_ADDRESS SPIO_NOC_ROUTER_0_7_7_P7_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_P7_RPERR_OFFSET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 164944 R0_7 register p7_rperr 0x4C0F0 R/W 0x00000000 Spio_noc_router_0_7_7_p7_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 164696 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 164707 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 164718 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 164729 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_7_7_P7_RPERR_CR_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERR_CR_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_CR_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_CR_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERR_CR_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERR_CR_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 164740 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_7_7_P7_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 164751 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_0_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_0_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_0_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_0_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_0_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 164762 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_0_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_0_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_0_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_0_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 164773 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_0_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_0_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_0_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_0_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 164785 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_0_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_0_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_0_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_0_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 164796 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_1_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_1_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_1_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_1_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_1_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 164808 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_1_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_1_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_1_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_1_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 164820 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_1_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_1_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_1_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_1_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 164833 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_1_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_1_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_1_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_1_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 164845 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_2_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_2_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_2_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_2_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_2_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 164857 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_2_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_2_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_2_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_2_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 164869 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_2_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_2_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_2_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_2_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 164882 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_2_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_2_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_2_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_2_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 164894 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_3_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_3_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_3_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_3_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_3_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 164906 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_3_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_3_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_3_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_3_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 164918 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_3_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_3_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_3_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_3_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 164931 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_3_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_3_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_3_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_3_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 164943 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_0_7_7_p0_rperrm router_0_7_7_p0_rperrm SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_ADDRESS SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_OFFSET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 165202 R0_7 register p0_rperrm 0x4C0F8 R/W 0x00000000 Spio_noc_router_0_7_7_p0_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 164966 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 164977 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 164988 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 164999 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_CR_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_CR_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_CR_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_CR_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_CR_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 165010 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 165021 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_0_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_0_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_0_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_0_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 165032 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_0_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 165043 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_0_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 165055 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_0_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 165066 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_1_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_1_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_1_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_1_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 165077 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_1_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 165088 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_1_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 165100 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_1_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 165111 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_2_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_2_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_2_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_2_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 165122 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_2_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 165133 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_2_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 165145 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_2_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 165156 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_3_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_3_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_3_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_3_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 165167 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_3_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 165178 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_3_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 165190 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_3_GET SPIO_NOC_ROUTER_0_7_7_P0_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 165201 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_0_7_7_p1_rperrm router_0_7_7_p1_rperrm SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_ADDRESS SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_OFFSET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 165460 R0_7 register p1_rperrm 0x4C100 R/W 0x00000000 Spio_noc_router_0_7_7_p1_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 165224 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 165235 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 165246 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 165257 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_CR_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_CR_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_CR_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_CR_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_CR_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 165268 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 165279 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_0_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_0_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_0_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_0_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 165290 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_0_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 165301 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_0_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 165313 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_0_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 165324 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_1_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_1_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_1_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_1_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 165335 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_1_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 165346 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_1_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 165358 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_1_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 165369 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_2_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_2_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_2_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_2_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 165380 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_2_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 165391 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_2_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 165403 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_2_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 165414 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_3_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_3_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_3_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_3_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 165425 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_3_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 165436 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_3_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 165448 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_3_GET SPIO_NOC_ROUTER_0_7_7_P1_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 165459 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_0_7_7_p2_rperrm router_0_7_7_p2_rperrm SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_ADDRESS SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_OFFSET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 165718 R0_7 register p2_rperrm 0x4C108 R/W 0x00000000 Spio_noc_router_0_7_7_p2_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 165482 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 165493 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 165504 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 165515 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_CR_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_CR_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_CR_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_CR_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_CR_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 165526 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 165537 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_0_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_0_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_0_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_0_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 165548 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_0_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 165559 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_0_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 165571 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_0_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 165582 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_1_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_1_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_1_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_1_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 165593 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_1_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 165604 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_1_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 165616 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_1_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 165627 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_2_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_2_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_2_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_2_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 165638 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_2_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 165649 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_2_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 165661 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_2_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 165672 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_3_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_3_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_3_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_3_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 165683 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_3_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 165694 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_3_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 165706 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_3_GET SPIO_NOC_ROUTER_0_7_7_P2_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 165717 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_0_7_7_p4_rperrm router_0_7_7_p4_rperrm SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_ADDRESS SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_OFFSET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 165976 R0_7 register p4_rperrm 0x4C118 R/W 0x00000000 Spio_noc_router_0_7_7_p4_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 165740 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 165751 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 165762 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 165773 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_CR_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_CR_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_CR_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_CR_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_CR_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 165784 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 165795 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_0_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_0_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_0_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_0_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 165806 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_0_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 165817 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_0_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 165829 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_0_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 165840 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_1_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_1_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_1_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_1_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 165851 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_1_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 165862 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_1_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 165874 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_1_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 165885 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_2_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_2_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_2_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_2_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 165896 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_2_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 165907 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_2_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 165919 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_2_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 165930 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_3_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_3_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_3_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_3_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 165941 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_3_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 165952 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_3_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 165964 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_3_GET SPIO_NOC_ROUTER_0_7_7_P4_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 165975 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_0_7_7_p5_rperrm router_0_7_7_p5_rperrm SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_ADDRESS SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_OFFSET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 166234 R0_7 register p5_rperrm 0x4C120 R/W 0x00000000 Spio_noc_router_0_7_7_p5_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 165998 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 166009 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 166020 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 166031 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_CR_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_CR_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_CR_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_CR_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_CR_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 166042 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 166053 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_0_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_0_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_0_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_0_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 166064 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_0_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 166075 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_0_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 166087 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_0_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 166098 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_1_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_1_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_1_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_1_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 166109 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_1_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 166120 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_1_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 166132 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_1_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 166143 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_2_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_2_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_2_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_2_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 166154 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_2_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 166165 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_2_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 166177 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_2_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 166188 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_3_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_3_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_3_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_3_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 166199 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_3_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 166210 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_3_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 166222 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_3_GET SPIO_NOC_ROUTER_0_7_7_P5_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 166233 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_0_7_7_p6_rperrm router_0_7_7_p6_rperrm SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_ADDRESS SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_OFFSET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 166492 R0_7 register p6_rperrm 0x4C128 R/W 0x00000000 Spio_noc_router_0_7_7_p6_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 166256 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 166267 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 166278 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 166289 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_CR_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_CR_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_CR_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_CR_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_CR_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 166300 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 166311 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_0_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_0_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_0_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_0_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 166322 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_0_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 166333 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_0_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 166345 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_0_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 166356 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_1_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_1_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_1_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_1_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 166367 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_1_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 166378 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_1_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 166390 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_1_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 166401 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_2_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_2_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_2_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_2_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 166412 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_2_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 166423 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_2_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 166435 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_2_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 166446 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_3_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_3_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_3_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_3_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 166457 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_3_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 166468 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_3_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 166480 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_3_GET SPIO_NOC_ROUTER_0_7_7_P6_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 166491 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_0_7_7_p7_rperrm router_0_7_7_p7_rperrm SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_ADDRESS SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_OFFSET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 166750 R0_7 register p7_rperrm 0x4C130 R/W 0x00000000 Spio_noc_router_0_7_7_p7_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 166514 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 166525 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 166536 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 166547 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_CR_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_CR_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_CR_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_CR_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_CR_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 166558 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 166569 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_0_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_0_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_0_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_0_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 166580 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_0_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 166591 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_0_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 166603 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_0_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 166614 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_1_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_1_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_1_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_1_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 166625 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_1_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 166636 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_1_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 166648 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_1_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 166659 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_2_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_2_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_2_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_2_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 166670 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_2_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 166681 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_2_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 166693 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_2_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 166704 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_3_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_3_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_3_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_3_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 166715 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_3_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 166726 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_3_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 166738 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_3_GET SPIO_NOC_ROUTER_0_7_7_P7_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 166749 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_0_7_7_roecc router_0_7_7_roecc SPIO_NOC_ROUTER_0_7_7_ROECC_ADDRESS SPIO_NOC_ROUTER_0_7_7_ROECC_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_ROECC_OFFSET SPIO_NOC_ROUTER_0_7_7_ROECC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 166823 R0_7 register roecc 0x4C138 R/W 0x00000000 Spio_noc_router_0_7_7_roecc This register is used to select which hardware events will increment the output event counter. false false false false OVC SPIO_NOC_ROUTER_0_7_7_ROECC_OVC_WIDTH SPIO_NOC_ROUTER_0_7_7_ROECC_OVC_MSB SPIO_NOC_ROUTER_0_7_7_ROECC_OVC_LSB SPIO_NOC_ROUTER_0_7_7_ROECC_OVC_RANGE SPIO_NOC_ROUTER_0_7_7_ROECC_OVC_RESET SPIO_NOC_ROUTER_0_7_7_ROECC_OVC_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROECC_OVC_GET SPIO_NOC_ROUTER_0_7_7_ROECC_OVC_SET ns_noc_io_spio_soc_ip.csr 166768 OVC Bit map to select output VCs to monitor events on 3 0 0x0 R/W OP SPIO_NOC_ROUTER_0_7_7_ROECC_OP_WIDTH SPIO_NOC_ROUTER_0_7_7_ROECC_OP_MSB SPIO_NOC_ROUTER_0_7_7_ROECC_OP_LSB SPIO_NOC_ROUTER_0_7_7_ROECC_OP_RANGE SPIO_NOC_ROUTER_0_7_7_ROECC_OP_RESET SPIO_NOC_ROUTER_0_7_7_ROECC_OP_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROECC_OP_GET SPIO_NOC_ROUTER_0_7_7_ROECC_OP_SET ns_noc_io_spio_soc_ip.csr 166779 OP Output port on which the event is captured 6 4 0x0 R/W UNSD_7_7 SPIO_NOC_ROUTER_0_7_7_ROECC_UNSD_7_7_WIDTH SPIO_NOC_ROUTER_0_7_7_ROECC_UNSD_7_7_MSB SPIO_NOC_ROUTER_0_7_7_ROECC_UNSD_7_7_LSB SPIO_NOC_ROUTER_0_7_7_ROECC_UNSD_7_7_RANGE SPIO_NOC_ROUTER_0_7_7_ROECC_UNSD_7_7_RESET SPIO_NOC_ROUTER_0_7_7_ROECC_UNSD_7_7_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROECC_UNSD_7_7_GET SPIO_NOC_ROUTER_0_7_7_ROECC_UNSD_7_7_SET ns_noc_io_spio_soc_ip.csr 166790 UNSD_7_7 7 7 0x0 R EVT SPIO_NOC_ROUTER_0_7_7_ROECC_EVT_WIDTH SPIO_NOC_ROUTER_0_7_7_ROECC_EVT_MSB SPIO_NOC_ROUTER_0_7_7_ROECC_EVT_LSB SPIO_NOC_ROUTER_0_7_7_ROECC_EVT_RANGE SPIO_NOC_ROUTER_0_7_7_ROECC_EVT_RESET SPIO_NOC_ROUTER_0_7_7_ROECC_EVT_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROECC_EVT_GET SPIO_NOC_ROUTER_0_7_7_ROECC_EVT_SET ns_noc_io_spio_soc_ip.csr 166811 EVT 100: Port stalled. Input flits are available for the port, but no output VC has credit 011: Generates count event when flits are available to be sent to output VC, but the VC has no credit 010: Generates count event on every flit sent on the selected output port and selected outpt VCs, this can be used to count total flits sent on a router output port 001: Generates count event on every EOP sent on the selected output port and selected output VCs, this can be used to count packets sent on a router output port 000: Disable 10 8 0x0 R/W UNSD_31_11 SPIO_NOC_ROUTER_0_7_7_ROECC_UNSD_31_11_WIDTH SPIO_NOC_ROUTER_0_7_7_ROECC_UNSD_31_11_MSB SPIO_NOC_ROUTER_0_7_7_ROECC_UNSD_31_11_LSB SPIO_NOC_ROUTER_0_7_7_ROECC_UNSD_31_11_RANGE SPIO_NOC_ROUTER_0_7_7_ROECC_UNSD_31_11_RESET SPIO_NOC_ROUTER_0_7_7_ROECC_UNSD_31_11_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROECC_UNSD_31_11_GET SPIO_NOC_ROUTER_0_7_7_ROECC_UNSD_31_11_SET ns_noc_io_spio_soc_ip.csr 166822 UNSD_31_11 31 11 0x000000 R register spio_noc.router_0_7_7_roec router_0_7_7_roec SPIO_NOC_ROUTER_0_7_7_ROEC_ADDRESS SPIO_NOC_ROUTER_0_7_7_ROEC_BYTE_ADDRESS SPIO_NOC_ROUTER_0_7_7_ROEC_OFFSET SPIO_NOC_ROUTER_0_7_7_ROEC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 166848 R0_7 register roec 0x4C140 R/W 0x00000000 Spio_noc_router_0_7_7_roec This register holds the output event counter. The value can be read to determine the current count value. The value can be written to initialize the counter. When events trigger a count, the counter will increment. When the counter increments at its highest value, it will roll over to zero and the overflow will mark the Router output Event Interrupt Status register, which could trigger an interrupt. false false false false EVENT_CNTR SPIO_NOC_ROUTER_0_7_7_ROEC_EVENT_CNTR_WIDTH SPIO_NOC_ROUTER_0_7_7_ROEC_EVENT_CNTR_MSB SPIO_NOC_ROUTER_0_7_7_ROEC_EVENT_CNTR_LSB SPIO_NOC_ROUTER_0_7_7_ROEC_EVENT_CNTR_RANGE SPIO_NOC_ROUTER_0_7_7_ROEC_EVENT_CNTR_RESET SPIO_NOC_ROUTER_0_7_7_ROEC_EVENT_CNTR_FIELD_MASK SPIO_NOC_ROUTER_0_7_7_ROEC_EVENT_CNTR_GET SPIO_NOC_ROUTER_0_7_7_ROEC_EVENT_CNTR_SET ns_noc_io_spio_soc_ip.csr 166847 EVENT_CNTR 32'bit event incrementing counter. Rollover from 32'hFFFFF -> 32'd0 sets the rollover status bit RE 31 0 0x00000000 R/W register spio_noc.router_0_8_8_rivcs_h router_0_8_8_rivcs_h SPIO_NOC_ROUTER_0_8_8_RIVCS_H_ADDRESS SPIO_NOC_ROUTER_0_8_8_RIVCS_H_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OFFSET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 167177 R0_8 register rivcs_h 0x50000 R 0x00000000 Spio_noc_router_0_8_8_rivcs_h This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 166873 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_0_SET ns_noc_io_spio_soc_ip.csr 166887 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_0_SET ns_noc_io_spio_soc_ip.csr 166903 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_0_SET ns_noc_io_spio_soc_ip.csr 166917 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_0_SET ns_noc_io_spio_soc_ip.csr 166928 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_0_SET ns_noc_io_spio_soc_ip.csr 166939 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 166952 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_1_SET ns_noc_io_spio_soc_ip.csr 166966 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_1_SET ns_noc_io_spio_soc_ip.csr 166982 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_1_SET ns_noc_io_spio_soc_ip.csr 166996 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_1_SET ns_noc_io_spio_soc_ip.csr 167007 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_1_SET ns_noc_io_spio_soc_ip.csr 167018 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 167031 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_2_SET ns_noc_io_spio_soc_ip.csr 167045 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_2_SET ns_noc_io_spio_soc_ip.csr 167061 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_2_SET ns_noc_io_spio_soc_ip.csr 167075 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_2_SET ns_noc_io_spio_soc_ip.csr 167086 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_2_SET ns_noc_io_spio_soc_ip.csr 167097 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 167110 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_UP_3_SET ns_noc_io_spio_soc_ip.csr 167124 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_S_3_SET ns_noc_io_spio_soc_ip.csr 167140 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_B_3_SET ns_noc_io_spio_soc_ip.csr 167154 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_F_3_SET ns_noc_io_spio_soc_ip.csr 167165 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_H_V_3_SET ns_noc_io_spio_soc_ip.csr 167176 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_0_8_8_rivcs_w router_0_8_8_rivcs_w SPIO_NOC_ROUTER_0_8_8_RIVCS_W_ADDRESS SPIO_NOC_ROUTER_0_8_8_RIVCS_W_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OFFSET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 167506 R0_8 register rivcs_w 0x50018 R 0x00000000 Spio_noc_router_0_8_8_rivcs_w This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 167202 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_0_SET ns_noc_io_spio_soc_ip.csr 167216 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_0_SET ns_noc_io_spio_soc_ip.csr 167232 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_0_SET ns_noc_io_spio_soc_ip.csr 167246 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_0_SET ns_noc_io_spio_soc_ip.csr 167257 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_0_SET ns_noc_io_spio_soc_ip.csr 167268 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 167281 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_1_SET ns_noc_io_spio_soc_ip.csr 167295 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_1_SET ns_noc_io_spio_soc_ip.csr 167311 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_1_SET ns_noc_io_spio_soc_ip.csr 167325 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_1_SET ns_noc_io_spio_soc_ip.csr 167336 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_1_SET ns_noc_io_spio_soc_ip.csr 167347 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 167360 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_2_SET ns_noc_io_spio_soc_ip.csr 167374 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_2_SET ns_noc_io_spio_soc_ip.csr 167390 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_2_SET ns_noc_io_spio_soc_ip.csr 167404 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_2_SET ns_noc_io_spio_soc_ip.csr 167415 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_2_SET ns_noc_io_spio_soc_ip.csr 167426 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 167439 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_UP_3_SET ns_noc_io_spio_soc_ip.csr 167453 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_S_3_SET ns_noc_io_spio_soc_ip.csr 167469 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_B_3_SET ns_noc_io_spio_soc_ip.csr 167483 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_F_3_SET ns_noc_io_spio_soc_ip.csr 167494 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_W_V_3_SET ns_noc_io_spio_soc_ip.csr 167505 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_0_8_8_rivcs_n router_0_8_8_rivcs_n SPIO_NOC_ROUTER_0_8_8_RIVCS_N_ADDRESS SPIO_NOC_ROUTER_0_8_8_RIVCS_N_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OFFSET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 167835 R0_8 register rivcs_n 0x50020 R 0x00000000 Spio_noc_router_0_8_8_rivcs_n This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 167531 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_0_SET ns_noc_io_spio_soc_ip.csr 167545 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_0_SET ns_noc_io_spio_soc_ip.csr 167561 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_0_SET ns_noc_io_spio_soc_ip.csr 167575 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_0_SET ns_noc_io_spio_soc_ip.csr 167586 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_0_SET ns_noc_io_spio_soc_ip.csr 167597 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 167610 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_1_SET ns_noc_io_spio_soc_ip.csr 167624 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_1_SET ns_noc_io_spio_soc_ip.csr 167640 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_1_SET ns_noc_io_spio_soc_ip.csr 167654 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_1_SET ns_noc_io_spio_soc_ip.csr 167665 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_1_SET ns_noc_io_spio_soc_ip.csr 167676 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 167689 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_2_SET ns_noc_io_spio_soc_ip.csr 167703 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_2_SET ns_noc_io_spio_soc_ip.csr 167719 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_2_SET ns_noc_io_spio_soc_ip.csr 167733 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_2_SET ns_noc_io_spio_soc_ip.csr 167744 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_2_SET ns_noc_io_spio_soc_ip.csr 167755 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 167768 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_UP_3_SET ns_noc_io_spio_soc_ip.csr 167782 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_S_3_SET ns_noc_io_spio_soc_ip.csr 167798 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_B_3_SET ns_noc_io_spio_soc_ip.csr 167812 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_F_3_SET ns_noc_io_spio_soc_ip.csr 167823 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_N_V_3_SET ns_noc_io_spio_soc_ip.csr 167834 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_0_8_8_rivcs_i router_0_8_8_rivcs_i SPIO_NOC_ROUTER_0_8_8_RIVCS_I_ADDRESS SPIO_NOC_ROUTER_0_8_8_RIVCS_I_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OFFSET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 168164 R0_8 register rivcs_i 0x50028 R 0x00000000 Spio_noc_router_0_8_8_rivcs_i This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 167860 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_0_SET ns_noc_io_spio_soc_ip.csr 167874 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_0_SET ns_noc_io_spio_soc_ip.csr 167890 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_0_SET ns_noc_io_spio_soc_ip.csr 167904 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_0_SET ns_noc_io_spio_soc_ip.csr 167915 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_0_SET ns_noc_io_spio_soc_ip.csr 167926 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 167939 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_1_SET ns_noc_io_spio_soc_ip.csr 167953 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_1_SET ns_noc_io_spio_soc_ip.csr 167969 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_1_SET ns_noc_io_spio_soc_ip.csr 167983 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_1_SET ns_noc_io_spio_soc_ip.csr 167994 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_1_SET ns_noc_io_spio_soc_ip.csr 168005 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 168018 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_2_SET ns_noc_io_spio_soc_ip.csr 168032 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_2_SET ns_noc_io_spio_soc_ip.csr 168048 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_2_SET ns_noc_io_spio_soc_ip.csr 168062 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_2_SET ns_noc_io_spio_soc_ip.csr 168073 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_2_SET ns_noc_io_spio_soc_ip.csr 168084 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 168097 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_UP_3_SET ns_noc_io_spio_soc_ip.csr 168111 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_S_3_SET ns_noc_io_spio_soc_ip.csr 168127 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_B_3_SET ns_noc_io_spio_soc_ip.csr 168141 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_F_3_SET ns_noc_io_spio_soc_ip.csr 168152 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_I_V_3_SET ns_noc_io_spio_soc_ip.csr 168163 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_0_8_8_rivcs_j router_0_8_8_rivcs_j SPIO_NOC_ROUTER_0_8_8_RIVCS_J_ADDRESS SPIO_NOC_ROUTER_0_8_8_RIVCS_J_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OFFSET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 168493 R0_8 register rivcs_j 0x50030 R 0x00000000 Spio_noc_router_0_8_8_rivcs_j This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 168189 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_0_SET ns_noc_io_spio_soc_ip.csr 168203 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_0_SET ns_noc_io_spio_soc_ip.csr 168219 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_0_SET ns_noc_io_spio_soc_ip.csr 168233 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_0_SET ns_noc_io_spio_soc_ip.csr 168244 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_0_SET ns_noc_io_spio_soc_ip.csr 168255 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 168268 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_1_SET ns_noc_io_spio_soc_ip.csr 168282 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_1_SET ns_noc_io_spio_soc_ip.csr 168298 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_1_SET ns_noc_io_spio_soc_ip.csr 168312 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_1_SET ns_noc_io_spio_soc_ip.csr 168323 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_1_SET ns_noc_io_spio_soc_ip.csr 168334 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 168347 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_2_SET ns_noc_io_spio_soc_ip.csr 168361 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_2_SET ns_noc_io_spio_soc_ip.csr 168377 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_2_SET ns_noc_io_spio_soc_ip.csr 168391 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_2_SET ns_noc_io_spio_soc_ip.csr 168402 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_2_SET ns_noc_io_spio_soc_ip.csr 168413 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 168426 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_UP_3_SET ns_noc_io_spio_soc_ip.csr 168440 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_S_3_SET ns_noc_io_spio_soc_ip.csr 168456 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_B_3_SET ns_noc_io_spio_soc_ip.csr 168470 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_F_3_SET ns_noc_io_spio_soc_ip.csr 168481 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_J_V_3_SET ns_noc_io_spio_soc_ip.csr 168492 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_0_8_8_rivcs_k router_0_8_8_rivcs_k SPIO_NOC_ROUTER_0_8_8_RIVCS_K_ADDRESS SPIO_NOC_ROUTER_0_8_8_RIVCS_K_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OFFSET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 168822 R0_8 register rivcs_k 0x50038 R 0x00000000 Spio_noc_router_0_8_8_rivcs_k This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 168518 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_0_SET ns_noc_io_spio_soc_ip.csr 168532 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_0_SET ns_noc_io_spio_soc_ip.csr 168548 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_0_SET ns_noc_io_spio_soc_ip.csr 168562 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_0_SET ns_noc_io_spio_soc_ip.csr 168573 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_0_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_0_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_0_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_0_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_0_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_0_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_0_SET ns_noc_io_spio_soc_ip.csr 168584 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 168597 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_1_SET ns_noc_io_spio_soc_ip.csr 168611 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_1_SET ns_noc_io_spio_soc_ip.csr 168627 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_1_SET ns_noc_io_spio_soc_ip.csr 168641 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_1_SET ns_noc_io_spio_soc_ip.csr 168652 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_1_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_1_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_1_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_1_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_1_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_1_SET ns_noc_io_spio_soc_ip.csr 168663 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 168676 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_2_SET ns_noc_io_spio_soc_ip.csr 168690 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_2_SET ns_noc_io_spio_soc_ip.csr 168706 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_2_SET ns_noc_io_spio_soc_ip.csr 168720 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_2_SET ns_noc_io_spio_soc_ip.csr 168731 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_2_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_2_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_2_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_2_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_2_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_2_SET ns_noc_io_spio_soc_ip.csr 168742 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 168755 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_UP_3_SET ns_noc_io_spio_soc_ip.csr 168769 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_S_3_SET ns_noc_io_spio_soc_ip.csr 168785 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_B_3_SET ns_noc_io_spio_soc_ip.csr 168799 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_F_3_SET ns_noc_io_spio_soc_ip.csr 168810 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_3_MSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_3_LSB SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_3_RANGE SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_3_RESET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_3_GET SPIO_NOC_ROUTER_0_8_8_RIVCS_K_V_3_SET ns_noc_io_spio_soc_ip.csr 168821 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_0_8_8_rovcs_h router_0_8_8_rovcs_h SPIO_NOC_ROUTER_0_8_8_ROVCS_H_ADDRESS SPIO_NOC_ROUTER_0_8_8_ROVCS_H_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_ROVCS_H_OFFSET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 169083 R0_8 register rovcs_h 0x50040 R 0x00000101 Spio_noc_router_0_8_8_rovcs_h This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_0_SET ns_noc_io_spio_soc_ip.csr 168846 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_0_SET ns_noc_io_spio_soc_ip.csr 168860 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_0_SET ns_noc_io_spio_soc_ip.csr 168875 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_0_SET ns_noc_io_spio_soc_ip.csr 168886 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 168896 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_1_SET ns_noc_io_spio_soc_ip.csr 168908 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x1 R CE_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_1_SET ns_noc_io_spio_soc_ip.csr 168922 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_1_SET ns_noc_io_spio_soc_ip.csr 168937 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_1_SET ns_noc_io_spio_soc_ip.csr 168948 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 168958 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_2_SET ns_noc_io_spio_soc_ip.csr 168970 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_2_SET ns_noc_io_spio_soc_ip.csr 168984 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_2_SET ns_noc_io_spio_soc_ip.csr 168999 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_2_SET ns_noc_io_spio_soc_ip.csr 169010 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 169020 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CF_3_SET ns_noc_io_spio_soc_ip.csr 169032 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_CE_3_SET ns_noc_io_spio_soc_ip.csr 169046 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_VB_3_SET ns_noc_io_spio_soc_ip.csr 169061 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_RSV_3_SET ns_noc_io_spio_soc_ip.csr 169072 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_H_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 169082 UNSD_3 31 28 0x0 R register spio_noc.router_0_8_8_rovcs_w router_0_8_8_rovcs_w SPIO_NOC_ROUTER_0_8_8_ROVCS_W_ADDRESS SPIO_NOC_ROUTER_0_8_8_ROVCS_W_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_ROVCS_W_OFFSET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 169344 R0_8 register rovcs_w 0x50058 R 0x00000001 Spio_noc_router_0_8_8_rovcs_w This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_0_SET ns_noc_io_spio_soc_ip.csr 169107 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_0_SET ns_noc_io_spio_soc_ip.csr 169121 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_0_SET ns_noc_io_spio_soc_ip.csr 169136 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_0_SET ns_noc_io_spio_soc_ip.csr 169147 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 169157 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_1_SET ns_noc_io_spio_soc_ip.csr 169169 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_1_SET ns_noc_io_spio_soc_ip.csr 169183 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_1_SET ns_noc_io_spio_soc_ip.csr 169198 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_1_SET ns_noc_io_spio_soc_ip.csr 169209 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 169219 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_2_SET ns_noc_io_spio_soc_ip.csr 169231 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_2_SET ns_noc_io_spio_soc_ip.csr 169245 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_2_SET ns_noc_io_spio_soc_ip.csr 169260 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_2_SET ns_noc_io_spio_soc_ip.csr 169271 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 169281 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CF_3_SET ns_noc_io_spio_soc_ip.csr 169293 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_CE_3_SET ns_noc_io_spio_soc_ip.csr 169307 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_VB_3_SET ns_noc_io_spio_soc_ip.csr 169322 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_RSV_3_SET ns_noc_io_spio_soc_ip.csr 169333 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_W_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 169343 UNSD_3 31 28 0x0 R register spio_noc.router_0_8_8_rovcs_n router_0_8_8_rovcs_n SPIO_NOC_ROUTER_0_8_8_ROVCS_N_ADDRESS SPIO_NOC_ROUTER_0_8_8_ROVCS_N_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_ROVCS_N_OFFSET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 169605 R0_8 register rovcs_n 0x50060 R 0x00000101 Spio_noc_router_0_8_8_rovcs_n This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_0_SET ns_noc_io_spio_soc_ip.csr 169368 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_0_SET ns_noc_io_spio_soc_ip.csr 169382 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_0_SET ns_noc_io_spio_soc_ip.csr 169397 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_0_SET ns_noc_io_spio_soc_ip.csr 169408 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 169418 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_1_SET ns_noc_io_spio_soc_ip.csr 169430 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x1 R CE_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_1_SET ns_noc_io_spio_soc_ip.csr 169444 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_1_SET ns_noc_io_spio_soc_ip.csr 169459 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_1_SET ns_noc_io_spio_soc_ip.csr 169470 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 169480 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_2_SET ns_noc_io_spio_soc_ip.csr 169492 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_2_SET ns_noc_io_spio_soc_ip.csr 169506 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_2_SET ns_noc_io_spio_soc_ip.csr 169521 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_2_SET ns_noc_io_spio_soc_ip.csr 169532 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 169542 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CF_3_SET ns_noc_io_spio_soc_ip.csr 169554 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_CE_3_SET ns_noc_io_spio_soc_ip.csr 169568 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_VB_3_SET ns_noc_io_spio_soc_ip.csr 169583 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_RSV_3_SET ns_noc_io_spio_soc_ip.csr 169594 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_N_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 169604 UNSD_3 31 28 0x0 R register spio_noc.router_0_8_8_rovcs_i router_0_8_8_rovcs_i SPIO_NOC_ROUTER_0_8_8_ROVCS_I_ADDRESS SPIO_NOC_ROUTER_0_8_8_ROVCS_I_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_ROVCS_I_OFFSET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 169866 R0_8 register rovcs_i 0x50068 R 0x00000101 Spio_noc_router_0_8_8_rovcs_i This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_0_SET ns_noc_io_spio_soc_ip.csr 169629 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_0_SET ns_noc_io_spio_soc_ip.csr 169643 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_0_SET ns_noc_io_spio_soc_ip.csr 169658 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_0_SET ns_noc_io_spio_soc_ip.csr 169669 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 169679 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_1_SET ns_noc_io_spio_soc_ip.csr 169691 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x1 R CE_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_1_SET ns_noc_io_spio_soc_ip.csr 169705 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_1_SET ns_noc_io_spio_soc_ip.csr 169720 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_1_SET ns_noc_io_spio_soc_ip.csr 169731 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 169741 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_2_SET ns_noc_io_spio_soc_ip.csr 169753 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_2_SET ns_noc_io_spio_soc_ip.csr 169767 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_2_SET ns_noc_io_spio_soc_ip.csr 169782 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_2_SET ns_noc_io_spio_soc_ip.csr 169793 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 169803 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CF_3_SET ns_noc_io_spio_soc_ip.csr 169815 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_CE_3_SET ns_noc_io_spio_soc_ip.csr 169829 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_VB_3_SET ns_noc_io_spio_soc_ip.csr 169844 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_RSV_3_SET ns_noc_io_spio_soc_ip.csr 169855 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_I_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 169865 UNSD_3 31 28 0x0 R register spio_noc.router_0_8_8_rovcs_j router_0_8_8_rovcs_j SPIO_NOC_ROUTER_0_8_8_ROVCS_J_ADDRESS SPIO_NOC_ROUTER_0_8_8_ROVCS_J_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_ROVCS_J_OFFSET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 170127 R0_8 register rovcs_j 0x50070 R 0x00000101 Spio_noc_router_0_8_8_rovcs_j This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_0_SET ns_noc_io_spio_soc_ip.csr 169890 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_0_SET ns_noc_io_spio_soc_ip.csr 169904 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_0_SET ns_noc_io_spio_soc_ip.csr 169919 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_0_SET ns_noc_io_spio_soc_ip.csr 169930 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 169940 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_1_SET ns_noc_io_spio_soc_ip.csr 169952 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x1 R CE_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_1_SET ns_noc_io_spio_soc_ip.csr 169966 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_1_SET ns_noc_io_spio_soc_ip.csr 169981 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_1_SET ns_noc_io_spio_soc_ip.csr 169992 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 170002 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_2_SET ns_noc_io_spio_soc_ip.csr 170014 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_2_SET ns_noc_io_spio_soc_ip.csr 170028 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_2_SET ns_noc_io_spio_soc_ip.csr 170043 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_2_SET ns_noc_io_spio_soc_ip.csr 170054 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 170064 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CF_3_SET ns_noc_io_spio_soc_ip.csr 170076 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_CE_3_SET ns_noc_io_spio_soc_ip.csr 170090 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_VB_3_SET ns_noc_io_spio_soc_ip.csr 170105 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_RSV_3_SET ns_noc_io_spio_soc_ip.csr 170116 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_J_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 170126 UNSD_3 31 28 0x0 R register spio_noc.router_0_8_8_rovcs_k router_0_8_8_rovcs_k SPIO_NOC_ROUTER_0_8_8_ROVCS_K_ADDRESS SPIO_NOC_ROUTER_0_8_8_ROVCS_K_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_ROVCS_K_OFFSET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 170388 R0_8 register rovcs_k 0x50078 R 0x00000101 Spio_noc_router_0_8_8_rovcs_k This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_0_SET ns_noc_io_spio_soc_ip.csr 170151 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_0_SET ns_noc_io_spio_soc_ip.csr 170165 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_0_SET ns_noc_io_spio_soc_ip.csr 170180 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_0_SET ns_noc_io_spio_soc_ip.csr 170191 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_0_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_0_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_0_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_0_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_0_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_0_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 170201 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_1_SET ns_noc_io_spio_soc_ip.csr 170213 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x1 R CE_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_1_SET ns_noc_io_spio_soc_ip.csr 170227 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_1_SET ns_noc_io_spio_soc_ip.csr 170242 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_1_SET ns_noc_io_spio_soc_ip.csr 170253 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_1_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_1_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_1_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_1_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_1_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_1_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 170263 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_2_SET ns_noc_io_spio_soc_ip.csr 170275 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_2_SET ns_noc_io_spio_soc_ip.csr 170289 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_2_SET ns_noc_io_spio_soc_ip.csr 170304 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_2_SET ns_noc_io_spio_soc_ip.csr 170315 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_2_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_2_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_2_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_2_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_2_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_2_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 170325 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CF_3_SET ns_noc_io_spio_soc_ip.csr 170337 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_CE_3_SET ns_noc_io_spio_soc_ip.csr 170351 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_VB_3_SET ns_noc_io_spio_soc_ip.csr 170366 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_RSV_3_SET ns_noc_io_spio_soc_ip.csr 170377 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_3_WIDTH SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_3_MSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_3_LSB SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_3_RANGE SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_3_RESET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_3_GET SPIO_NOC_ROUTER_0_8_8_ROVCS_K_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 170387 UNSD_3 31 28 0x0 R register spio_noc.router_0_8_8_re router_0_8_8_re SPIO_NOC_ROUTER_0_8_8_RE_ADDRESS SPIO_NOC_ROUTER_0_8_8_RE_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_RE_OFFSET SPIO_NOC_ROUTER_0_8_8_RE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 170562 R0_8 register re 0x50080 R/W 0x00000000 Spio_noc_router_0_8_8_re This register tracks the interrupt or error events that can occur in the router. The only interrupt event is the event counter overflow. This register is readable, and can be cleared by performing a write with the write data bits set to 0 for the bits that should be cleared. false false false false OVFI SPIO_NOC_ROUTER_0_8_8_RE_OVFI_WIDTH SPIO_NOC_ROUTER_0_8_8_RE_OVFI_MSB SPIO_NOC_ROUTER_0_8_8_RE_OVFI_LSB SPIO_NOC_ROUTER_0_8_8_RE_OVFI_RANGE SPIO_NOC_ROUTER_0_8_8_RE_OVFI_RESET SPIO_NOC_ROUTER_0_8_8_RE_OVFI_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RE_OVFI_GET SPIO_NOC_ROUTER_0_8_8_RE_OVFI_SET ns_noc_io_spio_soc_ip.csr 170414 OVFI 1'b1: In this status bit indicates that the router input event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 0 0 0x0 R/W CSR_PARERR SPIO_NOC_ROUTER_0_8_8_RE_CSR_PARERR_WIDTH SPIO_NOC_ROUTER_0_8_8_RE_CSR_PARERR_MSB SPIO_NOC_ROUTER_0_8_8_RE_CSR_PARERR_LSB SPIO_NOC_ROUTER_0_8_8_RE_CSR_PARERR_RANGE SPIO_NOC_ROUTER_0_8_8_RE_CSR_PARERR_RESET SPIO_NOC_ROUTER_0_8_8_RE_CSR_PARERR_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RE_CSR_PARERR_GET SPIO_NOC_ROUTER_0_8_8_RE_CSR_PARERR_SET ns_noc_io_spio_soc_ip.csr 170425 CSR_PARERR 1'b1: Parity error in config/status registers 1 1 0x0 R/W OVFO SPIO_NOC_ROUTER_0_8_8_RE_OVFO_WIDTH SPIO_NOC_ROUTER_0_8_8_RE_OVFO_MSB SPIO_NOC_ROUTER_0_8_8_RE_OVFO_LSB SPIO_NOC_ROUTER_0_8_8_RE_OVFO_RANGE SPIO_NOC_ROUTER_0_8_8_RE_OVFO_RESET SPIO_NOC_ROUTER_0_8_8_RE_OVFO_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RE_OVFO_GET SPIO_NOC_ROUTER_0_8_8_RE_OVFO_SET ns_noc_io_spio_soc_ip.csr 170439 OVFO 1'b1: In this status bit indicates that the router output event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 2 2 0x0 R/W UNSD_7_3 SPIO_NOC_ROUTER_0_8_8_RE_UNSD_7_3_WIDTH SPIO_NOC_ROUTER_0_8_8_RE_UNSD_7_3_MSB SPIO_NOC_ROUTER_0_8_8_RE_UNSD_7_3_LSB SPIO_NOC_ROUTER_0_8_8_RE_UNSD_7_3_RANGE SPIO_NOC_ROUTER_0_8_8_RE_UNSD_7_3_RESET SPIO_NOC_ROUTER_0_8_8_RE_UNSD_7_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RE_UNSD_7_3_GET SPIO_NOC_ROUTER_0_8_8_RE_UNSD_7_3_SET ns_noc_io_spio_soc_ip.csr 170450 UNSD_7_3 7 3 0x00 R PGE SPIO_NOC_ROUTER_0_8_8_RE_PGE_WIDTH SPIO_NOC_ROUTER_0_8_8_RE_PGE_MSB SPIO_NOC_ROUTER_0_8_8_RE_PGE_LSB SPIO_NOC_ROUTER_0_8_8_RE_PGE_RANGE SPIO_NOC_ROUTER_0_8_8_RE_PGE_RESET SPIO_NOC_ROUTER_0_8_8_RE_PGE_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RE_PGE_GET SPIO_NOC_ROUTER_0_8_8_RE_PGE_SET ns_noc_io_spio_soc_ip.csr 170462 PGE 1'b1: Power gating error, traffic received after router commited to power down 8 8 0x0 R/W NLU SPIO_NOC_ROUTER_0_8_8_RE_NLU_WIDTH SPIO_NOC_ROUTER_0_8_8_RE_NLU_MSB SPIO_NOC_ROUTER_0_8_8_RE_NLU_LSB SPIO_NOC_ROUTER_0_8_8_RE_NLU_RANGE SPIO_NOC_ROUTER_0_8_8_RE_NLU_RESET SPIO_NOC_ROUTER_0_8_8_RE_NLU_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RE_NLU_GET SPIO_NOC_ROUTER_0_8_8_RE_NLU_SET ns_noc_io_spio_soc_ip.csr 170473 NLU 1'b1: Traffic destined for North link which is unavailable 9 9 0x0 R/W ELU SPIO_NOC_ROUTER_0_8_8_RE_ELU_WIDTH SPIO_NOC_ROUTER_0_8_8_RE_ELU_MSB SPIO_NOC_ROUTER_0_8_8_RE_ELU_LSB SPIO_NOC_ROUTER_0_8_8_RE_ELU_RANGE SPIO_NOC_ROUTER_0_8_8_RE_ELU_RESET SPIO_NOC_ROUTER_0_8_8_RE_ELU_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RE_ELU_GET SPIO_NOC_ROUTER_0_8_8_RE_ELU_SET ns_noc_io_spio_soc_ip.csr 170484 ELU 1'b1: Traffic destined for East link which is unavailable 10 10 0x0 R/W WLU SPIO_NOC_ROUTER_0_8_8_RE_WLU_WIDTH SPIO_NOC_ROUTER_0_8_8_RE_WLU_MSB SPIO_NOC_ROUTER_0_8_8_RE_WLU_LSB SPIO_NOC_ROUTER_0_8_8_RE_WLU_RANGE SPIO_NOC_ROUTER_0_8_8_RE_WLU_RESET SPIO_NOC_ROUTER_0_8_8_RE_WLU_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RE_WLU_GET SPIO_NOC_ROUTER_0_8_8_RE_WLU_SET ns_noc_io_spio_soc_ip.csr 170495 WLU 1'b1: Traffic destined for West link which is unavailable 11 11 0x0 R/W SLU SPIO_NOC_ROUTER_0_8_8_RE_SLU_WIDTH SPIO_NOC_ROUTER_0_8_8_RE_SLU_MSB SPIO_NOC_ROUTER_0_8_8_RE_SLU_LSB SPIO_NOC_ROUTER_0_8_8_RE_SLU_RANGE SPIO_NOC_ROUTER_0_8_8_RE_SLU_RESET SPIO_NOC_ROUTER_0_8_8_RE_SLU_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RE_SLU_GET SPIO_NOC_ROUTER_0_8_8_RE_SLU_SET ns_noc_io_spio_soc_ip.csr 170506 SLU 1'b1: Traffic destined for South link which is unavailable 12 12 0x0 R/W HLU SPIO_NOC_ROUTER_0_8_8_RE_HLU_WIDTH SPIO_NOC_ROUTER_0_8_8_RE_HLU_MSB SPIO_NOC_ROUTER_0_8_8_RE_HLU_LSB SPIO_NOC_ROUTER_0_8_8_RE_HLU_RANGE SPIO_NOC_ROUTER_0_8_8_RE_HLU_RESET SPIO_NOC_ROUTER_0_8_8_RE_HLU_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RE_HLU_GET SPIO_NOC_ROUTER_0_8_8_RE_HLU_SET ns_noc_io_spio_soc_ip.csr 170517 HLU 1'b1: Traffic destined for H link which is unavailable 13 13 0x0 R/W ILU SPIO_NOC_ROUTER_0_8_8_RE_ILU_WIDTH SPIO_NOC_ROUTER_0_8_8_RE_ILU_MSB SPIO_NOC_ROUTER_0_8_8_RE_ILU_LSB SPIO_NOC_ROUTER_0_8_8_RE_ILU_RANGE SPIO_NOC_ROUTER_0_8_8_RE_ILU_RESET SPIO_NOC_ROUTER_0_8_8_RE_ILU_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RE_ILU_GET SPIO_NOC_ROUTER_0_8_8_RE_ILU_SET ns_noc_io_spio_soc_ip.csr 170528 ILU 1'b1: Traffic destined for I link which is unavailable 14 14 0x0 R/W JLU SPIO_NOC_ROUTER_0_8_8_RE_JLU_WIDTH SPIO_NOC_ROUTER_0_8_8_RE_JLU_MSB SPIO_NOC_ROUTER_0_8_8_RE_JLU_LSB SPIO_NOC_ROUTER_0_8_8_RE_JLU_RANGE SPIO_NOC_ROUTER_0_8_8_RE_JLU_RESET SPIO_NOC_ROUTER_0_8_8_RE_JLU_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RE_JLU_GET SPIO_NOC_ROUTER_0_8_8_RE_JLU_SET ns_noc_io_spio_soc_ip.csr 170539 JLU 1'b1: Traffic destined for J link which is unavailable 15 15 0x0 R/W KLU SPIO_NOC_ROUTER_0_8_8_RE_KLU_WIDTH SPIO_NOC_ROUTER_0_8_8_RE_KLU_MSB SPIO_NOC_ROUTER_0_8_8_RE_KLU_LSB SPIO_NOC_ROUTER_0_8_8_RE_KLU_RANGE SPIO_NOC_ROUTER_0_8_8_RE_KLU_RESET SPIO_NOC_ROUTER_0_8_8_RE_KLU_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RE_KLU_GET SPIO_NOC_ROUTER_0_8_8_RE_KLU_SET ns_noc_io_spio_soc_ip.csr 170550 KLU 1'b1: Traffic destined for K link which is unavailable 16 16 0x0 R/W UNSD_31_14 SPIO_NOC_ROUTER_0_8_8_RE_UNSD_31_14_WIDTH SPIO_NOC_ROUTER_0_8_8_RE_UNSD_31_14_MSB SPIO_NOC_ROUTER_0_8_8_RE_UNSD_31_14_LSB SPIO_NOC_ROUTER_0_8_8_RE_UNSD_31_14_RANGE SPIO_NOC_ROUTER_0_8_8_RE_UNSD_31_14_RESET SPIO_NOC_ROUTER_0_8_8_RE_UNSD_31_14_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RE_UNSD_31_14_GET SPIO_NOC_ROUTER_0_8_8_RE_UNSD_31_14_SET ns_noc_io_spio_soc_ip.csr 170561 UNSD_31_14 31 17 0x0000 R register spio_noc.router_0_8_8_rem router_0_8_8_rem SPIO_NOC_ROUTER_0_8_8_REM_ADDRESS SPIO_NOC_ROUTER_0_8_8_REM_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_REM_OFFSET SPIO_NOC_ROUTER_0_8_8_REM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 170735 R0_8 register rem 0x50088 R/W 0x0001fe00 Spio_noc_router_0_8_8_rem This register is used to select whether the interrupt events in the Router Event Interrupt Status register should send an interrupt when asserted. If the corresponding bit is set to 1, an interrupt will not be sent. This register can be read and written to. false false false false OVFIM SPIO_NOC_ROUTER_0_8_8_REM_OVFIM_WIDTH SPIO_NOC_ROUTER_0_8_8_REM_OVFIM_MSB SPIO_NOC_ROUTER_0_8_8_REM_OVFIM_LSB SPIO_NOC_ROUTER_0_8_8_REM_OVFIM_RANGE SPIO_NOC_ROUTER_0_8_8_REM_OVFIM_RESET SPIO_NOC_ROUTER_0_8_8_REM_OVFIM_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_REM_OVFIM_GET SPIO_NOC_ROUTER_0_8_8_REM_OVFIM_SET ns_noc_io_spio_soc_ip.csr 170588 OVFIM 1'b1: Masks or disables an interrupt from being generated by the input event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 0 0 0x0 R/W CSR_PARERRM SPIO_NOC_ROUTER_0_8_8_REM_CSR_PARERRM_WIDTH SPIO_NOC_ROUTER_0_8_8_REM_CSR_PARERRM_MSB SPIO_NOC_ROUTER_0_8_8_REM_CSR_PARERRM_LSB SPIO_NOC_ROUTER_0_8_8_REM_CSR_PARERRM_RANGE SPIO_NOC_ROUTER_0_8_8_REM_CSR_PARERRM_RESET SPIO_NOC_ROUTER_0_8_8_REM_CSR_PARERRM_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_REM_CSR_PARERRM_GET SPIO_NOC_ROUTER_0_8_8_REM_CSR_PARERRM_SET ns_noc_io_spio_soc_ip.csr 170599 CSR_PARERRM 1'b1: Mask CSR parity error interrupt 1 1 0x0 R/W OVFOM SPIO_NOC_ROUTER_0_8_8_REM_OVFOM_WIDTH SPIO_NOC_ROUTER_0_8_8_REM_OVFOM_MSB SPIO_NOC_ROUTER_0_8_8_REM_OVFOM_LSB SPIO_NOC_ROUTER_0_8_8_REM_OVFOM_RANGE SPIO_NOC_ROUTER_0_8_8_REM_OVFOM_RESET SPIO_NOC_ROUTER_0_8_8_REM_OVFOM_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_REM_OVFOM_GET SPIO_NOC_ROUTER_0_8_8_REM_OVFOM_SET ns_noc_io_spio_soc_ip.csr 170613 OVFOM 1'b1: Masks or disables an interrupt from being generated by the output event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 2 2 0x0 R/W UNSD_7_3 SPIO_NOC_ROUTER_0_8_8_REM_UNSD_7_3_WIDTH SPIO_NOC_ROUTER_0_8_8_REM_UNSD_7_3_MSB SPIO_NOC_ROUTER_0_8_8_REM_UNSD_7_3_LSB SPIO_NOC_ROUTER_0_8_8_REM_UNSD_7_3_RANGE SPIO_NOC_ROUTER_0_8_8_REM_UNSD_7_3_RESET SPIO_NOC_ROUTER_0_8_8_REM_UNSD_7_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_REM_UNSD_7_3_GET SPIO_NOC_ROUTER_0_8_8_REM_UNSD_7_3_SET ns_noc_io_spio_soc_ip.csr 170624 UNSD_7_3 7 3 0x00 R PGM SPIO_NOC_ROUTER_0_8_8_REM_PGM_WIDTH SPIO_NOC_ROUTER_0_8_8_REM_PGM_MSB SPIO_NOC_ROUTER_0_8_8_REM_PGM_LSB SPIO_NOC_ROUTER_0_8_8_REM_PGM_RANGE SPIO_NOC_ROUTER_0_8_8_REM_PGM_RESET SPIO_NOC_ROUTER_0_8_8_REM_PGM_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_REM_PGM_GET SPIO_NOC_ROUTER_0_8_8_REM_PGM_SET ns_noc_io_spio_soc_ip.csr 170635 PGM 1'b1: Mask PGE error interrupt 8 8 0x0 R/W MN SPIO_NOC_ROUTER_0_8_8_REM_MN_WIDTH SPIO_NOC_ROUTER_0_8_8_REM_MN_MSB SPIO_NOC_ROUTER_0_8_8_REM_MN_LSB SPIO_NOC_ROUTER_0_8_8_REM_MN_RANGE SPIO_NOC_ROUTER_0_8_8_REM_MN_RESET SPIO_NOC_ROUTER_0_8_8_REM_MN_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_REM_MN_GET SPIO_NOC_ROUTER_0_8_8_REM_MN_SET ns_noc_io_spio_soc_ip.csr 170646 MN 1'b1: Mask NLU error interrupt 9 9 0x1 R/W ME SPIO_NOC_ROUTER_0_8_8_REM_ME_WIDTH SPIO_NOC_ROUTER_0_8_8_REM_ME_MSB SPIO_NOC_ROUTER_0_8_8_REM_ME_LSB SPIO_NOC_ROUTER_0_8_8_REM_ME_RANGE SPIO_NOC_ROUTER_0_8_8_REM_ME_RESET SPIO_NOC_ROUTER_0_8_8_REM_ME_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_REM_ME_GET SPIO_NOC_ROUTER_0_8_8_REM_ME_SET ns_noc_io_spio_soc_ip.csr 170657 ME 1'b1: Mask ELU error interrupt 10 10 0x1 R/W MW SPIO_NOC_ROUTER_0_8_8_REM_MW_WIDTH SPIO_NOC_ROUTER_0_8_8_REM_MW_MSB SPIO_NOC_ROUTER_0_8_8_REM_MW_LSB SPIO_NOC_ROUTER_0_8_8_REM_MW_RANGE SPIO_NOC_ROUTER_0_8_8_REM_MW_RESET SPIO_NOC_ROUTER_0_8_8_REM_MW_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_REM_MW_GET SPIO_NOC_ROUTER_0_8_8_REM_MW_SET ns_noc_io_spio_soc_ip.csr 170668 MW 1'b1: Mask WLU error interrupt 11 11 0x1 R/W MS SPIO_NOC_ROUTER_0_8_8_REM_MS_WIDTH SPIO_NOC_ROUTER_0_8_8_REM_MS_MSB SPIO_NOC_ROUTER_0_8_8_REM_MS_LSB SPIO_NOC_ROUTER_0_8_8_REM_MS_RANGE SPIO_NOC_ROUTER_0_8_8_REM_MS_RESET SPIO_NOC_ROUTER_0_8_8_REM_MS_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_REM_MS_GET SPIO_NOC_ROUTER_0_8_8_REM_MS_SET ns_noc_io_spio_soc_ip.csr 170679 MS 1'b1: Mask SLU error interrupt 12 12 0x1 R/W MH SPIO_NOC_ROUTER_0_8_8_REM_MH_WIDTH SPIO_NOC_ROUTER_0_8_8_REM_MH_MSB SPIO_NOC_ROUTER_0_8_8_REM_MH_LSB SPIO_NOC_ROUTER_0_8_8_REM_MH_RANGE SPIO_NOC_ROUTER_0_8_8_REM_MH_RESET SPIO_NOC_ROUTER_0_8_8_REM_MH_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_REM_MH_GET SPIO_NOC_ROUTER_0_8_8_REM_MH_SET ns_noc_io_spio_soc_ip.csr 170690 MH 1'b1: Mask HLU error interrupt 13 13 0x1 R/W MI SPIO_NOC_ROUTER_0_8_8_REM_MI_WIDTH SPIO_NOC_ROUTER_0_8_8_REM_MI_MSB SPIO_NOC_ROUTER_0_8_8_REM_MI_LSB SPIO_NOC_ROUTER_0_8_8_REM_MI_RANGE SPIO_NOC_ROUTER_0_8_8_REM_MI_RESET SPIO_NOC_ROUTER_0_8_8_REM_MI_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_REM_MI_GET SPIO_NOC_ROUTER_0_8_8_REM_MI_SET ns_noc_io_spio_soc_ip.csr 170701 MI 1'b1: Mask ILU error interrupt 14 14 0x1 R/W MJ SPIO_NOC_ROUTER_0_8_8_REM_MJ_WIDTH SPIO_NOC_ROUTER_0_8_8_REM_MJ_MSB SPIO_NOC_ROUTER_0_8_8_REM_MJ_LSB SPIO_NOC_ROUTER_0_8_8_REM_MJ_RANGE SPIO_NOC_ROUTER_0_8_8_REM_MJ_RESET SPIO_NOC_ROUTER_0_8_8_REM_MJ_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_REM_MJ_GET SPIO_NOC_ROUTER_0_8_8_REM_MJ_SET ns_noc_io_spio_soc_ip.csr 170712 MJ 1'b1: Mask JLU error interrupt 15 15 0x1 R/W MK SPIO_NOC_ROUTER_0_8_8_REM_MK_WIDTH SPIO_NOC_ROUTER_0_8_8_REM_MK_MSB SPIO_NOC_ROUTER_0_8_8_REM_MK_LSB SPIO_NOC_ROUTER_0_8_8_REM_MK_RANGE SPIO_NOC_ROUTER_0_8_8_REM_MK_RESET SPIO_NOC_ROUTER_0_8_8_REM_MK_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_REM_MK_GET SPIO_NOC_ROUTER_0_8_8_REM_MK_SET ns_noc_io_spio_soc_ip.csr 170723 MK 1'b1: Mask KLU error interrupt 16 16 0x1 R/W UNSD_31_14 SPIO_NOC_ROUTER_0_8_8_REM_UNSD_31_14_WIDTH SPIO_NOC_ROUTER_0_8_8_REM_UNSD_31_14_MSB SPIO_NOC_ROUTER_0_8_8_REM_UNSD_31_14_LSB SPIO_NOC_ROUTER_0_8_8_REM_UNSD_31_14_RANGE SPIO_NOC_ROUTER_0_8_8_REM_UNSD_31_14_RESET SPIO_NOC_ROUTER_0_8_8_REM_UNSD_31_14_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_REM_UNSD_31_14_GET SPIO_NOC_ROUTER_0_8_8_REM_UNSD_31_14_SET ns_noc_io_spio_soc_ip.csr 170734 UNSD_31_14 31 17 0x0000 R register spio_noc.router_0_8_8_recc router_0_8_8_recc SPIO_NOC_ROUTER_0_8_8_RECC_ADDRESS SPIO_NOC_ROUTER_0_8_8_RECC_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_RECC_OFFSET SPIO_NOC_ROUTER_0_8_8_RECC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 170820 R0_8 register recc 0x50090 R/W 0x00000000 Spio_noc_router_0_8_8_recc This register is used to select which hardware events will increment the event counter. false false false false IVC SPIO_NOC_ROUTER_0_8_8_RECC_IVC_WIDTH SPIO_NOC_ROUTER_0_8_8_RECC_IVC_MSB SPIO_NOC_ROUTER_0_8_8_RECC_IVC_LSB SPIO_NOC_ROUTER_0_8_8_RECC_IVC_RANGE SPIO_NOC_ROUTER_0_8_8_RECC_IVC_RESET SPIO_NOC_ROUTER_0_8_8_RECC_IVC_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RECC_IVC_GET SPIO_NOC_ROUTER_0_8_8_RECC_IVC_SET ns_noc_io_spio_soc_ip.csr 170756 IVC 11: Input VC 3 10: Input VC 2 01: Input VC 1 00: Input VC 0 1 0 0x0 R/W UNSD_3_2 SPIO_NOC_ROUTER_0_8_8_RECC_UNSD_3_2_WIDTH SPIO_NOC_ROUTER_0_8_8_RECC_UNSD_3_2_MSB SPIO_NOC_ROUTER_0_8_8_RECC_UNSD_3_2_LSB SPIO_NOC_ROUTER_0_8_8_RECC_UNSD_3_2_RANGE SPIO_NOC_ROUTER_0_8_8_RECC_UNSD_3_2_RESET SPIO_NOC_ROUTER_0_8_8_RECC_UNSD_3_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RECC_UNSD_3_2_GET SPIO_NOC_ROUTER_0_8_8_RECC_UNSD_3_2_SET ns_noc_io_spio_soc_ip.csr 170767 UNSD_3_2 3 2 0x0 R INP SPIO_NOC_ROUTER_0_8_8_RECC_INP_WIDTH SPIO_NOC_ROUTER_0_8_8_RECC_INP_MSB SPIO_NOC_ROUTER_0_8_8_RECC_INP_LSB SPIO_NOC_ROUTER_0_8_8_RECC_INP_RANGE SPIO_NOC_ROUTER_0_8_8_RECC_INP_RESET SPIO_NOC_ROUTER_0_8_8_RECC_INP_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RECC_INP_GET SPIO_NOC_ROUTER_0_8_8_RECC_INP_SET ns_noc_io_spio_soc_ip.csr 170778 INP Input port on which the event is captured 6 4 0x0 R/W UNSD_7_7 SPIO_NOC_ROUTER_0_8_8_RECC_UNSD_7_7_WIDTH SPIO_NOC_ROUTER_0_8_8_RECC_UNSD_7_7_MSB SPIO_NOC_ROUTER_0_8_8_RECC_UNSD_7_7_LSB SPIO_NOC_ROUTER_0_8_8_RECC_UNSD_7_7_RANGE SPIO_NOC_ROUTER_0_8_8_RECC_UNSD_7_7_RESET SPIO_NOC_ROUTER_0_8_8_RECC_UNSD_7_7_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RECC_UNSD_7_7_GET SPIO_NOC_ROUTER_0_8_8_RECC_UNSD_7_7_SET ns_noc_io_spio_soc_ip.csr 170789 UNSD_7_7 7 7 0x0 R EVT SPIO_NOC_ROUTER_0_8_8_RECC_EVT_WIDTH SPIO_NOC_ROUTER_0_8_8_RECC_EVT_MSB SPIO_NOC_ROUTER_0_8_8_RECC_EVT_LSB SPIO_NOC_ROUTER_0_8_8_RECC_EVT_RANGE SPIO_NOC_ROUTER_0_8_8_RECC_EVT_RESET SPIO_NOC_ROUTER_0_8_8_RECC_EVT_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RECC_EVT_GET SPIO_NOC_ROUTER_0_8_8_RECC_EVT_SET ns_noc_io_spio_soc_ip.csr 170808 EVT 11: Generates count event when VC has valid data, but is stalled 10: Generates count event on every flit received for the selected input port and selected input VCs, this can be used to count total flits received on a router input port 01: Generates count event on every EOP received for the selected input port and selected input VCs, this can be used to count packets received on a router input port 00: Disable 9 8 0x0 R/W UNSD_31_10 SPIO_NOC_ROUTER_0_8_8_RECC_UNSD_31_10_WIDTH SPIO_NOC_ROUTER_0_8_8_RECC_UNSD_31_10_MSB SPIO_NOC_ROUTER_0_8_8_RECC_UNSD_31_10_LSB SPIO_NOC_ROUTER_0_8_8_RECC_UNSD_31_10_RANGE SPIO_NOC_ROUTER_0_8_8_RECC_UNSD_31_10_RESET SPIO_NOC_ROUTER_0_8_8_RECC_UNSD_31_10_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RECC_UNSD_31_10_GET SPIO_NOC_ROUTER_0_8_8_RECC_UNSD_31_10_SET ns_noc_io_spio_soc_ip.csr 170819 UNSD_31_10 31 10 0x000000 R register spio_noc.router_0_8_8_rec router_0_8_8_rec SPIO_NOC_ROUTER_0_8_8_REC_ADDRESS SPIO_NOC_ROUTER_0_8_8_REC_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_REC_OFFSET SPIO_NOC_ROUTER_0_8_8_REC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 170845 R0_8 register rec 0x50098 R/W 0x00000000 Spio_noc_router_0_8_8_rec This register holds the event counter. The value can be read to determine the current count value. The value can be written to initialize the counter. When events trigger a count, the counter will increment. When the counter increments at its highest value, it will roll over to zero and the overflow will mark the Router Event Interrupt Status register, which could trigger an interrupt. false false false false EVENT_CNTR SPIO_NOC_ROUTER_0_8_8_REC_EVENT_CNTR_WIDTH SPIO_NOC_ROUTER_0_8_8_REC_EVENT_CNTR_MSB SPIO_NOC_ROUTER_0_8_8_REC_EVENT_CNTR_LSB SPIO_NOC_ROUTER_0_8_8_REC_EVENT_CNTR_RANGE SPIO_NOC_ROUTER_0_8_8_REC_EVENT_CNTR_RESET SPIO_NOC_ROUTER_0_8_8_REC_EVENT_CNTR_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_REC_EVENT_CNTR_GET SPIO_NOC_ROUTER_0_8_8_REC_EVENT_CNTR_SET ns_noc_io_spio_soc_ip.csr 170844 EVENT_CNTR 32'bit event incrementing counter. Rollover from 32'hFFFFF -> 32'd0 sets the rollover status bit RE 31 0 0x00000000 R/W register spio_noc.router_0_8_8_id router_0_8_8_id SPIO_NOC_ROUTER_0_8_8_ID_ADDRESS SPIO_NOC_ROUTER_0_8_8_ID_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_ID_OFFSET SPIO_NOC_ROUTER_0_8_8_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 170914 R0_8 register id 0x500A0 R 0x010000e0 Spio_noc_router_0_8_8_id This register holds layer and position information for the router. It is a read-only register. It can be used for debugging software access to the NoC elements by confirming that a read has successfully targeted the correct NoC element. false false false false LAYER SPIO_NOC_ROUTER_0_8_8_ID_LAYER_WIDTH SPIO_NOC_ROUTER_0_8_8_ID_LAYER_MSB SPIO_NOC_ROUTER_0_8_8_ID_LAYER_LSB SPIO_NOC_ROUTER_0_8_8_ID_LAYER_RANGE SPIO_NOC_ROUTER_0_8_8_ID_LAYER_RESET SPIO_NOC_ROUTER_0_8_8_ID_LAYER_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ID_LAYER_GET SPIO_NOC_ROUTER_0_8_8_ID_LAYER_SET ns_noc_io_spio_soc_ip.csr 170870 LAYER 5-bit identifier of the NoC layer on which this router is located 4 0 0x00 R POS SPIO_NOC_ROUTER_0_8_8_ID_POS_WIDTH SPIO_NOC_ROUTER_0_8_8_ID_POS_MSB SPIO_NOC_ROUTER_0_8_8_ID_POS_LSB SPIO_NOC_ROUTER_0_8_8_ID_POS_RANGE SPIO_NOC_ROUTER_0_8_8_ID_POS_RESET SPIO_NOC_ROUTER_0_8_8_ID_POS_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ID_POS_GET SPIO_NOC_ROUTER_0_8_8_ID_POS_SET ns_noc_io_spio_soc_ip.csr 170881 POS 16-bit position ID of this router in the NoC 20 5 0x0007 R ZERO SPIO_NOC_ROUTER_0_8_8_ID_ZERO_WIDTH SPIO_NOC_ROUTER_0_8_8_ID_ZERO_MSB SPIO_NOC_ROUTER_0_8_8_ID_ZERO_LSB SPIO_NOC_ROUTER_0_8_8_ID_ZERO_RANGE SPIO_NOC_ROUTER_0_8_8_ID_ZERO_RESET SPIO_NOC_ROUTER_0_8_8_ID_ZERO_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ID_ZERO_GET SPIO_NOC_ROUTER_0_8_8_ID_ZERO_SET ns_noc_io_spio_soc_ip.csr 170892 ZERO Zeroes 23 21 0x0 R ONE SPIO_NOC_ROUTER_0_8_8_ID_ONE_WIDTH SPIO_NOC_ROUTER_0_8_8_ID_ONE_MSB SPIO_NOC_ROUTER_0_8_8_ID_ONE_LSB SPIO_NOC_ROUTER_0_8_8_ID_ONE_RANGE SPIO_NOC_ROUTER_0_8_8_ID_ONE_RESET SPIO_NOC_ROUTER_0_8_8_ID_ONE_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ID_ONE_GET SPIO_NOC_ROUTER_0_8_8_ID_ONE_SET ns_noc_io_spio_soc_ip.csr 170903 ONE One 24 24 0x1 R UNSD_31_25 SPIO_NOC_ROUTER_0_8_8_ID_UNSD_31_25_WIDTH SPIO_NOC_ROUTER_0_8_8_ID_UNSD_31_25_MSB SPIO_NOC_ROUTER_0_8_8_ID_UNSD_31_25_LSB SPIO_NOC_ROUTER_0_8_8_ID_UNSD_31_25_RANGE SPIO_NOC_ROUTER_0_8_8_ID_UNSD_31_25_RESET SPIO_NOC_ROUTER_0_8_8_ID_UNSD_31_25_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ID_UNSD_31_25_GET SPIO_NOC_ROUTER_0_8_8_ID_UNSD_31_25_SET ns_noc_io_spio_soc_ip.csr 170913 UNSD_31_25 31 25 0x00 R register spio_noc.router_0_8_8_rcgc router_0_8_8_rcgc SPIO_NOC_ROUTER_0_8_8_RCGC_ADDRESS SPIO_NOC_ROUTER_0_8_8_RCGC_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_RCGC_OFFSET SPIO_NOC_ROUTER_0_8_8_RCGC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 170940 R0_8 register rcgc 0x500A8 R/W 0x00000064 Spio_noc_router_0_8_8_rcgc Programmable interval used by coarse clock gating logic in routers.This count determines the consecutive number of idle cycle after which a router output port initiates coarse clock gating of the local port clock and de-asserts the 'busy' signal to the downstream router. This signal indicates inactivity to the downstream router and allows it to initiate coarse clock gating of its corresponding input port. false false false false HYSTERESIS_COUNTER SPIO_NOC_ROUTER_0_8_8_RCGC_HYSTERESIS_COUNTER_WIDTH SPIO_NOC_ROUTER_0_8_8_RCGC_HYSTERESIS_COUNTER_MSB SPIO_NOC_ROUTER_0_8_8_RCGC_HYSTERESIS_COUNTER_LSB SPIO_NOC_ROUTER_0_8_8_RCGC_HYSTERESIS_COUNTER_RANGE SPIO_NOC_ROUTER_0_8_8_RCGC_HYSTERESIS_COUNTER_RESET SPIO_NOC_ROUTER_0_8_8_RCGC_HYSTERESIS_COUNTER_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RCGC_HYSTERESIS_COUNTER_GET SPIO_NOC_ROUTER_0_8_8_RCGC_HYSTERESIS_COUNTER_SET ns_noc_io_spio_soc_ip.csr 170939 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W register spio_noc.router_0_8_8_rcgo router_0_8_8_rcgo SPIO_NOC_ROUTER_0_8_8_RCGO_ADDRESS SPIO_NOC_ROUTER_0_8_8_RCGO_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_RCGO_OFFSET SPIO_NOC_ROUTER_0_8_8_RCGO_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 170979 R0_8 register rcgo 0x500B0 R/W 0x00000000 Spio_noc_router_0_8_8_rcgo This register is used by coarse grained clock gating logic. This register can be set to override coarse clock gating for the entire router. Coarse clock gating for selective routers can be overridden by locally setting this register, if the user does not want incur and aggregate coarse clock gating cycle penalty over a "fast path/critical path" through the NoC. false false false false FPO SPIO_NOC_ROUTER_0_8_8_RCGO_FPO_WIDTH SPIO_NOC_ROUTER_0_8_8_RCGO_FPO_MSB SPIO_NOC_ROUTER_0_8_8_RCGO_FPO_LSB SPIO_NOC_ROUTER_0_8_8_RCGO_FPO_RANGE SPIO_NOC_ROUTER_0_8_8_RCGO_FPO_RESET SPIO_NOC_ROUTER_0_8_8_RCGO_FPO_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RCGO_FPO_GET SPIO_NOC_ROUTER_0_8_8_RCGO_FPO_SET ns_noc_io_spio_soc_ip.csr 170967 FPO 1'b1: Coarse clock gating is locally disabled (for fast path) 1'b0: Coarse clock gating is locally enabled 0 0 0x0 R/W UNSD_31_1 SPIO_NOC_ROUTER_0_8_8_RCGO_UNSD_31_1_WIDTH SPIO_NOC_ROUTER_0_8_8_RCGO_UNSD_31_1_MSB SPIO_NOC_ROUTER_0_8_8_RCGO_UNSD_31_1_LSB SPIO_NOC_ROUTER_0_8_8_RCGO_UNSD_31_1_RANGE SPIO_NOC_ROUTER_0_8_8_RCGO_UNSD_31_1_RESET SPIO_NOC_ROUTER_0_8_8_RCGO_UNSD_31_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_RCGO_UNSD_31_1_GET SPIO_NOC_ROUTER_0_8_8_RCGO_UNSD_31_1_SET ns_noc_io_spio_soc_ip.csr 170978 UNSD_31_1 31 1 0x00000000 R register spio_noc.router_0_8_8_p0_rperr router_0_8_8_p0_rperr SPIO_NOC_ROUTER_0_8_8_P0_RPERR_ADDRESS SPIO_NOC_ROUTER_0_8_8_P0_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_P0_RPERR_OFFSET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 171270 R0_8 register p0_rperr 0x500B8 R/W 0x00000000 Spio_noc_router_0_8_8_p0_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 171022 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 171033 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 171044 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 171055 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_8_8_P0_RPERR_CR_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERR_CR_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_CR_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_CR_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERR_CR_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERR_CR_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 171066 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_8_8_P0_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 171077 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_0_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_0_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_0_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_0_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_0_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 171088 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_0_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_0_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_0_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_0_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 171099 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_0_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_0_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_0_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_0_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 171111 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_0_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_0_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_0_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_0_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 171122 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_1_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_1_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_1_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_1_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_1_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 171134 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_1_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_1_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_1_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_1_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 171146 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_1_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_1_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_1_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_1_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 171159 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_1_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_1_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_1_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_1_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 171171 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_2_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_2_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_2_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_2_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_2_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 171183 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_2_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_2_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_2_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_2_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 171195 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_2_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_2_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_2_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_2_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 171208 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_2_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_2_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_2_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_2_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 171220 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_3_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_3_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_3_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_3_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_3_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 171232 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_3_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_3_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_3_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_3_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 171244 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_3_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_3_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_3_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_3_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 171257 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_3_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_3_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_3_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_3_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 171269 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_0_8_8_p2_rperr router_0_8_8_p2_rperr SPIO_NOC_ROUTER_0_8_8_P2_RPERR_ADDRESS SPIO_NOC_ROUTER_0_8_8_P2_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_P2_RPERR_OFFSET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 171557 R0_8 register p2_rperr 0x500C8 R/W 0x00000000 Spio_noc_router_0_8_8_p2_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 171313 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 171324 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 171335 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 171346 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_8_8_P2_RPERR_CR_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERR_CR_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_CR_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_CR_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERR_CR_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERR_CR_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 171357 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_8_8_P2_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 171368 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_0_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_0_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_0_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_0_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_0_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 171379 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_0_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_0_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_0_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_0_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 171390 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_0_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_0_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_0_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_0_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 171402 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_0_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_0_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_0_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_0_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 171413 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_1_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_1_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_1_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_1_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_1_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 171424 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_1_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_1_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_1_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_1_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 171435 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_1_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_1_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_1_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_1_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 171447 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_1_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_1_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_1_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_1_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 171458 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_2_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_2_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_2_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_2_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_2_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 171470 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_2_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_2_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_2_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_2_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 171482 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_2_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_2_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_2_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_2_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 171495 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_2_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_2_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_2_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_2_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 171507 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_3_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_3_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_3_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_3_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_3_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 171519 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_3_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_3_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_3_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_3_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 171531 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_3_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_3_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_3_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_3_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 171544 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_3_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_3_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_3_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_3_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 171556 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_0_8_8_p4_rperr router_0_8_8_p4_rperr SPIO_NOC_ROUTER_0_8_8_P4_RPERR_ADDRESS SPIO_NOC_ROUTER_0_8_8_P4_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_P4_RPERR_OFFSET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 171848 R0_8 register p4_rperr 0x500D8 R/W 0x00000000 Spio_noc_router_0_8_8_p4_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 171600 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 171611 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 171622 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 171633 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_8_8_P4_RPERR_CR_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERR_CR_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_CR_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_CR_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERR_CR_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERR_CR_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 171644 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_8_8_P4_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 171655 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_0_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_0_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_0_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_0_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_0_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 171666 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_0_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_0_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_0_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_0_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 171677 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_0_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_0_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_0_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_0_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 171689 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_0_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_0_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_0_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_0_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 171700 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_1_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_1_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_1_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_1_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_1_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 171712 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_1_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_1_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_1_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_1_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 171724 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_1_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_1_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_1_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_1_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 171737 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_1_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_1_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_1_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_1_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 171749 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_2_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_2_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_2_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_2_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_2_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 171761 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_2_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_2_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_2_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_2_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 171773 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_2_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_2_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_2_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_2_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 171786 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_2_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_2_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_2_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_2_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 171798 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_3_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_3_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_3_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_3_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_3_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 171810 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_3_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_3_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_3_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_3_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 171822 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_3_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_3_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_3_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_3_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 171835 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_3_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_3_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_3_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_3_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 171847 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_0_8_8_p5_rperr router_0_8_8_p5_rperr SPIO_NOC_ROUTER_0_8_8_P5_RPERR_ADDRESS SPIO_NOC_ROUTER_0_8_8_P5_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_P5_RPERR_OFFSET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 172139 R0_8 register p5_rperr 0x500E0 R/W 0x00000000 Spio_noc_router_0_8_8_p5_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 171891 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 171902 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 171913 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 171924 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_8_8_P5_RPERR_CR_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERR_CR_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_CR_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_CR_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERR_CR_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERR_CR_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 171935 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_8_8_P5_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 171946 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_0_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_0_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_0_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_0_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_0_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 171957 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_0_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_0_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_0_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_0_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 171968 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_0_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_0_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_0_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_0_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 171980 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_0_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_0_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_0_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_0_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 171991 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_1_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_1_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_1_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_1_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_1_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 172003 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_1_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_1_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_1_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_1_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 172015 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_1_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_1_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_1_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_1_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 172028 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_1_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_1_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_1_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_1_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 172040 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_2_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_2_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_2_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_2_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_2_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 172052 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_2_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_2_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_2_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_2_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 172064 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_2_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_2_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_2_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_2_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 172077 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_2_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_2_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_2_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_2_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 172089 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_3_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_3_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_3_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_3_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_3_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 172101 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_3_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_3_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_3_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_3_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 172113 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_3_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_3_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_3_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_3_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 172126 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_3_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_3_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_3_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_3_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 172138 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_0_8_8_p6_rperr router_0_8_8_p6_rperr SPIO_NOC_ROUTER_0_8_8_P6_RPERR_ADDRESS SPIO_NOC_ROUTER_0_8_8_P6_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_P6_RPERR_OFFSET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 172430 R0_8 register p6_rperr 0x500E8 R/W 0x00000000 Spio_noc_router_0_8_8_p6_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 172182 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 172193 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 172204 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 172215 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_8_8_P6_RPERR_CR_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERR_CR_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_CR_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_CR_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERR_CR_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERR_CR_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 172226 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_8_8_P6_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 172237 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_0_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_0_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_0_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_0_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_0_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 172248 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_0_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_0_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_0_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_0_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 172259 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_0_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_0_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_0_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_0_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 172271 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_0_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_0_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_0_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_0_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 172282 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_1_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_1_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_1_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_1_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_1_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 172294 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_1_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_1_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_1_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_1_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 172306 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_1_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_1_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_1_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_1_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 172319 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_1_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_1_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_1_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_1_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 172331 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_2_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_2_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_2_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_2_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_2_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 172343 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_2_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_2_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_2_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_2_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 172355 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_2_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_2_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_2_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_2_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 172368 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_2_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_2_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_2_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_2_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 172380 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_3_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_3_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_3_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_3_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_3_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 172392 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_3_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_3_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_3_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_3_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 172404 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_3_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_3_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_3_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_3_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 172417 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_3_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_3_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_3_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_3_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 172429 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_0_8_8_p7_rperr router_0_8_8_p7_rperr SPIO_NOC_ROUTER_0_8_8_P7_RPERR_ADDRESS SPIO_NOC_ROUTER_0_8_8_P7_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_P7_RPERR_OFFSET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 172721 R0_8 register p7_rperr 0x500F0 R/W 0x00000000 Spio_noc_router_0_8_8_p7_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 172473 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 172484 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 172495 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 172506 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_8_8_P7_RPERR_CR_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERR_CR_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_CR_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_CR_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERR_CR_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERR_CR_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 172517 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_8_8_P7_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 172528 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_0_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_0_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_0_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_0_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_0_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 172539 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_0_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_0_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_0_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_0_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 172550 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_0_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_0_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_0_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_0_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 172562 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_0_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_0_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_0_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_0_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 172573 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_1_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_1_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_1_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_1_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_1_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 172585 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_1_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_1_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_1_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_1_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 172597 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_1_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_1_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_1_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_1_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 172610 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_1_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_1_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_1_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_1_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 172622 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_2_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_2_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_2_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_2_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_2_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 172634 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_2_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_2_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_2_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_2_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 172646 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_2_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_2_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_2_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_2_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 172659 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_2_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_2_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_2_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_2_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 172671 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_3_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_3_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_3_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_3_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_3_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 172683 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_3_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_3_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_3_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_3_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 172695 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_3_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_3_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_3_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_3_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 172708 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_3_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_3_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_3_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_3_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 172720 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_0_8_8_p0_rperrm router_0_8_8_p0_rperrm SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_ADDRESS SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_OFFSET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 172979 R0_8 register p0_rperrm 0x500F8 R/W 0x00000000 Spio_noc_router_0_8_8_p0_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 172743 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 172754 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 172765 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 172776 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_CR_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_CR_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_CR_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_CR_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_CR_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 172787 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 172798 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_0_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_0_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_0_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_0_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 172809 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_0_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 172820 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_0_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 172832 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_0_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 172843 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_1_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_1_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_1_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_1_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 172854 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_1_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 172865 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_1_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 172877 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_1_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 172888 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_2_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_2_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_2_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_2_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 172899 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_2_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 172910 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_2_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 172922 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_2_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 172933 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_3_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_3_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_3_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_3_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 172944 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_3_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 172955 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_3_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 172967 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_3_GET SPIO_NOC_ROUTER_0_8_8_P0_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 172978 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_0_8_8_p2_rperrm router_0_8_8_p2_rperrm SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_ADDRESS SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_OFFSET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 173237 R0_8 register p2_rperrm 0x50108 R/W 0x00000000 Spio_noc_router_0_8_8_p2_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 173001 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 173012 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 173023 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 173034 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_CR_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_CR_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_CR_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_CR_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_CR_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 173045 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 173056 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_0_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_0_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_0_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_0_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 173067 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_0_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 173078 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_0_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 173090 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_0_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 173101 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_1_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_1_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_1_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_1_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 173112 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_1_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 173123 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_1_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 173135 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_1_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 173146 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_2_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_2_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_2_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_2_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 173157 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_2_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 173168 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_2_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 173180 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_2_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 173191 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_3_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_3_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_3_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_3_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 173202 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_3_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 173213 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_3_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 173225 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_3_GET SPIO_NOC_ROUTER_0_8_8_P2_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 173236 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_0_8_8_p4_rperrm router_0_8_8_p4_rperrm SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_ADDRESS SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_OFFSET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 173495 R0_8 register p4_rperrm 0x50118 R/W 0x00000000 Spio_noc_router_0_8_8_p4_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 173259 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 173270 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 173281 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 173292 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_CR_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_CR_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_CR_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_CR_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_CR_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 173303 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 173314 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_0_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_0_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_0_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_0_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 173325 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_0_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 173336 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_0_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 173348 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_0_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 173359 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_1_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_1_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_1_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_1_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 173370 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_1_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 173381 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_1_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 173393 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_1_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 173404 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_2_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_2_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_2_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_2_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 173415 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_2_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 173426 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_2_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 173438 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_2_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 173449 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_3_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_3_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_3_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_3_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 173460 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_3_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 173471 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_3_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 173483 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_3_GET SPIO_NOC_ROUTER_0_8_8_P4_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 173494 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_0_8_8_p5_rperrm router_0_8_8_p5_rperrm SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_ADDRESS SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_OFFSET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 173753 R0_8 register p5_rperrm 0x50120 R/W 0x00000000 Spio_noc_router_0_8_8_p5_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 173517 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 173528 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 173539 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 173550 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_CR_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_CR_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_CR_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_CR_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_CR_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 173561 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 173572 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_0_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_0_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_0_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_0_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 173583 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_0_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 173594 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_0_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 173606 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_0_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 173617 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_1_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_1_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_1_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_1_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 173628 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_1_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 173639 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_1_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 173651 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_1_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 173662 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_2_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_2_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_2_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_2_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 173673 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_2_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 173684 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_2_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 173696 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_2_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 173707 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_3_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_3_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_3_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_3_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 173718 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_3_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 173729 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_3_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 173741 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_3_GET SPIO_NOC_ROUTER_0_8_8_P5_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 173752 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_0_8_8_p6_rperrm router_0_8_8_p6_rperrm SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_ADDRESS SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_OFFSET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 174011 R0_8 register p6_rperrm 0x50128 R/W 0x00000000 Spio_noc_router_0_8_8_p6_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 173775 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 173786 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 173797 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 173808 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_CR_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_CR_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_CR_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_CR_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_CR_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 173819 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 173830 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_0_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_0_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_0_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_0_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 173841 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_0_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 173852 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_0_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 173864 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_0_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 173875 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_1_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_1_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_1_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_1_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 173886 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_1_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 173897 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_1_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 173909 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_1_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 173920 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_2_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_2_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_2_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_2_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 173931 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_2_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 173942 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_2_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 173954 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_2_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 173965 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_3_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_3_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_3_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_3_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 173976 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_3_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 173987 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_3_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 173999 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_3_GET SPIO_NOC_ROUTER_0_8_8_P6_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 174010 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_0_8_8_p7_rperrm router_0_8_8_p7_rperrm SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_ADDRESS SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_OFFSET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 174269 R0_8 register p7_rperrm 0x50130 R/W 0x00000000 Spio_noc_router_0_8_8_p7_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 174033 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 174044 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 174055 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 174066 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_CR_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_CR_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_CR_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_CR_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_CR_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 174077 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 174088 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_0_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_0_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_0_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_0_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 174099 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_0_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 174110 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_0_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 174122 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_0_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 174133 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_1_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_1_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_1_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_1_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 174144 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_1_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 174155 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_1_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 174167 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_1_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 174178 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_2_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_2_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_2_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_2_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 174189 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_2_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 174200 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_2_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 174212 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_2_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 174223 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_3_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_3_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_3_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_3_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 174234 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_3_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 174245 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_3_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 174257 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_3_GET SPIO_NOC_ROUTER_0_8_8_P7_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 174268 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_0_8_8_roecc router_0_8_8_roecc SPIO_NOC_ROUTER_0_8_8_ROECC_ADDRESS SPIO_NOC_ROUTER_0_8_8_ROECC_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_ROECC_OFFSET SPIO_NOC_ROUTER_0_8_8_ROECC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 174342 R0_8 register roecc 0x50138 R/W 0x00000000 Spio_noc_router_0_8_8_roecc This register is used to select which hardware events will increment the output event counter. false false false false OVC SPIO_NOC_ROUTER_0_8_8_ROECC_OVC_WIDTH SPIO_NOC_ROUTER_0_8_8_ROECC_OVC_MSB SPIO_NOC_ROUTER_0_8_8_ROECC_OVC_LSB SPIO_NOC_ROUTER_0_8_8_ROECC_OVC_RANGE SPIO_NOC_ROUTER_0_8_8_ROECC_OVC_RESET SPIO_NOC_ROUTER_0_8_8_ROECC_OVC_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROECC_OVC_GET SPIO_NOC_ROUTER_0_8_8_ROECC_OVC_SET ns_noc_io_spio_soc_ip.csr 174287 OVC Bit map to select output VCs to monitor events on 3 0 0x0 R/W OP SPIO_NOC_ROUTER_0_8_8_ROECC_OP_WIDTH SPIO_NOC_ROUTER_0_8_8_ROECC_OP_MSB SPIO_NOC_ROUTER_0_8_8_ROECC_OP_LSB SPIO_NOC_ROUTER_0_8_8_ROECC_OP_RANGE SPIO_NOC_ROUTER_0_8_8_ROECC_OP_RESET SPIO_NOC_ROUTER_0_8_8_ROECC_OP_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROECC_OP_GET SPIO_NOC_ROUTER_0_8_8_ROECC_OP_SET ns_noc_io_spio_soc_ip.csr 174298 OP Output port on which the event is captured 6 4 0x0 R/W UNSD_7_7 SPIO_NOC_ROUTER_0_8_8_ROECC_UNSD_7_7_WIDTH SPIO_NOC_ROUTER_0_8_8_ROECC_UNSD_7_7_MSB SPIO_NOC_ROUTER_0_8_8_ROECC_UNSD_7_7_LSB SPIO_NOC_ROUTER_0_8_8_ROECC_UNSD_7_7_RANGE SPIO_NOC_ROUTER_0_8_8_ROECC_UNSD_7_7_RESET SPIO_NOC_ROUTER_0_8_8_ROECC_UNSD_7_7_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROECC_UNSD_7_7_GET SPIO_NOC_ROUTER_0_8_8_ROECC_UNSD_7_7_SET ns_noc_io_spio_soc_ip.csr 174309 UNSD_7_7 7 7 0x0 R EVT SPIO_NOC_ROUTER_0_8_8_ROECC_EVT_WIDTH SPIO_NOC_ROUTER_0_8_8_ROECC_EVT_MSB SPIO_NOC_ROUTER_0_8_8_ROECC_EVT_LSB SPIO_NOC_ROUTER_0_8_8_ROECC_EVT_RANGE SPIO_NOC_ROUTER_0_8_8_ROECC_EVT_RESET SPIO_NOC_ROUTER_0_8_8_ROECC_EVT_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROECC_EVT_GET SPIO_NOC_ROUTER_0_8_8_ROECC_EVT_SET ns_noc_io_spio_soc_ip.csr 174330 EVT 100: Port stalled. Input flits are available for the port, but no output VC has credit 011: Generates count event when flits are available to be sent to output VC, but the VC has no credit 010: Generates count event on every flit sent on the selected output port and selected outpt VCs, this can be used to count total flits sent on a router output port 001: Generates count event on every EOP sent on the selected output port and selected output VCs, this can be used to count packets sent on a router output port 000: Disable 10 8 0x0 R/W UNSD_31_11 SPIO_NOC_ROUTER_0_8_8_ROECC_UNSD_31_11_WIDTH SPIO_NOC_ROUTER_0_8_8_ROECC_UNSD_31_11_MSB SPIO_NOC_ROUTER_0_8_8_ROECC_UNSD_31_11_LSB SPIO_NOC_ROUTER_0_8_8_ROECC_UNSD_31_11_RANGE SPIO_NOC_ROUTER_0_8_8_ROECC_UNSD_31_11_RESET SPIO_NOC_ROUTER_0_8_8_ROECC_UNSD_31_11_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROECC_UNSD_31_11_GET SPIO_NOC_ROUTER_0_8_8_ROECC_UNSD_31_11_SET ns_noc_io_spio_soc_ip.csr 174341 UNSD_31_11 31 11 0x000000 R register spio_noc.router_0_8_8_roec router_0_8_8_roec SPIO_NOC_ROUTER_0_8_8_ROEC_ADDRESS SPIO_NOC_ROUTER_0_8_8_ROEC_BYTE_ADDRESS SPIO_NOC_ROUTER_0_8_8_ROEC_OFFSET SPIO_NOC_ROUTER_0_8_8_ROEC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 174367 R0_8 register roec 0x50140 R/W 0x00000000 Spio_noc_router_0_8_8_roec This register holds the output event counter. The value can be read to determine the current count value. The value can be written to initialize the counter. When events trigger a count, the counter will increment. When the counter increments at its highest value, it will roll over to zero and the overflow will mark the Router output Event Interrupt Status register, which could trigger an interrupt. false false false false EVENT_CNTR SPIO_NOC_ROUTER_0_8_8_ROEC_EVENT_CNTR_WIDTH SPIO_NOC_ROUTER_0_8_8_ROEC_EVENT_CNTR_MSB SPIO_NOC_ROUTER_0_8_8_ROEC_EVENT_CNTR_LSB SPIO_NOC_ROUTER_0_8_8_ROEC_EVENT_CNTR_RANGE SPIO_NOC_ROUTER_0_8_8_ROEC_EVENT_CNTR_RESET SPIO_NOC_ROUTER_0_8_8_ROEC_EVENT_CNTR_FIELD_MASK SPIO_NOC_ROUTER_0_8_8_ROEC_EVENT_CNTR_GET SPIO_NOC_ROUTER_0_8_8_ROEC_EVENT_CNTR_SET ns_noc_io_spio_soc_ip.csr 174366 EVENT_CNTR 32'bit event incrementing counter. Rollover from 32'hFFFFF -> 32'd0 sets the rollover status bit RE 31 0 0x00000000 R/W register spio_noc.router_1_6_6_rivcs_h router_1_6_6_rivcs_h SPIO_NOC_ROUTER_1_6_6_RIVCS_H_ADDRESS SPIO_NOC_ROUTER_1_6_6_RIVCS_H_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OFFSET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 174696 R1_6 register rivcs_h 0x54000 R 0x00000000 Spio_noc_router_1_6_6_rivcs_h This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 174392 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_0_SET ns_noc_io_spio_soc_ip.csr 174406 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_0_SET ns_noc_io_spio_soc_ip.csr 174422 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_0_SET ns_noc_io_spio_soc_ip.csr 174436 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_0_SET ns_noc_io_spio_soc_ip.csr 174447 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_0_SET ns_noc_io_spio_soc_ip.csr 174458 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 174471 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_1_SET ns_noc_io_spio_soc_ip.csr 174485 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_1_SET ns_noc_io_spio_soc_ip.csr 174501 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_1_SET ns_noc_io_spio_soc_ip.csr 174515 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_1_SET ns_noc_io_spio_soc_ip.csr 174526 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_1_SET ns_noc_io_spio_soc_ip.csr 174537 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 174550 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_2_SET ns_noc_io_spio_soc_ip.csr 174564 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_2_SET ns_noc_io_spio_soc_ip.csr 174580 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_2_SET ns_noc_io_spio_soc_ip.csr 174594 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_2_SET ns_noc_io_spio_soc_ip.csr 174605 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_2_SET ns_noc_io_spio_soc_ip.csr 174616 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 174629 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_UP_3_SET ns_noc_io_spio_soc_ip.csr 174643 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_S_3_SET ns_noc_io_spio_soc_ip.csr 174659 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_B_3_SET ns_noc_io_spio_soc_ip.csr 174673 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_F_3_SET ns_noc_io_spio_soc_ip.csr 174684 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_H_V_3_SET ns_noc_io_spio_soc_ip.csr 174695 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_1_6_6_rivcs_e router_1_6_6_rivcs_e SPIO_NOC_ROUTER_1_6_6_RIVCS_E_ADDRESS SPIO_NOC_ROUTER_1_6_6_RIVCS_E_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OFFSET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 175025 R1_6 register rivcs_e 0x54008 R 0x00000000 Spio_noc_router_1_6_6_rivcs_e This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 174721 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_0_SET ns_noc_io_spio_soc_ip.csr 174735 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_0_SET ns_noc_io_spio_soc_ip.csr 174751 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_0_SET ns_noc_io_spio_soc_ip.csr 174765 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_0_SET ns_noc_io_spio_soc_ip.csr 174776 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_0_SET ns_noc_io_spio_soc_ip.csr 174787 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 174800 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_1_SET ns_noc_io_spio_soc_ip.csr 174814 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_1_SET ns_noc_io_spio_soc_ip.csr 174830 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_1_SET ns_noc_io_spio_soc_ip.csr 174844 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_1_SET ns_noc_io_spio_soc_ip.csr 174855 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_1_SET ns_noc_io_spio_soc_ip.csr 174866 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 174879 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_2_SET ns_noc_io_spio_soc_ip.csr 174893 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_2_SET ns_noc_io_spio_soc_ip.csr 174909 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_2_SET ns_noc_io_spio_soc_ip.csr 174923 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_2_SET ns_noc_io_spio_soc_ip.csr 174934 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_2_SET ns_noc_io_spio_soc_ip.csr 174945 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 174958 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_UP_3_SET ns_noc_io_spio_soc_ip.csr 174972 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_S_3_SET ns_noc_io_spio_soc_ip.csr 174988 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_B_3_SET ns_noc_io_spio_soc_ip.csr 175002 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_F_3_SET ns_noc_io_spio_soc_ip.csr 175013 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_E_V_3_SET ns_noc_io_spio_soc_ip.csr 175024 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_1_6_6_rivcs_s router_1_6_6_rivcs_s SPIO_NOC_ROUTER_1_6_6_RIVCS_S_ADDRESS SPIO_NOC_ROUTER_1_6_6_RIVCS_S_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OFFSET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 175354 R1_6 register rivcs_s 0x54010 R 0x00000000 Spio_noc_router_1_6_6_rivcs_s This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 175050 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_0_SET ns_noc_io_spio_soc_ip.csr 175064 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_0_SET ns_noc_io_spio_soc_ip.csr 175080 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_0_SET ns_noc_io_spio_soc_ip.csr 175094 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_0_SET ns_noc_io_spio_soc_ip.csr 175105 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_0_SET ns_noc_io_spio_soc_ip.csr 175116 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 175129 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_1_SET ns_noc_io_spio_soc_ip.csr 175143 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_1_SET ns_noc_io_spio_soc_ip.csr 175159 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_1_SET ns_noc_io_spio_soc_ip.csr 175173 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_1_SET ns_noc_io_spio_soc_ip.csr 175184 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_1_SET ns_noc_io_spio_soc_ip.csr 175195 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 175208 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_2_SET ns_noc_io_spio_soc_ip.csr 175222 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_2_SET ns_noc_io_spio_soc_ip.csr 175238 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_2_SET ns_noc_io_spio_soc_ip.csr 175252 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_2_SET ns_noc_io_spio_soc_ip.csr 175263 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_2_SET ns_noc_io_spio_soc_ip.csr 175274 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 175287 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_UP_3_SET ns_noc_io_spio_soc_ip.csr 175301 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_S_3_SET ns_noc_io_spio_soc_ip.csr 175317 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_B_3_SET ns_noc_io_spio_soc_ip.csr 175331 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_F_3_SET ns_noc_io_spio_soc_ip.csr 175342 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_S_V_3_SET ns_noc_io_spio_soc_ip.csr 175353 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_1_6_6_rivcs_w router_1_6_6_rivcs_w SPIO_NOC_ROUTER_1_6_6_RIVCS_W_ADDRESS SPIO_NOC_ROUTER_1_6_6_RIVCS_W_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OFFSET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 175683 R1_6 register rivcs_w 0x54018 R 0x00000000 Spio_noc_router_1_6_6_rivcs_w This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 175379 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_0_SET ns_noc_io_spio_soc_ip.csr 175393 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_0_SET ns_noc_io_spio_soc_ip.csr 175409 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_0_SET ns_noc_io_spio_soc_ip.csr 175423 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_0_SET ns_noc_io_spio_soc_ip.csr 175434 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_0_SET ns_noc_io_spio_soc_ip.csr 175445 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 175458 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_1_SET ns_noc_io_spio_soc_ip.csr 175472 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_1_SET ns_noc_io_spio_soc_ip.csr 175488 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_1_SET ns_noc_io_spio_soc_ip.csr 175502 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_1_SET ns_noc_io_spio_soc_ip.csr 175513 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_1_SET ns_noc_io_spio_soc_ip.csr 175524 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 175537 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_2_SET ns_noc_io_spio_soc_ip.csr 175551 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_2_SET ns_noc_io_spio_soc_ip.csr 175567 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_2_SET ns_noc_io_spio_soc_ip.csr 175581 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_2_SET ns_noc_io_spio_soc_ip.csr 175592 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_2_SET ns_noc_io_spio_soc_ip.csr 175603 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 175616 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_UP_3_SET ns_noc_io_spio_soc_ip.csr 175630 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_S_3_SET ns_noc_io_spio_soc_ip.csr 175646 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_B_3_SET ns_noc_io_spio_soc_ip.csr 175660 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_F_3_SET ns_noc_io_spio_soc_ip.csr 175671 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_W_V_3_SET ns_noc_io_spio_soc_ip.csr 175682 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_1_6_6_rivcs_n router_1_6_6_rivcs_n SPIO_NOC_ROUTER_1_6_6_RIVCS_N_ADDRESS SPIO_NOC_ROUTER_1_6_6_RIVCS_N_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OFFSET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 176012 R1_6 register rivcs_n 0x54020 R 0x00000000 Spio_noc_router_1_6_6_rivcs_n This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 175708 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_0_SET ns_noc_io_spio_soc_ip.csr 175722 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_0_SET ns_noc_io_spio_soc_ip.csr 175738 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_0_SET ns_noc_io_spio_soc_ip.csr 175752 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_0_SET ns_noc_io_spio_soc_ip.csr 175763 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_0_SET ns_noc_io_spio_soc_ip.csr 175774 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 175787 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_1_SET ns_noc_io_spio_soc_ip.csr 175801 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_1_SET ns_noc_io_spio_soc_ip.csr 175817 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_1_SET ns_noc_io_spio_soc_ip.csr 175831 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_1_SET ns_noc_io_spio_soc_ip.csr 175842 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_1_SET ns_noc_io_spio_soc_ip.csr 175853 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 175866 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_2_SET ns_noc_io_spio_soc_ip.csr 175880 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_2_SET ns_noc_io_spio_soc_ip.csr 175896 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_2_SET ns_noc_io_spio_soc_ip.csr 175910 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_2_SET ns_noc_io_spio_soc_ip.csr 175921 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_2_SET ns_noc_io_spio_soc_ip.csr 175932 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 175945 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_UP_3_SET ns_noc_io_spio_soc_ip.csr 175959 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_S_3_SET ns_noc_io_spio_soc_ip.csr 175975 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_B_3_SET ns_noc_io_spio_soc_ip.csr 175989 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_F_3_SET ns_noc_io_spio_soc_ip.csr 176000 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_N_V_3_SET ns_noc_io_spio_soc_ip.csr 176011 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_1_6_6_rivcs_i router_1_6_6_rivcs_i SPIO_NOC_ROUTER_1_6_6_RIVCS_I_ADDRESS SPIO_NOC_ROUTER_1_6_6_RIVCS_I_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OFFSET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 176341 R1_6 register rivcs_i 0x54028 R 0x00000000 Spio_noc_router_1_6_6_rivcs_i This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 176037 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_0_SET ns_noc_io_spio_soc_ip.csr 176051 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_0_SET ns_noc_io_spio_soc_ip.csr 176067 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_0_SET ns_noc_io_spio_soc_ip.csr 176081 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_0_SET ns_noc_io_spio_soc_ip.csr 176092 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_0_SET ns_noc_io_spio_soc_ip.csr 176103 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 176116 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_1_SET ns_noc_io_spio_soc_ip.csr 176130 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_1_SET ns_noc_io_spio_soc_ip.csr 176146 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_1_SET ns_noc_io_spio_soc_ip.csr 176160 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_1_SET ns_noc_io_spio_soc_ip.csr 176171 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_1_SET ns_noc_io_spio_soc_ip.csr 176182 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 176195 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_2_SET ns_noc_io_spio_soc_ip.csr 176209 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_2_SET ns_noc_io_spio_soc_ip.csr 176225 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_2_SET ns_noc_io_spio_soc_ip.csr 176239 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_2_SET ns_noc_io_spio_soc_ip.csr 176250 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_2_SET ns_noc_io_spio_soc_ip.csr 176261 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 176274 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_UP_3_SET ns_noc_io_spio_soc_ip.csr 176288 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_S_3_SET ns_noc_io_spio_soc_ip.csr 176304 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_B_3_SET ns_noc_io_spio_soc_ip.csr 176318 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_F_3_SET ns_noc_io_spio_soc_ip.csr 176329 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_I_V_3_SET ns_noc_io_spio_soc_ip.csr 176340 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_1_6_6_rivcs_j router_1_6_6_rivcs_j SPIO_NOC_ROUTER_1_6_6_RIVCS_J_ADDRESS SPIO_NOC_ROUTER_1_6_6_RIVCS_J_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OFFSET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 176670 R1_6 register rivcs_j 0x54030 R 0x00000000 Spio_noc_router_1_6_6_rivcs_j This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 176366 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_0_SET ns_noc_io_spio_soc_ip.csr 176380 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_0_SET ns_noc_io_spio_soc_ip.csr 176396 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_0_SET ns_noc_io_spio_soc_ip.csr 176410 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_0_SET ns_noc_io_spio_soc_ip.csr 176421 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_0_SET ns_noc_io_spio_soc_ip.csr 176432 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 176445 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_1_SET ns_noc_io_spio_soc_ip.csr 176459 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_1_SET ns_noc_io_spio_soc_ip.csr 176475 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_1_SET ns_noc_io_spio_soc_ip.csr 176489 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_1_SET ns_noc_io_spio_soc_ip.csr 176500 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_1_SET ns_noc_io_spio_soc_ip.csr 176511 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 176524 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_2_SET ns_noc_io_spio_soc_ip.csr 176538 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_2_SET ns_noc_io_spio_soc_ip.csr 176554 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_2_SET ns_noc_io_spio_soc_ip.csr 176568 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_2_SET ns_noc_io_spio_soc_ip.csr 176579 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_2_SET ns_noc_io_spio_soc_ip.csr 176590 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 176603 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_UP_3_SET ns_noc_io_spio_soc_ip.csr 176617 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_S_3_SET ns_noc_io_spio_soc_ip.csr 176633 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_B_3_SET ns_noc_io_spio_soc_ip.csr 176647 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_F_3_SET ns_noc_io_spio_soc_ip.csr 176658 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_J_V_3_SET ns_noc_io_spio_soc_ip.csr 176669 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_1_6_6_rivcs_k router_1_6_6_rivcs_k SPIO_NOC_ROUTER_1_6_6_RIVCS_K_ADDRESS SPIO_NOC_ROUTER_1_6_6_RIVCS_K_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OFFSET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 176999 R1_6 register rivcs_k 0x54038 R 0x00000000 Spio_noc_router_1_6_6_rivcs_k This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 176695 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_0_SET ns_noc_io_spio_soc_ip.csr 176709 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_0_SET ns_noc_io_spio_soc_ip.csr 176725 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_0_SET ns_noc_io_spio_soc_ip.csr 176739 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_0_SET ns_noc_io_spio_soc_ip.csr 176750 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_0_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_0_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_0_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_0_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_0_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_0_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_0_SET ns_noc_io_spio_soc_ip.csr 176761 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 176774 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_1_SET ns_noc_io_spio_soc_ip.csr 176788 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_1_SET ns_noc_io_spio_soc_ip.csr 176804 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_1_SET ns_noc_io_spio_soc_ip.csr 176818 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_1_SET ns_noc_io_spio_soc_ip.csr 176829 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_1_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_1_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_1_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_1_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_1_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_1_SET ns_noc_io_spio_soc_ip.csr 176840 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 176853 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_2_SET ns_noc_io_spio_soc_ip.csr 176867 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_2_SET ns_noc_io_spio_soc_ip.csr 176883 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_2_SET ns_noc_io_spio_soc_ip.csr 176897 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_2_SET ns_noc_io_spio_soc_ip.csr 176908 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_2_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_2_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_2_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_2_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_2_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_2_SET ns_noc_io_spio_soc_ip.csr 176919 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 176932 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_UP_3_SET ns_noc_io_spio_soc_ip.csr 176946 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_S_3_SET ns_noc_io_spio_soc_ip.csr 176962 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_B_3_SET ns_noc_io_spio_soc_ip.csr 176976 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_F_3_SET ns_noc_io_spio_soc_ip.csr 176987 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_3_MSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_3_LSB SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_3_RANGE SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_3_RESET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_3_GET SPIO_NOC_ROUTER_1_6_6_RIVCS_K_V_3_SET ns_noc_io_spio_soc_ip.csr 176998 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_1_6_6_rovcs_h router_1_6_6_rovcs_h SPIO_NOC_ROUTER_1_6_6_ROVCS_H_ADDRESS SPIO_NOC_ROUTER_1_6_6_ROVCS_H_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_ROVCS_H_OFFSET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 177260 R1_6 register rovcs_h 0x54040 R 0x00000001 Spio_noc_router_1_6_6_rovcs_h This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_0_SET ns_noc_io_spio_soc_ip.csr 177023 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_0_SET ns_noc_io_spio_soc_ip.csr 177037 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_0_SET ns_noc_io_spio_soc_ip.csr 177052 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_0_SET ns_noc_io_spio_soc_ip.csr 177063 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 177073 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_1_SET ns_noc_io_spio_soc_ip.csr 177085 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_1_SET ns_noc_io_spio_soc_ip.csr 177099 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_1_SET ns_noc_io_spio_soc_ip.csr 177114 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_1_SET ns_noc_io_spio_soc_ip.csr 177125 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 177135 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_2_SET ns_noc_io_spio_soc_ip.csr 177147 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_2_SET ns_noc_io_spio_soc_ip.csr 177161 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_2_SET ns_noc_io_spio_soc_ip.csr 177176 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_2_SET ns_noc_io_spio_soc_ip.csr 177187 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 177197 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CF_3_SET ns_noc_io_spio_soc_ip.csr 177209 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_CE_3_SET ns_noc_io_spio_soc_ip.csr 177223 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_VB_3_SET ns_noc_io_spio_soc_ip.csr 177238 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_RSV_3_SET ns_noc_io_spio_soc_ip.csr 177249 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 177259 UNSD_3 31 28 0x0 R register spio_noc.router_1_6_6_rovcs_e router_1_6_6_rovcs_e SPIO_NOC_ROUTER_1_6_6_ROVCS_E_ADDRESS SPIO_NOC_ROUTER_1_6_6_ROVCS_E_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_ROVCS_E_OFFSET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 177521 R1_6 register rovcs_e 0x54048 R 0x00000101 Spio_noc_router_1_6_6_rovcs_e This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_0_SET ns_noc_io_spio_soc_ip.csr 177284 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_0_SET ns_noc_io_spio_soc_ip.csr 177298 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_0_SET ns_noc_io_spio_soc_ip.csr 177313 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_0_SET ns_noc_io_spio_soc_ip.csr 177324 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 177334 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_1_SET ns_noc_io_spio_soc_ip.csr 177346 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x1 R CE_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_1_SET ns_noc_io_spio_soc_ip.csr 177360 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_1_SET ns_noc_io_spio_soc_ip.csr 177375 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_1_SET ns_noc_io_spio_soc_ip.csr 177386 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 177396 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_2_SET ns_noc_io_spio_soc_ip.csr 177408 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_2_SET ns_noc_io_spio_soc_ip.csr 177422 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_2_SET ns_noc_io_spio_soc_ip.csr 177437 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_2_SET ns_noc_io_spio_soc_ip.csr 177448 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 177458 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CF_3_SET ns_noc_io_spio_soc_ip.csr 177470 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_CE_3_SET ns_noc_io_spio_soc_ip.csr 177484 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_VB_3_SET ns_noc_io_spio_soc_ip.csr 177499 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_RSV_3_SET ns_noc_io_spio_soc_ip.csr 177510 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 177520 UNSD_3 31 28 0x0 R register spio_noc.router_1_6_6_rovcs_s router_1_6_6_rovcs_s SPIO_NOC_ROUTER_1_6_6_ROVCS_S_ADDRESS SPIO_NOC_ROUTER_1_6_6_ROVCS_S_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_ROVCS_S_OFFSET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 177782 R1_6 register rovcs_s 0x54050 R 0x00000001 Spio_noc_router_1_6_6_rovcs_s This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_0_SET ns_noc_io_spio_soc_ip.csr 177545 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_0_SET ns_noc_io_spio_soc_ip.csr 177559 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_0_SET ns_noc_io_spio_soc_ip.csr 177574 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_0_SET ns_noc_io_spio_soc_ip.csr 177585 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 177595 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_1_SET ns_noc_io_spio_soc_ip.csr 177607 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_1_SET ns_noc_io_spio_soc_ip.csr 177621 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_1_SET ns_noc_io_spio_soc_ip.csr 177636 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_1_SET ns_noc_io_spio_soc_ip.csr 177647 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 177657 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_2_SET ns_noc_io_spio_soc_ip.csr 177669 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_2_SET ns_noc_io_spio_soc_ip.csr 177683 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_2_SET ns_noc_io_spio_soc_ip.csr 177698 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_2_SET ns_noc_io_spio_soc_ip.csr 177709 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 177719 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CF_3_SET ns_noc_io_spio_soc_ip.csr 177731 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_CE_3_SET ns_noc_io_spio_soc_ip.csr 177745 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_VB_3_SET ns_noc_io_spio_soc_ip.csr 177760 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_RSV_3_SET ns_noc_io_spio_soc_ip.csr 177771 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 177781 UNSD_3 31 28 0x0 R register spio_noc.router_1_6_6_rovcs_w router_1_6_6_rovcs_w SPIO_NOC_ROUTER_1_6_6_ROVCS_W_ADDRESS SPIO_NOC_ROUTER_1_6_6_ROVCS_W_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_ROVCS_W_OFFSET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 178043 R1_6 register rovcs_w 0x54058 R 0x00000001 Spio_noc_router_1_6_6_rovcs_w This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_0_SET ns_noc_io_spio_soc_ip.csr 177806 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_0_SET ns_noc_io_spio_soc_ip.csr 177820 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_0_SET ns_noc_io_spio_soc_ip.csr 177835 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_0_SET ns_noc_io_spio_soc_ip.csr 177846 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 177856 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_1_SET ns_noc_io_spio_soc_ip.csr 177868 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_1_SET ns_noc_io_spio_soc_ip.csr 177882 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_1_SET ns_noc_io_spio_soc_ip.csr 177897 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_1_SET ns_noc_io_spio_soc_ip.csr 177908 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 177918 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_2_SET ns_noc_io_spio_soc_ip.csr 177930 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_2_SET ns_noc_io_spio_soc_ip.csr 177944 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_2_SET ns_noc_io_spio_soc_ip.csr 177959 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_2_SET ns_noc_io_spio_soc_ip.csr 177970 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 177980 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CF_3_SET ns_noc_io_spio_soc_ip.csr 177992 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_CE_3_SET ns_noc_io_spio_soc_ip.csr 178006 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_VB_3_SET ns_noc_io_spio_soc_ip.csr 178021 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_RSV_3_SET ns_noc_io_spio_soc_ip.csr 178032 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 178042 UNSD_3 31 28 0x0 R register spio_noc.router_1_6_6_rovcs_n router_1_6_6_rovcs_n SPIO_NOC_ROUTER_1_6_6_ROVCS_N_ADDRESS SPIO_NOC_ROUTER_1_6_6_ROVCS_N_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_ROVCS_N_OFFSET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 178304 R1_6 register rovcs_n 0x54060 R 0x00000001 Spio_noc_router_1_6_6_rovcs_n This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_0_SET ns_noc_io_spio_soc_ip.csr 178067 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_0_SET ns_noc_io_spio_soc_ip.csr 178081 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_0_SET ns_noc_io_spio_soc_ip.csr 178096 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_0_SET ns_noc_io_spio_soc_ip.csr 178107 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 178117 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_1_SET ns_noc_io_spio_soc_ip.csr 178129 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_1_SET ns_noc_io_spio_soc_ip.csr 178143 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_1_SET ns_noc_io_spio_soc_ip.csr 178158 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_1_SET ns_noc_io_spio_soc_ip.csr 178169 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 178179 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_2_SET ns_noc_io_spio_soc_ip.csr 178191 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_2_SET ns_noc_io_spio_soc_ip.csr 178205 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_2_SET ns_noc_io_spio_soc_ip.csr 178220 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_2_SET ns_noc_io_spio_soc_ip.csr 178231 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 178241 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CF_3_SET ns_noc_io_spio_soc_ip.csr 178253 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_CE_3_SET ns_noc_io_spio_soc_ip.csr 178267 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_VB_3_SET ns_noc_io_spio_soc_ip.csr 178282 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_RSV_3_SET ns_noc_io_spio_soc_ip.csr 178293 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 178303 UNSD_3 31 28 0x0 R register spio_noc.router_1_6_6_rovcs_i router_1_6_6_rovcs_i SPIO_NOC_ROUTER_1_6_6_ROVCS_I_ADDRESS SPIO_NOC_ROUTER_1_6_6_ROVCS_I_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_ROVCS_I_OFFSET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 178565 R1_6 register rovcs_i 0x54068 R 0x00000001 Spio_noc_router_1_6_6_rovcs_i This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_0_SET ns_noc_io_spio_soc_ip.csr 178328 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_0_SET ns_noc_io_spio_soc_ip.csr 178342 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_0_SET ns_noc_io_spio_soc_ip.csr 178357 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_0_SET ns_noc_io_spio_soc_ip.csr 178368 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 178378 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_1_SET ns_noc_io_spio_soc_ip.csr 178390 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_1_SET ns_noc_io_spio_soc_ip.csr 178404 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_1_SET ns_noc_io_spio_soc_ip.csr 178419 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_1_SET ns_noc_io_spio_soc_ip.csr 178430 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 178440 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_2_SET ns_noc_io_spio_soc_ip.csr 178452 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_2_SET ns_noc_io_spio_soc_ip.csr 178466 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_2_SET ns_noc_io_spio_soc_ip.csr 178481 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_2_SET ns_noc_io_spio_soc_ip.csr 178492 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 178502 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CF_3_SET ns_noc_io_spio_soc_ip.csr 178514 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_CE_3_SET ns_noc_io_spio_soc_ip.csr 178528 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_VB_3_SET ns_noc_io_spio_soc_ip.csr 178543 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_RSV_3_SET ns_noc_io_spio_soc_ip.csr 178554 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 178564 UNSD_3 31 28 0x0 R register spio_noc.router_1_6_6_rovcs_j router_1_6_6_rovcs_j SPIO_NOC_ROUTER_1_6_6_ROVCS_J_ADDRESS SPIO_NOC_ROUTER_1_6_6_ROVCS_J_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_ROVCS_J_OFFSET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 178826 R1_6 register rovcs_j 0x54070 R 0x00000001 Spio_noc_router_1_6_6_rovcs_j This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_0_SET ns_noc_io_spio_soc_ip.csr 178589 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_0_SET ns_noc_io_spio_soc_ip.csr 178603 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_0_SET ns_noc_io_spio_soc_ip.csr 178618 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_0_SET ns_noc_io_spio_soc_ip.csr 178629 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 178639 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_1_SET ns_noc_io_spio_soc_ip.csr 178651 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_1_SET ns_noc_io_spio_soc_ip.csr 178665 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_1_SET ns_noc_io_spio_soc_ip.csr 178680 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_1_SET ns_noc_io_spio_soc_ip.csr 178691 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 178701 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_2_SET ns_noc_io_spio_soc_ip.csr 178713 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_2_SET ns_noc_io_spio_soc_ip.csr 178727 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_2_SET ns_noc_io_spio_soc_ip.csr 178742 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_2_SET ns_noc_io_spio_soc_ip.csr 178753 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 178763 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CF_3_SET ns_noc_io_spio_soc_ip.csr 178775 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_CE_3_SET ns_noc_io_spio_soc_ip.csr 178789 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_VB_3_SET ns_noc_io_spio_soc_ip.csr 178804 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_RSV_3_SET ns_noc_io_spio_soc_ip.csr 178815 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 178825 UNSD_3 31 28 0x0 R register spio_noc.router_1_6_6_rovcs_k router_1_6_6_rovcs_k SPIO_NOC_ROUTER_1_6_6_ROVCS_K_ADDRESS SPIO_NOC_ROUTER_1_6_6_ROVCS_K_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_ROVCS_K_OFFSET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 179087 R1_6 register rovcs_k 0x54078 R 0x00000001 Spio_noc_router_1_6_6_rovcs_k This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_0_SET ns_noc_io_spio_soc_ip.csr 178850 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_0_SET ns_noc_io_spio_soc_ip.csr 178864 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_0_SET ns_noc_io_spio_soc_ip.csr 178879 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_0_SET ns_noc_io_spio_soc_ip.csr 178890 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_0_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_0_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_0_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_0_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_0_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_0_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 178900 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_1_SET ns_noc_io_spio_soc_ip.csr 178912 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_1_SET ns_noc_io_spio_soc_ip.csr 178926 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_1_SET ns_noc_io_spio_soc_ip.csr 178941 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_1_SET ns_noc_io_spio_soc_ip.csr 178952 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_1_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_1_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_1_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_1_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_1_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_1_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 178962 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_2_SET ns_noc_io_spio_soc_ip.csr 178974 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_2_SET ns_noc_io_spio_soc_ip.csr 178988 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_2_SET ns_noc_io_spio_soc_ip.csr 179003 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_2_SET ns_noc_io_spio_soc_ip.csr 179014 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_2_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_2_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_2_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_2_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_2_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_2_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 179024 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CF_3_SET ns_noc_io_spio_soc_ip.csr 179036 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_CE_3_SET ns_noc_io_spio_soc_ip.csr 179050 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_VB_3_SET ns_noc_io_spio_soc_ip.csr 179065 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_RSV_3_SET ns_noc_io_spio_soc_ip.csr 179076 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_3_WIDTH SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_3_MSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_3_LSB SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_3_RANGE SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_3_RESET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_3_GET SPIO_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 179086 UNSD_3 31 28 0x0 R register spio_noc.router_1_6_6_re router_1_6_6_re SPIO_NOC_ROUTER_1_6_6_RE_ADDRESS SPIO_NOC_ROUTER_1_6_6_RE_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_RE_OFFSET SPIO_NOC_ROUTER_1_6_6_RE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 179261 R1_6 register re 0x54080 R/W 0x00000000 Spio_noc_router_1_6_6_re This register tracks the interrupt or error events that can occur in the router. The only interrupt event is the event counter overflow. This register is readable, and can be cleared by performing a write with the write data bits set to 0 for the bits that should be cleared. false false false false OVFI SPIO_NOC_ROUTER_1_6_6_RE_OVFI_WIDTH SPIO_NOC_ROUTER_1_6_6_RE_OVFI_MSB SPIO_NOC_ROUTER_1_6_6_RE_OVFI_LSB SPIO_NOC_ROUTER_1_6_6_RE_OVFI_RANGE SPIO_NOC_ROUTER_1_6_6_RE_OVFI_RESET SPIO_NOC_ROUTER_1_6_6_RE_OVFI_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RE_OVFI_GET SPIO_NOC_ROUTER_1_6_6_RE_OVFI_SET ns_noc_io_spio_soc_ip.csr 179113 OVFI 1'b1: In this status bit indicates that the router input event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 0 0 0x0 R/W CSR_PARERR SPIO_NOC_ROUTER_1_6_6_RE_CSR_PARERR_WIDTH SPIO_NOC_ROUTER_1_6_6_RE_CSR_PARERR_MSB SPIO_NOC_ROUTER_1_6_6_RE_CSR_PARERR_LSB SPIO_NOC_ROUTER_1_6_6_RE_CSR_PARERR_RANGE SPIO_NOC_ROUTER_1_6_6_RE_CSR_PARERR_RESET SPIO_NOC_ROUTER_1_6_6_RE_CSR_PARERR_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RE_CSR_PARERR_GET SPIO_NOC_ROUTER_1_6_6_RE_CSR_PARERR_SET ns_noc_io_spio_soc_ip.csr 179124 CSR_PARERR 1'b1: Parity error in config/status registers 1 1 0x0 R/W OVFO SPIO_NOC_ROUTER_1_6_6_RE_OVFO_WIDTH SPIO_NOC_ROUTER_1_6_6_RE_OVFO_MSB SPIO_NOC_ROUTER_1_6_6_RE_OVFO_LSB SPIO_NOC_ROUTER_1_6_6_RE_OVFO_RANGE SPIO_NOC_ROUTER_1_6_6_RE_OVFO_RESET SPIO_NOC_ROUTER_1_6_6_RE_OVFO_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RE_OVFO_GET SPIO_NOC_ROUTER_1_6_6_RE_OVFO_SET ns_noc_io_spio_soc_ip.csr 179138 OVFO 1'b1: In this status bit indicates that the router output event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 2 2 0x0 R/W UNSD_7_3 SPIO_NOC_ROUTER_1_6_6_RE_UNSD_7_3_WIDTH SPIO_NOC_ROUTER_1_6_6_RE_UNSD_7_3_MSB SPIO_NOC_ROUTER_1_6_6_RE_UNSD_7_3_LSB SPIO_NOC_ROUTER_1_6_6_RE_UNSD_7_3_RANGE SPIO_NOC_ROUTER_1_6_6_RE_UNSD_7_3_RESET SPIO_NOC_ROUTER_1_6_6_RE_UNSD_7_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RE_UNSD_7_3_GET SPIO_NOC_ROUTER_1_6_6_RE_UNSD_7_3_SET ns_noc_io_spio_soc_ip.csr 179149 UNSD_7_3 7 3 0x00 R PGE SPIO_NOC_ROUTER_1_6_6_RE_PGE_WIDTH SPIO_NOC_ROUTER_1_6_6_RE_PGE_MSB SPIO_NOC_ROUTER_1_6_6_RE_PGE_LSB SPIO_NOC_ROUTER_1_6_6_RE_PGE_RANGE SPIO_NOC_ROUTER_1_6_6_RE_PGE_RESET SPIO_NOC_ROUTER_1_6_6_RE_PGE_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RE_PGE_GET SPIO_NOC_ROUTER_1_6_6_RE_PGE_SET ns_noc_io_spio_soc_ip.csr 179161 PGE 1'b1: Power gating error, traffic received after router commited to power down 8 8 0x0 R/W NLU SPIO_NOC_ROUTER_1_6_6_RE_NLU_WIDTH SPIO_NOC_ROUTER_1_6_6_RE_NLU_MSB SPIO_NOC_ROUTER_1_6_6_RE_NLU_LSB SPIO_NOC_ROUTER_1_6_6_RE_NLU_RANGE SPIO_NOC_ROUTER_1_6_6_RE_NLU_RESET SPIO_NOC_ROUTER_1_6_6_RE_NLU_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RE_NLU_GET SPIO_NOC_ROUTER_1_6_6_RE_NLU_SET ns_noc_io_spio_soc_ip.csr 179172 NLU 1'b1: Traffic destined for North link which is unavailable 9 9 0x0 R/W ELU SPIO_NOC_ROUTER_1_6_6_RE_ELU_WIDTH SPIO_NOC_ROUTER_1_6_6_RE_ELU_MSB SPIO_NOC_ROUTER_1_6_6_RE_ELU_LSB SPIO_NOC_ROUTER_1_6_6_RE_ELU_RANGE SPIO_NOC_ROUTER_1_6_6_RE_ELU_RESET SPIO_NOC_ROUTER_1_6_6_RE_ELU_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RE_ELU_GET SPIO_NOC_ROUTER_1_6_6_RE_ELU_SET ns_noc_io_spio_soc_ip.csr 179183 ELU 1'b1: Traffic destined for East link which is unavailable 10 10 0x0 R/W WLU SPIO_NOC_ROUTER_1_6_6_RE_WLU_WIDTH SPIO_NOC_ROUTER_1_6_6_RE_WLU_MSB SPIO_NOC_ROUTER_1_6_6_RE_WLU_LSB SPIO_NOC_ROUTER_1_6_6_RE_WLU_RANGE SPIO_NOC_ROUTER_1_6_6_RE_WLU_RESET SPIO_NOC_ROUTER_1_6_6_RE_WLU_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RE_WLU_GET SPIO_NOC_ROUTER_1_6_6_RE_WLU_SET ns_noc_io_spio_soc_ip.csr 179194 WLU 1'b1: Traffic destined for West link which is unavailable 11 11 0x0 R/W SLU SPIO_NOC_ROUTER_1_6_6_RE_SLU_WIDTH SPIO_NOC_ROUTER_1_6_6_RE_SLU_MSB SPIO_NOC_ROUTER_1_6_6_RE_SLU_LSB SPIO_NOC_ROUTER_1_6_6_RE_SLU_RANGE SPIO_NOC_ROUTER_1_6_6_RE_SLU_RESET SPIO_NOC_ROUTER_1_6_6_RE_SLU_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RE_SLU_GET SPIO_NOC_ROUTER_1_6_6_RE_SLU_SET ns_noc_io_spio_soc_ip.csr 179205 SLU 1'b1: Traffic destined for South link which is unavailable 12 12 0x0 R/W HLU SPIO_NOC_ROUTER_1_6_6_RE_HLU_WIDTH SPIO_NOC_ROUTER_1_6_6_RE_HLU_MSB SPIO_NOC_ROUTER_1_6_6_RE_HLU_LSB SPIO_NOC_ROUTER_1_6_6_RE_HLU_RANGE SPIO_NOC_ROUTER_1_6_6_RE_HLU_RESET SPIO_NOC_ROUTER_1_6_6_RE_HLU_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RE_HLU_GET SPIO_NOC_ROUTER_1_6_6_RE_HLU_SET ns_noc_io_spio_soc_ip.csr 179216 HLU 1'b1: Traffic destined for H link which is unavailable 13 13 0x0 R/W ILU SPIO_NOC_ROUTER_1_6_6_RE_ILU_WIDTH SPIO_NOC_ROUTER_1_6_6_RE_ILU_MSB SPIO_NOC_ROUTER_1_6_6_RE_ILU_LSB SPIO_NOC_ROUTER_1_6_6_RE_ILU_RANGE SPIO_NOC_ROUTER_1_6_6_RE_ILU_RESET SPIO_NOC_ROUTER_1_6_6_RE_ILU_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RE_ILU_GET SPIO_NOC_ROUTER_1_6_6_RE_ILU_SET ns_noc_io_spio_soc_ip.csr 179227 ILU 1'b1: Traffic destined for I link which is unavailable 14 14 0x0 R/W JLU SPIO_NOC_ROUTER_1_6_6_RE_JLU_WIDTH SPIO_NOC_ROUTER_1_6_6_RE_JLU_MSB SPIO_NOC_ROUTER_1_6_6_RE_JLU_LSB SPIO_NOC_ROUTER_1_6_6_RE_JLU_RANGE SPIO_NOC_ROUTER_1_6_6_RE_JLU_RESET SPIO_NOC_ROUTER_1_6_6_RE_JLU_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RE_JLU_GET SPIO_NOC_ROUTER_1_6_6_RE_JLU_SET ns_noc_io_spio_soc_ip.csr 179238 JLU 1'b1: Traffic destined for J link which is unavailable 15 15 0x0 R/W KLU SPIO_NOC_ROUTER_1_6_6_RE_KLU_WIDTH SPIO_NOC_ROUTER_1_6_6_RE_KLU_MSB SPIO_NOC_ROUTER_1_6_6_RE_KLU_LSB SPIO_NOC_ROUTER_1_6_6_RE_KLU_RANGE SPIO_NOC_ROUTER_1_6_6_RE_KLU_RESET SPIO_NOC_ROUTER_1_6_6_RE_KLU_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RE_KLU_GET SPIO_NOC_ROUTER_1_6_6_RE_KLU_SET ns_noc_io_spio_soc_ip.csr 179249 KLU 1'b1: Traffic destined for K link which is unavailable 16 16 0x0 R/W UNSD_31_14 SPIO_NOC_ROUTER_1_6_6_RE_UNSD_31_14_WIDTH SPIO_NOC_ROUTER_1_6_6_RE_UNSD_31_14_MSB SPIO_NOC_ROUTER_1_6_6_RE_UNSD_31_14_LSB SPIO_NOC_ROUTER_1_6_6_RE_UNSD_31_14_RANGE SPIO_NOC_ROUTER_1_6_6_RE_UNSD_31_14_RESET SPIO_NOC_ROUTER_1_6_6_RE_UNSD_31_14_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RE_UNSD_31_14_GET SPIO_NOC_ROUTER_1_6_6_RE_UNSD_31_14_SET ns_noc_io_spio_soc_ip.csr 179260 UNSD_31_14 31 17 0x0000 R register spio_noc.router_1_6_6_rem router_1_6_6_rem SPIO_NOC_ROUTER_1_6_6_REM_ADDRESS SPIO_NOC_ROUTER_1_6_6_REM_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_REM_OFFSET SPIO_NOC_ROUTER_1_6_6_REM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 179434 R1_6 register rem 0x54088 R/W 0x0001fe00 Spio_noc_router_1_6_6_rem This register is used to select whether the interrupt events in the Router Event Interrupt Status register should send an interrupt when asserted. If the corresponding bit is set to 1, an interrupt will not be sent. This register can be read and written to. false false false false OVFIM SPIO_NOC_ROUTER_1_6_6_REM_OVFIM_WIDTH SPIO_NOC_ROUTER_1_6_6_REM_OVFIM_MSB SPIO_NOC_ROUTER_1_6_6_REM_OVFIM_LSB SPIO_NOC_ROUTER_1_6_6_REM_OVFIM_RANGE SPIO_NOC_ROUTER_1_6_6_REM_OVFIM_RESET SPIO_NOC_ROUTER_1_6_6_REM_OVFIM_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_REM_OVFIM_GET SPIO_NOC_ROUTER_1_6_6_REM_OVFIM_SET ns_noc_io_spio_soc_ip.csr 179287 OVFIM 1'b1: Masks or disables an interrupt from being generated by the input event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 0 0 0x0 R/W CSR_PARERRM SPIO_NOC_ROUTER_1_6_6_REM_CSR_PARERRM_WIDTH SPIO_NOC_ROUTER_1_6_6_REM_CSR_PARERRM_MSB SPIO_NOC_ROUTER_1_6_6_REM_CSR_PARERRM_LSB SPIO_NOC_ROUTER_1_6_6_REM_CSR_PARERRM_RANGE SPIO_NOC_ROUTER_1_6_6_REM_CSR_PARERRM_RESET SPIO_NOC_ROUTER_1_6_6_REM_CSR_PARERRM_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_REM_CSR_PARERRM_GET SPIO_NOC_ROUTER_1_6_6_REM_CSR_PARERRM_SET ns_noc_io_spio_soc_ip.csr 179298 CSR_PARERRM 1'b1: Mask CSR parity error interrupt 1 1 0x0 R/W OVFOM SPIO_NOC_ROUTER_1_6_6_REM_OVFOM_WIDTH SPIO_NOC_ROUTER_1_6_6_REM_OVFOM_MSB SPIO_NOC_ROUTER_1_6_6_REM_OVFOM_LSB SPIO_NOC_ROUTER_1_6_6_REM_OVFOM_RANGE SPIO_NOC_ROUTER_1_6_6_REM_OVFOM_RESET SPIO_NOC_ROUTER_1_6_6_REM_OVFOM_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_REM_OVFOM_GET SPIO_NOC_ROUTER_1_6_6_REM_OVFOM_SET ns_noc_io_spio_soc_ip.csr 179312 OVFOM 1'b1: Masks or disables an interrupt from being generated by the output event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 2 2 0x0 R/W UNSD_7_3 SPIO_NOC_ROUTER_1_6_6_REM_UNSD_7_3_WIDTH SPIO_NOC_ROUTER_1_6_6_REM_UNSD_7_3_MSB SPIO_NOC_ROUTER_1_6_6_REM_UNSD_7_3_LSB SPIO_NOC_ROUTER_1_6_6_REM_UNSD_7_3_RANGE SPIO_NOC_ROUTER_1_6_6_REM_UNSD_7_3_RESET SPIO_NOC_ROUTER_1_6_6_REM_UNSD_7_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_REM_UNSD_7_3_GET SPIO_NOC_ROUTER_1_6_6_REM_UNSD_7_3_SET ns_noc_io_spio_soc_ip.csr 179323 UNSD_7_3 7 3 0x00 R PGM SPIO_NOC_ROUTER_1_6_6_REM_PGM_WIDTH SPIO_NOC_ROUTER_1_6_6_REM_PGM_MSB SPIO_NOC_ROUTER_1_6_6_REM_PGM_LSB SPIO_NOC_ROUTER_1_6_6_REM_PGM_RANGE SPIO_NOC_ROUTER_1_6_6_REM_PGM_RESET SPIO_NOC_ROUTER_1_6_6_REM_PGM_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_REM_PGM_GET SPIO_NOC_ROUTER_1_6_6_REM_PGM_SET ns_noc_io_spio_soc_ip.csr 179334 PGM 1'b1: Mask PGE error interrupt 8 8 0x0 R/W MN SPIO_NOC_ROUTER_1_6_6_REM_MN_WIDTH SPIO_NOC_ROUTER_1_6_6_REM_MN_MSB SPIO_NOC_ROUTER_1_6_6_REM_MN_LSB SPIO_NOC_ROUTER_1_6_6_REM_MN_RANGE SPIO_NOC_ROUTER_1_6_6_REM_MN_RESET SPIO_NOC_ROUTER_1_6_6_REM_MN_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_REM_MN_GET SPIO_NOC_ROUTER_1_6_6_REM_MN_SET ns_noc_io_spio_soc_ip.csr 179345 MN 1'b1: Mask NLU error interrupt 9 9 0x1 R/W ME SPIO_NOC_ROUTER_1_6_6_REM_ME_WIDTH SPIO_NOC_ROUTER_1_6_6_REM_ME_MSB SPIO_NOC_ROUTER_1_6_6_REM_ME_LSB SPIO_NOC_ROUTER_1_6_6_REM_ME_RANGE SPIO_NOC_ROUTER_1_6_6_REM_ME_RESET SPIO_NOC_ROUTER_1_6_6_REM_ME_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_REM_ME_GET SPIO_NOC_ROUTER_1_6_6_REM_ME_SET ns_noc_io_spio_soc_ip.csr 179356 ME 1'b1: Mask ELU error interrupt 10 10 0x1 R/W MW SPIO_NOC_ROUTER_1_6_6_REM_MW_WIDTH SPIO_NOC_ROUTER_1_6_6_REM_MW_MSB SPIO_NOC_ROUTER_1_6_6_REM_MW_LSB SPIO_NOC_ROUTER_1_6_6_REM_MW_RANGE SPIO_NOC_ROUTER_1_6_6_REM_MW_RESET SPIO_NOC_ROUTER_1_6_6_REM_MW_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_REM_MW_GET SPIO_NOC_ROUTER_1_6_6_REM_MW_SET ns_noc_io_spio_soc_ip.csr 179367 MW 1'b1: Mask WLU error interrupt 11 11 0x1 R/W MS SPIO_NOC_ROUTER_1_6_6_REM_MS_WIDTH SPIO_NOC_ROUTER_1_6_6_REM_MS_MSB SPIO_NOC_ROUTER_1_6_6_REM_MS_LSB SPIO_NOC_ROUTER_1_6_6_REM_MS_RANGE SPIO_NOC_ROUTER_1_6_6_REM_MS_RESET SPIO_NOC_ROUTER_1_6_6_REM_MS_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_REM_MS_GET SPIO_NOC_ROUTER_1_6_6_REM_MS_SET ns_noc_io_spio_soc_ip.csr 179378 MS 1'b1: Mask SLU error interrupt 12 12 0x1 R/W MH SPIO_NOC_ROUTER_1_6_6_REM_MH_WIDTH SPIO_NOC_ROUTER_1_6_6_REM_MH_MSB SPIO_NOC_ROUTER_1_6_6_REM_MH_LSB SPIO_NOC_ROUTER_1_6_6_REM_MH_RANGE SPIO_NOC_ROUTER_1_6_6_REM_MH_RESET SPIO_NOC_ROUTER_1_6_6_REM_MH_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_REM_MH_GET SPIO_NOC_ROUTER_1_6_6_REM_MH_SET ns_noc_io_spio_soc_ip.csr 179389 MH 1'b1: Mask HLU error interrupt 13 13 0x1 R/W MI SPIO_NOC_ROUTER_1_6_6_REM_MI_WIDTH SPIO_NOC_ROUTER_1_6_6_REM_MI_MSB SPIO_NOC_ROUTER_1_6_6_REM_MI_LSB SPIO_NOC_ROUTER_1_6_6_REM_MI_RANGE SPIO_NOC_ROUTER_1_6_6_REM_MI_RESET SPIO_NOC_ROUTER_1_6_6_REM_MI_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_REM_MI_GET SPIO_NOC_ROUTER_1_6_6_REM_MI_SET ns_noc_io_spio_soc_ip.csr 179400 MI 1'b1: Mask ILU error interrupt 14 14 0x1 R/W MJ SPIO_NOC_ROUTER_1_6_6_REM_MJ_WIDTH SPIO_NOC_ROUTER_1_6_6_REM_MJ_MSB SPIO_NOC_ROUTER_1_6_6_REM_MJ_LSB SPIO_NOC_ROUTER_1_6_6_REM_MJ_RANGE SPIO_NOC_ROUTER_1_6_6_REM_MJ_RESET SPIO_NOC_ROUTER_1_6_6_REM_MJ_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_REM_MJ_GET SPIO_NOC_ROUTER_1_6_6_REM_MJ_SET ns_noc_io_spio_soc_ip.csr 179411 MJ 1'b1: Mask JLU error interrupt 15 15 0x1 R/W MK SPIO_NOC_ROUTER_1_6_6_REM_MK_WIDTH SPIO_NOC_ROUTER_1_6_6_REM_MK_MSB SPIO_NOC_ROUTER_1_6_6_REM_MK_LSB SPIO_NOC_ROUTER_1_6_6_REM_MK_RANGE SPIO_NOC_ROUTER_1_6_6_REM_MK_RESET SPIO_NOC_ROUTER_1_6_6_REM_MK_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_REM_MK_GET SPIO_NOC_ROUTER_1_6_6_REM_MK_SET ns_noc_io_spio_soc_ip.csr 179422 MK 1'b1: Mask KLU error interrupt 16 16 0x1 R/W UNSD_31_14 SPIO_NOC_ROUTER_1_6_6_REM_UNSD_31_14_WIDTH SPIO_NOC_ROUTER_1_6_6_REM_UNSD_31_14_MSB SPIO_NOC_ROUTER_1_6_6_REM_UNSD_31_14_LSB SPIO_NOC_ROUTER_1_6_6_REM_UNSD_31_14_RANGE SPIO_NOC_ROUTER_1_6_6_REM_UNSD_31_14_RESET SPIO_NOC_ROUTER_1_6_6_REM_UNSD_31_14_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_REM_UNSD_31_14_GET SPIO_NOC_ROUTER_1_6_6_REM_UNSD_31_14_SET ns_noc_io_spio_soc_ip.csr 179433 UNSD_31_14 31 17 0x0000 R register spio_noc.router_1_6_6_recc router_1_6_6_recc SPIO_NOC_ROUTER_1_6_6_RECC_ADDRESS SPIO_NOC_ROUTER_1_6_6_RECC_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_RECC_OFFSET SPIO_NOC_ROUTER_1_6_6_RECC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 179519 R1_6 register recc 0x54090 R/W 0x00000000 Spio_noc_router_1_6_6_recc This register is used to select which hardware events will increment the event counter. false false false false IVC SPIO_NOC_ROUTER_1_6_6_RECC_IVC_WIDTH SPIO_NOC_ROUTER_1_6_6_RECC_IVC_MSB SPIO_NOC_ROUTER_1_6_6_RECC_IVC_LSB SPIO_NOC_ROUTER_1_6_6_RECC_IVC_RANGE SPIO_NOC_ROUTER_1_6_6_RECC_IVC_RESET SPIO_NOC_ROUTER_1_6_6_RECC_IVC_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RECC_IVC_GET SPIO_NOC_ROUTER_1_6_6_RECC_IVC_SET ns_noc_io_spio_soc_ip.csr 179455 IVC 11: Input VC 3 10: Input VC 2 01: Input VC 1 00: Input VC 0 1 0 0x0 R/W UNSD_3_2 SPIO_NOC_ROUTER_1_6_6_RECC_UNSD_3_2_WIDTH SPIO_NOC_ROUTER_1_6_6_RECC_UNSD_3_2_MSB SPIO_NOC_ROUTER_1_6_6_RECC_UNSD_3_2_LSB SPIO_NOC_ROUTER_1_6_6_RECC_UNSD_3_2_RANGE SPIO_NOC_ROUTER_1_6_6_RECC_UNSD_3_2_RESET SPIO_NOC_ROUTER_1_6_6_RECC_UNSD_3_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RECC_UNSD_3_2_GET SPIO_NOC_ROUTER_1_6_6_RECC_UNSD_3_2_SET ns_noc_io_spio_soc_ip.csr 179466 UNSD_3_2 3 2 0x0 R INP SPIO_NOC_ROUTER_1_6_6_RECC_INP_WIDTH SPIO_NOC_ROUTER_1_6_6_RECC_INP_MSB SPIO_NOC_ROUTER_1_6_6_RECC_INP_LSB SPIO_NOC_ROUTER_1_6_6_RECC_INP_RANGE SPIO_NOC_ROUTER_1_6_6_RECC_INP_RESET SPIO_NOC_ROUTER_1_6_6_RECC_INP_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RECC_INP_GET SPIO_NOC_ROUTER_1_6_6_RECC_INP_SET ns_noc_io_spio_soc_ip.csr 179477 INP Input port on which the event is captured 6 4 0x0 R/W UNSD_7_7 SPIO_NOC_ROUTER_1_6_6_RECC_UNSD_7_7_WIDTH SPIO_NOC_ROUTER_1_6_6_RECC_UNSD_7_7_MSB SPIO_NOC_ROUTER_1_6_6_RECC_UNSD_7_7_LSB SPIO_NOC_ROUTER_1_6_6_RECC_UNSD_7_7_RANGE SPIO_NOC_ROUTER_1_6_6_RECC_UNSD_7_7_RESET SPIO_NOC_ROUTER_1_6_6_RECC_UNSD_7_7_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RECC_UNSD_7_7_GET SPIO_NOC_ROUTER_1_6_6_RECC_UNSD_7_7_SET ns_noc_io_spio_soc_ip.csr 179488 UNSD_7_7 7 7 0x0 R EVT SPIO_NOC_ROUTER_1_6_6_RECC_EVT_WIDTH SPIO_NOC_ROUTER_1_6_6_RECC_EVT_MSB SPIO_NOC_ROUTER_1_6_6_RECC_EVT_LSB SPIO_NOC_ROUTER_1_6_6_RECC_EVT_RANGE SPIO_NOC_ROUTER_1_6_6_RECC_EVT_RESET SPIO_NOC_ROUTER_1_6_6_RECC_EVT_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RECC_EVT_GET SPIO_NOC_ROUTER_1_6_6_RECC_EVT_SET ns_noc_io_spio_soc_ip.csr 179507 EVT 11: Generates count event when VC has valid data, but is stalled 10: Generates count event on every flit received for the selected input port and selected input VCs, this can be used to count total flits received on a router input port 01: Generates count event on every EOP received for the selected input port and selected input VCs, this can be used to count packets received on a router input port 00: Disable 9 8 0x0 R/W UNSD_31_10 SPIO_NOC_ROUTER_1_6_6_RECC_UNSD_31_10_WIDTH SPIO_NOC_ROUTER_1_6_6_RECC_UNSD_31_10_MSB SPIO_NOC_ROUTER_1_6_6_RECC_UNSD_31_10_LSB SPIO_NOC_ROUTER_1_6_6_RECC_UNSD_31_10_RANGE SPIO_NOC_ROUTER_1_6_6_RECC_UNSD_31_10_RESET SPIO_NOC_ROUTER_1_6_6_RECC_UNSD_31_10_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RECC_UNSD_31_10_GET SPIO_NOC_ROUTER_1_6_6_RECC_UNSD_31_10_SET ns_noc_io_spio_soc_ip.csr 179518 UNSD_31_10 31 10 0x000000 R register spio_noc.router_1_6_6_rec router_1_6_6_rec SPIO_NOC_ROUTER_1_6_6_REC_ADDRESS SPIO_NOC_ROUTER_1_6_6_REC_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_REC_OFFSET SPIO_NOC_ROUTER_1_6_6_REC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 179544 R1_6 register rec 0x54098 R/W 0x00000000 Spio_noc_router_1_6_6_rec This register holds the event counter. The value can be read to determine the current count value. The value can be written to initialize the counter. When events trigger a count, the counter will increment. When the counter increments at its highest value, it will roll over to zero and the overflow will mark the Router Event Interrupt Status register, which could trigger an interrupt. false false false false EVENT_CNTR SPIO_NOC_ROUTER_1_6_6_REC_EVENT_CNTR_WIDTH SPIO_NOC_ROUTER_1_6_6_REC_EVENT_CNTR_MSB SPIO_NOC_ROUTER_1_6_6_REC_EVENT_CNTR_LSB SPIO_NOC_ROUTER_1_6_6_REC_EVENT_CNTR_RANGE SPIO_NOC_ROUTER_1_6_6_REC_EVENT_CNTR_RESET SPIO_NOC_ROUTER_1_6_6_REC_EVENT_CNTR_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_REC_EVENT_CNTR_GET SPIO_NOC_ROUTER_1_6_6_REC_EVENT_CNTR_SET ns_noc_io_spio_soc_ip.csr 179543 EVENT_CNTR 32'bit event incrementing counter. Rollover from 32'hFFFFF -> 32'd0 sets the rollover status bit RE 31 0 0x00000000 R/W register spio_noc.router_1_6_6_id router_1_6_6_id SPIO_NOC_ROUTER_1_6_6_ID_ADDRESS SPIO_NOC_ROUTER_1_6_6_ID_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_ID_OFFSET SPIO_NOC_ROUTER_1_6_6_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 179613 R1_6 register id 0x540A0 R 0x010000a1 Spio_noc_router_1_6_6_id This register holds layer and position information for the router. It is a read-only register. It can be used for debugging software access to the NoC elements by confirming that a read has successfully targeted the correct NoC element. false false false false LAYER SPIO_NOC_ROUTER_1_6_6_ID_LAYER_WIDTH SPIO_NOC_ROUTER_1_6_6_ID_LAYER_MSB SPIO_NOC_ROUTER_1_6_6_ID_LAYER_LSB SPIO_NOC_ROUTER_1_6_6_ID_LAYER_RANGE SPIO_NOC_ROUTER_1_6_6_ID_LAYER_RESET SPIO_NOC_ROUTER_1_6_6_ID_LAYER_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ID_LAYER_GET SPIO_NOC_ROUTER_1_6_6_ID_LAYER_SET ns_noc_io_spio_soc_ip.csr 179569 LAYER 5-bit identifier of the NoC layer on which this router is located 4 0 0x01 R POS SPIO_NOC_ROUTER_1_6_6_ID_POS_WIDTH SPIO_NOC_ROUTER_1_6_6_ID_POS_MSB SPIO_NOC_ROUTER_1_6_6_ID_POS_LSB SPIO_NOC_ROUTER_1_6_6_ID_POS_RANGE SPIO_NOC_ROUTER_1_6_6_ID_POS_RESET SPIO_NOC_ROUTER_1_6_6_ID_POS_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ID_POS_GET SPIO_NOC_ROUTER_1_6_6_ID_POS_SET ns_noc_io_spio_soc_ip.csr 179580 POS 16-bit position ID of this router in the NoC 20 5 0x0005 R ZERO SPIO_NOC_ROUTER_1_6_6_ID_ZERO_WIDTH SPIO_NOC_ROUTER_1_6_6_ID_ZERO_MSB SPIO_NOC_ROUTER_1_6_6_ID_ZERO_LSB SPIO_NOC_ROUTER_1_6_6_ID_ZERO_RANGE SPIO_NOC_ROUTER_1_6_6_ID_ZERO_RESET SPIO_NOC_ROUTER_1_6_6_ID_ZERO_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ID_ZERO_GET SPIO_NOC_ROUTER_1_6_6_ID_ZERO_SET ns_noc_io_spio_soc_ip.csr 179591 ZERO Zeroes 23 21 0x0 R ONE SPIO_NOC_ROUTER_1_6_6_ID_ONE_WIDTH SPIO_NOC_ROUTER_1_6_6_ID_ONE_MSB SPIO_NOC_ROUTER_1_6_6_ID_ONE_LSB SPIO_NOC_ROUTER_1_6_6_ID_ONE_RANGE SPIO_NOC_ROUTER_1_6_6_ID_ONE_RESET SPIO_NOC_ROUTER_1_6_6_ID_ONE_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ID_ONE_GET SPIO_NOC_ROUTER_1_6_6_ID_ONE_SET ns_noc_io_spio_soc_ip.csr 179602 ONE One 24 24 0x1 R UNSD_31_25 SPIO_NOC_ROUTER_1_6_6_ID_UNSD_31_25_WIDTH SPIO_NOC_ROUTER_1_6_6_ID_UNSD_31_25_MSB SPIO_NOC_ROUTER_1_6_6_ID_UNSD_31_25_LSB SPIO_NOC_ROUTER_1_6_6_ID_UNSD_31_25_RANGE SPIO_NOC_ROUTER_1_6_6_ID_UNSD_31_25_RESET SPIO_NOC_ROUTER_1_6_6_ID_UNSD_31_25_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ID_UNSD_31_25_GET SPIO_NOC_ROUTER_1_6_6_ID_UNSD_31_25_SET ns_noc_io_spio_soc_ip.csr 179612 UNSD_31_25 31 25 0x00 R register spio_noc.router_1_6_6_rcgc router_1_6_6_rcgc SPIO_NOC_ROUTER_1_6_6_RCGC_ADDRESS SPIO_NOC_ROUTER_1_6_6_RCGC_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_RCGC_OFFSET SPIO_NOC_ROUTER_1_6_6_RCGC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 179639 R1_6 register rcgc 0x540A8 R/W 0x00000064 Spio_noc_router_1_6_6_rcgc Programmable interval used by coarse clock gating logic in routers.This count determines the consecutive number of idle cycle after which a router output port initiates coarse clock gating of the local port clock and de-asserts the 'busy' signal to the downstream router. This signal indicates inactivity to the downstream router and allows it to initiate coarse clock gating of its corresponding input port. false false false false HYSTERESIS_COUNTER SPIO_NOC_ROUTER_1_6_6_RCGC_HYSTERESIS_COUNTER_WIDTH SPIO_NOC_ROUTER_1_6_6_RCGC_HYSTERESIS_COUNTER_MSB SPIO_NOC_ROUTER_1_6_6_RCGC_HYSTERESIS_COUNTER_LSB SPIO_NOC_ROUTER_1_6_6_RCGC_HYSTERESIS_COUNTER_RANGE SPIO_NOC_ROUTER_1_6_6_RCGC_HYSTERESIS_COUNTER_RESET SPIO_NOC_ROUTER_1_6_6_RCGC_HYSTERESIS_COUNTER_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RCGC_HYSTERESIS_COUNTER_GET SPIO_NOC_ROUTER_1_6_6_RCGC_HYSTERESIS_COUNTER_SET ns_noc_io_spio_soc_ip.csr 179638 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W register spio_noc.router_1_6_6_rcgo router_1_6_6_rcgo SPIO_NOC_ROUTER_1_6_6_RCGO_ADDRESS SPIO_NOC_ROUTER_1_6_6_RCGO_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_RCGO_OFFSET SPIO_NOC_ROUTER_1_6_6_RCGO_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 179678 R1_6 register rcgo 0x540B0 R/W 0x00000000 Spio_noc_router_1_6_6_rcgo This register is used by coarse grained clock gating logic. This register can be set to override coarse clock gating for the entire router. Coarse clock gating for selective routers can be overridden by locally setting this register, if the user does not want incur and aggregate coarse clock gating cycle penalty over a "fast path/critical path" through the NoC. false false false false FPO SPIO_NOC_ROUTER_1_6_6_RCGO_FPO_WIDTH SPIO_NOC_ROUTER_1_6_6_RCGO_FPO_MSB SPIO_NOC_ROUTER_1_6_6_RCGO_FPO_LSB SPIO_NOC_ROUTER_1_6_6_RCGO_FPO_RANGE SPIO_NOC_ROUTER_1_6_6_RCGO_FPO_RESET SPIO_NOC_ROUTER_1_6_6_RCGO_FPO_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RCGO_FPO_GET SPIO_NOC_ROUTER_1_6_6_RCGO_FPO_SET ns_noc_io_spio_soc_ip.csr 179666 FPO 1'b1: Coarse clock gating is locally disabled (for fast path) 1'b0: Coarse clock gating is locally enabled 0 0 0x0 R/W UNSD_31_1 SPIO_NOC_ROUTER_1_6_6_RCGO_UNSD_31_1_WIDTH SPIO_NOC_ROUTER_1_6_6_RCGO_UNSD_31_1_MSB SPIO_NOC_ROUTER_1_6_6_RCGO_UNSD_31_1_LSB SPIO_NOC_ROUTER_1_6_6_RCGO_UNSD_31_1_RANGE SPIO_NOC_ROUTER_1_6_6_RCGO_UNSD_31_1_RESET SPIO_NOC_ROUTER_1_6_6_RCGO_UNSD_31_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_RCGO_UNSD_31_1_GET SPIO_NOC_ROUTER_1_6_6_RCGO_UNSD_31_1_SET ns_noc_io_spio_soc_ip.csr 179677 UNSD_31_1 31 1 0x00000000 R register spio_noc.router_1_6_6_p0_rperr router_1_6_6_p0_rperr SPIO_NOC_ROUTER_1_6_6_P0_RPERR_ADDRESS SPIO_NOC_ROUTER_1_6_6_P0_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_P0_RPERR_OFFSET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 179969 R1_6 register p0_rperr 0x540B8 R/W 0x00000000 Spio_noc_router_1_6_6_p0_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 179721 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 179732 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 179743 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 179754 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_6_6_P0_RPERR_CR_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERR_CR_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_CR_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_CR_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERR_CR_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERR_CR_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 179765 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_6_6_P0_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 179776 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_0_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_0_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_0_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_0_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_0_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 179787 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_0_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_0_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_0_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_0_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 179798 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_0_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_0_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_0_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_0_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 179810 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_0_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_0_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_0_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_0_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 179821 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_1_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_1_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_1_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_1_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_1_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 179833 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_1_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_1_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_1_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_1_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 179845 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_1_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_1_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_1_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_1_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 179858 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_1_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_1_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_1_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_1_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 179870 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_2_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_2_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_2_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_2_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_2_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 179882 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_2_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_2_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_2_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_2_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 179894 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_2_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_2_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_2_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_2_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 179907 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_2_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_2_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_2_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_2_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 179919 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_3_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_3_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_3_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_3_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_3_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 179931 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_3_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_3_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_3_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_3_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 179943 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_3_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_3_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_3_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_3_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 179956 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_3_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_3_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_3_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_3_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 179968 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_1_6_6_p1_rperr router_1_6_6_p1_rperr SPIO_NOC_ROUTER_1_6_6_P1_RPERR_ADDRESS SPIO_NOC_ROUTER_1_6_6_P1_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_P1_RPERR_OFFSET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 180260 R1_6 register p1_rperr 0x540C0 R/W 0x00000000 Spio_noc_router_1_6_6_p1_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 180012 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 180023 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 180034 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 180045 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_6_6_P1_RPERR_CR_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERR_CR_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_CR_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_CR_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERR_CR_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERR_CR_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 180056 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_6_6_P1_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 180067 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_0_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_0_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_0_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_0_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_0_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 180078 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_0_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_0_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_0_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_0_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 180089 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_0_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_0_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_0_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_0_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 180101 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_0_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_0_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_0_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_0_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 180112 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_1_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_1_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_1_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_1_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_1_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 180124 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_1_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_1_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_1_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_1_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 180136 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_1_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_1_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_1_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_1_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 180149 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_1_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_1_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_1_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_1_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 180161 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_2_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_2_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_2_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_2_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_2_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 180173 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_2_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_2_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_2_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_2_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 180185 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_2_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_2_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_2_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_2_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 180198 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_2_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_2_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_2_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_2_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 180210 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_3_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_3_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_3_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_3_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_3_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 180222 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_3_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_3_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_3_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_3_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 180234 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_3_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_3_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_3_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_3_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 180247 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_3_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_3_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_3_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_3_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 180259 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_1_6_6_p2_rperr router_1_6_6_p2_rperr SPIO_NOC_ROUTER_1_6_6_P2_RPERR_ADDRESS SPIO_NOC_ROUTER_1_6_6_P2_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_P2_RPERR_OFFSET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 180551 R1_6 register p2_rperr 0x540C8 R/W 0x00000000 Spio_noc_router_1_6_6_p2_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 180303 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 180314 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 180325 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 180336 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_6_6_P2_RPERR_CR_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERR_CR_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_CR_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_CR_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERR_CR_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERR_CR_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 180347 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_6_6_P2_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 180358 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_0_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_0_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_0_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_0_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_0_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 180369 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_0_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_0_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_0_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_0_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 180380 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_0_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_0_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_0_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_0_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 180392 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_0_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_0_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_0_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_0_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 180403 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_1_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_1_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_1_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_1_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_1_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 180415 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_1_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_1_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_1_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_1_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 180427 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_1_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_1_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_1_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_1_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 180440 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_1_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_1_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_1_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_1_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 180452 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_2_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_2_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_2_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_2_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_2_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 180464 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_2_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_2_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_2_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_2_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 180476 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_2_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_2_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_2_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_2_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 180489 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_2_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_2_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_2_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_2_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 180501 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_3_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_3_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_3_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_3_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_3_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 180513 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_3_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_3_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_3_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_3_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 180525 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_3_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_3_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_3_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_3_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 180538 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_3_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_3_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_3_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_3_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 180550 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_1_6_6_p3_rperr router_1_6_6_p3_rperr SPIO_NOC_ROUTER_1_6_6_P3_RPERR_ADDRESS SPIO_NOC_ROUTER_1_6_6_P3_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_P3_RPERR_OFFSET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 180842 R1_6 register p3_rperr 0x540D0 R/W 0x00000000 Spio_noc_router_1_6_6_p3_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 180594 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 180605 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 180616 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 180627 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_6_6_P3_RPERR_CR_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERR_CR_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_CR_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_CR_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERR_CR_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERR_CR_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 180638 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_6_6_P3_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 180649 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_0_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_0_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_0_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_0_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_0_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 180660 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_0_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_0_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_0_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_0_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 180671 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_0_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_0_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_0_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_0_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 180683 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_0_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_0_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_0_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_0_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 180694 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_1_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_1_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_1_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_1_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_1_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 180706 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_1_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_1_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_1_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_1_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 180718 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_1_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_1_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_1_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_1_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 180731 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_1_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_1_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_1_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_1_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 180743 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_2_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_2_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_2_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_2_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_2_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 180755 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_2_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_2_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_2_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_2_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 180767 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_2_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_2_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_2_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_2_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 180780 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_2_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_2_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_2_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_2_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 180792 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_3_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_3_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_3_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_3_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_3_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 180804 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_3_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_3_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_3_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_3_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 180816 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_3_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_3_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_3_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_3_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 180829 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_3_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_3_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_3_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_3_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 180841 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_1_6_6_p4_rperr router_1_6_6_p4_rperr SPIO_NOC_ROUTER_1_6_6_P4_RPERR_ADDRESS SPIO_NOC_ROUTER_1_6_6_P4_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_P4_RPERR_OFFSET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 181133 R1_6 register p4_rperr 0x540D8 R/W 0x00000000 Spio_noc_router_1_6_6_p4_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 180885 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 180896 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 180907 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 180918 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_6_6_P4_RPERR_CR_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERR_CR_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_CR_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_CR_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERR_CR_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERR_CR_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 180929 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_6_6_P4_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 180940 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_0_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_0_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_0_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_0_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_0_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 180951 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_0_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_0_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_0_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_0_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 180962 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_0_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_0_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_0_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_0_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 180974 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_0_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_0_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_0_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_0_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 180985 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_1_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_1_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_1_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_1_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_1_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 180997 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_1_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_1_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_1_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_1_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 181009 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_1_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_1_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_1_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_1_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 181022 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_1_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_1_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_1_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_1_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 181034 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_2_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_2_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_2_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_2_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_2_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 181046 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_2_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_2_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_2_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_2_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 181058 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_2_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_2_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_2_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_2_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 181071 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_2_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_2_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_2_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_2_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 181083 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_3_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_3_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_3_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_3_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_3_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 181095 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_3_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_3_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_3_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_3_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 181107 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_3_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_3_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_3_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_3_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 181120 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_3_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_3_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_3_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_3_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 181132 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_1_6_6_p5_rperr router_1_6_6_p5_rperr SPIO_NOC_ROUTER_1_6_6_P5_RPERR_ADDRESS SPIO_NOC_ROUTER_1_6_6_P5_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_P5_RPERR_OFFSET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 181420 R1_6 register p5_rperr 0x540E0 R/W 0x00000000 Spio_noc_router_1_6_6_p5_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 181176 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 181187 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 181198 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 181209 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_6_6_P5_RPERR_CR_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERR_CR_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_CR_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_CR_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERR_CR_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERR_CR_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 181220 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_6_6_P5_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 181231 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_0_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_0_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_0_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_0_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_0_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 181242 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_0_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_0_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_0_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_0_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 181253 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_0_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_0_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_0_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_0_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 181265 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_0_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_0_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_0_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_0_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 181276 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_1_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_1_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_1_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_1_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_1_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 181287 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_1_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_1_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_1_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_1_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 181298 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_1_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_1_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_1_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_1_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 181310 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_1_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_1_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_1_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_1_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 181321 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_2_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_2_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_2_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_2_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_2_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 181333 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_2_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_2_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_2_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_2_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 181345 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_2_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_2_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_2_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_2_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 181358 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_2_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_2_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_2_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_2_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 181370 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_3_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_3_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_3_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_3_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_3_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 181382 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_3_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_3_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_3_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_3_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 181394 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_3_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_3_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_3_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_3_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 181407 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_3_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_3_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_3_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_3_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 181419 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_1_6_6_p6_rperr router_1_6_6_p6_rperr SPIO_NOC_ROUTER_1_6_6_P6_RPERR_ADDRESS SPIO_NOC_ROUTER_1_6_6_P6_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_P6_RPERR_OFFSET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 181711 R1_6 register p6_rperr 0x540E8 R/W 0x00000000 Spio_noc_router_1_6_6_p6_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 181463 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 181474 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 181485 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 181496 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_6_6_P6_RPERR_CR_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERR_CR_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_CR_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_CR_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERR_CR_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERR_CR_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 181507 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_6_6_P6_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 181518 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_0_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_0_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_0_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_0_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_0_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 181529 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_0_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_0_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_0_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_0_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 181540 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_0_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_0_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_0_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_0_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 181552 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_0_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_0_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_0_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_0_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 181563 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_1_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_1_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_1_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_1_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_1_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 181575 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_1_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_1_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_1_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_1_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 181587 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_1_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_1_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_1_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_1_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 181600 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_1_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_1_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_1_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_1_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 181612 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_2_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_2_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_2_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_2_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_2_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 181624 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_2_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_2_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_2_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_2_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 181636 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_2_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_2_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_2_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_2_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 181649 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_2_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_2_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_2_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_2_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 181661 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_3_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_3_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_3_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_3_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_3_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 181673 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_3_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_3_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_3_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_3_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 181685 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_3_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_3_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_3_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_3_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 181698 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_3_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_3_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_3_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_3_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 181710 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_1_6_6_p7_rperr router_1_6_6_p7_rperr SPIO_NOC_ROUTER_1_6_6_P7_RPERR_ADDRESS SPIO_NOC_ROUTER_1_6_6_P7_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_P7_RPERR_OFFSET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 182002 R1_6 register p7_rperr 0x540F0 R/W 0x00000000 Spio_noc_router_1_6_6_p7_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 181754 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 181765 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 181776 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 181787 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_6_6_P7_RPERR_CR_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERR_CR_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_CR_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_CR_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERR_CR_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERR_CR_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 181798 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_6_6_P7_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 181809 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_0_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_0_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_0_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_0_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_0_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 181820 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_0_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_0_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_0_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_0_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 181831 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_0_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_0_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_0_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_0_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 181843 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_0_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_0_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_0_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_0_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 181854 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_1_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_1_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_1_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_1_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_1_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 181866 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_1_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_1_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_1_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_1_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 181878 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_1_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_1_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_1_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_1_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 181891 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_1_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_1_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_1_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_1_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 181903 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_2_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_2_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_2_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_2_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_2_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 181915 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_2_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_2_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_2_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_2_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 181927 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_2_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_2_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_2_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_2_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 181940 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_2_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_2_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_2_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_2_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 181952 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_3_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_3_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_3_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_3_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_3_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 181964 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_3_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_3_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_3_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_3_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 181976 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_3_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_3_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_3_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_3_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 181989 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_3_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_3_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_3_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_3_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 182001 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_1_6_6_p0_rperrm router_1_6_6_p0_rperrm SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_ADDRESS SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_OFFSET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 182260 R1_6 register p0_rperrm 0x540F8 R/W 0x00000000 Spio_noc_router_1_6_6_p0_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 182024 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 182035 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 182046 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 182057 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_CR_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_CR_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_CR_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_CR_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_CR_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 182068 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 182079 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_0_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_0_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_0_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_0_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 182090 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_0_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 182101 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_0_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 182113 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_0_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 182124 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_1_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_1_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_1_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_1_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 182135 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_1_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 182146 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_1_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 182158 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_1_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 182169 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_2_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_2_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_2_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_2_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 182180 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_2_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 182191 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_2_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 182203 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_2_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 182214 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_3_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_3_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_3_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_3_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 182225 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_3_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 182236 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_3_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 182248 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_3_GET SPIO_NOC_ROUTER_1_6_6_P0_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 182259 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_1_6_6_p1_rperrm router_1_6_6_p1_rperrm SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_ADDRESS SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_OFFSET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 182518 R1_6 register p1_rperrm 0x54100 R/W 0x00000000 Spio_noc_router_1_6_6_p1_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 182282 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 182293 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 182304 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 182315 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_CR_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_CR_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_CR_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_CR_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_CR_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 182326 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 182337 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_0_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_0_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_0_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_0_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 182348 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_0_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 182359 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_0_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 182371 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_0_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 182382 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_1_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_1_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_1_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_1_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 182393 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_1_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 182404 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_1_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 182416 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_1_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 182427 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_2_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_2_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_2_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_2_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 182438 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_2_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 182449 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_2_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 182461 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_2_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 182472 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_3_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_3_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_3_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_3_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 182483 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_3_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 182494 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_3_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 182506 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_3_GET SPIO_NOC_ROUTER_1_6_6_P1_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 182517 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_1_6_6_p2_rperrm router_1_6_6_p2_rperrm SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_ADDRESS SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_OFFSET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 182776 R1_6 register p2_rperrm 0x54108 R/W 0x00000000 Spio_noc_router_1_6_6_p2_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 182540 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 182551 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 182562 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 182573 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_CR_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_CR_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_CR_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_CR_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_CR_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 182584 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 182595 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_0_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_0_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_0_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_0_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 182606 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_0_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 182617 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_0_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 182629 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_0_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 182640 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_1_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_1_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_1_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_1_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 182651 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_1_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 182662 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_1_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 182674 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_1_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 182685 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_2_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_2_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_2_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_2_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 182696 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_2_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 182707 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_2_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 182719 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_2_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 182730 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_3_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_3_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_3_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_3_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 182741 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_3_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 182752 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_3_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 182764 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_3_GET SPIO_NOC_ROUTER_1_6_6_P2_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 182775 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_1_6_6_p3_rperrm router_1_6_6_p3_rperrm SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_ADDRESS SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_OFFSET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 183034 R1_6 register p3_rperrm 0x54110 R/W 0x00000000 Spio_noc_router_1_6_6_p3_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 182798 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 182809 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 182820 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 182831 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_CR_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_CR_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_CR_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_CR_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_CR_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 182842 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 182853 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_0_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_0_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_0_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_0_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 182864 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_0_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 182875 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_0_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 182887 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_0_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 182898 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_1_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_1_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_1_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_1_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 182909 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_1_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 182920 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_1_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 182932 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_1_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 182943 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_2_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_2_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_2_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_2_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 182954 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_2_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 182965 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_2_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 182977 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_2_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 182988 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_3_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_3_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_3_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_3_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 182999 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_3_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 183010 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_3_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 183022 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_3_GET SPIO_NOC_ROUTER_1_6_6_P3_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 183033 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_1_6_6_p4_rperrm router_1_6_6_p4_rperrm SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_ADDRESS SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_OFFSET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 183292 R1_6 register p4_rperrm 0x54118 R/W 0x00000000 Spio_noc_router_1_6_6_p4_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 183056 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 183067 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 183078 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 183089 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_CR_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_CR_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_CR_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_CR_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_CR_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 183100 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 183111 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_0_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_0_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_0_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_0_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 183122 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_0_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 183133 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_0_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 183145 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_0_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 183156 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_1_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_1_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_1_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_1_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 183167 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_1_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 183178 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_1_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 183190 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_1_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 183201 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_2_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_2_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_2_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_2_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 183212 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_2_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 183223 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_2_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 183235 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_2_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 183246 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_3_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_3_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_3_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_3_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 183257 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_3_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 183268 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_3_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 183280 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_3_GET SPIO_NOC_ROUTER_1_6_6_P4_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 183291 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_1_6_6_p5_rperrm router_1_6_6_p5_rperrm SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_ADDRESS SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_OFFSET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 183550 R1_6 register p5_rperrm 0x54120 R/W 0x00000000 Spio_noc_router_1_6_6_p5_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 183314 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 183325 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 183336 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 183347 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_CR_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_CR_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_CR_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_CR_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_CR_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 183358 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 183369 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_0_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_0_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_0_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_0_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 183380 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_0_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 183391 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_0_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 183403 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_0_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 183414 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_1_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_1_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_1_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_1_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 183425 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_1_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 183436 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_1_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 183448 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_1_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 183459 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_2_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_2_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_2_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_2_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 183470 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_2_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 183481 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_2_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 183493 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_2_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 183504 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_3_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_3_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_3_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_3_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 183515 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_3_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 183526 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_3_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 183538 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_3_GET SPIO_NOC_ROUTER_1_6_6_P5_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 183549 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_1_6_6_p6_rperrm router_1_6_6_p6_rperrm SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_ADDRESS SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_OFFSET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 183808 R1_6 register p6_rperrm 0x54128 R/W 0x00000000 Spio_noc_router_1_6_6_p6_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 183572 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 183583 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 183594 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 183605 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_CR_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_CR_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_CR_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_CR_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_CR_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 183616 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 183627 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_0_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_0_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_0_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_0_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 183638 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_0_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 183649 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_0_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 183661 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_0_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 183672 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_1_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_1_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_1_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_1_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 183683 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_1_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 183694 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_1_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 183706 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_1_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 183717 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_2_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_2_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_2_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_2_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 183728 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_2_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 183739 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_2_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 183751 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_2_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 183762 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_3_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_3_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_3_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_3_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 183773 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_3_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 183784 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_3_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 183796 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_3_GET SPIO_NOC_ROUTER_1_6_6_P6_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 183807 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_1_6_6_p7_rperrm router_1_6_6_p7_rperrm SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_ADDRESS SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_OFFSET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 184066 R1_6 register p7_rperrm 0x54130 R/W 0x00000000 Spio_noc_router_1_6_6_p7_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 183830 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 183841 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 183852 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 183863 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_CR_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_CR_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_CR_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_CR_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_CR_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 183874 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 183885 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_0_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_0_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_0_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_0_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 183896 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_0_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 183907 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_0_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 183919 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_0_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 183930 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_1_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_1_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_1_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_1_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 183941 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_1_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 183952 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_1_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 183964 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_1_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 183975 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_2_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_2_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_2_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_2_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 183986 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_2_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 183997 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_2_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 184009 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_2_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 184020 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_3_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_3_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_3_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_3_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 184031 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_3_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 184042 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_3_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 184054 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_3_GET SPIO_NOC_ROUTER_1_6_6_P7_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 184065 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_1_6_6_roecc router_1_6_6_roecc SPIO_NOC_ROUTER_1_6_6_ROECC_ADDRESS SPIO_NOC_ROUTER_1_6_6_ROECC_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_ROECC_OFFSET SPIO_NOC_ROUTER_1_6_6_ROECC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 184139 R1_6 register roecc 0x54138 R/W 0x00000000 Spio_noc_router_1_6_6_roecc This register is used to select which hardware events will increment the output event counter. false false false false OVC SPIO_NOC_ROUTER_1_6_6_ROECC_OVC_WIDTH SPIO_NOC_ROUTER_1_6_6_ROECC_OVC_MSB SPIO_NOC_ROUTER_1_6_6_ROECC_OVC_LSB SPIO_NOC_ROUTER_1_6_6_ROECC_OVC_RANGE SPIO_NOC_ROUTER_1_6_6_ROECC_OVC_RESET SPIO_NOC_ROUTER_1_6_6_ROECC_OVC_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROECC_OVC_GET SPIO_NOC_ROUTER_1_6_6_ROECC_OVC_SET ns_noc_io_spio_soc_ip.csr 184084 OVC Bit map to select output VCs to monitor events on 3 0 0x0 R/W OP SPIO_NOC_ROUTER_1_6_6_ROECC_OP_WIDTH SPIO_NOC_ROUTER_1_6_6_ROECC_OP_MSB SPIO_NOC_ROUTER_1_6_6_ROECC_OP_LSB SPIO_NOC_ROUTER_1_6_6_ROECC_OP_RANGE SPIO_NOC_ROUTER_1_6_6_ROECC_OP_RESET SPIO_NOC_ROUTER_1_6_6_ROECC_OP_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROECC_OP_GET SPIO_NOC_ROUTER_1_6_6_ROECC_OP_SET ns_noc_io_spio_soc_ip.csr 184095 OP Output port on which the event is captured 6 4 0x0 R/W UNSD_7_7 SPIO_NOC_ROUTER_1_6_6_ROECC_UNSD_7_7_WIDTH SPIO_NOC_ROUTER_1_6_6_ROECC_UNSD_7_7_MSB SPIO_NOC_ROUTER_1_6_6_ROECC_UNSD_7_7_LSB SPIO_NOC_ROUTER_1_6_6_ROECC_UNSD_7_7_RANGE SPIO_NOC_ROUTER_1_6_6_ROECC_UNSD_7_7_RESET SPIO_NOC_ROUTER_1_6_6_ROECC_UNSD_7_7_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROECC_UNSD_7_7_GET SPIO_NOC_ROUTER_1_6_6_ROECC_UNSD_7_7_SET ns_noc_io_spio_soc_ip.csr 184106 UNSD_7_7 7 7 0x0 R EVT SPIO_NOC_ROUTER_1_6_6_ROECC_EVT_WIDTH SPIO_NOC_ROUTER_1_6_6_ROECC_EVT_MSB SPIO_NOC_ROUTER_1_6_6_ROECC_EVT_LSB SPIO_NOC_ROUTER_1_6_6_ROECC_EVT_RANGE SPIO_NOC_ROUTER_1_6_6_ROECC_EVT_RESET SPIO_NOC_ROUTER_1_6_6_ROECC_EVT_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROECC_EVT_GET SPIO_NOC_ROUTER_1_6_6_ROECC_EVT_SET ns_noc_io_spio_soc_ip.csr 184127 EVT 100: Port stalled. Input flits are available for the port, but no output VC has credit 011: Generates count event when flits are available to be sent to output VC, but the VC has no credit 010: Generates count event on every flit sent on the selected output port and selected outpt VCs, this can be used to count total flits sent on a router output port 001: Generates count event on every EOP sent on the selected output port and selected output VCs, this can be used to count packets sent on a router output port 000: Disable 10 8 0x0 R/W UNSD_31_11 SPIO_NOC_ROUTER_1_6_6_ROECC_UNSD_31_11_WIDTH SPIO_NOC_ROUTER_1_6_6_ROECC_UNSD_31_11_MSB SPIO_NOC_ROUTER_1_6_6_ROECC_UNSD_31_11_LSB SPIO_NOC_ROUTER_1_6_6_ROECC_UNSD_31_11_RANGE SPIO_NOC_ROUTER_1_6_6_ROECC_UNSD_31_11_RESET SPIO_NOC_ROUTER_1_6_6_ROECC_UNSD_31_11_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROECC_UNSD_31_11_GET SPIO_NOC_ROUTER_1_6_6_ROECC_UNSD_31_11_SET ns_noc_io_spio_soc_ip.csr 184138 UNSD_31_11 31 11 0x000000 R register spio_noc.router_1_6_6_roec router_1_6_6_roec SPIO_NOC_ROUTER_1_6_6_ROEC_ADDRESS SPIO_NOC_ROUTER_1_6_6_ROEC_BYTE_ADDRESS SPIO_NOC_ROUTER_1_6_6_ROEC_OFFSET SPIO_NOC_ROUTER_1_6_6_ROEC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 184164 R1_6 register roec 0x54140 R/W 0x00000000 Spio_noc_router_1_6_6_roec This register holds the output event counter. The value can be read to determine the current count value. The value can be written to initialize the counter. When events trigger a count, the counter will increment. When the counter increments at its highest value, it will roll over to zero and the overflow will mark the Router output Event Interrupt Status register, which could trigger an interrupt. false false false false EVENT_CNTR SPIO_NOC_ROUTER_1_6_6_ROEC_EVENT_CNTR_WIDTH SPIO_NOC_ROUTER_1_6_6_ROEC_EVENT_CNTR_MSB SPIO_NOC_ROUTER_1_6_6_ROEC_EVENT_CNTR_LSB SPIO_NOC_ROUTER_1_6_6_ROEC_EVENT_CNTR_RANGE SPIO_NOC_ROUTER_1_6_6_ROEC_EVENT_CNTR_RESET SPIO_NOC_ROUTER_1_6_6_ROEC_EVENT_CNTR_FIELD_MASK SPIO_NOC_ROUTER_1_6_6_ROEC_EVENT_CNTR_GET SPIO_NOC_ROUTER_1_6_6_ROEC_EVENT_CNTR_SET ns_noc_io_spio_soc_ip.csr 184163 EVENT_CNTR 32'bit event incrementing counter. Rollover from 32'hFFFFF -> 32'd0 sets the rollover status bit RE 31 0 0x00000000 R/W register spio_noc.router_1_7_7_rivcs_h router_1_7_7_rivcs_h SPIO_NOC_ROUTER_1_7_7_RIVCS_H_ADDRESS SPIO_NOC_ROUTER_1_7_7_RIVCS_H_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OFFSET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 184493 R1_7 register rivcs_h 0x58000 R 0x00000000 Spio_noc_router_1_7_7_rivcs_h This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 184189 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_0_SET ns_noc_io_spio_soc_ip.csr 184203 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_0_SET ns_noc_io_spio_soc_ip.csr 184219 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_0_SET ns_noc_io_spio_soc_ip.csr 184233 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_0_SET ns_noc_io_spio_soc_ip.csr 184244 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_0_SET ns_noc_io_spio_soc_ip.csr 184255 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 184268 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_1_SET ns_noc_io_spio_soc_ip.csr 184282 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_1_SET ns_noc_io_spio_soc_ip.csr 184298 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_1_SET ns_noc_io_spio_soc_ip.csr 184312 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_1_SET ns_noc_io_spio_soc_ip.csr 184323 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_1_SET ns_noc_io_spio_soc_ip.csr 184334 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 184347 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_2_SET ns_noc_io_spio_soc_ip.csr 184361 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_2_SET ns_noc_io_spio_soc_ip.csr 184377 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_2_SET ns_noc_io_spio_soc_ip.csr 184391 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_2_SET ns_noc_io_spio_soc_ip.csr 184402 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_2_SET ns_noc_io_spio_soc_ip.csr 184413 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 184426 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_UP_3_SET ns_noc_io_spio_soc_ip.csr 184440 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_S_3_SET ns_noc_io_spio_soc_ip.csr 184456 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_B_3_SET ns_noc_io_spio_soc_ip.csr 184470 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_F_3_SET ns_noc_io_spio_soc_ip.csr 184481 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_H_V_3_SET ns_noc_io_spio_soc_ip.csr 184492 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_1_7_7_rivcs_e router_1_7_7_rivcs_e SPIO_NOC_ROUTER_1_7_7_RIVCS_E_ADDRESS SPIO_NOC_ROUTER_1_7_7_RIVCS_E_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OFFSET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 184822 R1_7 register rivcs_e 0x58008 R 0x00000000 Spio_noc_router_1_7_7_rivcs_e This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 184518 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_0_SET ns_noc_io_spio_soc_ip.csr 184532 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_0_SET ns_noc_io_spio_soc_ip.csr 184548 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_0_SET ns_noc_io_spio_soc_ip.csr 184562 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_0_SET ns_noc_io_spio_soc_ip.csr 184573 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_0_SET ns_noc_io_spio_soc_ip.csr 184584 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 184597 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_1_SET ns_noc_io_spio_soc_ip.csr 184611 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_1_SET ns_noc_io_spio_soc_ip.csr 184627 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_1_SET ns_noc_io_spio_soc_ip.csr 184641 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_1_SET ns_noc_io_spio_soc_ip.csr 184652 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_1_SET ns_noc_io_spio_soc_ip.csr 184663 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 184676 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_2_SET ns_noc_io_spio_soc_ip.csr 184690 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_2_SET ns_noc_io_spio_soc_ip.csr 184706 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_2_SET ns_noc_io_spio_soc_ip.csr 184720 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_2_SET ns_noc_io_spio_soc_ip.csr 184731 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_2_SET ns_noc_io_spio_soc_ip.csr 184742 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 184755 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_UP_3_SET ns_noc_io_spio_soc_ip.csr 184769 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_S_3_SET ns_noc_io_spio_soc_ip.csr 184785 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_B_3_SET ns_noc_io_spio_soc_ip.csr 184799 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_F_3_SET ns_noc_io_spio_soc_ip.csr 184810 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_E_V_3_SET ns_noc_io_spio_soc_ip.csr 184821 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_1_7_7_rivcs_w router_1_7_7_rivcs_w SPIO_NOC_ROUTER_1_7_7_RIVCS_W_ADDRESS SPIO_NOC_ROUTER_1_7_7_RIVCS_W_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OFFSET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 185151 R1_7 register rivcs_w 0x58018 R 0x00000000 Spio_noc_router_1_7_7_rivcs_w This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 184847 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_0_SET ns_noc_io_spio_soc_ip.csr 184861 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_0_SET ns_noc_io_spio_soc_ip.csr 184877 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_0_SET ns_noc_io_spio_soc_ip.csr 184891 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_0_SET ns_noc_io_spio_soc_ip.csr 184902 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_0_SET ns_noc_io_spio_soc_ip.csr 184913 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 184926 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_1_SET ns_noc_io_spio_soc_ip.csr 184940 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_1_SET ns_noc_io_spio_soc_ip.csr 184956 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_1_SET ns_noc_io_spio_soc_ip.csr 184970 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_1_SET ns_noc_io_spio_soc_ip.csr 184981 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_1_SET ns_noc_io_spio_soc_ip.csr 184992 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 185005 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_2_SET ns_noc_io_spio_soc_ip.csr 185019 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_2_SET ns_noc_io_spio_soc_ip.csr 185035 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_2_SET ns_noc_io_spio_soc_ip.csr 185049 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_2_SET ns_noc_io_spio_soc_ip.csr 185060 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_2_SET ns_noc_io_spio_soc_ip.csr 185071 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 185084 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_UP_3_SET ns_noc_io_spio_soc_ip.csr 185098 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_S_3_SET ns_noc_io_spio_soc_ip.csr 185114 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_B_3_SET ns_noc_io_spio_soc_ip.csr 185128 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_F_3_SET ns_noc_io_spio_soc_ip.csr 185139 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_W_V_3_SET ns_noc_io_spio_soc_ip.csr 185150 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_1_7_7_rivcs_n router_1_7_7_rivcs_n SPIO_NOC_ROUTER_1_7_7_RIVCS_N_ADDRESS SPIO_NOC_ROUTER_1_7_7_RIVCS_N_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OFFSET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 185480 R1_7 register rivcs_n 0x58020 R 0x00000000 Spio_noc_router_1_7_7_rivcs_n This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 185176 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_0_SET ns_noc_io_spio_soc_ip.csr 185190 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_0_SET ns_noc_io_spio_soc_ip.csr 185206 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_0_SET ns_noc_io_spio_soc_ip.csr 185220 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_0_SET ns_noc_io_spio_soc_ip.csr 185231 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_0_SET ns_noc_io_spio_soc_ip.csr 185242 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 185255 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_1_SET ns_noc_io_spio_soc_ip.csr 185269 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_1_SET ns_noc_io_spio_soc_ip.csr 185285 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_1_SET ns_noc_io_spio_soc_ip.csr 185299 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_1_SET ns_noc_io_spio_soc_ip.csr 185310 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_1_SET ns_noc_io_spio_soc_ip.csr 185321 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 185334 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_2_SET ns_noc_io_spio_soc_ip.csr 185348 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_2_SET ns_noc_io_spio_soc_ip.csr 185364 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_2_SET ns_noc_io_spio_soc_ip.csr 185378 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_2_SET ns_noc_io_spio_soc_ip.csr 185389 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_2_SET ns_noc_io_spio_soc_ip.csr 185400 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 185413 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_UP_3_SET ns_noc_io_spio_soc_ip.csr 185427 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_S_3_SET ns_noc_io_spio_soc_ip.csr 185443 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_B_3_SET ns_noc_io_spio_soc_ip.csr 185457 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_F_3_SET ns_noc_io_spio_soc_ip.csr 185468 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_N_V_3_SET ns_noc_io_spio_soc_ip.csr 185479 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_1_7_7_rivcs_i router_1_7_7_rivcs_i SPIO_NOC_ROUTER_1_7_7_RIVCS_I_ADDRESS SPIO_NOC_ROUTER_1_7_7_RIVCS_I_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OFFSET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 185809 R1_7 register rivcs_i 0x58028 R 0x00000000 Spio_noc_router_1_7_7_rivcs_i This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 185505 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_0_SET ns_noc_io_spio_soc_ip.csr 185519 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_0_SET ns_noc_io_spio_soc_ip.csr 185535 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_0_SET ns_noc_io_spio_soc_ip.csr 185549 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_0_SET ns_noc_io_spio_soc_ip.csr 185560 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_0_SET ns_noc_io_spio_soc_ip.csr 185571 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 185584 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_1_SET ns_noc_io_spio_soc_ip.csr 185598 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_1_SET ns_noc_io_spio_soc_ip.csr 185614 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_1_SET ns_noc_io_spio_soc_ip.csr 185628 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_1_SET ns_noc_io_spio_soc_ip.csr 185639 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_1_SET ns_noc_io_spio_soc_ip.csr 185650 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 185663 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_2_SET ns_noc_io_spio_soc_ip.csr 185677 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_2_SET ns_noc_io_spio_soc_ip.csr 185693 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_2_SET ns_noc_io_spio_soc_ip.csr 185707 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_2_SET ns_noc_io_spio_soc_ip.csr 185718 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_2_SET ns_noc_io_spio_soc_ip.csr 185729 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 185742 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_UP_3_SET ns_noc_io_spio_soc_ip.csr 185756 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_S_3_SET ns_noc_io_spio_soc_ip.csr 185772 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_B_3_SET ns_noc_io_spio_soc_ip.csr 185786 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_F_3_SET ns_noc_io_spio_soc_ip.csr 185797 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_I_V_3_SET ns_noc_io_spio_soc_ip.csr 185808 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_1_7_7_rivcs_j router_1_7_7_rivcs_j SPIO_NOC_ROUTER_1_7_7_RIVCS_J_ADDRESS SPIO_NOC_ROUTER_1_7_7_RIVCS_J_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OFFSET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 186138 R1_7 register rivcs_j 0x58030 R 0x00000000 Spio_noc_router_1_7_7_rivcs_j This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 185834 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_0_SET ns_noc_io_spio_soc_ip.csr 185848 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_0_SET ns_noc_io_spio_soc_ip.csr 185864 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_0_SET ns_noc_io_spio_soc_ip.csr 185878 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_0_SET ns_noc_io_spio_soc_ip.csr 185889 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_0_SET ns_noc_io_spio_soc_ip.csr 185900 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 185913 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_1_SET ns_noc_io_spio_soc_ip.csr 185927 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_1_SET ns_noc_io_spio_soc_ip.csr 185943 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_1_SET ns_noc_io_spio_soc_ip.csr 185957 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_1_SET ns_noc_io_spio_soc_ip.csr 185968 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_1_SET ns_noc_io_spio_soc_ip.csr 185979 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 185992 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_2_SET ns_noc_io_spio_soc_ip.csr 186006 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_2_SET ns_noc_io_spio_soc_ip.csr 186022 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_2_SET ns_noc_io_spio_soc_ip.csr 186036 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_2_SET ns_noc_io_spio_soc_ip.csr 186047 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_2_SET ns_noc_io_spio_soc_ip.csr 186058 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 186071 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_UP_3_SET ns_noc_io_spio_soc_ip.csr 186085 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_S_3_SET ns_noc_io_spio_soc_ip.csr 186101 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_B_3_SET ns_noc_io_spio_soc_ip.csr 186115 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_F_3_SET ns_noc_io_spio_soc_ip.csr 186126 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_J_V_3_SET ns_noc_io_spio_soc_ip.csr 186137 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_1_7_7_rivcs_k router_1_7_7_rivcs_k SPIO_NOC_ROUTER_1_7_7_RIVCS_K_ADDRESS SPIO_NOC_ROUTER_1_7_7_RIVCS_K_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OFFSET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 186467 R1_7 register rivcs_k 0x58038 R 0x00000000 Spio_noc_router_1_7_7_rivcs_k This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 186163 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_0_SET ns_noc_io_spio_soc_ip.csr 186177 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_0_SET ns_noc_io_spio_soc_ip.csr 186193 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_0_SET ns_noc_io_spio_soc_ip.csr 186207 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_0_SET ns_noc_io_spio_soc_ip.csr 186218 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_0_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_0_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_0_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_0_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_0_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_0_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_0_SET ns_noc_io_spio_soc_ip.csr 186229 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 186242 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_1_SET ns_noc_io_spio_soc_ip.csr 186256 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_1_SET ns_noc_io_spio_soc_ip.csr 186272 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_1_SET ns_noc_io_spio_soc_ip.csr 186286 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_1_SET ns_noc_io_spio_soc_ip.csr 186297 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_1_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_1_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_1_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_1_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_1_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_1_SET ns_noc_io_spio_soc_ip.csr 186308 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 186321 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_2_SET ns_noc_io_spio_soc_ip.csr 186335 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_2_SET ns_noc_io_spio_soc_ip.csr 186351 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_2_SET ns_noc_io_spio_soc_ip.csr 186365 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_2_SET ns_noc_io_spio_soc_ip.csr 186376 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_2_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_2_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_2_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_2_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_2_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_2_SET ns_noc_io_spio_soc_ip.csr 186387 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 186400 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_UP_3_SET ns_noc_io_spio_soc_ip.csr 186414 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_S_3_SET ns_noc_io_spio_soc_ip.csr 186430 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_B_3_SET ns_noc_io_spio_soc_ip.csr 186444 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_F_3_SET ns_noc_io_spio_soc_ip.csr 186455 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_3_MSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_3_LSB SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_3_RANGE SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_3_RESET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_3_GET SPIO_NOC_ROUTER_1_7_7_RIVCS_K_V_3_SET ns_noc_io_spio_soc_ip.csr 186466 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_1_7_7_rovcs_h router_1_7_7_rovcs_h SPIO_NOC_ROUTER_1_7_7_ROVCS_H_ADDRESS SPIO_NOC_ROUTER_1_7_7_ROVCS_H_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_ROVCS_H_OFFSET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 186728 R1_7 register rovcs_h 0x58040 R 0x00000001 Spio_noc_router_1_7_7_rovcs_h This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_0_SET ns_noc_io_spio_soc_ip.csr 186491 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_0_SET ns_noc_io_spio_soc_ip.csr 186505 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_0_SET ns_noc_io_spio_soc_ip.csr 186520 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_0_SET ns_noc_io_spio_soc_ip.csr 186531 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 186541 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_1_SET ns_noc_io_spio_soc_ip.csr 186553 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_1_SET ns_noc_io_spio_soc_ip.csr 186567 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_1_SET ns_noc_io_spio_soc_ip.csr 186582 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_1_SET ns_noc_io_spio_soc_ip.csr 186593 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 186603 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_2_SET ns_noc_io_spio_soc_ip.csr 186615 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_2_SET ns_noc_io_spio_soc_ip.csr 186629 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_2_SET ns_noc_io_spio_soc_ip.csr 186644 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_2_SET ns_noc_io_spio_soc_ip.csr 186655 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 186665 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CF_3_SET ns_noc_io_spio_soc_ip.csr 186677 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_CE_3_SET ns_noc_io_spio_soc_ip.csr 186691 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_VB_3_SET ns_noc_io_spio_soc_ip.csr 186706 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_RSV_3_SET ns_noc_io_spio_soc_ip.csr 186717 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_H_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 186727 UNSD_3 31 28 0x0 R register spio_noc.router_1_7_7_rovcs_e router_1_7_7_rovcs_e SPIO_NOC_ROUTER_1_7_7_ROVCS_E_ADDRESS SPIO_NOC_ROUTER_1_7_7_ROVCS_E_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_ROVCS_E_OFFSET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 186989 R1_7 register rovcs_e 0x58048 R 0x00000101 Spio_noc_router_1_7_7_rovcs_e This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_0_SET ns_noc_io_spio_soc_ip.csr 186752 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_0_SET ns_noc_io_spio_soc_ip.csr 186766 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_0_SET ns_noc_io_spio_soc_ip.csr 186781 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_0_SET ns_noc_io_spio_soc_ip.csr 186792 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 186802 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_1_SET ns_noc_io_spio_soc_ip.csr 186814 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x1 R CE_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_1_SET ns_noc_io_spio_soc_ip.csr 186828 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_1_SET ns_noc_io_spio_soc_ip.csr 186843 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_1_SET ns_noc_io_spio_soc_ip.csr 186854 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 186864 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_2_SET ns_noc_io_spio_soc_ip.csr 186876 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_2_SET ns_noc_io_spio_soc_ip.csr 186890 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_2_SET ns_noc_io_spio_soc_ip.csr 186905 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_2_SET ns_noc_io_spio_soc_ip.csr 186916 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 186926 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CF_3_SET ns_noc_io_spio_soc_ip.csr 186938 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_CE_3_SET ns_noc_io_spio_soc_ip.csr 186952 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_VB_3_SET ns_noc_io_spio_soc_ip.csr 186967 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_RSV_3_SET ns_noc_io_spio_soc_ip.csr 186978 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_E_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 186988 UNSD_3 31 28 0x0 R register spio_noc.router_1_7_7_rovcs_w router_1_7_7_rovcs_w SPIO_NOC_ROUTER_1_7_7_ROVCS_W_ADDRESS SPIO_NOC_ROUTER_1_7_7_ROVCS_W_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_ROVCS_W_OFFSET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 187250 R1_7 register rovcs_w 0x58058 R 0x00000001 Spio_noc_router_1_7_7_rovcs_w This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_0_SET ns_noc_io_spio_soc_ip.csr 187013 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_0_SET ns_noc_io_spio_soc_ip.csr 187027 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_0_SET ns_noc_io_spio_soc_ip.csr 187042 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_0_SET ns_noc_io_spio_soc_ip.csr 187053 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 187063 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_1_SET ns_noc_io_spio_soc_ip.csr 187075 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_1_SET ns_noc_io_spio_soc_ip.csr 187089 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_1_SET ns_noc_io_spio_soc_ip.csr 187104 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_1_SET ns_noc_io_spio_soc_ip.csr 187115 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 187125 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_2_SET ns_noc_io_spio_soc_ip.csr 187137 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_2_SET ns_noc_io_spio_soc_ip.csr 187151 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_2_SET ns_noc_io_spio_soc_ip.csr 187166 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_2_SET ns_noc_io_spio_soc_ip.csr 187177 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 187187 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CF_3_SET ns_noc_io_spio_soc_ip.csr 187199 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_CE_3_SET ns_noc_io_spio_soc_ip.csr 187213 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_VB_3_SET ns_noc_io_spio_soc_ip.csr 187228 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_RSV_3_SET ns_noc_io_spio_soc_ip.csr 187239 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_W_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 187249 UNSD_3 31 28 0x0 R register spio_noc.router_1_7_7_rovcs_n router_1_7_7_rovcs_n SPIO_NOC_ROUTER_1_7_7_ROVCS_N_ADDRESS SPIO_NOC_ROUTER_1_7_7_ROVCS_N_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_ROVCS_N_OFFSET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 187511 R1_7 register rovcs_n 0x58060 R 0x00000101 Spio_noc_router_1_7_7_rovcs_n This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_0_SET ns_noc_io_spio_soc_ip.csr 187274 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_0_SET ns_noc_io_spio_soc_ip.csr 187288 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_0_SET ns_noc_io_spio_soc_ip.csr 187303 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_0_SET ns_noc_io_spio_soc_ip.csr 187314 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 187324 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_1_SET ns_noc_io_spio_soc_ip.csr 187336 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x1 R CE_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_1_SET ns_noc_io_spio_soc_ip.csr 187350 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_1_SET ns_noc_io_spio_soc_ip.csr 187365 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_1_SET ns_noc_io_spio_soc_ip.csr 187376 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 187386 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_2_SET ns_noc_io_spio_soc_ip.csr 187398 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_2_SET ns_noc_io_spio_soc_ip.csr 187412 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_2_SET ns_noc_io_spio_soc_ip.csr 187427 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_2_SET ns_noc_io_spio_soc_ip.csr 187438 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 187448 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CF_3_SET ns_noc_io_spio_soc_ip.csr 187460 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_CE_3_SET ns_noc_io_spio_soc_ip.csr 187474 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_VB_3_SET ns_noc_io_spio_soc_ip.csr 187489 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_RSV_3_SET ns_noc_io_spio_soc_ip.csr 187500 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_N_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 187510 UNSD_3 31 28 0x0 R register spio_noc.router_1_7_7_rovcs_i router_1_7_7_rovcs_i SPIO_NOC_ROUTER_1_7_7_ROVCS_I_ADDRESS SPIO_NOC_ROUTER_1_7_7_ROVCS_I_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_ROVCS_I_OFFSET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 187772 R1_7 register rovcs_i 0x58068 R 0x00000101 Spio_noc_router_1_7_7_rovcs_i This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_0_SET ns_noc_io_spio_soc_ip.csr 187535 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_0_SET ns_noc_io_spio_soc_ip.csr 187549 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_0_SET ns_noc_io_spio_soc_ip.csr 187564 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_0_SET ns_noc_io_spio_soc_ip.csr 187575 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 187585 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_1_SET ns_noc_io_spio_soc_ip.csr 187597 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x1 R CE_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_1_SET ns_noc_io_spio_soc_ip.csr 187611 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_1_SET ns_noc_io_spio_soc_ip.csr 187626 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_1_SET ns_noc_io_spio_soc_ip.csr 187637 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 187647 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_2_SET ns_noc_io_spio_soc_ip.csr 187659 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_2_SET ns_noc_io_spio_soc_ip.csr 187673 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_2_SET ns_noc_io_spio_soc_ip.csr 187688 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_2_SET ns_noc_io_spio_soc_ip.csr 187699 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 187709 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CF_3_SET ns_noc_io_spio_soc_ip.csr 187721 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_CE_3_SET ns_noc_io_spio_soc_ip.csr 187735 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_VB_3_SET ns_noc_io_spio_soc_ip.csr 187750 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_RSV_3_SET ns_noc_io_spio_soc_ip.csr 187761 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_I_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 187771 UNSD_3 31 28 0x0 R register spio_noc.router_1_7_7_rovcs_j router_1_7_7_rovcs_j SPIO_NOC_ROUTER_1_7_7_ROVCS_J_ADDRESS SPIO_NOC_ROUTER_1_7_7_ROVCS_J_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_ROVCS_J_OFFSET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 188033 R1_7 register rovcs_j 0x58070 R 0x00000001 Spio_noc_router_1_7_7_rovcs_j This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_0_SET ns_noc_io_spio_soc_ip.csr 187796 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_0_SET ns_noc_io_spio_soc_ip.csr 187810 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_0_SET ns_noc_io_spio_soc_ip.csr 187825 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_0_SET ns_noc_io_spio_soc_ip.csr 187836 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 187846 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_1_SET ns_noc_io_spio_soc_ip.csr 187858 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_1_SET ns_noc_io_spio_soc_ip.csr 187872 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_1_SET ns_noc_io_spio_soc_ip.csr 187887 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_1_SET ns_noc_io_spio_soc_ip.csr 187898 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 187908 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_2_SET ns_noc_io_spio_soc_ip.csr 187920 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_2_SET ns_noc_io_spio_soc_ip.csr 187934 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_2_SET ns_noc_io_spio_soc_ip.csr 187949 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_2_SET ns_noc_io_spio_soc_ip.csr 187960 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 187970 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CF_3_SET ns_noc_io_spio_soc_ip.csr 187982 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_CE_3_SET ns_noc_io_spio_soc_ip.csr 187996 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_VB_3_SET ns_noc_io_spio_soc_ip.csr 188011 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_RSV_3_SET ns_noc_io_spio_soc_ip.csr 188022 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_J_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 188032 UNSD_3 31 28 0x0 R register spio_noc.router_1_7_7_rovcs_k router_1_7_7_rovcs_k SPIO_NOC_ROUTER_1_7_7_ROVCS_K_ADDRESS SPIO_NOC_ROUTER_1_7_7_ROVCS_K_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_ROVCS_K_OFFSET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 188294 R1_7 register rovcs_k 0x58078 R 0x00000001 Spio_noc_router_1_7_7_rovcs_k This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_0_SET ns_noc_io_spio_soc_ip.csr 188057 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_0_SET ns_noc_io_spio_soc_ip.csr 188071 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_0_SET ns_noc_io_spio_soc_ip.csr 188086 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_0_SET ns_noc_io_spio_soc_ip.csr 188097 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_0_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_0_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_0_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_0_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_0_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_0_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 188107 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_1_SET ns_noc_io_spio_soc_ip.csr 188119 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_1_SET ns_noc_io_spio_soc_ip.csr 188133 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_1_SET ns_noc_io_spio_soc_ip.csr 188148 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_1_SET ns_noc_io_spio_soc_ip.csr 188159 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_1_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_1_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_1_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_1_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_1_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_1_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 188169 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_2_SET ns_noc_io_spio_soc_ip.csr 188181 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_2_SET ns_noc_io_spio_soc_ip.csr 188195 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_2_SET ns_noc_io_spio_soc_ip.csr 188210 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_2_SET ns_noc_io_spio_soc_ip.csr 188221 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_2_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_2_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_2_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_2_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_2_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_2_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 188231 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CF_3_SET ns_noc_io_spio_soc_ip.csr 188243 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_CE_3_SET ns_noc_io_spio_soc_ip.csr 188257 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_VB_3_SET ns_noc_io_spio_soc_ip.csr 188272 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_RSV_3_SET ns_noc_io_spio_soc_ip.csr 188283 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_3_WIDTH SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_3_MSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_3_LSB SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_3_RANGE SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_3_RESET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_3_GET SPIO_NOC_ROUTER_1_7_7_ROVCS_K_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 188293 UNSD_3 31 28 0x0 R register spio_noc.router_1_7_7_re router_1_7_7_re SPIO_NOC_ROUTER_1_7_7_RE_ADDRESS SPIO_NOC_ROUTER_1_7_7_RE_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_RE_OFFSET SPIO_NOC_ROUTER_1_7_7_RE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 188468 R1_7 register re 0x58080 R/W 0x00000000 Spio_noc_router_1_7_7_re This register tracks the interrupt or error events that can occur in the router. The only interrupt event is the event counter overflow. This register is readable, and can be cleared by performing a write with the write data bits set to 0 for the bits that should be cleared. false false false false OVFI SPIO_NOC_ROUTER_1_7_7_RE_OVFI_WIDTH SPIO_NOC_ROUTER_1_7_7_RE_OVFI_MSB SPIO_NOC_ROUTER_1_7_7_RE_OVFI_LSB SPIO_NOC_ROUTER_1_7_7_RE_OVFI_RANGE SPIO_NOC_ROUTER_1_7_7_RE_OVFI_RESET SPIO_NOC_ROUTER_1_7_7_RE_OVFI_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RE_OVFI_GET SPIO_NOC_ROUTER_1_7_7_RE_OVFI_SET ns_noc_io_spio_soc_ip.csr 188320 OVFI 1'b1: In this status bit indicates that the router input event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 0 0 0x0 R/W CSR_PARERR SPIO_NOC_ROUTER_1_7_7_RE_CSR_PARERR_WIDTH SPIO_NOC_ROUTER_1_7_7_RE_CSR_PARERR_MSB SPIO_NOC_ROUTER_1_7_7_RE_CSR_PARERR_LSB SPIO_NOC_ROUTER_1_7_7_RE_CSR_PARERR_RANGE SPIO_NOC_ROUTER_1_7_7_RE_CSR_PARERR_RESET SPIO_NOC_ROUTER_1_7_7_RE_CSR_PARERR_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RE_CSR_PARERR_GET SPIO_NOC_ROUTER_1_7_7_RE_CSR_PARERR_SET ns_noc_io_spio_soc_ip.csr 188331 CSR_PARERR 1'b1: Parity error in config/status registers 1 1 0x0 R/W OVFO SPIO_NOC_ROUTER_1_7_7_RE_OVFO_WIDTH SPIO_NOC_ROUTER_1_7_7_RE_OVFO_MSB SPIO_NOC_ROUTER_1_7_7_RE_OVFO_LSB SPIO_NOC_ROUTER_1_7_7_RE_OVFO_RANGE SPIO_NOC_ROUTER_1_7_7_RE_OVFO_RESET SPIO_NOC_ROUTER_1_7_7_RE_OVFO_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RE_OVFO_GET SPIO_NOC_ROUTER_1_7_7_RE_OVFO_SET ns_noc_io_spio_soc_ip.csr 188345 OVFO 1'b1: In this status bit indicates that the router output event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 2 2 0x0 R/W UNSD_7_3 SPIO_NOC_ROUTER_1_7_7_RE_UNSD_7_3_WIDTH SPIO_NOC_ROUTER_1_7_7_RE_UNSD_7_3_MSB SPIO_NOC_ROUTER_1_7_7_RE_UNSD_7_3_LSB SPIO_NOC_ROUTER_1_7_7_RE_UNSD_7_3_RANGE SPIO_NOC_ROUTER_1_7_7_RE_UNSD_7_3_RESET SPIO_NOC_ROUTER_1_7_7_RE_UNSD_7_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RE_UNSD_7_3_GET SPIO_NOC_ROUTER_1_7_7_RE_UNSD_7_3_SET ns_noc_io_spio_soc_ip.csr 188356 UNSD_7_3 7 3 0x00 R PGE SPIO_NOC_ROUTER_1_7_7_RE_PGE_WIDTH SPIO_NOC_ROUTER_1_7_7_RE_PGE_MSB SPIO_NOC_ROUTER_1_7_7_RE_PGE_LSB SPIO_NOC_ROUTER_1_7_7_RE_PGE_RANGE SPIO_NOC_ROUTER_1_7_7_RE_PGE_RESET SPIO_NOC_ROUTER_1_7_7_RE_PGE_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RE_PGE_GET SPIO_NOC_ROUTER_1_7_7_RE_PGE_SET ns_noc_io_spio_soc_ip.csr 188368 PGE 1'b1: Power gating error, traffic received after router commited to power down 8 8 0x0 R/W NLU SPIO_NOC_ROUTER_1_7_7_RE_NLU_WIDTH SPIO_NOC_ROUTER_1_7_7_RE_NLU_MSB SPIO_NOC_ROUTER_1_7_7_RE_NLU_LSB SPIO_NOC_ROUTER_1_7_7_RE_NLU_RANGE SPIO_NOC_ROUTER_1_7_7_RE_NLU_RESET SPIO_NOC_ROUTER_1_7_7_RE_NLU_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RE_NLU_GET SPIO_NOC_ROUTER_1_7_7_RE_NLU_SET ns_noc_io_spio_soc_ip.csr 188379 NLU 1'b1: Traffic destined for North link which is unavailable 9 9 0x0 R/W ELU SPIO_NOC_ROUTER_1_7_7_RE_ELU_WIDTH SPIO_NOC_ROUTER_1_7_7_RE_ELU_MSB SPIO_NOC_ROUTER_1_7_7_RE_ELU_LSB SPIO_NOC_ROUTER_1_7_7_RE_ELU_RANGE SPIO_NOC_ROUTER_1_7_7_RE_ELU_RESET SPIO_NOC_ROUTER_1_7_7_RE_ELU_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RE_ELU_GET SPIO_NOC_ROUTER_1_7_7_RE_ELU_SET ns_noc_io_spio_soc_ip.csr 188390 ELU 1'b1: Traffic destined for East link which is unavailable 10 10 0x0 R/W WLU SPIO_NOC_ROUTER_1_7_7_RE_WLU_WIDTH SPIO_NOC_ROUTER_1_7_7_RE_WLU_MSB SPIO_NOC_ROUTER_1_7_7_RE_WLU_LSB SPIO_NOC_ROUTER_1_7_7_RE_WLU_RANGE SPIO_NOC_ROUTER_1_7_7_RE_WLU_RESET SPIO_NOC_ROUTER_1_7_7_RE_WLU_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RE_WLU_GET SPIO_NOC_ROUTER_1_7_7_RE_WLU_SET ns_noc_io_spio_soc_ip.csr 188401 WLU 1'b1: Traffic destined for West link which is unavailable 11 11 0x0 R/W SLU SPIO_NOC_ROUTER_1_7_7_RE_SLU_WIDTH SPIO_NOC_ROUTER_1_7_7_RE_SLU_MSB SPIO_NOC_ROUTER_1_7_7_RE_SLU_LSB SPIO_NOC_ROUTER_1_7_7_RE_SLU_RANGE SPIO_NOC_ROUTER_1_7_7_RE_SLU_RESET SPIO_NOC_ROUTER_1_7_7_RE_SLU_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RE_SLU_GET SPIO_NOC_ROUTER_1_7_7_RE_SLU_SET ns_noc_io_spio_soc_ip.csr 188412 SLU 1'b1: Traffic destined for South link which is unavailable 12 12 0x0 R/W HLU SPIO_NOC_ROUTER_1_7_7_RE_HLU_WIDTH SPIO_NOC_ROUTER_1_7_7_RE_HLU_MSB SPIO_NOC_ROUTER_1_7_7_RE_HLU_LSB SPIO_NOC_ROUTER_1_7_7_RE_HLU_RANGE SPIO_NOC_ROUTER_1_7_7_RE_HLU_RESET SPIO_NOC_ROUTER_1_7_7_RE_HLU_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RE_HLU_GET SPIO_NOC_ROUTER_1_7_7_RE_HLU_SET ns_noc_io_spio_soc_ip.csr 188423 HLU 1'b1: Traffic destined for H link which is unavailable 13 13 0x0 R/W ILU SPIO_NOC_ROUTER_1_7_7_RE_ILU_WIDTH SPIO_NOC_ROUTER_1_7_7_RE_ILU_MSB SPIO_NOC_ROUTER_1_7_7_RE_ILU_LSB SPIO_NOC_ROUTER_1_7_7_RE_ILU_RANGE SPIO_NOC_ROUTER_1_7_7_RE_ILU_RESET SPIO_NOC_ROUTER_1_7_7_RE_ILU_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RE_ILU_GET SPIO_NOC_ROUTER_1_7_7_RE_ILU_SET ns_noc_io_spio_soc_ip.csr 188434 ILU 1'b1: Traffic destined for I link which is unavailable 14 14 0x0 R/W JLU SPIO_NOC_ROUTER_1_7_7_RE_JLU_WIDTH SPIO_NOC_ROUTER_1_7_7_RE_JLU_MSB SPIO_NOC_ROUTER_1_7_7_RE_JLU_LSB SPIO_NOC_ROUTER_1_7_7_RE_JLU_RANGE SPIO_NOC_ROUTER_1_7_7_RE_JLU_RESET SPIO_NOC_ROUTER_1_7_7_RE_JLU_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RE_JLU_GET SPIO_NOC_ROUTER_1_7_7_RE_JLU_SET ns_noc_io_spio_soc_ip.csr 188445 JLU 1'b1: Traffic destined for J link which is unavailable 15 15 0x0 R/W KLU SPIO_NOC_ROUTER_1_7_7_RE_KLU_WIDTH SPIO_NOC_ROUTER_1_7_7_RE_KLU_MSB SPIO_NOC_ROUTER_1_7_7_RE_KLU_LSB SPIO_NOC_ROUTER_1_7_7_RE_KLU_RANGE SPIO_NOC_ROUTER_1_7_7_RE_KLU_RESET SPIO_NOC_ROUTER_1_7_7_RE_KLU_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RE_KLU_GET SPIO_NOC_ROUTER_1_7_7_RE_KLU_SET ns_noc_io_spio_soc_ip.csr 188456 KLU 1'b1: Traffic destined for K link which is unavailable 16 16 0x0 R/W UNSD_31_14 SPIO_NOC_ROUTER_1_7_7_RE_UNSD_31_14_WIDTH SPIO_NOC_ROUTER_1_7_7_RE_UNSD_31_14_MSB SPIO_NOC_ROUTER_1_7_7_RE_UNSD_31_14_LSB SPIO_NOC_ROUTER_1_7_7_RE_UNSD_31_14_RANGE SPIO_NOC_ROUTER_1_7_7_RE_UNSD_31_14_RESET SPIO_NOC_ROUTER_1_7_7_RE_UNSD_31_14_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RE_UNSD_31_14_GET SPIO_NOC_ROUTER_1_7_7_RE_UNSD_31_14_SET ns_noc_io_spio_soc_ip.csr 188467 UNSD_31_14 31 17 0x0000 R register spio_noc.router_1_7_7_rem router_1_7_7_rem SPIO_NOC_ROUTER_1_7_7_REM_ADDRESS SPIO_NOC_ROUTER_1_7_7_REM_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_REM_OFFSET SPIO_NOC_ROUTER_1_7_7_REM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 188641 R1_7 register rem 0x58088 R/W 0x0001fe00 Spio_noc_router_1_7_7_rem This register is used to select whether the interrupt events in the Router Event Interrupt Status register should send an interrupt when asserted. If the corresponding bit is set to 1, an interrupt will not be sent. This register can be read and written to. false false false false OVFIM SPIO_NOC_ROUTER_1_7_7_REM_OVFIM_WIDTH SPIO_NOC_ROUTER_1_7_7_REM_OVFIM_MSB SPIO_NOC_ROUTER_1_7_7_REM_OVFIM_LSB SPIO_NOC_ROUTER_1_7_7_REM_OVFIM_RANGE SPIO_NOC_ROUTER_1_7_7_REM_OVFIM_RESET SPIO_NOC_ROUTER_1_7_7_REM_OVFIM_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_REM_OVFIM_GET SPIO_NOC_ROUTER_1_7_7_REM_OVFIM_SET ns_noc_io_spio_soc_ip.csr 188494 OVFIM 1'b1: Masks or disables an interrupt from being generated by the input event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 0 0 0x0 R/W CSR_PARERRM SPIO_NOC_ROUTER_1_7_7_REM_CSR_PARERRM_WIDTH SPIO_NOC_ROUTER_1_7_7_REM_CSR_PARERRM_MSB SPIO_NOC_ROUTER_1_7_7_REM_CSR_PARERRM_LSB SPIO_NOC_ROUTER_1_7_7_REM_CSR_PARERRM_RANGE SPIO_NOC_ROUTER_1_7_7_REM_CSR_PARERRM_RESET SPIO_NOC_ROUTER_1_7_7_REM_CSR_PARERRM_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_REM_CSR_PARERRM_GET SPIO_NOC_ROUTER_1_7_7_REM_CSR_PARERRM_SET ns_noc_io_spio_soc_ip.csr 188505 CSR_PARERRM 1'b1: Mask CSR parity error interrupt 1 1 0x0 R/W OVFOM SPIO_NOC_ROUTER_1_7_7_REM_OVFOM_WIDTH SPIO_NOC_ROUTER_1_7_7_REM_OVFOM_MSB SPIO_NOC_ROUTER_1_7_7_REM_OVFOM_LSB SPIO_NOC_ROUTER_1_7_7_REM_OVFOM_RANGE SPIO_NOC_ROUTER_1_7_7_REM_OVFOM_RESET SPIO_NOC_ROUTER_1_7_7_REM_OVFOM_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_REM_OVFOM_GET SPIO_NOC_ROUTER_1_7_7_REM_OVFOM_SET ns_noc_io_spio_soc_ip.csr 188519 OVFOM 1'b1: Masks or disables an interrupt from being generated by the output event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 2 2 0x0 R/W UNSD_7_3 SPIO_NOC_ROUTER_1_7_7_REM_UNSD_7_3_WIDTH SPIO_NOC_ROUTER_1_7_7_REM_UNSD_7_3_MSB SPIO_NOC_ROUTER_1_7_7_REM_UNSD_7_3_LSB SPIO_NOC_ROUTER_1_7_7_REM_UNSD_7_3_RANGE SPIO_NOC_ROUTER_1_7_7_REM_UNSD_7_3_RESET SPIO_NOC_ROUTER_1_7_7_REM_UNSD_7_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_REM_UNSD_7_3_GET SPIO_NOC_ROUTER_1_7_7_REM_UNSD_7_3_SET ns_noc_io_spio_soc_ip.csr 188530 UNSD_7_3 7 3 0x00 R PGM SPIO_NOC_ROUTER_1_7_7_REM_PGM_WIDTH SPIO_NOC_ROUTER_1_7_7_REM_PGM_MSB SPIO_NOC_ROUTER_1_7_7_REM_PGM_LSB SPIO_NOC_ROUTER_1_7_7_REM_PGM_RANGE SPIO_NOC_ROUTER_1_7_7_REM_PGM_RESET SPIO_NOC_ROUTER_1_7_7_REM_PGM_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_REM_PGM_GET SPIO_NOC_ROUTER_1_7_7_REM_PGM_SET ns_noc_io_spio_soc_ip.csr 188541 PGM 1'b1: Mask PGE error interrupt 8 8 0x0 R/W MN SPIO_NOC_ROUTER_1_7_7_REM_MN_WIDTH SPIO_NOC_ROUTER_1_7_7_REM_MN_MSB SPIO_NOC_ROUTER_1_7_7_REM_MN_LSB SPIO_NOC_ROUTER_1_7_7_REM_MN_RANGE SPIO_NOC_ROUTER_1_7_7_REM_MN_RESET SPIO_NOC_ROUTER_1_7_7_REM_MN_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_REM_MN_GET SPIO_NOC_ROUTER_1_7_7_REM_MN_SET ns_noc_io_spio_soc_ip.csr 188552 MN 1'b1: Mask NLU error interrupt 9 9 0x1 R/W ME SPIO_NOC_ROUTER_1_7_7_REM_ME_WIDTH SPIO_NOC_ROUTER_1_7_7_REM_ME_MSB SPIO_NOC_ROUTER_1_7_7_REM_ME_LSB SPIO_NOC_ROUTER_1_7_7_REM_ME_RANGE SPIO_NOC_ROUTER_1_7_7_REM_ME_RESET SPIO_NOC_ROUTER_1_7_7_REM_ME_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_REM_ME_GET SPIO_NOC_ROUTER_1_7_7_REM_ME_SET ns_noc_io_spio_soc_ip.csr 188563 ME 1'b1: Mask ELU error interrupt 10 10 0x1 R/W MW SPIO_NOC_ROUTER_1_7_7_REM_MW_WIDTH SPIO_NOC_ROUTER_1_7_7_REM_MW_MSB SPIO_NOC_ROUTER_1_7_7_REM_MW_LSB SPIO_NOC_ROUTER_1_7_7_REM_MW_RANGE SPIO_NOC_ROUTER_1_7_7_REM_MW_RESET SPIO_NOC_ROUTER_1_7_7_REM_MW_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_REM_MW_GET SPIO_NOC_ROUTER_1_7_7_REM_MW_SET ns_noc_io_spio_soc_ip.csr 188574 MW 1'b1: Mask WLU error interrupt 11 11 0x1 R/W MS SPIO_NOC_ROUTER_1_7_7_REM_MS_WIDTH SPIO_NOC_ROUTER_1_7_7_REM_MS_MSB SPIO_NOC_ROUTER_1_7_7_REM_MS_LSB SPIO_NOC_ROUTER_1_7_7_REM_MS_RANGE SPIO_NOC_ROUTER_1_7_7_REM_MS_RESET SPIO_NOC_ROUTER_1_7_7_REM_MS_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_REM_MS_GET SPIO_NOC_ROUTER_1_7_7_REM_MS_SET ns_noc_io_spio_soc_ip.csr 188585 MS 1'b1: Mask SLU error interrupt 12 12 0x1 R/W MH SPIO_NOC_ROUTER_1_7_7_REM_MH_WIDTH SPIO_NOC_ROUTER_1_7_7_REM_MH_MSB SPIO_NOC_ROUTER_1_7_7_REM_MH_LSB SPIO_NOC_ROUTER_1_7_7_REM_MH_RANGE SPIO_NOC_ROUTER_1_7_7_REM_MH_RESET SPIO_NOC_ROUTER_1_7_7_REM_MH_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_REM_MH_GET SPIO_NOC_ROUTER_1_7_7_REM_MH_SET ns_noc_io_spio_soc_ip.csr 188596 MH 1'b1: Mask HLU error interrupt 13 13 0x1 R/W MI SPIO_NOC_ROUTER_1_7_7_REM_MI_WIDTH SPIO_NOC_ROUTER_1_7_7_REM_MI_MSB SPIO_NOC_ROUTER_1_7_7_REM_MI_LSB SPIO_NOC_ROUTER_1_7_7_REM_MI_RANGE SPIO_NOC_ROUTER_1_7_7_REM_MI_RESET SPIO_NOC_ROUTER_1_7_7_REM_MI_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_REM_MI_GET SPIO_NOC_ROUTER_1_7_7_REM_MI_SET ns_noc_io_spio_soc_ip.csr 188607 MI 1'b1: Mask ILU error interrupt 14 14 0x1 R/W MJ SPIO_NOC_ROUTER_1_7_7_REM_MJ_WIDTH SPIO_NOC_ROUTER_1_7_7_REM_MJ_MSB SPIO_NOC_ROUTER_1_7_7_REM_MJ_LSB SPIO_NOC_ROUTER_1_7_7_REM_MJ_RANGE SPIO_NOC_ROUTER_1_7_7_REM_MJ_RESET SPIO_NOC_ROUTER_1_7_7_REM_MJ_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_REM_MJ_GET SPIO_NOC_ROUTER_1_7_7_REM_MJ_SET ns_noc_io_spio_soc_ip.csr 188618 MJ 1'b1: Mask JLU error interrupt 15 15 0x1 R/W MK SPIO_NOC_ROUTER_1_7_7_REM_MK_WIDTH SPIO_NOC_ROUTER_1_7_7_REM_MK_MSB SPIO_NOC_ROUTER_1_7_7_REM_MK_LSB SPIO_NOC_ROUTER_1_7_7_REM_MK_RANGE SPIO_NOC_ROUTER_1_7_7_REM_MK_RESET SPIO_NOC_ROUTER_1_7_7_REM_MK_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_REM_MK_GET SPIO_NOC_ROUTER_1_7_7_REM_MK_SET ns_noc_io_spio_soc_ip.csr 188629 MK 1'b1: Mask KLU error interrupt 16 16 0x1 R/W UNSD_31_14 SPIO_NOC_ROUTER_1_7_7_REM_UNSD_31_14_WIDTH SPIO_NOC_ROUTER_1_7_7_REM_UNSD_31_14_MSB SPIO_NOC_ROUTER_1_7_7_REM_UNSD_31_14_LSB SPIO_NOC_ROUTER_1_7_7_REM_UNSD_31_14_RANGE SPIO_NOC_ROUTER_1_7_7_REM_UNSD_31_14_RESET SPIO_NOC_ROUTER_1_7_7_REM_UNSD_31_14_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_REM_UNSD_31_14_GET SPIO_NOC_ROUTER_1_7_7_REM_UNSD_31_14_SET ns_noc_io_spio_soc_ip.csr 188640 UNSD_31_14 31 17 0x0000 R register spio_noc.router_1_7_7_recc router_1_7_7_recc SPIO_NOC_ROUTER_1_7_7_RECC_ADDRESS SPIO_NOC_ROUTER_1_7_7_RECC_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_RECC_OFFSET SPIO_NOC_ROUTER_1_7_7_RECC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 188726 R1_7 register recc 0x58090 R/W 0x00000000 Spio_noc_router_1_7_7_recc This register is used to select which hardware events will increment the event counter. false false false false IVC SPIO_NOC_ROUTER_1_7_7_RECC_IVC_WIDTH SPIO_NOC_ROUTER_1_7_7_RECC_IVC_MSB SPIO_NOC_ROUTER_1_7_7_RECC_IVC_LSB SPIO_NOC_ROUTER_1_7_7_RECC_IVC_RANGE SPIO_NOC_ROUTER_1_7_7_RECC_IVC_RESET SPIO_NOC_ROUTER_1_7_7_RECC_IVC_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RECC_IVC_GET SPIO_NOC_ROUTER_1_7_7_RECC_IVC_SET ns_noc_io_spio_soc_ip.csr 188662 IVC 11: Input VC 3 10: Input VC 2 01: Input VC 1 00: Input VC 0 1 0 0x0 R/W UNSD_3_2 SPIO_NOC_ROUTER_1_7_7_RECC_UNSD_3_2_WIDTH SPIO_NOC_ROUTER_1_7_7_RECC_UNSD_3_2_MSB SPIO_NOC_ROUTER_1_7_7_RECC_UNSD_3_2_LSB SPIO_NOC_ROUTER_1_7_7_RECC_UNSD_3_2_RANGE SPIO_NOC_ROUTER_1_7_7_RECC_UNSD_3_2_RESET SPIO_NOC_ROUTER_1_7_7_RECC_UNSD_3_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RECC_UNSD_3_2_GET SPIO_NOC_ROUTER_1_7_7_RECC_UNSD_3_2_SET ns_noc_io_spio_soc_ip.csr 188673 UNSD_3_2 3 2 0x0 R INP SPIO_NOC_ROUTER_1_7_7_RECC_INP_WIDTH SPIO_NOC_ROUTER_1_7_7_RECC_INP_MSB SPIO_NOC_ROUTER_1_7_7_RECC_INP_LSB SPIO_NOC_ROUTER_1_7_7_RECC_INP_RANGE SPIO_NOC_ROUTER_1_7_7_RECC_INP_RESET SPIO_NOC_ROUTER_1_7_7_RECC_INP_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RECC_INP_GET SPIO_NOC_ROUTER_1_7_7_RECC_INP_SET ns_noc_io_spio_soc_ip.csr 188684 INP Input port on which the event is captured 6 4 0x0 R/W UNSD_7_7 SPIO_NOC_ROUTER_1_7_7_RECC_UNSD_7_7_WIDTH SPIO_NOC_ROUTER_1_7_7_RECC_UNSD_7_7_MSB SPIO_NOC_ROUTER_1_7_7_RECC_UNSD_7_7_LSB SPIO_NOC_ROUTER_1_7_7_RECC_UNSD_7_7_RANGE SPIO_NOC_ROUTER_1_7_7_RECC_UNSD_7_7_RESET SPIO_NOC_ROUTER_1_7_7_RECC_UNSD_7_7_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RECC_UNSD_7_7_GET SPIO_NOC_ROUTER_1_7_7_RECC_UNSD_7_7_SET ns_noc_io_spio_soc_ip.csr 188695 UNSD_7_7 7 7 0x0 R EVT SPIO_NOC_ROUTER_1_7_7_RECC_EVT_WIDTH SPIO_NOC_ROUTER_1_7_7_RECC_EVT_MSB SPIO_NOC_ROUTER_1_7_7_RECC_EVT_LSB SPIO_NOC_ROUTER_1_7_7_RECC_EVT_RANGE SPIO_NOC_ROUTER_1_7_7_RECC_EVT_RESET SPIO_NOC_ROUTER_1_7_7_RECC_EVT_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RECC_EVT_GET SPIO_NOC_ROUTER_1_7_7_RECC_EVT_SET ns_noc_io_spio_soc_ip.csr 188714 EVT 11: Generates count event when VC has valid data, but is stalled 10: Generates count event on every flit received for the selected input port and selected input VCs, this can be used to count total flits received on a router input port 01: Generates count event on every EOP received for the selected input port and selected input VCs, this can be used to count packets received on a router input port 00: Disable 9 8 0x0 R/W UNSD_31_10 SPIO_NOC_ROUTER_1_7_7_RECC_UNSD_31_10_WIDTH SPIO_NOC_ROUTER_1_7_7_RECC_UNSD_31_10_MSB SPIO_NOC_ROUTER_1_7_7_RECC_UNSD_31_10_LSB SPIO_NOC_ROUTER_1_7_7_RECC_UNSD_31_10_RANGE SPIO_NOC_ROUTER_1_7_7_RECC_UNSD_31_10_RESET SPIO_NOC_ROUTER_1_7_7_RECC_UNSD_31_10_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RECC_UNSD_31_10_GET SPIO_NOC_ROUTER_1_7_7_RECC_UNSD_31_10_SET ns_noc_io_spio_soc_ip.csr 188725 UNSD_31_10 31 10 0x000000 R register spio_noc.router_1_7_7_rec router_1_7_7_rec SPIO_NOC_ROUTER_1_7_7_REC_ADDRESS SPIO_NOC_ROUTER_1_7_7_REC_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_REC_OFFSET SPIO_NOC_ROUTER_1_7_7_REC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 188751 R1_7 register rec 0x58098 R/W 0x00000000 Spio_noc_router_1_7_7_rec This register holds the event counter. The value can be read to determine the current count value. The value can be written to initialize the counter. When events trigger a count, the counter will increment. When the counter increments at its highest value, it will roll over to zero and the overflow will mark the Router Event Interrupt Status register, which could trigger an interrupt. false false false false EVENT_CNTR SPIO_NOC_ROUTER_1_7_7_REC_EVENT_CNTR_WIDTH SPIO_NOC_ROUTER_1_7_7_REC_EVENT_CNTR_MSB SPIO_NOC_ROUTER_1_7_7_REC_EVENT_CNTR_LSB SPIO_NOC_ROUTER_1_7_7_REC_EVENT_CNTR_RANGE SPIO_NOC_ROUTER_1_7_7_REC_EVENT_CNTR_RESET SPIO_NOC_ROUTER_1_7_7_REC_EVENT_CNTR_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_REC_EVENT_CNTR_GET SPIO_NOC_ROUTER_1_7_7_REC_EVENT_CNTR_SET ns_noc_io_spio_soc_ip.csr 188750 EVENT_CNTR 32'bit event incrementing counter. Rollover from 32'hFFFFF -> 32'd0 sets the rollover status bit RE 31 0 0x00000000 R/W register spio_noc.router_1_7_7_id router_1_7_7_id SPIO_NOC_ROUTER_1_7_7_ID_ADDRESS SPIO_NOC_ROUTER_1_7_7_ID_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_ID_OFFSET SPIO_NOC_ROUTER_1_7_7_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 188820 R1_7 register id 0x580A0 R 0x010000c1 Spio_noc_router_1_7_7_id This register holds layer and position information for the router. It is a read-only register. It can be used for debugging software access to the NoC elements by confirming that a read has successfully targeted the correct NoC element. false false false false LAYER SPIO_NOC_ROUTER_1_7_7_ID_LAYER_WIDTH SPIO_NOC_ROUTER_1_7_7_ID_LAYER_MSB SPIO_NOC_ROUTER_1_7_7_ID_LAYER_LSB SPIO_NOC_ROUTER_1_7_7_ID_LAYER_RANGE SPIO_NOC_ROUTER_1_7_7_ID_LAYER_RESET SPIO_NOC_ROUTER_1_7_7_ID_LAYER_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ID_LAYER_GET SPIO_NOC_ROUTER_1_7_7_ID_LAYER_SET ns_noc_io_spio_soc_ip.csr 188776 LAYER 5-bit identifier of the NoC layer on which this router is located 4 0 0x01 R POS SPIO_NOC_ROUTER_1_7_7_ID_POS_WIDTH SPIO_NOC_ROUTER_1_7_7_ID_POS_MSB SPIO_NOC_ROUTER_1_7_7_ID_POS_LSB SPIO_NOC_ROUTER_1_7_7_ID_POS_RANGE SPIO_NOC_ROUTER_1_7_7_ID_POS_RESET SPIO_NOC_ROUTER_1_7_7_ID_POS_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ID_POS_GET SPIO_NOC_ROUTER_1_7_7_ID_POS_SET ns_noc_io_spio_soc_ip.csr 188787 POS 16-bit position ID of this router in the NoC 20 5 0x0006 R ZERO SPIO_NOC_ROUTER_1_7_7_ID_ZERO_WIDTH SPIO_NOC_ROUTER_1_7_7_ID_ZERO_MSB SPIO_NOC_ROUTER_1_7_7_ID_ZERO_LSB SPIO_NOC_ROUTER_1_7_7_ID_ZERO_RANGE SPIO_NOC_ROUTER_1_7_7_ID_ZERO_RESET SPIO_NOC_ROUTER_1_7_7_ID_ZERO_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ID_ZERO_GET SPIO_NOC_ROUTER_1_7_7_ID_ZERO_SET ns_noc_io_spio_soc_ip.csr 188798 ZERO Zeroes 23 21 0x0 R ONE SPIO_NOC_ROUTER_1_7_7_ID_ONE_WIDTH SPIO_NOC_ROUTER_1_7_7_ID_ONE_MSB SPIO_NOC_ROUTER_1_7_7_ID_ONE_LSB SPIO_NOC_ROUTER_1_7_7_ID_ONE_RANGE SPIO_NOC_ROUTER_1_7_7_ID_ONE_RESET SPIO_NOC_ROUTER_1_7_7_ID_ONE_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ID_ONE_GET SPIO_NOC_ROUTER_1_7_7_ID_ONE_SET ns_noc_io_spio_soc_ip.csr 188809 ONE One 24 24 0x1 R UNSD_31_25 SPIO_NOC_ROUTER_1_7_7_ID_UNSD_31_25_WIDTH SPIO_NOC_ROUTER_1_7_7_ID_UNSD_31_25_MSB SPIO_NOC_ROUTER_1_7_7_ID_UNSD_31_25_LSB SPIO_NOC_ROUTER_1_7_7_ID_UNSD_31_25_RANGE SPIO_NOC_ROUTER_1_7_7_ID_UNSD_31_25_RESET SPIO_NOC_ROUTER_1_7_7_ID_UNSD_31_25_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ID_UNSD_31_25_GET SPIO_NOC_ROUTER_1_7_7_ID_UNSD_31_25_SET ns_noc_io_spio_soc_ip.csr 188819 UNSD_31_25 31 25 0x00 R register spio_noc.router_1_7_7_rcgc router_1_7_7_rcgc SPIO_NOC_ROUTER_1_7_7_RCGC_ADDRESS SPIO_NOC_ROUTER_1_7_7_RCGC_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_RCGC_OFFSET SPIO_NOC_ROUTER_1_7_7_RCGC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 188846 R1_7 register rcgc 0x580A8 R/W 0x00000064 Spio_noc_router_1_7_7_rcgc Programmable interval used by coarse clock gating logic in routers.This count determines the consecutive number of idle cycle after which a router output port initiates coarse clock gating of the local port clock and de-asserts the 'busy' signal to the downstream router. This signal indicates inactivity to the downstream router and allows it to initiate coarse clock gating of its corresponding input port. false false false false HYSTERESIS_COUNTER SPIO_NOC_ROUTER_1_7_7_RCGC_HYSTERESIS_COUNTER_WIDTH SPIO_NOC_ROUTER_1_7_7_RCGC_HYSTERESIS_COUNTER_MSB SPIO_NOC_ROUTER_1_7_7_RCGC_HYSTERESIS_COUNTER_LSB SPIO_NOC_ROUTER_1_7_7_RCGC_HYSTERESIS_COUNTER_RANGE SPIO_NOC_ROUTER_1_7_7_RCGC_HYSTERESIS_COUNTER_RESET SPIO_NOC_ROUTER_1_7_7_RCGC_HYSTERESIS_COUNTER_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RCGC_HYSTERESIS_COUNTER_GET SPIO_NOC_ROUTER_1_7_7_RCGC_HYSTERESIS_COUNTER_SET ns_noc_io_spio_soc_ip.csr 188845 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W register spio_noc.router_1_7_7_rcgo router_1_7_7_rcgo SPIO_NOC_ROUTER_1_7_7_RCGO_ADDRESS SPIO_NOC_ROUTER_1_7_7_RCGO_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_RCGO_OFFSET SPIO_NOC_ROUTER_1_7_7_RCGO_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 188885 R1_7 register rcgo 0x580B0 R/W 0x00000000 Spio_noc_router_1_7_7_rcgo This register is used by coarse grained clock gating logic. This register can be set to override coarse clock gating for the entire router. Coarse clock gating for selective routers can be overridden by locally setting this register, if the user does not want incur and aggregate coarse clock gating cycle penalty over a "fast path/critical path" through the NoC. false false false false FPO SPIO_NOC_ROUTER_1_7_7_RCGO_FPO_WIDTH SPIO_NOC_ROUTER_1_7_7_RCGO_FPO_MSB SPIO_NOC_ROUTER_1_7_7_RCGO_FPO_LSB SPIO_NOC_ROUTER_1_7_7_RCGO_FPO_RANGE SPIO_NOC_ROUTER_1_7_7_RCGO_FPO_RESET SPIO_NOC_ROUTER_1_7_7_RCGO_FPO_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RCGO_FPO_GET SPIO_NOC_ROUTER_1_7_7_RCGO_FPO_SET ns_noc_io_spio_soc_ip.csr 188873 FPO 1'b1: Coarse clock gating is locally disabled (for fast path) 1'b0: Coarse clock gating is locally enabled 0 0 0x0 R/W UNSD_31_1 SPIO_NOC_ROUTER_1_7_7_RCGO_UNSD_31_1_WIDTH SPIO_NOC_ROUTER_1_7_7_RCGO_UNSD_31_1_MSB SPIO_NOC_ROUTER_1_7_7_RCGO_UNSD_31_1_LSB SPIO_NOC_ROUTER_1_7_7_RCGO_UNSD_31_1_RANGE SPIO_NOC_ROUTER_1_7_7_RCGO_UNSD_31_1_RESET SPIO_NOC_ROUTER_1_7_7_RCGO_UNSD_31_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_RCGO_UNSD_31_1_GET SPIO_NOC_ROUTER_1_7_7_RCGO_UNSD_31_1_SET ns_noc_io_spio_soc_ip.csr 188884 UNSD_31_1 31 1 0x00000000 R register spio_noc.router_1_7_7_p0_rperr router_1_7_7_p0_rperr SPIO_NOC_ROUTER_1_7_7_P0_RPERR_ADDRESS SPIO_NOC_ROUTER_1_7_7_P0_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_P0_RPERR_OFFSET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 189176 R1_7 register p0_rperr 0x580B8 R/W 0x00000000 Spio_noc_router_1_7_7_p0_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 188928 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 188939 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 188950 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 188961 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_7_7_P0_RPERR_CR_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERR_CR_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_CR_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_CR_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERR_CR_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERR_CR_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 188972 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_7_7_P0_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 188983 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_0_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_0_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_0_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_0_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_0_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 188994 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_0_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_0_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_0_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_0_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 189005 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_0_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_0_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_0_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_0_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 189017 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_0_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_0_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_0_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_0_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 189028 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_1_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_1_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_1_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_1_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_1_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 189040 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_1_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_1_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_1_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_1_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 189052 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_1_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_1_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_1_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_1_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 189065 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_1_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_1_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_1_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_1_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 189077 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_2_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_2_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_2_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_2_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_2_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 189089 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_2_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_2_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_2_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_2_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 189101 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_2_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_2_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_2_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_2_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 189114 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_2_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_2_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_2_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_2_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 189126 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_3_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_3_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_3_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_3_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_3_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 189138 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_3_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_3_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_3_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_3_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 189150 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_3_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_3_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_3_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_3_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 189163 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_3_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_3_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_3_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_3_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 189175 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_1_7_7_p1_rperr router_1_7_7_p1_rperr SPIO_NOC_ROUTER_1_7_7_P1_RPERR_ADDRESS SPIO_NOC_ROUTER_1_7_7_P1_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_P1_RPERR_OFFSET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 189467 R1_7 register p1_rperr 0x580C0 R/W 0x00000000 Spio_noc_router_1_7_7_p1_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 189219 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 189230 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 189241 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 189252 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_7_7_P1_RPERR_CR_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERR_CR_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_CR_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_CR_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERR_CR_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERR_CR_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 189263 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_7_7_P1_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 189274 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_0_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_0_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_0_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_0_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_0_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 189285 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_0_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_0_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_0_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_0_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 189296 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_0_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_0_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_0_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_0_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 189308 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_0_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_0_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_0_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_0_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 189319 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_1_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_1_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_1_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_1_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_1_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 189331 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_1_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_1_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_1_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_1_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 189343 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_1_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_1_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_1_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_1_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 189356 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_1_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_1_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_1_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_1_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 189368 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_2_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_2_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_2_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_2_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_2_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 189380 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_2_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_2_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_2_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_2_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 189392 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_2_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_2_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_2_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_2_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 189405 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_2_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_2_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_2_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_2_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 189417 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_3_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_3_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_3_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_3_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_3_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 189429 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_3_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_3_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_3_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_3_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 189441 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_3_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_3_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_3_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_3_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 189454 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_3_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_3_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_3_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_3_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 189466 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_1_7_7_p2_rperr router_1_7_7_p2_rperr SPIO_NOC_ROUTER_1_7_7_P2_RPERR_ADDRESS SPIO_NOC_ROUTER_1_7_7_P2_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_P2_RPERR_OFFSET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 189754 R1_7 register p2_rperr 0x580C8 R/W 0x00000000 Spio_noc_router_1_7_7_p2_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 189510 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 189521 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 189532 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 189543 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_7_7_P2_RPERR_CR_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERR_CR_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_CR_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_CR_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERR_CR_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERR_CR_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 189554 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_7_7_P2_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 189565 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_0_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_0_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_0_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_0_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_0_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 189576 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_0_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_0_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_0_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_0_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 189587 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_0_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_0_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_0_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_0_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 189599 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_0_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_0_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_0_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_0_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 189610 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_1_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_1_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_1_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_1_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_1_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 189621 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_1_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_1_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_1_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_1_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 189632 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_1_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_1_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_1_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_1_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 189644 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_1_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_1_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_1_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_1_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 189655 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_2_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_2_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_2_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_2_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_2_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 189667 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_2_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_2_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_2_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_2_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 189679 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_2_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_2_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_2_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_2_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 189692 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_2_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_2_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_2_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_2_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 189704 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_3_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_3_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_3_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_3_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_3_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 189716 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_3_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_3_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_3_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_3_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 189728 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_3_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_3_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_3_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_3_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 189741 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_3_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_3_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_3_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_3_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 189753 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_1_7_7_p4_rperr router_1_7_7_p4_rperr SPIO_NOC_ROUTER_1_7_7_P4_RPERR_ADDRESS SPIO_NOC_ROUTER_1_7_7_P4_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_P4_RPERR_OFFSET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 190045 R1_7 register p4_rperr 0x580D8 R/W 0x00000000 Spio_noc_router_1_7_7_p4_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 189797 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 189808 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 189819 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 189830 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_7_7_P4_RPERR_CR_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERR_CR_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_CR_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_CR_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERR_CR_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERR_CR_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 189841 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_7_7_P4_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 189852 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_0_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_0_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_0_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_0_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_0_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 189863 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_0_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_0_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_0_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_0_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 189874 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_0_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_0_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_0_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_0_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 189886 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_0_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_0_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_0_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_0_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 189897 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_1_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_1_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_1_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_1_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_1_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 189909 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_1_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_1_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_1_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_1_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 189921 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_1_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_1_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_1_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_1_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 189934 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_1_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_1_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_1_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_1_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 189946 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_2_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_2_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_2_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_2_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_2_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 189958 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_2_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_2_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_2_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_2_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 189970 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_2_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_2_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_2_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_2_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 189983 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_2_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_2_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_2_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_2_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 189995 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_3_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_3_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_3_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_3_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_3_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 190007 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_3_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_3_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_3_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_3_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 190019 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_3_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_3_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_3_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_3_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 190032 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_3_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_3_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_3_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_3_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 190044 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_1_7_7_p5_rperr router_1_7_7_p5_rperr SPIO_NOC_ROUTER_1_7_7_P5_RPERR_ADDRESS SPIO_NOC_ROUTER_1_7_7_P5_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_P5_RPERR_OFFSET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 190336 R1_7 register p5_rperr 0x580E0 R/W 0x00000000 Spio_noc_router_1_7_7_p5_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 190088 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 190099 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 190110 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 190121 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_7_7_P5_RPERR_CR_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERR_CR_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_CR_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_CR_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERR_CR_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERR_CR_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 190132 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_7_7_P5_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 190143 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_0_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_0_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_0_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_0_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_0_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 190154 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_0_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_0_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_0_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_0_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 190165 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_0_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_0_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_0_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_0_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 190177 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_0_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_0_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_0_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_0_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 190188 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_1_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_1_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_1_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_1_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_1_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 190200 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_1_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_1_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_1_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_1_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 190212 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_1_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_1_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_1_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_1_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 190225 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_1_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_1_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_1_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_1_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 190237 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_2_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_2_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_2_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_2_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_2_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 190249 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_2_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_2_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_2_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_2_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 190261 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_2_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_2_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_2_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_2_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 190274 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_2_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_2_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_2_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_2_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 190286 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_3_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_3_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_3_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_3_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_3_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 190298 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_3_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_3_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_3_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_3_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 190310 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_3_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_3_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_3_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_3_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 190323 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_3_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_3_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_3_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_3_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 190335 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_1_7_7_p6_rperr router_1_7_7_p6_rperr SPIO_NOC_ROUTER_1_7_7_P6_RPERR_ADDRESS SPIO_NOC_ROUTER_1_7_7_P6_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_P6_RPERR_OFFSET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 190627 R1_7 register p6_rperr 0x580E8 R/W 0x00000000 Spio_noc_router_1_7_7_p6_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 190379 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 190390 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 190401 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 190412 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_7_7_P6_RPERR_CR_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERR_CR_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_CR_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_CR_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERR_CR_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERR_CR_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 190423 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_7_7_P6_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 190434 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_0_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_0_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_0_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_0_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_0_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 190445 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_0_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_0_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_0_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_0_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 190456 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_0_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_0_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_0_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_0_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 190468 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_0_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_0_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_0_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_0_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 190479 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_1_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_1_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_1_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_1_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_1_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 190491 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_1_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_1_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_1_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_1_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 190503 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_1_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_1_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_1_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_1_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 190516 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_1_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_1_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_1_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_1_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 190528 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_2_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_2_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_2_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_2_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_2_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 190540 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_2_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_2_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_2_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_2_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 190552 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_2_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_2_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_2_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_2_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 190565 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_2_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_2_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_2_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_2_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 190577 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_3_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_3_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_3_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_3_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_3_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 190589 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_3_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_3_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_3_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_3_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 190601 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_3_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_3_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_3_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_3_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 190614 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_3_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_3_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_3_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_3_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 190626 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_1_7_7_p7_rperr router_1_7_7_p7_rperr SPIO_NOC_ROUTER_1_7_7_P7_RPERR_ADDRESS SPIO_NOC_ROUTER_1_7_7_P7_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_P7_RPERR_OFFSET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 190918 R1_7 register p7_rperr 0x580F0 R/W 0x00000000 Spio_noc_router_1_7_7_p7_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 190670 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 190681 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 190692 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 190703 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_7_7_P7_RPERR_CR_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERR_CR_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_CR_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_CR_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERR_CR_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERR_CR_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 190714 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_7_7_P7_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 190725 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_0_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_0_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_0_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_0_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_0_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 190736 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_0_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_0_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_0_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_0_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 190747 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_0_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_0_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_0_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_0_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 190759 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_0_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_0_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_0_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_0_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 190770 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_1_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_1_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_1_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_1_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_1_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 190782 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_1_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_1_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_1_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_1_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 190794 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_1_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_1_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_1_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_1_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 190807 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_1_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_1_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_1_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_1_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 190819 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_2_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_2_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_2_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_2_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_2_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 190831 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_2_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_2_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_2_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_2_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 190843 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_2_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_2_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_2_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_2_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 190856 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_2_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_2_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_2_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_2_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 190868 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_3_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_3_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_3_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_3_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_3_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 190880 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_3_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_3_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_3_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_3_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 190892 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_3_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_3_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_3_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_3_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 190905 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_3_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_3_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_3_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_3_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 190917 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_1_7_7_p0_rperrm router_1_7_7_p0_rperrm SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_ADDRESS SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_OFFSET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 191176 R1_7 register p0_rperrm 0x580F8 R/W 0x00000000 Spio_noc_router_1_7_7_p0_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 190940 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 190951 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 190962 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 190973 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_CR_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_CR_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_CR_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_CR_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_CR_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 190984 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 190995 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_0_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_0_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_0_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_0_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 191006 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_0_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 191017 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_0_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 191029 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_0_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 191040 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_1_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_1_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_1_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_1_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 191051 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_1_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 191062 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_1_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 191074 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_1_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 191085 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_2_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_2_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_2_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_2_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 191096 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_2_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 191107 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_2_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 191119 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_2_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 191130 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_3_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_3_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_3_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_3_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 191141 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_3_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 191152 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_3_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 191164 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_3_GET SPIO_NOC_ROUTER_1_7_7_P0_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 191175 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_1_7_7_p1_rperrm router_1_7_7_p1_rperrm SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_ADDRESS SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_OFFSET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 191434 R1_7 register p1_rperrm 0x58100 R/W 0x00000000 Spio_noc_router_1_7_7_p1_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 191198 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 191209 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 191220 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 191231 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_CR_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_CR_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_CR_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_CR_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_CR_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 191242 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 191253 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_0_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_0_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_0_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_0_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 191264 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_0_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 191275 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_0_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 191287 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_0_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 191298 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_1_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_1_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_1_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_1_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 191309 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_1_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 191320 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_1_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 191332 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_1_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 191343 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_2_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_2_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_2_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_2_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 191354 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_2_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 191365 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_2_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 191377 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_2_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 191388 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_3_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_3_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_3_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_3_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 191399 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_3_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 191410 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_3_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 191422 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_3_GET SPIO_NOC_ROUTER_1_7_7_P1_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 191433 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_1_7_7_p2_rperrm router_1_7_7_p2_rperrm SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_ADDRESS SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_OFFSET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 191692 R1_7 register p2_rperrm 0x58108 R/W 0x00000000 Spio_noc_router_1_7_7_p2_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 191456 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 191467 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 191478 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 191489 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_CR_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_CR_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_CR_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_CR_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_CR_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 191500 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 191511 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_0_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_0_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_0_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_0_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 191522 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_0_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 191533 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_0_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 191545 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_0_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 191556 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_1_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_1_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_1_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_1_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 191567 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_1_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 191578 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_1_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 191590 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_1_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 191601 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_2_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_2_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_2_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_2_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 191612 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_2_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 191623 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_2_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 191635 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_2_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 191646 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_3_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_3_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_3_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_3_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 191657 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_3_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 191668 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_3_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 191680 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_3_GET SPIO_NOC_ROUTER_1_7_7_P2_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 191691 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_1_7_7_p4_rperrm router_1_7_7_p4_rperrm SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_ADDRESS SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_OFFSET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 191950 R1_7 register p4_rperrm 0x58118 R/W 0x00000000 Spio_noc_router_1_7_7_p4_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 191714 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 191725 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 191736 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 191747 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_CR_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_CR_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_CR_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_CR_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_CR_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 191758 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 191769 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_0_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_0_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_0_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_0_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 191780 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_0_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 191791 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_0_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 191803 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_0_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 191814 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_1_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_1_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_1_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_1_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 191825 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_1_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 191836 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_1_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 191848 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_1_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 191859 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_2_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_2_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_2_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_2_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 191870 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_2_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 191881 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_2_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 191893 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_2_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 191904 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_3_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_3_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_3_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_3_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 191915 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_3_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 191926 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_3_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 191938 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_3_GET SPIO_NOC_ROUTER_1_7_7_P4_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 191949 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_1_7_7_p5_rperrm router_1_7_7_p5_rperrm SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_ADDRESS SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_OFFSET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 192208 R1_7 register p5_rperrm 0x58120 R/W 0x00000000 Spio_noc_router_1_7_7_p5_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 191972 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 191983 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 191994 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 192005 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_CR_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_CR_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_CR_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_CR_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_CR_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 192016 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 192027 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_0_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_0_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_0_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_0_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 192038 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_0_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 192049 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_0_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 192061 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_0_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 192072 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_1_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_1_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_1_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_1_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 192083 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_1_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 192094 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_1_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 192106 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_1_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 192117 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_2_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_2_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_2_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_2_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 192128 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_2_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 192139 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_2_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 192151 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_2_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 192162 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_3_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_3_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_3_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_3_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 192173 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_3_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 192184 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_3_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 192196 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_3_GET SPIO_NOC_ROUTER_1_7_7_P5_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 192207 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_1_7_7_p6_rperrm router_1_7_7_p6_rperrm SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_ADDRESS SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_OFFSET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 192466 R1_7 register p6_rperrm 0x58128 R/W 0x00000000 Spio_noc_router_1_7_7_p6_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 192230 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 192241 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 192252 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 192263 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_CR_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_CR_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_CR_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_CR_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_CR_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 192274 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 192285 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_0_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_0_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_0_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_0_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 192296 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_0_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 192307 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_0_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 192319 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_0_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 192330 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_1_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_1_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_1_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_1_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 192341 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_1_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 192352 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_1_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 192364 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_1_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 192375 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_2_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_2_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_2_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_2_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 192386 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_2_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 192397 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_2_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 192409 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_2_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 192420 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_3_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_3_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_3_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_3_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 192431 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_3_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 192442 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_3_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 192454 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_3_GET SPIO_NOC_ROUTER_1_7_7_P6_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 192465 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_1_7_7_p7_rperrm router_1_7_7_p7_rperrm SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_ADDRESS SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_OFFSET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 192724 R1_7 register p7_rperrm 0x58130 R/W 0x00000000 Spio_noc_router_1_7_7_p7_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 192488 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 192499 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 192510 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 192521 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_CR_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_CR_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_CR_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_CR_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_CR_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 192532 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 192543 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_0_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_0_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_0_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_0_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 192554 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_0_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 192565 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_0_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 192577 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_0_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 192588 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_1_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_1_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_1_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_1_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 192599 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_1_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 192610 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_1_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 192622 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_1_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 192633 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_2_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_2_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_2_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_2_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 192644 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_2_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 192655 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_2_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 192667 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_2_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 192678 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_3_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_3_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_3_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_3_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 192689 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_3_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 192700 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_3_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 192712 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_3_GET SPIO_NOC_ROUTER_1_7_7_P7_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 192723 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_1_7_7_roecc router_1_7_7_roecc SPIO_NOC_ROUTER_1_7_7_ROECC_ADDRESS SPIO_NOC_ROUTER_1_7_7_ROECC_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_ROECC_OFFSET SPIO_NOC_ROUTER_1_7_7_ROECC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 192797 R1_7 register roecc 0x58138 R/W 0x00000000 Spio_noc_router_1_7_7_roecc This register is used to select which hardware events will increment the output event counter. false false false false OVC SPIO_NOC_ROUTER_1_7_7_ROECC_OVC_WIDTH SPIO_NOC_ROUTER_1_7_7_ROECC_OVC_MSB SPIO_NOC_ROUTER_1_7_7_ROECC_OVC_LSB SPIO_NOC_ROUTER_1_7_7_ROECC_OVC_RANGE SPIO_NOC_ROUTER_1_7_7_ROECC_OVC_RESET SPIO_NOC_ROUTER_1_7_7_ROECC_OVC_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROECC_OVC_GET SPIO_NOC_ROUTER_1_7_7_ROECC_OVC_SET ns_noc_io_spio_soc_ip.csr 192742 OVC Bit map to select output VCs to monitor events on 3 0 0x0 R/W OP SPIO_NOC_ROUTER_1_7_7_ROECC_OP_WIDTH SPIO_NOC_ROUTER_1_7_7_ROECC_OP_MSB SPIO_NOC_ROUTER_1_7_7_ROECC_OP_LSB SPIO_NOC_ROUTER_1_7_7_ROECC_OP_RANGE SPIO_NOC_ROUTER_1_7_7_ROECC_OP_RESET SPIO_NOC_ROUTER_1_7_7_ROECC_OP_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROECC_OP_GET SPIO_NOC_ROUTER_1_7_7_ROECC_OP_SET ns_noc_io_spio_soc_ip.csr 192753 OP Output port on which the event is captured 6 4 0x0 R/W UNSD_7_7 SPIO_NOC_ROUTER_1_7_7_ROECC_UNSD_7_7_WIDTH SPIO_NOC_ROUTER_1_7_7_ROECC_UNSD_7_7_MSB SPIO_NOC_ROUTER_1_7_7_ROECC_UNSD_7_7_LSB SPIO_NOC_ROUTER_1_7_7_ROECC_UNSD_7_7_RANGE SPIO_NOC_ROUTER_1_7_7_ROECC_UNSD_7_7_RESET SPIO_NOC_ROUTER_1_7_7_ROECC_UNSD_7_7_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROECC_UNSD_7_7_GET SPIO_NOC_ROUTER_1_7_7_ROECC_UNSD_7_7_SET ns_noc_io_spio_soc_ip.csr 192764 UNSD_7_7 7 7 0x0 R EVT SPIO_NOC_ROUTER_1_7_7_ROECC_EVT_WIDTH SPIO_NOC_ROUTER_1_7_7_ROECC_EVT_MSB SPIO_NOC_ROUTER_1_7_7_ROECC_EVT_LSB SPIO_NOC_ROUTER_1_7_7_ROECC_EVT_RANGE SPIO_NOC_ROUTER_1_7_7_ROECC_EVT_RESET SPIO_NOC_ROUTER_1_7_7_ROECC_EVT_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROECC_EVT_GET SPIO_NOC_ROUTER_1_7_7_ROECC_EVT_SET ns_noc_io_spio_soc_ip.csr 192785 EVT 100: Port stalled. Input flits are available for the port, but no output VC has credit 011: Generates count event when flits are available to be sent to output VC, but the VC has no credit 010: Generates count event on every flit sent on the selected output port and selected outpt VCs, this can be used to count total flits sent on a router output port 001: Generates count event on every EOP sent on the selected output port and selected output VCs, this can be used to count packets sent on a router output port 000: Disable 10 8 0x0 R/W UNSD_31_11 SPIO_NOC_ROUTER_1_7_7_ROECC_UNSD_31_11_WIDTH SPIO_NOC_ROUTER_1_7_7_ROECC_UNSD_31_11_MSB SPIO_NOC_ROUTER_1_7_7_ROECC_UNSD_31_11_LSB SPIO_NOC_ROUTER_1_7_7_ROECC_UNSD_31_11_RANGE SPIO_NOC_ROUTER_1_7_7_ROECC_UNSD_31_11_RESET SPIO_NOC_ROUTER_1_7_7_ROECC_UNSD_31_11_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROECC_UNSD_31_11_GET SPIO_NOC_ROUTER_1_7_7_ROECC_UNSD_31_11_SET ns_noc_io_spio_soc_ip.csr 192796 UNSD_31_11 31 11 0x000000 R register spio_noc.router_1_7_7_roec router_1_7_7_roec SPIO_NOC_ROUTER_1_7_7_ROEC_ADDRESS SPIO_NOC_ROUTER_1_7_7_ROEC_BYTE_ADDRESS SPIO_NOC_ROUTER_1_7_7_ROEC_OFFSET SPIO_NOC_ROUTER_1_7_7_ROEC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 192822 R1_7 register roec 0x58140 R/W 0x00000000 Spio_noc_router_1_7_7_roec This register holds the output event counter. The value can be read to determine the current count value. The value can be written to initialize the counter. When events trigger a count, the counter will increment. When the counter increments at its highest value, it will roll over to zero and the overflow will mark the Router output Event Interrupt Status register, which could trigger an interrupt. false false false false EVENT_CNTR SPIO_NOC_ROUTER_1_7_7_ROEC_EVENT_CNTR_WIDTH SPIO_NOC_ROUTER_1_7_7_ROEC_EVENT_CNTR_MSB SPIO_NOC_ROUTER_1_7_7_ROEC_EVENT_CNTR_LSB SPIO_NOC_ROUTER_1_7_7_ROEC_EVENT_CNTR_RANGE SPIO_NOC_ROUTER_1_7_7_ROEC_EVENT_CNTR_RESET SPIO_NOC_ROUTER_1_7_7_ROEC_EVENT_CNTR_FIELD_MASK SPIO_NOC_ROUTER_1_7_7_ROEC_EVENT_CNTR_GET SPIO_NOC_ROUTER_1_7_7_ROEC_EVENT_CNTR_SET ns_noc_io_spio_soc_ip.csr 192821 EVENT_CNTR 32'bit event incrementing counter. Rollover from 32'hFFFFF -> 32'd0 sets the rollover status bit RE 31 0 0x00000000 R/W register spio_noc.router_1_8_8_rivcs_h router_1_8_8_rivcs_h SPIO_NOC_ROUTER_1_8_8_RIVCS_H_ADDRESS SPIO_NOC_ROUTER_1_8_8_RIVCS_H_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OFFSET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 193151 R1_8 register rivcs_h 0x5C000 R 0x00000000 Spio_noc_router_1_8_8_rivcs_h This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 192847 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_0_SET ns_noc_io_spio_soc_ip.csr 192861 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_0_SET ns_noc_io_spio_soc_ip.csr 192877 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_0_SET ns_noc_io_spio_soc_ip.csr 192891 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_0_SET ns_noc_io_spio_soc_ip.csr 192902 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_0_SET ns_noc_io_spio_soc_ip.csr 192913 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 192926 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_1_SET ns_noc_io_spio_soc_ip.csr 192940 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_1_SET ns_noc_io_spio_soc_ip.csr 192956 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_1_SET ns_noc_io_spio_soc_ip.csr 192970 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_1_SET ns_noc_io_spio_soc_ip.csr 192981 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_1_SET ns_noc_io_spio_soc_ip.csr 192992 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 193005 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_2_SET ns_noc_io_spio_soc_ip.csr 193019 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_2_SET ns_noc_io_spio_soc_ip.csr 193035 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_2_SET ns_noc_io_spio_soc_ip.csr 193049 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_2_SET ns_noc_io_spio_soc_ip.csr 193060 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_2_SET ns_noc_io_spio_soc_ip.csr 193071 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 193084 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_UP_3_SET ns_noc_io_spio_soc_ip.csr 193098 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_S_3_SET ns_noc_io_spio_soc_ip.csr 193114 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_B_3_SET ns_noc_io_spio_soc_ip.csr 193128 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_F_3_SET ns_noc_io_spio_soc_ip.csr 193139 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_H_V_3_SET ns_noc_io_spio_soc_ip.csr 193150 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_1_8_8_rivcs_w router_1_8_8_rivcs_w SPIO_NOC_ROUTER_1_8_8_RIVCS_W_ADDRESS SPIO_NOC_ROUTER_1_8_8_RIVCS_W_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OFFSET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 193480 R1_8 register rivcs_w 0x5C018 R 0x00000000 Spio_noc_router_1_8_8_rivcs_w This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 193176 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_0_SET ns_noc_io_spio_soc_ip.csr 193190 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_0_SET ns_noc_io_spio_soc_ip.csr 193206 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_0_SET ns_noc_io_spio_soc_ip.csr 193220 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_0_SET ns_noc_io_spio_soc_ip.csr 193231 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_0_SET ns_noc_io_spio_soc_ip.csr 193242 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 193255 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_1_SET ns_noc_io_spio_soc_ip.csr 193269 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_1_SET ns_noc_io_spio_soc_ip.csr 193285 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_1_SET ns_noc_io_spio_soc_ip.csr 193299 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_1_SET ns_noc_io_spio_soc_ip.csr 193310 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_1_SET ns_noc_io_spio_soc_ip.csr 193321 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 193334 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_2_SET ns_noc_io_spio_soc_ip.csr 193348 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_2_SET ns_noc_io_spio_soc_ip.csr 193364 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_2_SET ns_noc_io_spio_soc_ip.csr 193378 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_2_SET ns_noc_io_spio_soc_ip.csr 193389 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_2_SET ns_noc_io_spio_soc_ip.csr 193400 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 193413 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_UP_3_SET ns_noc_io_spio_soc_ip.csr 193427 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_S_3_SET ns_noc_io_spio_soc_ip.csr 193443 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_B_3_SET ns_noc_io_spio_soc_ip.csr 193457 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_F_3_SET ns_noc_io_spio_soc_ip.csr 193468 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_W_V_3_SET ns_noc_io_spio_soc_ip.csr 193479 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_1_8_8_rivcs_n router_1_8_8_rivcs_n SPIO_NOC_ROUTER_1_8_8_RIVCS_N_ADDRESS SPIO_NOC_ROUTER_1_8_8_RIVCS_N_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OFFSET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 193809 R1_8 register rivcs_n 0x5C020 R 0x00000000 Spio_noc_router_1_8_8_rivcs_n This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 193505 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_0_SET ns_noc_io_spio_soc_ip.csr 193519 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_0_SET ns_noc_io_spio_soc_ip.csr 193535 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_0_SET ns_noc_io_spio_soc_ip.csr 193549 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_0_SET ns_noc_io_spio_soc_ip.csr 193560 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_0_SET ns_noc_io_spio_soc_ip.csr 193571 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 193584 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_1_SET ns_noc_io_spio_soc_ip.csr 193598 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_1_SET ns_noc_io_spio_soc_ip.csr 193614 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_1_SET ns_noc_io_spio_soc_ip.csr 193628 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_1_SET ns_noc_io_spio_soc_ip.csr 193639 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_1_SET ns_noc_io_spio_soc_ip.csr 193650 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 193663 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_2_SET ns_noc_io_spio_soc_ip.csr 193677 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_2_SET ns_noc_io_spio_soc_ip.csr 193693 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_2_SET ns_noc_io_spio_soc_ip.csr 193707 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_2_SET ns_noc_io_spio_soc_ip.csr 193718 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_2_SET ns_noc_io_spio_soc_ip.csr 193729 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 193742 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_UP_3_SET ns_noc_io_spio_soc_ip.csr 193756 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_S_3_SET ns_noc_io_spio_soc_ip.csr 193772 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_B_3_SET ns_noc_io_spio_soc_ip.csr 193786 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_F_3_SET ns_noc_io_spio_soc_ip.csr 193797 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_N_V_3_SET ns_noc_io_spio_soc_ip.csr 193808 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_1_8_8_rivcs_i router_1_8_8_rivcs_i SPIO_NOC_ROUTER_1_8_8_RIVCS_I_ADDRESS SPIO_NOC_ROUTER_1_8_8_RIVCS_I_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OFFSET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 194138 R1_8 register rivcs_i 0x5C028 R 0x00000000 Spio_noc_router_1_8_8_rivcs_i This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 193834 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_0_SET ns_noc_io_spio_soc_ip.csr 193848 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_0_SET ns_noc_io_spio_soc_ip.csr 193864 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_0_SET ns_noc_io_spio_soc_ip.csr 193878 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_0_SET ns_noc_io_spio_soc_ip.csr 193889 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_0_SET ns_noc_io_spio_soc_ip.csr 193900 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 193913 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_1_SET ns_noc_io_spio_soc_ip.csr 193927 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_1_SET ns_noc_io_spio_soc_ip.csr 193943 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_1_SET ns_noc_io_spio_soc_ip.csr 193957 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_1_SET ns_noc_io_spio_soc_ip.csr 193968 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_1_SET ns_noc_io_spio_soc_ip.csr 193979 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 193992 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_2_SET ns_noc_io_spio_soc_ip.csr 194006 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_2_SET ns_noc_io_spio_soc_ip.csr 194022 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_2_SET ns_noc_io_spio_soc_ip.csr 194036 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_2_SET ns_noc_io_spio_soc_ip.csr 194047 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_2_SET ns_noc_io_spio_soc_ip.csr 194058 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 194071 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_UP_3_SET ns_noc_io_spio_soc_ip.csr 194085 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_S_3_SET ns_noc_io_spio_soc_ip.csr 194101 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_B_3_SET ns_noc_io_spio_soc_ip.csr 194115 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_F_3_SET ns_noc_io_spio_soc_ip.csr 194126 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_I_V_3_SET ns_noc_io_spio_soc_ip.csr 194137 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_1_8_8_rivcs_j router_1_8_8_rivcs_j SPIO_NOC_ROUTER_1_8_8_RIVCS_J_ADDRESS SPIO_NOC_ROUTER_1_8_8_RIVCS_J_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OFFSET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 194467 R1_8 register rivcs_j 0x5C030 R 0x00000000 Spio_noc_router_1_8_8_rivcs_j This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 194163 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_0_SET ns_noc_io_spio_soc_ip.csr 194177 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_0_SET ns_noc_io_spio_soc_ip.csr 194193 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_0_SET ns_noc_io_spio_soc_ip.csr 194207 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_0_SET ns_noc_io_spio_soc_ip.csr 194218 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_0_SET ns_noc_io_spio_soc_ip.csr 194229 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 194242 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_1_SET ns_noc_io_spio_soc_ip.csr 194256 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_1_SET ns_noc_io_spio_soc_ip.csr 194272 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_1_SET ns_noc_io_spio_soc_ip.csr 194286 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_1_SET ns_noc_io_spio_soc_ip.csr 194297 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_1_SET ns_noc_io_spio_soc_ip.csr 194308 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 194321 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_2_SET ns_noc_io_spio_soc_ip.csr 194335 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_2_SET ns_noc_io_spio_soc_ip.csr 194351 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_2_SET ns_noc_io_spio_soc_ip.csr 194365 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_2_SET ns_noc_io_spio_soc_ip.csr 194376 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_2_SET ns_noc_io_spio_soc_ip.csr 194387 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 194400 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_UP_3_SET ns_noc_io_spio_soc_ip.csr 194414 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_S_3_SET ns_noc_io_spio_soc_ip.csr 194430 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_B_3_SET ns_noc_io_spio_soc_ip.csr 194444 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_F_3_SET ns_noc_io_spio_soc_ip.csr 194455 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_J_V_3_SET ns_noc_io_spio_soc_ip.csr 194466 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_1_8_8_rivcs_k router_1_8_8_rivcs_k SPIO_NOC_ROUTER_1_8_8_RIVCS_K_ADDRESS SPIO_NOC_ROUTER_1_8_8_RIVCS_K_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OFFSET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 194796 R1_8 register rivcs_k 0x5C038 R 0x00000000 Spio_noc_router_1_8_8_rivcs_k This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_0_SET ns_noc_io_spio_soc_ip.csr 194492 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_0_SET ns_noc_io_spio_soc_ip.csr 194506 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_0_SET ns_noc_io_spio_soc_ip.csr 194522 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_0_SET ns_noc_io_spio_soc_ip.csr 194536 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_0_SET ns_noc_io_spio_soc_ip.csr 194547 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_0_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_0_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_0_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_0_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_0_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_0_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_0_SET ns_noc_io_spio_soc_ip.csr 194558 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_1_SET ns_noc_io_spio_soc_ip.csr 194571 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_1_SET ns_noc_io_spio_soc_ip.csr 194585 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_1_SET ns_noc_io_spio_soc_ip.csr 194601 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_1_SET ns_noc_io_spio_soc_ip.csr 194615 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_1_SET ns_noc_io_spio_soc_ip.csr 194626 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_1_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_1_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_1_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_1_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_1_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_1_SET ns_noc_io_spio_soc_ip.csr 194637 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_2_SET ns_noc_io_spio_soc_ip.csr 194650 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_2_SET ns_noc_io_spio_soc_ip.csr 194664 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_2_SET ns_noc_io_spio_soc_ip.csr 194680 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_2_SET ns_noc_io_spio_soc_ip.csr 194694 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_2_SET ns_noc_io_spio_soc_ip.csr 194705 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_2_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_2_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_2_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_2_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_2_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_2_SET ns_noc_io_spio_soc_ip.csr 194716 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_OUTP_3_SET ns_noc_io_spio_soc_ip.csr 194729 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_UP_3_SET ns_noc_io_spio_soc_ip.csr 194743 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_S_3_SET ns_noc_io_spio_soc_ip.csr 194759 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_B_3_SET ns_noc_io_spio_soc_ip.csr 194773 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_F_3_SET ns_noc_io_spio_soc_ip.csr 194784 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_3_MSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_3_LSB SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_3_RANGE SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_3_RESET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_3_GET SPIO_NOC_ROUTER_1_8_8_RIVCS_K_V_3_SET ns_noc_io_spio_soc_ip.csr 194795 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register spio_noc.router_1_8_8_rovcs_h router_1_8_8_rovcs_h SPIO_NOC_ROUTER_1_8_8_ROVCS_H_ADDRESS SPIO_NOC_ROUTER_1_8_8_ROVCS_H_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_ROVCS_H_OFFSET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 195057 R1_8 register rovcs_h 0x5C040 R 0x00000101 Spio_noc_router_1_8_8_rovcs_h This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_0_SET ns_noc_io_spio_soc_ip.csr 194820 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_0_SET ns_noc_io_spio_soc_ip.csr 194834 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_0_SET ns_noc_io_spio_soc_ip.csr 194849 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_0_SET ns_noc_io_spio_soc_ip.csr 194860 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 194870 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_1_SET ns_noc_io_spio_soc_ip.csr 194882 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x1 R CE_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_1_SET ns_noc_io_spio_soc_ip.csr 194896 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_1_SET ns_noc_io_spio_soc_ip.csr 194911 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_1_SET ns_noc_io_spio_soc_ip.csr 194922 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 194932 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_2_SET ns_noc_io_spio_soc_ip.csr 194944 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_2_SET ns_noc_io_spio_soc_ip.csr 194958 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_2_SET ns_noc_io_spio_soc_ip.csr 194973 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_2_SET ns_noc_io_spio_soc_ip.csr 194984 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 194994 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CF_3_SET ns_noc_io_spio_soc_ip.csr 195006 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_CE_3_SET ns_noc_io_spio_soc_ip.csr 195020 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_VB_3_SET ns_noc_io_spio_soc_ip.csr 195035 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_RSV_3_SET ns_noc_io_spio_soc_ip.csr 195046 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_H_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 195056 UNSD_3 31 28 0x0 R register spio_noc.router_1_8_8_rovcs_w router_1_8_8_rovcs_w SPIO_NOC_ROUTER_1_8_8_ROVCS_W_ADDRESS SPIO_NOC_ROUTER_1_8_8_ROVCS_W_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_ROVCS_W_OFFSET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 195318 R1_8 register rovcs_w 0x5C058 R 0x00000001 Spio_noc_router_1_8_8_rovcs_w This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_0_SET ns_noc_io_spio_soc_ip.csr 195081 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_0_SET ns_noc_io_spio_soc_ip.csr 195095 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_0_SET ns_noc_io_spio_soc_ip.csr 195110 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_0_SET ns_noc_io_spio_soc_ip.csr 195121 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 195131 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_1_SET ns_noc_io_spio_soc_ip.csr 195143 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_1_SET ns_noc_io_spio_soc_ip.csr 195157 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_1_SET ns_noc_io_spio_soc_ip.csr 195172 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_1_SET ns_noc_io_spio_soc_ip.csr 195183 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 195193 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_2_SET ns_noc_io_spio_soc_ip.csr 195205 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_2_SET ns_noc_io_spio_soc_ip.csr 195219 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_2_SET ns_noc_io_spio_soc_ip.csr 195234 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_2_SET ns_noc_io_spio_soc_ip.csr 195245 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 195255 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CF_3_SET ns_noc_io_spio_soc_ip.csr 195267 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_CE_3_SET ns_noc_io_spio_soc_ip.csr 195281 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_VB_3_SET ns_noc_io_spio_soc_ip.csr 195296 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_RSV_3_SET ns_noc_io_spio_soc_ip.csr 195307 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_W_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 195317 UNSD_3 31 28 0x0 R register spio_noc.router_1_8_8_rovcs_n router_1_8_8_rovcs_n SPIO_NOC_ROUTER_1_8_8_ROVCS_N_ADDRESS SPIO_NOC_ROUTER_1_8_8_ROVCS_N_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_ROVCS_N_OFFSET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 195579 R1_8 register rovcs_n 0x5C060 R 0x00000101 Spio_noc_router_1_8_8_rovcs_n This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_0_SET ns_noc_io_spio_soc_ip.csr 195342 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_0_SET ns_noc_io_spio_soc_ip.csr 195356 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_0_SET ns_noc_io_spio_soc_ip.csr 195371 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_0_SET ns_noc_io_spio_soc_ip.csr 195382 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 195392 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_1_SET ns_noc_io_spio_soc_ip.csr 195404 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x1 R CE_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_1_SET ns_noc_io_spio_soc_ip.csr 195418 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_1_SET ns_noc_io_spio_soc_ip.csr 195433 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_1_SET ns_noc_io_spio_soc_ip.csr 195444 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 195454 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_2_SET ns_noc_io_spio_soc_ip.csr 195466 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_2_SET ns_noc_io_spio_soc_ip.csr 195480 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_2_SET ns_noc_io_spio_soc_ip.csr 195495 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_2_SET ns_noc_io_spio_soc_ip.csr 195506 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 195516 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CF_3_SET ns_noc_io_spio_soc_ip.csr 195528 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_CE_3_SET ns_noc_io_spio_soc_ip.csr 195542 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_VB_3_SET ns_noc_io_spio_soc_ip.csr 195557 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_RSV_3_SET ns_noc_io_spio_soc_ip.csr 195568 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_N_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 195578 UNSD_3 31 28 0x0 R register spio_noc.router_1_8_8_rovcs_i router_1_8_8_rovcs_i SPIO_NOC_ROUTER_1_8_8_ROVCS_I_ADDRESS SPIO_NOC_ROUTER_1_8_8_ROVCS_I_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_ROVCS_I_OFFSET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 195840 R1_8 register rovcs_i 0x5C068 R 0x00000101 Spio_noc_router_1_8_8_rovcs_i This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_0_SET ns_noc_io_spio_soc_ip.csr 195603 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_0_SET ns_noc_io_spio_soc_ip.csr 195617 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_0_SET ns_noc_io_spio_soc_ip.csr 195632 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_0_SET ns_noc_io_spio_soc_ip.csr 195643 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 195653 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_1_SET ns_noc_io_spio_soc_ip.csr 195665 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x1 R CE_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_1_SET ns_noc_io_spio_soc_ip.csr 195679 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_1_SET ns_noc_io_spio_soc_ip.csr 195694 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_1_SET ns_noc_io_spio_soc_ip.csr 195705 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 195715 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_2_SET ns_noc_io_spio_soc_ip.csr 195727 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_2_SET ns_noc_io_spio_soc_ip.csr 195741 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_2_SET ns_noc_io_spio_soc_ip.csr 195756 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_2_SET ns_noc_io_spio_soc_ip.csr 195767 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 195777 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CF_3_SET ns_noc_io_spio_soc_ip.csr 195789 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_CE_3_SET ns_noc_io_spio_soc_ip.csr 195803 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_VB_3_SET ns_noc_io_spio_soc_ip.csr 195818 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_RSV_3_SET ns_noc_io_spio_soc_ip.csr 195829 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_I_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 195839 UNSD_3 31 28 0x0 R register spio_noc.router_1_8_8_rovcs_j router_1_8_8_rovcs_j SPIO_NOC_ROUTER_1_8_8_ROVCS_J_ADDRESS SPIO_NOC_ROUTER_1_8_8_ROVCS_J_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_ROVCS_J_OFFSET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 196101 R1_8 register rovcs_j 0x5C070 R 0x00000101 Spio_noc_router_1_8_8_rovcs_j This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_0_SET ns_noc_io_spio_soc_ip.csr 195864 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_0_SET ns_noc_io_spio_soc_ip.csr 195878 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_0_SET ns_noc_io_spio_soc_ip.csr 195893 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_0_SET ns_noc_io_spio_soc_ip.csr 195904 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 195914 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_1_SET ns_noc_io_spio_soc_ip.csr 195926 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x1 R CE_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_1_SET ns_noc_io_spio_soc_ip.csr 195940 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_1_SET ns_noc_io_spio_soc_ip.csr 195955 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_1_SET ns_noc_io_spio_soc_ip.csr 195966 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 195976 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_2_SET ns_noc_io_spio_soc_ip.csr 195988 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_2_SET ns_noc_io_spio_soc_ip.csr 196002 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_2_SET ns_noc_io_spio_soc_ip.csr 196017 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_2_SET ns_noc_io_spio_soc_ip.csr 196028 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 196038 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CF_3_SET ns_noc_io_spio_soc_ip.csr 196050 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_CE_3_SET ns_noc_io_spio_soc_ip.csr 196064 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_VB_3_SET ns_noc_io_spio_soc_ip.csr 196079 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_RSV_3_SET ns_noc_io_spio_soc_ip.csr 196090 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_J_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 196100 UNSD_3 31 28 0x0 R register spio_noc.router_1_8_8_rovcs_k router_1_8_8_rovcs_k SPIO_NOC_ROUTER_1_8_8_ROVCS_K_ADDRESS SPIO_NOC_ROUTER_1_8_8_ROVCS_K_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_ROVCS_K_OFFSET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 196362 R1_8 register rovcs_k 0x5C078 R 0x00000101 Spio_noc_router_1_8_8_rovcs_k This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_0_SET ns_noc_io_spio_soc_ip.csr 196125 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_0_SET ns_noc_io_spio_soc_ip.csr 196139 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_0_SET ns_noc_io_spio_soc_ip.csr 196154 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_0_SET ns_noc_io_spio_soc_ip.csr 196165 RSV_0 Reserved 3 3 0x0 R UNSD_0 SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_0_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_0_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_0_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_0_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_0_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_0_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_0_SET ns_noc_io_spio_soc_ip.csr 196175 UNSD_0 7 4 0x0 R CF_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_1_SET ns_noc_io_spio_soc_ip.csr 196187 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x1 R CE_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_1_SET ns_noc_io_spio_soc_ip.csr 196201 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_1_SET ns_noc_io_spio_soc_ip.csr 196216 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_1_SET ns_noc_io_spio_soc_ip.csr 196227 RSV_1 Reserved 11 11 0x0 R UNSD_1 SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_1_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_1_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_1_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_1_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_1_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_1_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_1_SET ns_noc_io_spio_soc_ip.csr 196237 UNSD_1 15 12 0x0 R CF_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_2_SET ns_noc_io_spio_soc_ip.csr 196249 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_2_SET ns_noc_io_spio_soc_ip.csr 196263 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_2_SET ns_noc_io_spio_soc_ip.csr 196278 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_2_SET ns_noc_io_spio_soc_ip.csr 196289 RSV_2 Reserved 19 19 0x0 R UNSD_2 SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_2_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_2_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_2_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_2_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_2_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_2_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_2_SET ns_noc_io_spio_soc_ip.csr 196299 UNSD_2 23 20 0x0 R CF_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CF_3_SET ns_noc_io_spio_soc_ip.csr 196311 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_CE_3_SET ns_noc_io_spio_soc_ip.csr 196325 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_VB_3_SET ns_noc_io_spio_soc_ip.csr 196340 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_RSV_3_SET ns_noc_io_spio_soc_ip.csr 196351 RSV_3 Reserved 27 27 0x0 R UNSD_3 SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_3_WIDTH SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_3_MSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_3_LSB SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_3_RANGE SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_3_RESET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_3_GET SPIO_NOC_ROUTER_1_8_8_ROVCS_K_UNSD_3_SET ns_noc_io_spio_soc_ip.csr 196361 UNSD_3 31 28 0x0 R register spio_noc.router_1_8_8_re router_1_8_8_re SPIO_NOC_ROUTER_1_8_8_RE_ADDRESS SPIO_NOC_ROUTER_1_8_8_RE_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_RE_OFFSET SPIO_NOC_ROUTER_1_8_8_RE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 196536 R1_8 register re 0x5C080 R/W 0x00000000 Spio_noc_router_1_8_8_re This register tracks the interrupt or error events that can occur in the router. The only interrupt event is the event counter overflow. This register is readable, and can be cleared by performing a write with the write data bits set to 0 for the bits that should be cleared. false false false false OVFI SPIO_NOC_ROUTER_1_8_8_RE_OVFI_WIDTH SPIO_NOC_ROUTER_1_8_8_RE_OVFI_MSB SPIO_NOC_ROUTER_1_8_8_RE_OVFI_LSB SPIO_NOC_ROUTER_1_8_8_RE_OVFI_RANGE SPIO_NOC_ROUTER_1_8_8_RE_OVFI_RESET SPIO_NOC_ROUTER_1_8_8_RE_OVFI_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RE_OVFI_GET SPIO_NOC_ROUTER_1_8_8_RE_OVFI_SET ns_noc_io_spio_soc_ip.csr 196388 OVFI 1'b1: In this status bit indicates that the router input event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 0 0 0x0 R/W CSR_PARERR SPIO_NOC_ROUTER_1_8_8_RE_CSR_PARERR_WIDTH SPIO_NOC_ROUTER_1_8_8_RE_CSR_PARERR_MSB SPIO_NOC_ROUTER_1_8_8_RE_CSR_PARERR_LSB SPIO_NOC_ROUTER_1_8_8_RE_CSR_PARERR_RANGE SPIO_NOC_ROUTER_1_8_8_RE_CSR_PARERR_RESET SPIO_NOC_ROUTER_1_8_8_RE_CSR_PARERR_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RE_CSR_PARERR_GET SPIO_NOC_ROUTER_1_8_8_RE_CSR_PARERR_SET ns_noc_io_spio_soc_ip.csr 196399 CSR_PARERR 1'b1: Parity error in config/status registers 1 1 0x0 R/W OVFO SPIO_NOC_ROUTER_1_8_8_RE_OVFO_WIDTH SPIO_NOC_ROUTER_1_8_8_RE_OVFO_MSB SPIO_NOC_ROUTER_1_8_8_RE_OVFO_LSB SPIO_NOC_ROUTER_1_8_8_RE_OVFO_RANGE SPIO_NOC_ROUTER_1_8_8_RE_OVFO_RESET SPIO_NOC_ROUTER_1_8_8_RE_OVFO_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RE_OVFO_GET SPIO_NOC_ROUTER_1_8_8_RE_OVFO_SET ns_noc_io_spio_soc_ip.csr 196413 OVFO 1'b1: In this status bit indicates that the router output event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 2 2 0x0 R/W UNSD_7_3 SPIO_NOC_ROUTER_1_8_8_RE_UNSD_7_3_WIDTH SPIO_NOC_ROUTER_1_8_8_RE_UNSD_7_3_MSB SPIO_NOC_ROUTER_1_8_8_RE_UNSD_7_3_LSB SPIO_NOC_ROUTER_1_8_8_RE_UNSD_7_3_RANGE SPIO_NOC_ROUTER_1_8_8_RE_UNSD_7_3_RESET SPIO_NOC_ROUTER_1_8_8_RE_UNSD_7_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RE_UNSD_7_3_GET SPIO_NOC_ROUTER_1_8_8_RE_UNSD_7_3_SET ns_noc_io_spio_soc_ip.csr 196424 UNSD_7_3 7 3 0x00 R PGE SPIO_NOC_ROUTER_1_8_8_RE_PGE_WIDTH SPIO_NOC_ROUTER_1_8_8_RE_PGE_MSB SPIO_NOC_ROUTER_1_8_8_RE_PGE_LSB SPIO_NOC_ROUTER_1_8_8_RE_PGE_RANGE SPIO_NOC_ROUTER_1_8_8_RE_PGE_RESET SPIO_NOC_ROUTER_1_8_8_RE_PGE_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RE_PGE_GET SPIO_NOC_ROUTER_1_8_8_RE_PGE_SET ns_noc_io_spio_soc_ip.csr 196436 PGE 1'b1: Power gating error, traffic received after router commited to power down 8 8 0x0 R/W NLU SPIO_NOC_ROUTER_1_8_8_RE_NLU_WIDTH SPIO_NOC_ROUTER_1_8_8_RE_NLU_MSB SPIO_NOC_ROUTER_1_8_8_RE_NLU_LSB SPIO_NOC_ROUTER_1_8_8_RE_NLU_RANGE SPIO_NOC_ROUTER_1_8_8_RE_NLU_RESET SPIO_NOC_ROUTER_1_8_8_RE_NLU_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RE_NLU_GET SPIO_NOC_ROUTER_1_8_8_RE_NLU_SET ns_noc_io_spio_soc_ip.csr 196447 NLU 1'b1: Traffic destined for North link which is unavailable 9 9 0x0 R/W ELU SPIO_NOC_ROUTER_1_8_8_RE_ELU_WIDTH SPIO_NOC_ROUTER_1_8_8_RE_ELU_MSB SPIO_NOC_ROUTER_1_8_8_RE_ELU_LSB SPIO_NOC_ROUTER_1_8_8_RE_ELU_RANGE SPIO_NOC_ROUTER_1_8_8_RE_ELU_RESET SPIO_NOC_ROUTER_1_8_8_RE_ELU_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RE_ELU_GET SPIO_NOC_ROUTER_1_8_8_RE_ELU_SET ns_noc_io_spio_soc_ip.csr 196458 ELU 1'b1: Traffic destined for East link which is unavailable 10 10 0x0 R/W WLU SPIO_NOC_ROUTER_1_8_8_RE_WLU_WIDTH SPIO_NOC_ROUTER_1_8_8_RE_WLU_MSB SPIO_NOC_ROUTER_1_8_8_RE_WLU_LSB SPIO_NOC_ROUTER_1_8_8_RE_WLU_RANGE SPIO_NOC_ROUTER_1_8_8_RE_WLU_RESET SPIO_NOC_ROUTER_1_8_8_RE_WLU_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RE_WLU_GET SPIO_NOC_ROUTER_1_8_8_RE_WLU_SET ns_noc_io_spio_soc_ip.csr 196469 WLU 1'b1: Traffic destined for West link which is unavailable 11 11 0x0 R/W SLU SPIO_NOC_ROUTER_1_8_8_RE_SLU_WIDTH SPIO_NOC_ROUTER_1_8_8_RE_SLU_MSB SPIO_NOC_ROUTER_1_8_8_RE_SLU_LSB SPIO_NOC_ROUTER_1_8_8_RE_SLU_RANGE SPIO_NOC_ROUTER_1_8_8_RE_SLU_RESET SPIO_NOC_ROUTER_1_8_8_RE_SLU_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RE_SLU_GET SPIO_NOC_ROUTER_1_8_8_RE_SLU_SET ns_noc_io_spio_soc_ip.csr 196480 SLU 1'b1: Traffic destined for South link which is unavailable 12 12 0x0 R/W HLU SPIO_NOC_ROUTER_1_8_8_RE_HLU_WIDTH SPIO_NOC_ROUTER_1_8_8_RE_HLU_MSB SPIO_NOC_ROUTER_1_8_8_RE_HLU_LSB SPIO_NOC_ROUTER_1_8_8_RE_HLU_RANGE SPIO_NOC_ROUTER_1_8_8_RE_HLU_RESET SPIO_NOC_ROUTER_1_8_8_RE_HLU_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RE_HLU_GET SPIO_NOC_ROUTER_1_8_8_RE_HLU_SET ns_noc_io_spio_soc_ip.csr 196491 HLU 1'b1: Traffic destined for H link which is unavailable 13 13 0x0 R/W ILU SPIO_NOC_ROUTER_1_8_8_RE_ILU_WIDTH SPIO_NOC_ROUTER_1_8_8_RE_ILU_MSB SPIO_NOC_ROUTER_1_8_8_RE_ILU_LSB SPIO_NOC_ROUTER_1_8_8_RE_ILU_RANGE SPIO_NOC_ROUTER_1_8_8_RE_ILU_RESET SPIO_NOC_ROUTER_1_8_8_RE_ILU_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RE_ILU_GET SPIO_NOC_ROUTER_1_8_8_RE_ILU_SET ns_noc_io_spio_soc_ip.csr 196502 ILU 1'b1: Traffic destined for I link which is unavailable 14 14 0x0 R/W JLU SPIO_NOC_ROUTER_1_8_8_RE_JLU_WIDTH SPIO_NOC_ROUTER_1_8_8_RE_JLU_MSB SPIO_NOC_ROUTER_1_8_8_RE_JLU_LSB SPIO_NOC_ROUTER_1_8_8_RE_JLU_RANGE SPIO_NOC_ROUTER_1_8_8_RE_JLU_RESET SPIO_NOC_ROUTER_1_8_8_RE_JLU_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RE_JLU_GET SPIO_NOC_ROUTER_1_8_8_RE_JLU_SET ns_noc_io_spio_soc_ip.csr 196513 JLU 1'b1: Traffic destined for J link which is unavailable 15 15 0x0 R/W KLU SPIO_NOC_ROUTER_1_8_8_RE_KLU_WIDTH SPIO_NOC_ROUTER_1_8_8_RE_KLU_MSB SPIO_NOC_ROUTER_1_8_8_RE_KLU_LSB SPIO_NOC_ROUTER_1_8_8_RE_KLU_RANGE SPIO_NOC_ROUTER_1_8_8_RE_KLU_RESET SPIO_NOC_ROUTER_1_8_8_RE_KLU_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RE_KLU_GET SPIO_NOC_ROUTER_1_8_8_RE_KLU_SET ns_noc_io_spio_soc_ip.csr 196524 KLU 1'b1: Traffic destined for K link which is unavailable 16 16 0x0 R/W UNSD_31_14 SPIO_NOC_ROUTER_1_8_8_RE_UNSD_31_14_WIDTH SPIO_NOC_ROUTER_1_8_8_RE_UNSD_31_14_MSB SPIO_NOC_ROUTER_1_8_8_RE_UNSD_31_14_LSB SPIO_NOC_ROUTER_1_8_8_RE_UNSD_31_14_RANGE SPIO_NOC_ROUTER_1_8_8_RE_UNSD_31_14_RESET SPIO_NOC_ROUTER_1_8_8_RE_UNSD_31_14_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RE_UNSD_31_14_GET SPIO_NOC_ROUTER_1_8_8_RE_UNSD_31_14_SET ns_noc_io_spio_soc_ip.csr 196535 UNSD_31_14 31 17 0x0000 R register spio_noc.router_1_8_8_rem router_1_8_8_rem SPIO_NOC_ROUTER_1_8_8_REM_ADDRESS SPIO_NOC_ROUTER_1_8_8_REM_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_REM_OFFSET SPIO_NOC_ROUTER_1_8_8_REM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 196709 R1_8 register rem 0x5C088 R/W 0x0001fe00 Spio_noc_router_1_8_8_rem This register is used to select whether the interrupt events in the Router Event Interrupt Status register should send an interrupt when asserted. If the corresponding bit is set to 1, an interrupt will not be sent. This register can be read and written to. false false false false OVFIM SPIO_NOC_ROUTER_1_8_8_REM_OVFIM_WIDTH SPIO_NOC_ROUTER_1_8_8_REM_OVFIM_MSB SPIO_NOC_ROUTER_1_8_8_REM_OVFIM_LSB SPIO_NOC_ROUTER_1_8_8_REM_OVFIM_RANGE SPIO_NOC_ROUTER_1_8_8_REM_OVFIM_RESET SPIO_NOC_ROUTER_1_8_8_REM_OVFIM_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_REM_OVFIM_GET SPIO_NOC_ROUTER_1_8_8_REM_OVFIM_SET ns_noc_io_spio_soc_ip.csr 196562 OVFIM 1'b1: Masks or disables an interrupt from being generated by the input event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 0 0 0x0 R/W CSR_PARERRM SPIO_NOC_ROUTER_1_8_8_REM_CSR_PARERRM_WIDTH SPIO_NOC_ROUTER_1_8_8_REM_CSR_PARERRM_MSB SPIO_NOC_ROUTER_1_8_8_REM_CSR_PARERRM_LSB SPIO_NOC_ROUTER_1_8_8_REM_CSR_PARERRM_RANGE SPIO_NOC_ROUTER_1_8_8_REM_CSR_PARERRM_RESET SPIO_NOC_ROUTER_1_8_8_REM_CSR_PARERRM_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_REM_CSR_PARERRM_GET SPIO_NOC_ROUTER_1_8_8_REM_CSR_PARERRM_SET ns_noc_io_spio_soc_ip.csr 196573 CSR_PARERRM 1'b1: Mask CSR parity error interrupt 1 1 0x0 R/W OVFOM SPIO_NOC_ROUTER_1_8_8_REM_OVFOM_WIDTH SPIO_NOC_ROUTER_1_8_8_REM_OVFOM_MSB SPIO_NOC_ROUTER_1_8_8_REM_OVFOM_LSB SPIO_NOC_ROUTER_1_8_8_REM_OVFOM_RANGE SPIO_NOC_ROUTER_1_8_8_REM_OVFOM_RESET SPIO_NOC_ROUTER_1_8_8_REM_OVFOM_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_REM_OVFOM_GET SPIO_NOC_ROUTER_1_8_8_REM_OVFOM_SET ns_noc_io_spio_soc_ip.csr 196587 OVFOM 1'b1: Masks or disables an interrupt from being generated by the output event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 2 2 0x0 R/W UNSD_7_3 SPIO_NOC_ROUTER_1_8_8_REM_UNSD_7_3_WIDTH SPIO_NOC_ROUTER_1_8_8_REM_UNSD_7_3_MSB SPIO_NOC_ROUTER_1_8_8_REM_UNSD_7_3_LSB SPIO_NOC_ROUTER_1_8_8_REM_UNSD_7_3_RANGE SPIO_NOC_ROUTER_1_8_8_REM_UNSD_7_3_RESET SPIO_NOC_ROUTER_1_8_8_REM_UNSD_7_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_REM_UNSD_7_3_GET SPIO_NOC_ROUTER_1_8_8_REM_UNSD_7_3_SET ns_noc_io_spio_soc_ip.csr 196598 UNSD_7_3 7 3 0x00 R PGM SPIO_NOC_ROUTER_1_8_8_REM_PGM_WIDTH SPIO_NOC_ROUTER_1_8_8_REM_PGM_MSB SPIO_NOC_ROUTER_1_8_8_REM_PGM_LSB SPIO_NOC_ROUTER_1_8_8_REM_PGM_RANGE SPIO_NOC_ROUTER_1_8_8_REM_PGM_RESET SPIO_NOC_ROUTER_1_8_8_REM_PGM_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_REM_PGM_GET SPIO_NOC_ROUTER_1_8_8_REM_PGM_SET ns_noc_io_spio_soc_ip.csr 196609 PGM 1'b1: Mask PGE error interrupt 8 8 0x0 R/W MN SPIO_NOC_ROUTER_1_8_8_REM_MN_WIDTH SPIO_NOC_ROUTER_1_8_8_REM_MN_MSB SPIO_NOC_ROUTER_1_8_8_REM_MN_LSB SPIO_NOC_ROUTER_1_8_8_REM_MN_RANGE SPIO_NOC_ROUTER_1_8_8_REM_MN_RESET SPIO_NOC_ROUTER_1_8_8_REM_MN_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_REM_MN_GET SPIO_NOC_ROUTER_1_8_8_REM_MN_SET ns_noc_io_spio_soc_ip.csr 196620 MN 1'b1: Mask NLU error interrupt 9 9 0x1 R/W ME SPIO_NOC_ROUTER_1_8_8_REM_ME_WIDTH SPIO_NOC_ROUTER_1_8_8_REM_ME_MSB SPIO_NOC_ROUTER_1_8_8_REM_ME_LSB SPIO_NOC_ROUTER_1_8_8_REM_ME_RANGE SPIO_NOC_ROUTER_1_8_8_REM_ME_RESET SPIO_NOC_ROUTER_1_8_8_REM_ME_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_REM_ME_GET SPIO_NOC_ROUTER_1_8_8_REM_ME_SET ns_noc_io_spio_soc_ip.csr 196631 ME 1'b1: Mask ELU error interrupt 10 10 0x1 R/W MW SPIO_NOC_ROUTER_1_8_8_REM_MW_WIDTH SPIO_NOC_ROUTER_1_8_8_REM_MW_MSB SPIO_NOC_ROUTER_1_8_8_REM_MW_LSB SPIO_NOC_ROUTER_1_8_8_REM_MW_RANGE SPIO_NOC_ROUTER_1_8_8_REM_MW_RESET SPIO_NOC_ROUTER_1_8_8_REM_MW_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_REM_MW_GET SPIO_NOC_ROUTER_1_8_8_REM_MW_SET ns_noc_io_spio_soc_ip.csr 196642 MW 1'b1: Mask WLU error interrupt 11 11 0x1 R/W MS SPIO_NOC_ROUTER_1_8_8_REM_MS_WIDTH SPIO_NOC_ROUTER_1_8_8_REM_MS_MSB SPIO_NOC_ROUTER_1_8_8_REM_MS_LSB SPIO_NOC_ROUTER_1_8_8_REM_MS_RANGE SPIO_NOC_ROUTER_1_8_8_REM_MS_RESET SPIO_NOC_ROUTER_1_8_8_REM_MS_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_REM_MS_GET SPIO_NOC_ROUTER_1_8_8_REM_MS_SET ns_noc_io_spio_soc_ip.csr 196653 MS 1'b1: Mask SLU error interrupt 12 12 0x1 R/W MH SPIO_NOC_ROUTER_1_8_8_REM_MH_WIDTH SPIO_NOC_ROUTER_1_8_8_REM_MH_MSB SPIO_NOC_ROUTER_1_8_8_REM_MH_LSB SPIO_NOC_ROUTER_1_8_8_REM_MH_RANGE SPIO_NOC_ROUTER_1_8_8_REM_MH_RESET SPIO_NOC_ROUTER_1_8_8_REM_MH_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_REM_MH_GET SPIO_NOC_ROUTER_1_8_8_REM_MH_SET ns_noc_io_spio_soc_ip.csr 196664 MH 1'b1: Mask HLU error interrupt 13 13 0x1 R/W MI SPIO_NOC_ROUTER_1_8_8_REM_MI_WIDTH SPIO_NOC_ROUTER_1_8_8_REM_MI_MSB SPIO_NOC_ROUTER_1_8_8_REM_MI_LSB SPIO_NOC_ROUTER_1_8_8_REM_MI_RANGE SPIO_NOC_ROUTER_1_8_8_REM_MI_RESET SPIO_NOC_ROUTER_1_8_8_REM_MI_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_REM_MI_GET SPIO_NOC_ROUTER_1_8_8_REM_MI_SET ns_noc_io_spio_soc_ip.csr 196675 MI 1'b1: Mask ILU error interrupt 14 14 0x1 R/W MJ SPIO_NOC_ROUTER_1_8_8_REM_MJ_WIDTH SPIO_NOC_ROUTER_1_8_8_REM_MJ_MSB SPIO_NOC_ROUTER_1_8_8_REM_MJ_LSB SPIO_NOC_ROUTER_1_8_8_REM_MJ_RANGE SPIO_NOC_ROUTER_1_8_8_REM_MJ_RESET SPIO_NOC_ROUTER_1_8_8_REM_MJ_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_REM_MJ_GET SPIO_NOC_ROUTER_1_8_8_REM_MJ_SET ns_noc_io_spio_soc_ip.csr 196686 MJ 1'b1: Mask JLU error interrupt 15 15 0x1 R/W MK SPIO_NOC_ROUTER_1_8_8_REM_MK_WIDTH SPIO_NOC_ROUTER_1_8_8_REM_MK_MSB SPIO_NOC_ROUTER_1_8_8_REM_MK_LSB SPIO_NOC_ROUTER_1_8_8_REM_MK_RANGE SPIO_NOC_ROUTER_1_8_8_REM_MK_RESET SPIO_NOC_ROUTER_1_8_8_REM_MK_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_REM_MK_GET SPIO_NOC_ROUTER_1_8_8_REM_MK_SET ns_noc_io_spio_soc_ip.csr 196697 MK 1'b1: Mask KLU error interrupt 16 16 0x1 R/W UNSD_31_14 SPIO_NOC_ROUTER_1_8_8_REM_UNSD_31_14_WIDTH SPIO_NOC_ROUTER_1_8_8_REM_UNSD_31_14_MSB SPIO_NOC_ROUTER_1_8_8_REM_UNSD_31_14_LSB SPIO_NOC_ROUTER_1_8_8_REM_UNSD_31_14_RANGE SPIO_NOC_ROUTER_1_8_8_REM_UNSD_31_14_RESET SPIO_NOC_ROUTER_1_8_8_REM_UNSD_31_14_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_REM_UNSD_31_14_GET SPIO_NOC_ROUTER_1_8_8_REM_UNSD_31_14_SET ns_noc_io_spio_soc_ip.csr 196708 UNSD_31_14 31 17 0x0000 R register spio_noc.router_1_8_8_recc router_1_8_8_recc SPIO_NOC_ROUTER_1_8_8_RECC_ADDRESS SPIO_NOC_ROUTER_1_8_8_RECC_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_RECC_OFFSET SPIO_NOC_ROUTER_1_8_8_RECC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 196794 R1_8 register recc 0x5C090 R/W 0x00000000 Spio_noc_router_1_8_8_recc This register is used to select which hardware events will increment the event counter. false false false false IVC SPIO_NOC_ROUTER_1_8_8_RECC_IVC_WIDTH SPIO_NOC_ROUTER_1_8_8_RECC_IVC_MSB SPIO_NOC_ROUTER_1_8_8_RECC_IVC_LSB SPIO_NOC_ROUTER_1_8_8_RECC_IVC_RANGE SPIO_NOC_ROUTER_1_8_8_RECC_IVC_RESET SPIO_NOC_ROUTER_1_8_8_RECC_IVC_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RECC_IVC_GET SPIO_NOC_ROUTER_1_8_8_RECC_IVC_SET ns_noc_io_spio_soc_ip.csr 196730 IVC 11: Input VC 3 10: Input VC 2 01: Input VC 1 00: Input VC 0 1 0 0x0 R/W UNSD_3_2 SPIO_NOC_ROUTER_1_8_8_RECC_UNSD_3_2_WIDTH SPIO_NOC_ROUTER_1_8_8_RECC_UNSD_3_2_MSB SPIO_NOC_ROUTER_1_8_8_RECC_UNSD_3_2_LSB SPIO_NOC_ROUTER_1_8_8_RECC_UNSD_3_2_RANGE SPIO_NOC_ROUTER_1_8_8_RECC_UNSD_3_2_RESET SPIO_NOC_ROUTER_1_8_8_RECC_UNSD_3_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RECC_UNSD_3_2_GET SPIO_NOC_ROUTER_1_8_8_RECC_UNSD_3_2_SET ns_noc_io_spio_soc_ip.csr 196741 UNSD_3_2 3 2 0x0 R INP SPIO_NOC_ROUTER_1_8_8_RECC_INP_WIDTH SPIO_NOC_ROUTER_1_8_8_RECC_INP_MSB SPIO_NOC_ROUTER_1_8_8_RECC_INP_LSB SPIO_NOC_ROUTER_1_8_8_RECC_INP_RANGE SPIO_NOC_ROUTER_1_8_8_RECC_INP_RESET SPIO_NOC_ROUTER_1_8_8_RECC_INP_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RECC_INP_GET SPIO_NOC_ROUTER_1_8_8_RECC_INP_SET ns_noc_io_spio_soc_ip.csr 196752 INP Input port on which the event is captured 6 4 0x0 R/W UNSD_7_7 SPIO_NOC_ROUTER_1_8_8_RECC_UNSD_7_7_WIDTH SPIO_NOC_ROUTER_1_8_8_RECC_UNSD_7_7_MSB SPIO_NOC_ROUTER_1_8_8_RECC_UNSD_7_7_LSB SPIO_NOC_ROUTER_1_8_8_RECC_UNSD_7_7_RANGE SPIO_NOC_ROUTER_1_8_8_RECC_UNSD_7_7_RESET SPIO_NOC_ROUTER_1_8_8_RECC_UNSD_7_7_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RECC_UNSD_7_7_GET SPIO_NOC_ROUTER_1_8_8_RECC_UNSD_7_7_SET ns_noc_io_spio_soc_ip.csr 196763 UNSD_7_7 7 7 0x0 R EVT SPIO_NOC_ROUTER_1_8_8_RECC_EVT_WIDTH SPIO_NOC_ROUTER_1_8_8_RECC_EVT_MSB SPIO_NOC_ROUTER_1_8_8_RECC_EVT_LSB SPIO_NOC_ROUTER_1_8_8_RECC_EVT_RANGE SPIO_NOC_ROUTER_1_8_8_RECC_EVT_RESET SPIO_NOC_ROUTER_1_8_8_RECC_EVT_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RECC_EVT_GET SPIO_NOC_ROUTER_1_8_8_RECC_EVT_SET ns_noc_io_spio_soc_ip.csr 196782 EVT 11: Generates count event when VC has valid data, but is stalled 10: Generates count event on every flit received for the selected input port and selected input VCs, this can be used to count total flits received on a router input port 01: Generates count event on every EOP received for the selected input port and selected input VCs, this can be used to count packets received on a router input port 00: Disable 9 8 0x0 R/W UNSD_31_10 SPIO_NOC_ROUTER_1_8_8_RECC_UNSD_31_10_WIDTH SPIO_NOC_ROUTER_1_8_8_RECC_UNSD_31_10_MSB SPIO_NOC_ROUTER_1_8_8_RECC_UNSD_31_10_LSB SPIO_NOC_ROUTER_1_8_8_RECC_UNSD_31_10_RANGE SPIO_NOC_ROUTER_1_8_8_RECC_UNSD_31_10_RESET SPIO_NOC_ROUTER_1_8_8_RECC_UNSD_31_10_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RECC_UNSD_31_10_GET SPIO_NOC_ROUTER_1_8_8_RECC_UNSD_31_10_SET ns_noc_io_spio_soc_ip.csr 196793 UNSD_31_10 31 10 0x000000 R register spio_noc.router_1_8_8_rec router_1_8_8_rec SPIO_NOC_ROUTER_1_8_8_REC_ADDRESS SPIO_NOC_ROUTER_1_8_8_REC_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_REC_OFFSET SPIO_NOC_ROUTER_1_8_8_REC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 196819 R1_8 register rec 0x5C098 R/W 0x00000000 Spio_noc_router_1_8_8_rec This register holds the event counter. The value can be read to determine the current count value. The value can be written to initialize the counter. When events trigger a count, the counter will increment. When the counter increments at its highest value, it will roll over to zero and the overflow will mark the Router Event Interrupt Status register, which could trigger an interrupt. false false false false EVENT_CNTR SPIO_NOC_ROUTER_1_8_8_REC_EVENT_CNTR_WIDTH SPIO_NOC_ROUTER_1_8_8_REC_EVENT_CNTR_MSB SPIO_NOC_ROUTER_1_8_8_REC_EVENT_CNTR_LSB SPIO_NOC_ROUTER_1_8_8_REC_EVENT_CNTR_RANGE SPIO_NOC_ROUTER_1_8_8_REC_EVENT_CNTR_RESET SPIO_NOC_ROUTER_1_8_8_REC_EVENT_CNTR_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_REC_EVENT_CNTR_GET SPIO_NOC_ROUTER_1_8_8_REC_EVENT_CNTR_SET ns_noc_io_spio_soc_ip.csr 196818 EVENT_CNTR 32'bit event incrementing counter. Rollover from 32'hFFFFF -> 32'd0 sets the rollover status bit RE 31 0 0x00000000 R/W register spio_noc.router_1_8_8_id router_1_8_8_id SPIO_NOC_ROUTER_1_8_8_ID_ADDRESS SPIO_NOC_ROUTER_1_8_8_ID_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_ID_OFFSET SPIO_NOC_ROUTER_1_8_8_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 196888 R1_8 register id 0x5C0A0 R 0x010000e1 Spio_noc_router_1_8_8_id This register holds layer and position information for the router. It is a read-only register. It can be used for debugging software access to the NoC elements by confirming that a read has successfully targeted the correct NoC element. false false false false LAYER SPIO_NOC_ROUTER_1_8_8_ID_LAYER_WIDTH SPIO_NOC_ROUTER_1_8_8_ID_LAYER_MSB SPIO_NOC_ROUTER_1_8_8_ID_LAYER_LSB SPIO_NOC_ROUTER_1_8_8_ID_LAYER_RANGE SPIO_NOC_ROUTER_1_8_8_ID_LAYER_RESET SPIO_NOC_ROUTER_1_8_8_ID_LAYER_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ID_LAYER_GET SPIO_NOC_ROUTER_1_8_8_ID_LAYER_SET ns_noc_io_spio_soc_ip.csr 196844 LAYER 5-bit identifier of the NoC layer on which this router is located 4 0 0x01 R POS SPIO_NOC_ROUTER_1_8_8_ID_POS_WIDTH SPIO_NOC_ROUTER_1_8_8_ID_POS_MSB SPIO_NOC_ROUTER_1_8_8_ID_POS_LSB SPIO_NOC_ROUTER_1_8_8_ID_POS_RANGE SPIO_NOC_ROUTER_1_8_8_ID_POS_RESET SPIO_NOC_ROUTER_1_8_8_ID_POS_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ID_POS_GET SPIO_NOC_ROUTER_1_8_8_ID_POS_SET ns_noc_io_spio_soc_ip.csr 196855 POS 16-bit position ID of this router in the NoC 20 5 0x0007 R ZERO SPIO_NOC_ROUTER_1_8_8_ID_ZERO_WIDTH SPIO_NOC_ROUTER_1_8_8_ID_ZERO_MSB SPIO_NOC_ROUTER_1_8_8_ID_ZERO_LSB SPIO_NOC_ROUTER_1_8_8_ID_ZERO_RANGE SPIO_NOC_ROUTER_1_8_8_ID_ZERO_RESET SPIO_NOC_ROUTER_1_8_8_ID_ZERO_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ID_ZERO_GET SPIO_NOC_ROUTER_1_8_8_ID_ZERO_SET ns_noc_io_spio_soc_ip.csr 196866 ZERO Zeroes 23 21 0x0 R ONE SPIO_NOC_ROUTER_1_8_8_ID_ONE_WIDTH SPIO_NOC_ROUTER_1_8_8_ID_ONE_MSB SPIO_NOC_ROUTER_1_8_8_ID_ONE_LSB SPIO_NOC_ROUTER_1_8_8_ID_ONE_RANGE SPIO_NOC_ROUTER_1_8_8_ID_ONE_RESET SPIO_NOC_ROUTER_1_8_8_ID_ONE_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ID_ONE_GET SPIO_NOC_ROUTER_1_8_8_ID_ONE_SET ns_noc_io_spio_soc_ip.csr 196877 ONE One 24 24 0x1 R UNSD_31_25 SPIO_NOC_ROUTER_1_8_8_ID_UNSD_31_25_WIDTH SPIO_NOC_ROUTER_1_8_8_ID_UNSD_31_25_MSB SPIO_NOC_ROUTER_1_8_8_ID_UNSD_31_25_LSB SPIO_NOC_ROUTER_1_8_8_ID_UNSD_31_25_RANGE SPIO_NOC_ROUTER_1_8_8_ID_UNSD_31_25_RESET SPIO_NOC_ROUTER_1_8_8_ID_UNSD_31_25_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ID_UNSD_31_25_GET SPIO_NOC_ROUTER_1_8_8_ID_UNSD_31_25_SET ns_noc_io_spio_soc_ip.csr 196887 UNSD_31_25 31 25 0x00 R register spio_noc.router_1_8_8_rcgc router_1_8_8_rcgc SPIO_NOC_ROUTER_1_8_8_RCGC_ADDRESS SPIO_NOC_ROUTER_1_8_8_RCGC_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_RCGC_OFFSET SPIO_NOC_ROUTER_1_8_8_RCGC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 196914 R1_8 register rcgc 0x5C0A8 R/W 0x00000064 Spio_noc_router_1_8_8_rcgc Programmable interval used by coarse clock gating logic in routers.This count determines the consecutive number of idle cycle after which a router output port initiates coarse clock gating of the local port clock and de-asserts the 'busy' signal to the downstream router. This signal indicates inactivity to the downstream router and allows it to initiate coarse clock gating of its corresponding input port. false false false false HYSTERESIS_COUNTER SPIO_NOC_ROUTER_1_8_8_RCGC_HYSTERESIS_COUNTER_WIDTH SPIO_NOC_ROUTER_1_8_8_RCGC_HYSTERESIS_COUNTER_MSB SPIO_NOC_ROUTER_1_8_8_RCGC_HYSTERESIS_COUNTER_LSB SPIO_NOC_ROUTER_1_8_8_RCGC_HYSTERESIS_COUNTER_RANGE SPIO_NOC_ROUTER_1_8_8_RCGC_HYSTERESIS_COUNTER_RESET SPIO_NOC_ROUTER_1_8_8_RCGC_HYSTERESIS_COUNTER_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RCGC_HYSTERESIS_COUNTER_GET SPIO_NOC_ROUTER_1_8_8_RCGC_HYSTERESIS_COUNTER_SET ns_noc_io_spio_soc_ip.csr 196913 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W register spio_noc.router_1_8_8_rcgo router_1_8_8_rcgo SPIO_NOC_ROUTER_1_8_8_RCGO_ADDRESS SPIO_NOC_ROUTER_1_8_8_RCGO_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_RCGO_OFFSET SPIO_NOC_ROUTER_1_8_8_RCGO_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 196953 R1_8 register rcgo 0x5C0B0 R/W 0x00000000 Spio_noc_router_1_8_8_rcgo This register is used by coarse grained clock gating logic. This register can be set to override coarse clock gating for the entire router. Coarse clock gating for selective routers can be overridden by locally setting this register, if the user does not want incur and aggregate coarse clock gating cycle penalty over a "fast path/critical path" through the NoC. false false false false FPO SPIO_NOC_ROUTER_1_8_8_RCGO_FPO_WIDTH SPIO_NOC_ROUTER_1_8_8_RCGO_FPO_MSB SPIO_NOC_ROUTER_1_8_8_RCGO_FPO_LSB SPIO_NOC_ROUTER_1_8_8_RCGO_FPO_RANGE SPIO_NOC_ROUTER_1_8_8_RCGO_FPO_RESET SPIO_NOC_ROUTER_1_8_8_RCGO_FPO_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RCGO_FPO_GET SPIO_NOC_ROUTER_1_8_8_RCGO_FPO_SET ns_noc_io_spio_soc_ip.csr 196941 FPO 1'b1: Coarse clock gating is locally disabled (for fast path) 1'b0: Coarse clock gating is locally enabled 0 0 0x0 R/W UNSD_31_1 SPIO_NOC_ROUTER_1_8_8_RCGO_UNSD_31_1_WIDTH SPIO_NOC_ROUTER_1_8_8_RCGO_UNSD_31_1_MSB SPIO_NOC_ROUTER_1_8_8_RCGO_UNSD_31_1_LSB SPIO_NOC_ROUTER_1_8_8_RCGO_UNSD_31_1_RANGE SPIO_NOC_ROUTER_1_8_8_RCGO_UNSD_31_1_RESET SPIO_NOC_ROUTER_1_8_8_RCGO_UNSD_31_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_RCGO_UNSD_31_1_GET SPIO_NOC_ROUTER_1_8_8_RCGO_UNSD_31_1_SET ns_noc_io_spio_soc_ip.csr 196952 UNSD_31_1 31 1 0x00000000 R register spio_noc.router_1_8_8_p0_rperr router_1_8_8_p0_rperr SPIO_NOC_ROUTER_1_8_8_P0_RPERR_ADDRESS SPIO_NOC_ROUTER_1_8_8_P0_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_P0_RPERR_OFFSET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 197244 R1_8 register p0_rperr 0x5C0B8 R/W 0x00000000 Spio_noc_router_1_8_8_p0_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 196996 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 197007 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 197018 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 197029 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_8_8_P0_RPERR_CR_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERR_CR_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_CR_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_CR_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERR_CR_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERR_CR_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 197040 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_8_8_P0_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 197051 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_0_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_0_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_0_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_0_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_0_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 197062 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_0_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_0_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_0_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_0_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 197073 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_0_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_0_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_0_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_0_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 197085 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_0_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_0_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_0_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_0_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 197096 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_1_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_1_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_1_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_1_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_1_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 197108 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_1_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_1_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_1_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_1_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 197120 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_1_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_1_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_1_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_1_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 197133 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_1_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_1_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_1_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_1_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 197145 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_2_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_2_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_2_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_2_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_2_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 197157 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_2_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_2_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_2_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_2_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 197169 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_2_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_2_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_2_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_2_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 197182 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_2_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_2_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_2_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_2_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 197194 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_3_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_3_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_3_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_3_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_3_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 197206 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_3_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_3_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_3_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_3_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 197218 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_3_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_3_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_3_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_3_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 197231 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_3_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_3_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_3_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_3_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 197243 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_1_8_8_p2_rperr router_1_8_8_p2_rperr SPIO_NOC_ROUTER_1_8_8_P2_RPERR_ADDRESS SPIO_NOC_ROUTER_1_8_8_P2_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_P2_RPERR_OFFSET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 197531 R1_8 register p2_rperr 0x5C0C8 R/W 0x00000000 Spio_noc_router_1_8_8_p2_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 197287 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 197298 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 197309 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 197320 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_8_8_P2_RPERR_CR_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERR_CR_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_CR_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_CR_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERR_CR_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERR_CR_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 197331 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_8_8_P2_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 197342 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_0_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_0_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_0_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_0_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_0_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 197353 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_0_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_0_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_0_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_0_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 197364 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_0_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_0_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_0_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_0_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 197376 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_0_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_0_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_0_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_0_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 197387 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_1_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_1_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_1_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_1_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_1_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 197398 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_1_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_1_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_1_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_1_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 197409 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_1_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_1_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_1_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_1_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 197421 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_1_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_1_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_1_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_1_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 197432 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_2_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_2_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_2_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_2_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_2_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 197444 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_2_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_2_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_2_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_2_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 197456 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_2_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_2_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_2_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_2_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 197469 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_2_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_2_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_2_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_2_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 197481 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_3_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_3_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_3_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_3_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_3_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 197493 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_3_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_3_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_3_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_3_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 197505 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_3_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_3_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_3_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_3_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 197518 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_3_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_3_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_3_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_3_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 197530 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_1_8_8_p4_rperr router_1_8_8_p4_rperr SPIO_NOC_ROUTER_1_8_8_P4_RPERR_ADDRESS SPIO_NOC_ROUTER_1_8_8_P4_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_P4_RPERR_OFFSET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 197822 R1_8 register p4_rperr 0x5C0D8 R/W 0x00000000 Spio_noc_router_1_8_8_p4_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 197574 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 197585 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 197596 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 197607 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_8_8_P4_RPERR_CR_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERR_CR_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_CR_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_CR_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERR_CR_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERR_CR_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 197618 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_8_8_P4_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 197629 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_0_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_0_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_0_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_0_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_0_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 197640 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_0_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_0_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_0_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_0_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 197651 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_0_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_0_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_0_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_0_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 197663 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_0_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_0_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_0_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_0_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 197674 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_1_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_1_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_1_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_1_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_1_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 197686 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_1_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_1_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_1_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_1_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 197698 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_1_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_1_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_1_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_1_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 197711 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_1_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_1_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_1_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_1_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 197723 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_2_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_2_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_2_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_2_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_2_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 197735 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_2_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_2_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_2_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_2_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 197747 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_2_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_2_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_2_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_2_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 197760 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_2_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_2_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_2_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_2_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 197772 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_3_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_3_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_3_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_3_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_3_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 197784 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_3_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_3_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_3_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_3_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 197796 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_3_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_3_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_3_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_3_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 197809 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_3_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_3_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_3_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_3_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 197821 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_1_8_8_p5_rperr router_1_8_8_p5_rperr SPIO_NOC_ROUTER_1_8_8_P5_RPERR_ADDRESS SPIO_NOC_ROUTER_1_8_8_P5_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_P5_RPERR_OFFSET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 198113 R1_8 register p5_rperr 0x5C0E0 R/W 0x00000000 Spio_noc_router_1_8_8_p5_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 197865 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 197876 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 197887 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 197898 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_8_8_P5_RPERR_CR_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERR_CR_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_CR_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_CR_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERR_CR_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERR_CR_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 197909 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_8_8_P5_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 197920 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_0_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_0_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_0_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_0_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_0_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 197931 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_0_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_0_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_0_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_0_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 197942 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_0_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_0_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_0_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_0_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 197954 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_0_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_0_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_0_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_0_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 197965 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_1_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_1_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_1_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_1_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_1_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 197977 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_1_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_1_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_1_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_1_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 197989 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_1_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_1_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_1_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_1_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 198002 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_1_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_1_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_1_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_1_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 198014 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_2_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_2_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_2_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_2_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_2_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 198026 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_2_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_2_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_2_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_2_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 198038 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_2_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_2_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_2_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_2_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 198051 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_2_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_2_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_2_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_2_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 198063 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_3_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_3_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_3_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_3_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_3_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 198075 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_3_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_3_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_3_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_3_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 198087 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_3_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_3_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_3_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_3_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 198100 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_3_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_3_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_3_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_3_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 198112 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_1_8_8_p6_rperr router_1_8_8_p6_rperr SPIO_NOC_ROUTER_1_8_8_P6_RPERR_ADDRESS SPIO_NOC_ROUTER_1_8_8_P6_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_P6_RPERR_OFFSET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 198404 R1_8 register p6_rperr 0x5C0E8 R/W 0x00000000 Spio_noc_router_1_8_8_p6_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 198156 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 198167 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 198178 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 198189 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_8_8_P6_RPERR_CR_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERR_CR_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_CR_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_CR_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERR_CR_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERR_CR_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 198200 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_8_8_P6_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 198211 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_0_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_0_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_0_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_0_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_0_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 198222 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_0_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_0_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_0_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_0_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 198233 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_0_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_0_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_0_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_0_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 198245 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_0_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_0_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_0_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_0_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 198256 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_1_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_1_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_1_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_1_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_1_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 198268 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_1_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_1_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_1_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_1_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 198280 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_1_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_1_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_1_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_1_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 198293 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_1_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_1_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_1_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_1_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 198305 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_2_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_2_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_2_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_2_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_2_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 198317 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_2_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_2_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_2_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_2_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 198329 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_2_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_2_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_2_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_2_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 198342 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_2_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_2_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_2_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_2_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 198354 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_3_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_3_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_3_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_3_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_3_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 198366 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_3_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_3_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_3_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_3_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 198378 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_3_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_3_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_3_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_3_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 198391 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_3_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_3_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_3_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_3_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 198403 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_1_8_8_p7_rperr router_1_8_8_p7_rperr SPIO_NOC_ROUTER_1_8_8_P7_RPERR_ADDRESS SPIO_NOC_ROUTER_1_8_8_P7_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_P7_RPERR_OFFSET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 198695 R1_8 register p7_rperr 0x5C0F0 R/W 0x00000000 Spio_noc_router_1_8_8_p7_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 198447 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 198458 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 198469 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 198480 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_8_8_P7_RPERR_CR_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERR_CR_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_CR_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_CR_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERR_CR_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERR_CR_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 198491 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_8_8_P7_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 198502 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_0_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_0_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_0_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_0_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_0_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 198513 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_0_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_0_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_0_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_0_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 198524 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_0_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_0_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_0_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_0_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 198536 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_0_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_0_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_0_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_0_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 198547 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_1_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_1_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_1_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_1_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_1_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 198559 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_1_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_1_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_1_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_1_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 198571 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_1_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_1_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_1_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_1_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 198584 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_1_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_1_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_1_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_1_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 198596 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_2_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_2_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_2_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_2_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_2_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 198608 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_2_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_2_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_2_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_2_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 198620 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_2_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_2_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_2_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_2_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 198633 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_2_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_2_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_2_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_2_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 198645 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_3_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_3_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_3_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_3_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_3_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 198657 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_3_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_3_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_3_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_3_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 198669 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_3_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_3_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_3_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_3_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 198682 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_3_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_3_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_3_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_3_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 198694 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_1_8_8_p0_rperrm router_1_8_8_p0_rperrm SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_ADDRESS SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_OFFSET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 198953 R1_8 register p0_rperrm 0x5C0F8 R/W 0x00000000 Spio_noc_router_1_8_8_p0_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 198717 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 198728 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 198739 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 198750 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_CR_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_CR_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_CR_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_CR_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_CR_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 198761 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 198772 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_0_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_0_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_0_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_0_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 198783 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_0_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 198794 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_0_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 198806 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_0_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 198817 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_1_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_1_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_1_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_1_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 198828 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_1_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 198839 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_1_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 198851 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_1_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 198862 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_2_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_2_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_2_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_2_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 198873 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_2_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 198884 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_2_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 198896 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_2_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 198907 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_3_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_3_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_3_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_3_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 198918 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_3_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 198929 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_3_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 198941 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_3_GET SPIO_NOC_ROUTER_1_8_8_P0_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 198952 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_1_8_8_p2_rperrm router_1_8_8_p2_rperrm SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_ADDRESS SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_OFFSET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 199211 R1_8 register p2_rperrm 0x5C108 R/W 0x00000000 Spio_noc_router_1_8_8_p2_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 198975 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 198986 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 198997 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 199008 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_CR_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_CR_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_CR_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_CR_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_CR_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 199019 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 199030 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_0_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_0_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_0_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_0_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 199041 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_0_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 199052 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_0_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 199064 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_0_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 199075 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_1_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_1_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_1_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_1_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 199086 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_1_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 199097 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_1_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 199109 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_1_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 199120 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_2_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_2_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_2_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_2_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 199131 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_2_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 199142 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_2_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 199154 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_2_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 199165 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_3_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_3_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_3_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_3_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 199176 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_3_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 199187 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_3_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 199199 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_3_GET SPIO_NOC_ROUTER_1_8_8_P2_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 199210 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_1_8_8_p4_rperrm router_1_8_8_p4_rperrm SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_ADDRESS SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_OFFSET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 199469 R1_8 register p4_rperrm 0x5C118 R/W 0x00000000 Spio_noc_router_1_8_8_p4_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 199233 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 199244 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 199255 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 199266 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_CR_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_CR_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_CR_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_CR_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_CR_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 199277 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 199288 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_0_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_0_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_0_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_0_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 199299 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_0_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 199310 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_0_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 199322 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_0_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 199333 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_1_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_1_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_1_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_1_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 199344 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_1_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 199355 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_1_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 199367 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_1_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 199378 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_2_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_2_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_2_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_2_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 199389 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_2_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 199400 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_2_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 199412 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_2_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 199423 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_3_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_3_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_3_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_3_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 199434 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_3_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 199445 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_3_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 199457 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_3_GET SPIO_NOC_ROUTER_1_8_8_P4_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 199468 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_1_8_8_p5_rperrm router_1_8_8_p5_rperrm SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_ADDRESS SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_OFFSET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 199727 R1_8 register p5_rperrm 0x5C120 R/W 0x00000000 Spio_noc_router_1_8_8_p5_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 199491 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 199502 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 199513 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 199524 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_CR_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_CR_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_CR_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_CR_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_CR_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 199535 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 199546 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_0_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_0_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_0_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_0_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 199557 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_0_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 199568 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_0_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 199580 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_0_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 199591 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_1_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_1_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_1_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_1_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 199602 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_1_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 199613 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_1_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 199625 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_1_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 199636 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_2_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_2_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_2_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_2_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 199647 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_2_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 199658 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_2_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 199670 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_2_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 199681 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_3_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_3_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_3_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_3_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 199692 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_3_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 199703 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_3_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 199715 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_3_GET SPIO_NOC_ROUTER_1_8_8_P5_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 199726 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_1_8_8_p6_rperrm router_1_8_8_p6_rperrm SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_ADDRESS SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_OFFSET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 199985 R1_8 register p6_rperrm 0x5C128 R/W 0x00000000 Spio_noc_router_1_8_8_p6_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 199749 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 199760 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 199771 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 199782 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_CR_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_CR_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_CR_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_CR_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_CR_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 199793 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 199804 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_0_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_0_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_0_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_0_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 199815 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_0_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 199826 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_0_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 199838 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_0_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 199849 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_1_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_1_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_1_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_1_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 199860 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_1_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 199871 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_1_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 199883 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_1_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 199894 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_2_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_2_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_2_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_2_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 199905 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_2_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 199916 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_2_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 199928 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_2_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 199939 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_3_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_3_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_3_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_3_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 199950 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_3_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 199961 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_3_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 199973 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_3_GET SPIO_NOC_ROUTER_1_8_8_P6_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 199984 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_1_8_8_p7_rperrm router_1_8_8_p7_rperrm SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_ADDRESS SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_OFFSET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 200243 R1_8 register p7_rperrm 0x5C130 R/W 0x00000000 Spio_noc_router_1_8_8_p7_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 200007 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 200018 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 200029 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 200040 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_CR_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_CR_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_CR_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_CR_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_CR_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 200051 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 200062 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_0_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_0_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_0_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_0_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 200073 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_0_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 200084 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_0_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 200096 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_0_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 200107 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_1_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_1_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_1_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_1_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 200118 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_1_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 200129 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_1_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 200141 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_1_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 200152 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_2_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_2_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_2_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_2_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 200163 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_2_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 200174 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_2_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 200186 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_2_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 200197 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_3_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_3_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_3_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_3_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 200208 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_3_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 200219 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_3_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 200231 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_3_GET SPIO_NOC_ROUTER_1_8_8_P7_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 200242 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_1_8_8_roecc router_1_8_8_roecc SPIO_NOC_ROUTER_1_8_8_ROECC_ADDRESS SPIO_NOC_ROUTER_1_8_8_ROECC_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_ROECC_OFFSET SPIO_NOC_ROUTER_1_8_8_ROECC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 200316 R1_8 register roecc 0x5C138 R/W 0x00000000 Spio_noc_router_1_8_8_roecc This register is used to select which hardware events will increment the output event counter. false false false false OVC SPIO_NOC_ROUTER_1_8_8_ROECC_OVC_WIDTH SPIO_NOC_ROUTER_1_8_8_ROECC_OVC_MSB SPIO_NOC_ROUTER_1_8_8_ROECC_OVC_LSB SPIO_NOC_ROUTER_1_8_8_ROECC_OVC_RANGE SPIO_NOC_ROUTER_1_8_8_ROECC_OVC_RESET SPIO_NOC_ROUTER_1_8_8_ROECC_OVC_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROECC_OVC_GET SPIO_NOC_ROUTER_1_8_8_ROECC_OVC_SET ns_noc_io_spio_soc_ip.csr 200261 OVC Bit map to select output VCs to monitor events on 3 0 0x0 R/W OP SPIO_NOC_ROUTER_1_8_8_ROECC_OP_WIDTH SPIO_NOC_ROUTER_1_8_8_ROECC_OP_MSB SPIO_NOC_ROUTER_1_8_8_ROECC_OP_LSB SPIO_NOC_ROUTER_1_8_8_ROECC_OP_RANGE SPIO_NOC_ROUTER_1_8_8_ROECC_OP_RESET SPIO_NOC_ROUTER_1_8_8_ROECC_OP_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROECC_OP_GET SPIO_NOC_ROUTER_1_8_8_ROECC_OP_SET ns_noc_io_spio_soc_ip.csr 200272 OP Output port on which the event is captured 6 4 0x0 R/W UNSD_7_7 SPIO_NOC_ROUTER_1_8_8_ROECC_UNSD_7_7_WIDTH SPIO_NOC_ROUTER_1_8_8_ROECC_UNSD_7_7_MSB SPIO_NOC_ROUTER_1_8_8_ROECC_UNSD_7_7_LSB SPIO_NOC_ROUTER_1_8_8_ROECC_UNSD_7_7_RANGE SPIO_NOC_ROUTER_1_8_8_ROECC_UNSD_7_7_RESET SPIO_NOC_ROUTER_1_8_8_ROECC_UNSD_7_7_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROECC_UNSD_7_7_GET SPIO_NOC_ROUTER_1_8_8_ROECC_UNSD_7_7_SET ns_noc_io_spio_soc_ip.csr 200283 UNSD_7_7 7 7 0x0 R EVT SPIO_NOC_ROUTER_1_8_8_ROECC_EVT_WIDTH SPIO_NOC_ROUTER_1_8_8_ROECC_EVT_MSB SPIO_NOC_ROUTER_1_8_8_ROECC_EVT_LSB SPIO_NOC_ROUTER_1_8_8_ROECC_EVT_RANGE SPIO_NOC_ROUTER_1_8_8_ROECC_EVT_RESET SPIO_NOC_ROUTER_1_8_8_ROECC_EVT_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROECC_EVT_GET SPIO_NOC_ROUTER_1_8_8_ROECC_EVT_SET ns_noc_io_spio_soc_ip.csr 200304 EVT 100: Port stalled. Input flits are available for the port, but no output VC has credit 011: Generates count event when flits are available to be sent to output VC, but the VC has no credit 010: Generates count event on every flit sent on the selected output port and selected outpt VCs, this can be used to count total flits sent on a router output port 001: Generates count event on every EOP sent on the selected output port and selected output VCs, this can be used to count packets sent on a router output port 000: Disable 10 8 0x0 R/W UNSD_31_11 SPIO_NOC_ROUTER_1_8_8_ROECC_UNSD_31_11_WIDTH SPIO_NOC_ROUTER_1_8_8_ROECC_UNSD_31_11_MSB SPIO_NOC_ROUTER_1_8_8_ROECC_UNSD_31_11_LSB SPIO_NOC_ROUTER_1_8_8_ROECC_UNSD_31_11_RANGE SPIO_NOC_ROUTER_1_8_8_ROECC_UNSD_31_11_RESET SPIO_NOC_ROUTER_1_8_8_ROECC_UNSD_31_11_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROECC_UNSD_31_11_GET SPIO_NOC_ROUTER_1_8_8_ROECC_UNSD_31_11_SET ns_noc_io_spio_soc_ip.csr 200315 UNSD_31_11 31 11 0x000000 R register spio_noc.router_1_8_8_roec router_1_8_8_roec SPIO_NOC_ROUTER_1_8_8_ROEC_ADDRESS SPIO_NOC_ROUTER_1_8_8_ROEC_BYTE_ADDRESS SPIO_NOC_ROUTER_1_8_8_ROEC_OFFSET SPIO_NOC_ROUTER_1_8_8_ROEC_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 200341 R1_8 register roec 0x5C140 R/W 0x00000000 Spio_noc_router_1_8_8_roec This register holds the output event counter. The value can be read to determine the current count value. The value can be written to initialize the counter. When events trigger a count, the counter will increment. When the counter increments at its highest value, it will roll over to zero and the overflow will mark the Router output Event Interrupt Status register, which could trigger an interrupt. false false false false EVENT_CNTR SPIO_NOC_ROUTER_1_8_8_ROEC_EVENT_CNTR_WIDTH SPIO_NOC_ROUTER_1_8_8_ROEC_EVENT_CNTR_MSB SPIO_NOC_ROUTER_1_8_8_ROEC_EVENT_CNTR_LSB SPIO_NOC_ROUTER_1_8_8_ROEC_EVENT_CNTR_RANGE SPIO_NOC_ROUTER_1_8_8_ROEC_EVENT_CNTR_RESET SPIO_NOC_ROUTER_1_8_8_ROEC_EVENT_CNTR_FIELD_MASK SPIO_NOC_ROUTER_1_8_8_ROEC_EVENT_CNTR_GET SPIO_NOC_ROUTER_1_8_8_ROEC_EVENT_CNTR_SET ns_noc_io_spio_soc_ip.csr 200340 EVENT_CNTR 32'bit event incrementing counter. Rollover from 32'hFFFFF -> 32'd0 sets the rollover status bit RE 31 0 0x00000000 R/W register spio_noc.router_2_1_1_re router_2_1_1_re SPIO_NOC_ROUTER_2_1_1_RE_ADDRESS SPIO_NOC_ROUTER_2_1_1_RE_BYTE_ADDRESS SPIO_NOC_ROUTER_2_1_1_RE_OFFSET SPIO_NOC_ROUTER_2_1_1_RE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 200515 R2_1 register re 0x60080 R/W 0x00000000 Spio_noc_router_2_1_1_re This register tracks the interrupt or error events that can occur in the router. The only interrupt event is the event counter overflow. This register is readable, and can be cleared by performing a write with the write data bits set to 0 for the bits that should be cleared. false false false false OVFI SPIO_NOC_ROUTER_2_1_1_RE_OVFI_WIDTH SPIO_NOC_ROUTER_2_1_1_RE_OVFI_MSB SPIO_NOC_ROUTER_2_1_1_RE_OVFI_LSB SPIO_NOC_ROUTER_2_1_1_RE_OVFI_RANGE SPIO_NOC_ROUTER_2_1_1_RE_OVFI_RESET SPIO_NOC_ROUTER_2_1_1_RE_OVFI_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_RE_OVFI_GET SPIO_NOC_ROUTER_2_1_1_RE_OVFI_SET ns_noc_io_spio_soc_ip.csr 200367 OVFI 1'b1: In this status bit indicates that the router input event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 0 0 0x0 R/W CSR_PARERR SPIO_NOC_ROUTER_2_1_1_RE_CSR_PARERR_WIDTH SPIO_NOC_ROUTER_2_1_1_RE_CSR_PARERR_MSB SPIO_NOC_ROUTER_2_1_1_RE_CSR_PARERR_LSB SPIO_NOC_ROUTER_2_1_1_RE_CSR_PARERR_RANGE SPIO_NOC_ROUTER_2_1_1_RE_CSR_PARERR_RESET SPIO_NOC_ROUTER_2_1_1_RE_CSR_PARERR_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_RE_CSR_PARERR_GET SPIO_NOC_ROUTER_2_1_1_RE_CSR_PARERR_SET ns_noc_io_spio_soc_ip.csr 200378 CSR_PARERR 1'b1: Parity error in config/status registers 1 1 0x0 R/W OVFO SPIO_NOC_ROUTER_2_1_1_RE_OVFO_WIDTH SPIO_NOC_ROUTER_2_1_1_RE_OVFO_MSB SPIO_NOC_ROUTER_2_1_1_RE_OVFO_LSB SPIO_NOC_ROUTER_2_1_1_RE_OVFO_RANGE SPIO_NOC_ROUTER_2_1_1_RE_OVFO_RESET SPIO_NOC_ROUTER_2_1_1_RE_OVFO_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_RE_OVFO_GET SPIO_NOC_ROUTER_2_1_1_RE_OVFO_SET ns_noc_io_spio_soc_ip.csr 200392 OVFO 1'b1: In this status bit indicates that the router output event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 2 2 0x0 R/W UNSD_7_3 SPIO_NOC_ROUTER_2_1_1_RE_UNSD_7_3_WIDTH SPIO_NOC_ROUTER_2_1_1_RE_UNSD_7_3_MSB SPIO_NOC_ROUTER_2_1_1_RE_UNSD_7_3_LSB SPIO_NOC_ROUTER_2_1_1_RE_UNSD_7_3_RANGE SPIO_NOC_ROUTER_2_1_1_RE_UNSD_7_3_RESET SPIO_NOC_ROUTER_2_1_1_RE_UNSD_7_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_RE_UNSD_7_3_GET SPIO_NOC_ROUTER_2_1_1_RE_UNSD_7_3_SET ns_noc_io_spio_soc_ip.csr 200403 UNSD_7_3 7 3 0x00 R PGE SPIO_NOC_ROUTER_2_1_1_RE_PGE_WIDTH SPIO_NOC_ROUTER_2_1_1_RE_PGE_MSB SPIO_NOC_ROUTER_2_1_1_RE_PGE_LSB SPIO_NOC_ROUTER_2_1_1_RE_PGE_RANGE SPIO_NOC_ROUTER_2_1_1_RE_PGE_RESET SPIO_NOC_ROUTER_2_1_1_RE_PGE_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_RE_PGE_GET SPIO_NOC_ROUTER_2_1_1_RE_PGE_SET ns_noc_io_spio_soc_ip.csr 200415 PGE 1'b1: Power gating error, traffic received after router commited to power down 8 8 0x0 R/W NLU SPIO_NOC_ROUTER_2_1_1_RE_NLU_WIDTH SPIO_NOC_ROUTER_2_1_1_RE_NLU_MSB SPIO_NOC_ROUTER_2_1_1_RE_NLU_LSB SPIO_NOC_ROUTER_2_1_1_RE_NLU_RANGE SPIO_NOC_ROUTER_2_1_1_RE_NLU_RESET SPIO_NOC_ROUTER_2_1_1_RE_NLU_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_RE_NLU_GET SPIO_NOC_ROUTER_2_1_1_RE_NLU_SET ns_noc_io_spio_soc_ip.csr 200426 NLU 1'b1: Traffic destined for North link which is unavailable 9 9 0x0 R/W ELU SPIO_NOC_ROUTER_2_1_1_RE_ELU_WIDTH SPIO_NOC_ROUTER_2_1_1_RE_ELU_MSB SPIO_NOC_ROUTER_2_1_1_RE_ELU_LSB SPIO_NOC_ROUTER_2_1_1_RE_ELU_RANGE SPIO_NOC_ROUTER_2_1_1_RE_ELU_RESET SPIO_NOC_ROUTER_2_1_1_RE_ELU_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_RE_ELU_GET SPIO_NOC_ROUTER_2_1_1_RE_ELU_SET ns_noc_io_spio_soc_ip.csr 200437 ELU 1'b1: Traffic destined for East link which is unavailable 10 10 0x0 R/W WLU SPIO_NOC_ROUTER_2_1_1_RE_WLU_WIDTH SPIO_NOC_ROUTER_2_1_1_RE_WLU_MSB SPIO_NOC_ROUTER_2_1_1_RE_WLU_LSB SPIO_NOC_ROUTER_2_1_1_RE_WLU_RANGE SPIO_NOC_ROUTER_2_1_1_RE_WLU_RESET SPIO_NOC_ROUTER_2_1_1_RE_WLU_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_RE_WLU_GET SPIO_NOC_ROUTER_2_1_1_RE_WLU_SET ns_noc_io_spio_soc_ip.csr 200448 WLU 1'b1: Traffic destined for West link which is unavailable 11 11 0x0 R/W SLU SPIO_NOC_ROUTER_2_1_1_RE_SLU_WIDTH SPIO_NOC_ROUTER_2_1_1_RE_SLU_MSB SPIO_NOC_ROUTER_2_1_1_RE_SLU_LSB SPIO_NOC_ROUTER_2_1_1_RE_SLU_RANGE SPIO_NOC_ROUTER_2_1_1_RE_SLU_RESET SPIO_NOC_ROUTER_2_1_1_RE_SLU_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_RE_SLU_GET SPIO_NOC_ROUTER_2_1_1_RE_SLU_SET ns_noc_io_spio_soc_ip.csr 200459 SLU 1'b1: Traffic destined for South link which is unavailable 12 12 0x0 R/W HLU SPIO_NOC_ROUTER_2_1_1_RE_HLU_WIDTH SPIO_NOC_ROUTER_2_1_1_RE_HLU_MSB SPIO_NOC_ROUTER_2_1_1_RE_HLU_LSB SPIO_NOC_ROUTER_2_1_1_RE_HLU_RANGE SPIO_NOC_ROUTER_2_1_1_RE_HLU_RESET SPIO_NOC_ROUTER_2_1_1_RE_HLU_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_RE_HLU_GET SPIO_NOC_ROUTER_2_1_1_RE_HLU_SET ns_noc_io_spio_soc_ip.csr 200470 HLU 1'b1: Traffic destined for H link which is unavailable 13 13 0x0 R/W ILU SPIO_NOC_ROUTER_2_1_1_RE_ILU_WIDTH SPIO_NOC_ROUTER_2_1_1_RE_ILU_MSB SPIO_NOC_ROUTER_2_1_1_RE_ILU_LSB SPIO_NOC_ROUTER_2_1_1_RE_ILU_RANGE SPIO_NOC_ROUTER_2_1_1_RE_ILU_RESET SPIO_NOC_ROUTER_2_1_1_RE_ILU_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_RE_ILU_GET SPIO_NOC_ROUTER_2_1_1_RE_ILU_SET ns_noc_io_spio_soc_ip.csr 200481 ILU 1'b1: Traffic destined for I link which is unavailable 14 14 0x0 R/W JLU SPIO_NOC_ROUTER_2_1_1_RE_JLU_WIDTH SPIO_NOC_ROUTER_2_1_1_RE_JLU_MSB SPIO_NOC_ROUTER_2_1_1_RE_JLU_LSB SPIO_NOC_ROUTER_2_1_1_RE_JLU_RANGE SPIO_NOC_ROUTER_2_1_1_RE_JLU_RESET SPIO_NOC_ROUTER_2_1_1_RE_JLU_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_RE_JLU_GET SPIO_NOC_ROUTER_2_1_1_RE_JLU_SET ns_noc_io_spio_soc_ip.csr 200492 JLU 1'b1: Traffic destined for J link which is unavailable 15 15 0x0 R/W KLU SPIO_NOC_ROUTER_2_1_1_RE_KLU_WIDTH SPIO_NOC_ROUTER_2_1_1_RE_KLU_MSB SPIO_NOC_ROUTER_2_1_1_RE_KLU_LSB SPIO_NOC_ROUTER_2_1_1_RE_KLU_RANGE SPIO_NOC_ROUTER_2_1_1_RE_KLU_RESET SPIO_NOC_ROUTER_2_1_1_RE_KLU_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_RE_KLU_GET SPIO_NOC_ROUTER_2_1_1_RE_KLU_SET ns_noc_io_spio_soc_ip.csr 200503 KLU 1'b1: Traffic destined for K link which is unavailable 16 16 0x0 R/W UNSD_31_14 SPIO_NOC_ROUTER_2_1_1_RE_UNSD_31_14_WIDTH SPIO_NOC_ROUTER_2_1_1_RE_UNSD_31_14_MSB SPIO_NOC_ROUTER_2_1_1_RE_UNSD_31_14_LSB SPIO_NOC_ROUTER_2_1_1_RE_UNSD_31_14_RANGE SPIO_NOC_ROUTER_2_1_1_RE_UNSD_31_14_RESET SPIO_NOC_ROUTER_2_1_1_RE_UNSD_31_14_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_RE_UNSD_31_14_GET SPIO_NOC_ROUTER_2_1_1_RE_UNSD_31_14_SET ns_noc_io_spio_soc_ip.csr 200514 UNSD_31_14 31 17 0x0000 R register spio_noc.router_2_1_1_rem router_2_1_1_rem SPIO_NOC_ROUTER_2_1_1_REM_ADDRESS SPIO_NOC_ROUTER_2_1_1_REM_BYTE_ADDRESS SPIO_NOC_ROUTER_2_1_1_REM_OFFSET SPIO_NOC_ROUTER_2_1_1_REM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 200688 R2_1 register rem 0x60088 R/W 0x0001fe00 Spio_noc_router_2_1_1_rem This register is used to select whether the interrupt events in the Router Event Interrupt Status register should send an interrupt when asserted. If the corresponding bit is set to 1, an interrupt will not be sent. This register can be read and written to. false false false false OVFIM SPIO_NOC_ROUTER_2_1_1_REM_OVFIM_WIDTH SPIO_NOC_ROUTER_2_1_1_REM_OVFIM_MSB SPIO_NOC_ROUTER_2_1_1_REM_OVFIM_LSB SPIO_NOC_ROUTER_2_1_1_REM_OVFIM_RANGE SPIO_NOC_ROUTER_2_1_1_REM_OVFIM_RESET SPIO_NOC_ROUTER_2_1_1_REM_OVFIM_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_REM_OVFIM_GET SPIO_NOC_ROUTER_2_1_1_REM_OVFIM_SET ns_noc_io_spio_soc_ip.csr 200541 OVFIM 1'b1: Masks or disables an interrupt from being generated by the input event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 0 0 0x0 R/W CSR_PARERRM SPIO_NOC_ROUTER_2_1_1_REM_CSR_PARERRM_WIDTH SPIO_NOC_ROUTER_2_1_1_REM_CSR_PARERRM_MSB SPIO_NOC_ROUTER_2_1_1_REM_CSR_PARERRM_LSB SPIO_NOC_ROUTER_2_1_1_REM_CSR_PARERRM_RANGE SPIO_NOC_ROUTER_2_1_1_REM_CSR_PARERRM_RESET SPIO_NOC_ROUTER_2_1_1_REM_CSR_PARERRM_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_REM_CSR_PARERRM_GET SPIO_NOC_ROUTER_2_1_1_REM_CSR_PARERRM_SET ns_noc_io_spio_soc_ip.csr 200552 CSR_PARERRM 1'b1: Mask CSR parity error interrupt 1 1 0x0 R/W OVFOM SPIO_NOC_ROUTER_2_1_1_REM_OVFOM_WIDTH SPIO_NOC_ROUTER_2_1_1_REM_OVFOM_MSB SPIO_NOC_ROUTER_2_1_1_REM_OVFOM_LSB SPIO_NOC_ROUTER_2_1_1_REM_OVFOM_RANGE SPIO_NOC_ROUTER_2_1_1_REM_OVFOM_RESET SPIO_NOC_ROUTER_2_1_1_REM_OVFOM_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_REM_OVFOM_GET SPIO_NOC_ROUTER_2_1_1_REM_OVFOM_SET ns_noc_io_spio_soc_ip.csr 200566 OVFOM 1'b1: Masks or disables an interrupt from being generated by the output event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 2 2 0x0 R/W UNSD_7_3 SPIO_NOC_ROUTER_2_1_1_REM_UNSD_7_3_WIDTH SPIO_NOC_ROUTER_2_1_1_REM_UNSD_7_3_MSB SPIO_NOC_ROUTER_2_1_1_REM_UNSD_7_3_LSB SPIO_NOC_ROUTER_2_1_1_REM_UNSD_7_3_RANGE SPIO_NOC_ROUTER_2_1_1_REM_UNSD_7_3_RESET SPIO_NOC_ROUTER_2_1_1_REM_UNSD_7_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_REM_UNSD_7_3_GET SPIO_NOC_ROUTER_2_1_1_REM_UNSD_7_3_SET ns_noc_io_spio_soc_ip.csr 200577 UNSD_7_3 7 3 0x00 R PGM SPIO_NOC_ROUTER_2_1_1_REM_PGM_WIDTH SPIO_NOC_ROUTER_2_1_1_REM_PGM_MSB SPIO_NOC_ROUTER_2_1_1_REM_PGM_LSB SPIO_NOC_ROUTER_2_1_1_REM_PGM_RANGE SPIO_NOC_ROUTER_2_1_1_REM_PGM_RESET SPIO_NOC_ROUTER_2_1_1_REM_PGM_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_REM_PGM_GET SPIO_NOC_ROUTER_2_1_1_REM_PGM_SET ns_noc_io_spio_soc_ip.csr 200588 PGM 1'b1: Mask PGE error interrupt 8 8 0x0 R/W MN SPIO_NOC_ROUTER_2_1_1_REM_MN_WIDTH SPIO_NOC_ROUTER_2_1_1_REM_MN_MSB SPIO_NOC_ROUTER_2_1_1_REM_MN_LSB SPIO_NOC_ROUTER_2_1_1_REM_MN_RANGE SPIO_NOC_ROUTER_2_1_1_REM_MN_RESET SPIO_NOC_ROUTER_2_1_1_REM_MN_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_REM_MN_GET SPIO_NOC_ROUTER_2_1_1_REM_MN_SET ns_noc_io_spio_soc_ip.csr 200599 MN 1'b1: Mask NLU error interrupt 9 9 0x1 R/W ME SPIO_NOC_ROUTER_2_1_1_REM_ME_WIDTH SPIO_NOC_ROUTER_2_1_1_REM_ME_MSB SPIO_NOC_ROUTER_2_1_1_REM_ME_LSB SPIO_NOC_ROUTER_2_1_1_REM_ME_RANGE SPIO_NOC_ROUTER_2_1_1_REM_ME_RESET SPIO_NOC_ROUTER_2_1_1_REM_ME_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_REM_ME_GET SPIO_NOC_ROUTER_2_1_1_REM_ME_SET ns_noc_io_spio_soc_ip.csr 200610 ME 1'b1: Mask ELU error interrupt 10 10 0x1 R/W MW SPIO_NOC_ROUTER_2_1_1_REM_MW_WIDTH SPIO_NOC_ROUTER_2_1_1_REM_MW_MSB SPIO_NOC_ROUTER_2_1_1_REM_MW_LSB SPIO_NOC_ROUTER_2_1_1_REM_MW_RANGE SPIO_NOC_ROUTER_2_1_1_REM_MW_RESET SPIO_NOC_ROUTER_2_1_1_REM_MW_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_REM_MW_GET SPIO_NOC_ROUTER_2_1_1_REM_MW_SET ns_noc_io_spio_soc_ip.csr 200621 MW 1'b1: Mask WLU error interrupt 11 11 0x1 R/W MS SPIO_NOC_ROUTER_2_1_1_REM_MS_WIDTH SPIO_NOC_ROUTER_2_1_1_REM_MS_MSB SPIO_NOC_ROUTER_2_1_1_REM_MS_LSB SPIO_NOC_ROUTER_2_1_1_REM_MS_RANGE SPIO_NOC_ROUTER_2_1_1_REM_MS_RESET SPIO_NOC_ROUTER_2_1_1_REM_MS_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_REM_MS_GET SPIO_NOC_ROUTER_2_1_1_REM_MS_SET ns_noc_io_spio_soc_ip.csr 200632 MS 1'b1: Mask SLU error interrupt 12 12 0x1 R/W MH SPIO_NOC_ROUTER_2_1_1_REM_MH_WIDTH SPIO_NOC_ROUTER_2_1_1_REM_MH_MSB SPIO_NOC_ROUTER_2_1_1_REM_MH_LSB SPIO_NOC_ROUTER_2_1_1_REM_MH_RANGE SPIO_NOC_ROUTER_2_1_1_REM_MH_RESET SPIO_NOC_ROUTER_2_1_1_REM_MH_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_REM_MH_GET SPIO_NOC_ROUTER_2_1_1_REM_MH_SET ns_noc_io_spio_soc_ip.csr 200643 MH 1'b1: Mask HLU error interrupt 13 13 0x1 R/W MI SPIO_NOC_ROUTER_2_1_1_REM_MI_WIDTH SPIO_NOC_ROUTER_2_1_1_REM_MI_MSB SPIO_NOC_ROUTER_2_1_1_REM_MI_LSB SPIO_NOC_ROUTER_2_1_1_REM_MI_RANGE SPIO_NOC_ROUTER_2_1_1_REM_MI_RESET SPIO_NOC_ROUTER_2_1_1_REM_MI_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_REM_MI_GET SPIO_NOC_ROUTER_2_1_1_REM_MI_SET ns_noc_io_spio_soc_ip.csr 200654 MI 1'b1: Mask ILU error interrupt 14 14 0x1 R/W MJ SPIO_NOC_ROUTER_2_1_1_REM_MJ_WIDTH SPIO_NOC_ROUTER_2_1_1_REM_MJ_MSB SPIO_NOC_ROUTER_2_1_1_REM_MJ_LSB SPIO_NOC_ROUTER_2_1_1_REM_MJ_RANGE SPIO_NOC_ROUTER_2_1_1_REM_MJ_RESET SPIO_NOC_ROUTER_2_1_1_REM_MJ_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_REM_MJ_GET SPIO_NOC_ROUTER_2_1_1_REM_MJ_SET ns_noc_io_spio_soc_ip.csr 200665 MJ 1'b1: Mask JLU error interrupt 15 15 0x1 R/W MK SPIO_NOC_ROUTER_2_1_1_REM_MK_WIDTH SPIO_NOC_ROUTER_2_1_1_REM_MK_MSB SPIO_NOC_ROUTER_2_1_1_REM_MK_LSB SPIO_NOC_ROUTER_2_1_1_REM_MK_RANGE SPIO_NOC_ROUTER_2_1_1_REM_MK_RESET SPIO_NOC_ROUTER_2_1_1_REM_MK_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_REM_MK_GET SPIO_NOC_ROUTER_2_1_1_REM_MK_SET ns_noc_io_spio_soc_ip.csr 200676 MK 1'b1: Mask KLU error interrupt 16 16 0x1 R/W UNSD_31_14 SPIO_NOC_ROUTER_2_1_1_REM_UNSD_31_14_WIDTH SPIO_NOC_ROUTER_2_1_1_REM_UNSD_31_14_MSB SPIO_NOC_ROUTER_2_1_1_REM_UNSD_31_14_LSB SPIO_NOC_ROUTER_2_1_1_REM_UNSD_31_14_RANGE SPIO_NOC_ROUTER_2_1_1_REM_UNSD_31_14_RESET SPIO_NOC_ROUTER_2_1_1_REM_UNSD_31_14_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_REM_UNSD_31_14_GET SPIO_NOC_ROUTER_2_1_1_REM_UNSD_31_14_SET ns_noc_io_spio_soc_ip.csr 200687 UNSD_31_14 31 17 0x0000 R register spio_noc.router_2_1_1_id router_2_1_1_id SPIO_NOC_ROUTER_2_1_1_ID_ADDRESS SPIO_NOC_ROUTER_2_1_1_ID_BYTE_ADDRESS SPIO_NOC_ROUTER_2_1_1_ID_OFFSET SPIO_NOC_ROUTER_2_1_1_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 200757 R2_1 register id 0x600A0 R 0x01000022 Spio_noc_router_2_1_1_id This register holds layer and position information for the router. It is a read-only register. It can be used for debugging software access to the NoC elements by confirming that a read has successfully targeted the correct NoC element. false false false false LAYER SPIO_NOC_ROUTER_2_1_1_ID_LAYER_WIDTH SPIO_NOC_ROUTER_2_1_1_ID_LAYER_MSB SPIO_NOC_ROUTER_2_1_1_ID_LAYER_LSB SPIO_NOC_ROUTER_2_1_1_ID_LAYER_RANGE SPIO_NOC_ROUTER_2_1_1_ID_LAYER_RESET SPIO_NOC_ROUTER_2_1_1_ID_LAYER_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_ID_LAYER_GET SPIO_NOC_ROUTER_2_1_1_ID_LAYER_SET ns_noc_io_spio_soc_ip.csr 200713 LAYER 5-bit identifier of the NoC layer on which this router is located 4 0 0x02 R POS SPIO_NOC_ROUTER_2_1_1_ID_POS_WIDTH SPIO_NOC_ROUTER_2_1_1_ID_POS_MSB SPIO_NOC_ROUTER_2_1_1_ID_POS_LSB SPIO_NOC_ROUTER_2_1_1_ID_POS_RANGE SPIO_NOC_ROUTER_2_1_1_ID_POS_RESET SPIO_NOC_ROUTER_2_1_1_ID_POS_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_ID_POS_GET SPIO_NOC_ROUTER_2_1_1_ID_POS_SET ns_noc_io_spio_soc_ip.csr 200724 POS 16-bit position ID of this router in the NoC 20 5 0x0001 R ZERO SPIO_NOC_ROUTER_2_1_1_ID_ZERO_WIDTH SPIO_NOC_ROUTER_2_1_1_ID_ZERO_MSB SPIO_NOC_ROUTER_2_1_1_ID_ZERO_LSB SPIO_NOC_ROUTER_2_1_1_ID_ZERO_RANGE SPIO_NOC_ROUTER_2_1_1_ID_ZERO_RESET SPIO_NOC_ROUTER_2_1_1_ID_ZERO_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_ID_ZERO_GET SPIO_NOC_ROUTER_2_1_1_ID_ZERO_SET ns_noc_io_spio_soc_ip.csr 200735 ZERO Zeroes 23 21 0x0 R ONE SPIO_NOC_ROUTER_2_1_1_ID_ONE_WIDTH SPIO_NOC_ROUTER_2_1_1_ID_ONE_MSB SPIO_NOC_ROUTER_2_1_1_ID_ONE_LSB SPIO_NOC_ROUTER_2_1_1_ID_ONE_RANGE SPIO_NOC_ROUTER_2_1_1_ID_ONE_RESET SPIO_NOC_ROUTER_2_1_1_ID_ONE_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_ID_ONE_GET SPIO_NOC_ROUTER_2_1_1_ID_ONE_SET ns_noc_io_spio_soc_ip.csr 200746 ONE One 24 24 0x1 R UNSD_31_25 SPIO_NOC_ROUTER_2_1_1_ID_UNSD_31_25_WIDTH SPIO_NOC_ROUTER_2_1_1_ID_UNSD_31_25_MSB SPIO_NOC_ROUTER_2_1_1_ID_UNSD_31_25_LSB SPIO_NOC_ROUTER_2_1_1_ID_UNSD_31_25_RANGE SPIO_NOC_ROUTER_2_1_1_ID_UNSD_31_25_RESET SPIO_NOC_ROUTER_2_1_1_ID_UNSD_31_25_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_ID_UNSD_31_25_GET SPIO_NOC_ROUTER_2_1_1_ID_UNSD_31_25_SET ns_noc_io_spio_soc_ip.csr 200756 UNSD_31_25 31 25 0x00 R register spio_noc.router_2_1_1_rcgo router_2_1_1_rcgo SPIO_NOC_ROUTER_2_1_1_RCGO_ADDRESS SPIO_NOC_ROUTER_2_1_1_RCGO_BYTE_ADDRESS SPIO_NOC_ROUTER_2_1_1_RCGO_OFFSET SPIO_NOC_ROUTER_2_1_1_RCGO_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 200796 R2_1 register rcgo 0x600B0 R/W 0x00000000 Spio_noc_router_2_1_1_rcgo This register is used by coarse grained clock gating logic. This register can be set to override coarse clock gating for the entire router. Coarse clock gating for selective routers can be overridden by locally setting this register, if the user does not want incur and aggregate coarse clock gating cycle penalty over a "fast path/critical path" through the NoC. false false false false FPO SPIO_NOC_ROUTER_2_1_1_RCGO_FPO_WIDTH SPIO_NOC_ROUTER_2_1_1_RCGO_FPO_MSB SPIO_NOC_ROUTER_2_1_1_RCGO_FPO_LSB SPIO_NOC_ROUTER_2_1_1_RCGO_FPO_RANGE SPIO_NOC_ROUTER_2_1_1_RCGO_FPO_RESET SPIO_NOC_ROUTER_2_1_1_RCGO_FPO_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_RCGO_FPO_GET SPIO_NOC_ROUTER_2_1_1_RCGO_FPO_SET ns_noc_io_spio_soc_ip.csr 200784 FPO 1'b1: Coarse clock gating is locally disabled (for fast path) 1'b0: Coarse clock gating is locally enabled 0 0 0x0 R/W UNSD_31_1 SPIO_NOC_ROUTER_2_1_1_RCGO_UNSD_31_1_WIDTH SPIO_NOC_ROUTER_2_1_1_RCGO_UNSD_31_1_MSB SPIO_NOC_ROUTER_2_1_1_RCGO_UNSD_31_1_LSB SPIO_NOC_ROUTER_2_1_1_RCGO_UNSD_31_1_RANGE SPIO_NOC_ROUTER_2_1_1_RCGO_UNSD_31_1_RESET SPIO_NOC_ROUTER_2_1_1_RCGO_UNSD_31_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_RCGO_UNSD_31_1_GET SPIO_NOC_ROUTER_2_1_1_RCGO_UNSD_31_1_SET ns_noc_io_spio_soc_ip.csr 200795 UNSD_31_1 31 1 0x00000000 R register spio_noc.router_2_1_1_p1_rperr router_2_1_1_p1_rperr SPIO_NOC_ROUTER_2_1_1_P1_RPERR_ADDRESS SPIO_NOC_ROUTER_2_1_1_P1_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_2_1_1_P1_RPERR_OFFSET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 201087 R2_1 register p1_rperr 0x600C0 R/W 0x00000000 Spio_noc_router_2_1_1_p1_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 200839 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 200850 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 200861 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 200872 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_2_1_1_P1_RPERR_CR_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERR_CR_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_CR_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_CR_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERR_CR_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERR_CR_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 200883 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_2_1_1_P1_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 200894 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_0_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_0_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_0_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_0_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_0_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 200905 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_0_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_0_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_0_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_0_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 200916 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_0_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_0_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_0_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_0_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 200928 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_0_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_0_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_0_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_0_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 200939 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_1_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_1_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_1_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_1_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_1_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 200951 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_1_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_1_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_1_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_1_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 200963 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_1_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_1_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_1_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_1_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 200976 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_1_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_1_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_1_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_1_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 200988 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_2_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_2_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_2_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_2_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_2_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 201000 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_2_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_2_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_2_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_2_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 201012 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_2_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_2_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_2_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_2_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 201025 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_2_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_2_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_2_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_2_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 201037 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_3_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_3_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_3_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_3_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_3_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 201049 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_3_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_3_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_3_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_3_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 201061 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_3_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_3_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_3_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_3_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 201074 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_3_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_3_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_3_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_3_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 201086 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_2_1_1_p2_rperr router_2_1_1_p2_rperr SPIO_NOC_ROUTER_2_1_1_P2_RPERR_ADDRESS SPIO_NOC_ROUTER_2_1_1_P2_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_2_1_1_P2_RPERR_OFFSET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 201378 R2_1 register p2_rperr 0x600C8 R/W 0x00000000 Spio_noc_router_2_1_1_p2_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 201130 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 201141 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 201152 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 201163 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_2_1_1_P2_RPERR_CR_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERR_CR_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_CR_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_CR_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERR_CR_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERR_CR_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 201174 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_2_1_1_P2_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 201185 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_0_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_0_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_0_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_0_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_0_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 201196 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_0_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_0_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_0_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_0_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 201207 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_0_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_0_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_0_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_0_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 201219 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_0_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_0_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_0_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_0_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 201230 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_1_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_1_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_1_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_1_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_1_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 201242 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_1_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_1_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_1_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_1_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 201254 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_1_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_1_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_1_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_1_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 201267 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_1_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_1_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_1_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_1_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 201279 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_2_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_2_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_2_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_2_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_2_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 201291 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_2_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_2_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_2_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_2_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 201303 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_2_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_2_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_2_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_2_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 201316 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_2_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_2_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_2_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_2_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 201328 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_3_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_3_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_3_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_3_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_3_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 201340 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_3_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_3_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_3_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_3_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 201352 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_3_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_3_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_3_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_3_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 201365 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_3_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_3_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_3_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_3_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 201377 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_2_1_1_p3_rperr router_2_1_1_p3_rperr SPIO_NOC_ROUTER_2_1_1_P3_RPERR_ADDRESS SPIO_NOC_ROUTER_2_1_1_P3_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_2_1_1_P3_RPERR_OFFSET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 201669 R2_1 register p3_rperr 0x600D0 R/W 0x00000000 Spio_noc_router_2_1_1_p3_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 201421 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 201432 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 201443 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 201454 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_2_1_1_P3_RPERR_CR_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERR_CR_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_CR_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_CR_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERR_CR_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERR_CR_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 201465 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_2_1_1_P3_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 201476 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_0_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_0_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_0_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_0_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_0_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 201487 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_0_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_0_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_0_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_0_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 201498 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_0_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_0_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_0_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_0_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 201510 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_0_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_0_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_0_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_0_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 201521 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_1_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_1_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_1_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_1_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_1_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 201533 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_1_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_1_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_1_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_1_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 201545 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_1_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_1_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_1_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_1_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 201558 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_1_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_1_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_1_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_1_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 201570 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_2_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_2_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_2_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_2_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_2_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 201582 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_2_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_2_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_2_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_2_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 201594 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_2_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_2_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_2_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_2_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 201607 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_2_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_2_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_2_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_2_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 201619 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_3_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_3_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_3_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_3_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_3_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 201631 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_3_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_3_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_3_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_3_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 201643 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_3_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_3_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_3_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_3_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 201656 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_3_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_3_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_3_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_3_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 201668 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_2_1_1_p4_rperr router_2_1_1_p4_rperr SPIO_NOC_ROUTER_2_1_1_P4_RPERR_ADDRESS SPIO_NOC_ROUTER_2_1_1_P4_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_2_1_1_P4_RPERR_OFFSET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 201960 R2_1 register p4_rperr 0x600D8 R/W 0x00000000 Spio_noc_router_2_1_1_p4_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 201712 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 201723 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 201734 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 201745 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_2_1_1_P4_RPERR_CR_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERR_CR_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_CR_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_CR_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERR_CR_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERR_CR_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 201756 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_2_1_1_P4_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 201767 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_0_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_0_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_0_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_0_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_0_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 201778 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_0_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_0_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_0_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_0_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 201789 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_0_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_0_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_0_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_0_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 201801 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_0_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_0_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_0_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_0_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 201812 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_1_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_1_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_1_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_1_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_1_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 201824 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_1_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_1_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_1_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_1_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 201836 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_1_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_1_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_1_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_1_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 201849 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_1_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_1_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_1_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_1_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 201861 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_2_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_2_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_2_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_2_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_2_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 201873 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_2_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_2_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_2_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_2_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 201885 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_2_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_2_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_2_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_2_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 201898 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_2_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_2_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_2_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_2_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 201910 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_3_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_3_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_3_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_3_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_3_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 201922 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_3_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_3_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_3_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_3_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 201934 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_3_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_3_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_3_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_3_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 201947 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_3_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_3_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_3_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_3_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 201959 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_2_1_1_p1_rperrm router_2_1_1_p1_rperrm SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_ADDRESS SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_OFFSET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 202218 R2_1 register p1_rperrm 0x60100 R/W 0x00000000 Spio_noc_router_2_1_1_p1_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 201982 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 201993 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 202004 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 202015 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_CR_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_CR_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_CR_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_CR_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_CR_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 202026 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 202037 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_0_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_0_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_0_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_0_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 202048 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_0_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 202059 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_0_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 202071 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_0_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 202082 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_1_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_1_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_1_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_1_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 202093 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_1_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 202104 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_1_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 202116 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_1_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 202127 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_2_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_2_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_2_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_2_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 202138 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_2_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 202149 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_2_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 202161 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_2_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 202172 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_3_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_3_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_3_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_3_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 202183 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_3_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 202194 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_3_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 202206 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_3_GET SPIO_NOC_ROUTER_2_1_1_P1_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 202217 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_2_1_1_p2_rperrm router_2_1_1_p2_rperrm SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_ADDRESS SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_OFFSET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 202476 R2_1 register p2_rperrm 0x60108 R/W 0x00000000 Spio_noc_router_2_1_1_p2_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 202240 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 202251 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 202262 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 202273 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_CR_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_CR_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_CR_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_CR_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_CR_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 202284 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 202295 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_0_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_0_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_0_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_0_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 202306 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_0_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 202317 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_0_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 202329 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_0_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 202340 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_1_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_1_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_1_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_1_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 202351 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_1_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 202362 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_1_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 202374 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_1_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 202385 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_2_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_2_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_2_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_2_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 202396 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_2_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 202407 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_2_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 202419 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_2_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 202430 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_3_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_3_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_3_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_3_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 202441 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_3_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 202452 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_3_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 202464 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_3_GET SPIO_NOC_ROUTER_2_1_1_P2_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 202475 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_2_1_1_p3_rperrm router_2_1_1_p3_rperrm SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_ADDRESS SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_OFFSET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 202734 R2_1 register p3_rperrm 0x60110 R/W 0x00000000 Spio_noc_router_2_1_1_p3_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 202498 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 202509 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 202520 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 202531 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_CR_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_CR_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_CR_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_CR_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_CR_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 202542 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 202553 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_0_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_0_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_0_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_0_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 202564 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_0_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 202575 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_0_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 202587 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_0_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 202598 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_1_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_1_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_1_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_1_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 202609 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_1_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 202620 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_1_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 202632 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_1_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 202643 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_2_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_2_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_2_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_2_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 202654 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_2_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 202665 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_2_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 202677 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_2_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 202688 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_3_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_3_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_3_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_3_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 202699 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_3_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 202710 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_3_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 202722 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_3_GET SPIO_NOC_ROUTER_2_1_1_P3_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 202733 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_2_1_1_p4_rperrm router_2_1_1_p4_rperrm SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_ADDRESS SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_OFFSET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 202992 R2_1 register p4_rperrm 0x60118 R/W 0x00000000 Spio_noc_router_2_1_1_p4_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 202756 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 202767 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 202778 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 202789 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_CR_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_CR_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_CR_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_CR_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_CR_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 202800 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 202811 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_0_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_0_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_0_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_0_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 202822 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_0_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 202833 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_0_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 202845 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_0_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 202856 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_1_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_1_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_1_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_1_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 202867 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_1_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 202878 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_1_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 202890 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_1_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 202901 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_2_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_2_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_2_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_2_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 202912 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_2_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 202923 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_2_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 202935 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_2_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 202946 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_3_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_3_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_3_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_3_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 202957 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_3_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 202968 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_3_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 202980 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_3_GET SPIO_NOC_ROUTER_2_1_1_P4_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 202991 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_2_6_6_re router_2_6_6_re SPIO_NOC_ROUTER_2_6_6_RE_ADDRESS SPIO_NOC_ROUTER_2_6_6_RE_BYTE_ADDRESS SPIO_NOC_ROUTER_2_6_6_RE_OFFSET SPIO_NOC_ROUTER_2_6_6_RE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 203166 R2_6 register re 0x64080 R/W 0x00000000 Spio_noc_router_2_6_6_re This register tracks the interrupt or error events that can occur in the router. The only interrupt event is the event counter overflow. This register is readable, and can be cleared by performing a write with the write data bits set to 0 for the bits that should be cleared. false false false false OVFI SPIO_NOC_ROUTER_2_6_6_RE_OVFI_WIDTH SPIO_NOC_ROUTER_2_6_6_RE_OVFI_MSB SPIO_NOC_ROUTER_2_6_6_RE_OVFI_LSB SPIO_NOC_ROUTER_2_6_6_RE_OVFI_RANGE SPIO_NOC_ROUTER_2_6_6_RE_OVFI_RESET SPIO_NOC_ROUTER_2_6_6_RE_OVFI_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_RE_OVFI_GET SPIO_NOC_ROUTER_2_6_6_RE_OVFI_SET ns_noc_io_spio_soc_ip.csr 203018 OVFI 1'b1: In this status bit indicates that the router input event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 0 0 0x0 R/W CSR_PARERR SPIO_NOC_ROUTER_2_6_6_RE_CSR_PARERR_WIDTH SPIO_NOC_ROUTER_2_6_6_RE_CSR_PARERR_MSB SPIO_NOC_ROUTER_2_6_6_RE_CSR_PARERR_LSB SPIO_NOC_ROUTER_2_6_6_RE_CSR_PARERR_RANGE SPIO_NOC_ROUTER_2_6_6_RE_CSR_PARERR_RESET SPIO_NOC_ROUTER_2_6_6_RE_CSR_PARERR_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_RE_CSR_PARERR_GET SPIO_NOC_ROUTER_2_6_6_RE_CSR_PARERR_SET ns_noc_io_spio_soc_ip.csr 203029 CSR_PARERR 1'b1: Parity error in config/status registers 1 1 0x0 R/W OVFO SPIO_NOC_ROUTER_2_6_6_RE_OVFO_WIDTH SPIO_NOC_ROUTER_2_6_6_RE_OVFO_MSB SPIO_NOC_ROUTER_2_6_6_RE_OVFO_LSB SPIO_NOC_ROUTER_2_6_6_RE_OVFO_RANGE SPIO_NOC_ROUTER_2_6_6_RE_OVFO_RESET SPIO_NOC_ROUTER_2_6_6_RE_OVFO_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_RE_OVFO_GET SPIO_NOC_ROUTER_2_6_6_RE_OVFO_SET ns_noc_io_spio_soc_ip.csr 203043 OVFO 1'b1: In this status bit indicates that the router output event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 2 2 0x0 R/W UNSD_7_3 SPIO_NOC_ROUTER_2_6_6_RE_UNSD_7_3_WIDTH SPIO_NOC_ROUTER_2_6_6_RE_UNSD_7_3_MSB SPIO_NOC_ROUTER_2_6_6_RE_UNSD_7_3_LSB SPIO_NOC_ROUTER_2_6_6_RE_UNSD_7_3_RANGE SPIO_NOC_ROUTER_2_6_6_RE_UNSD_7_3_RESET SPIO_NOC_ROUTER_2_6_6_RE_UNSD_7_3_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_RE_UNSD_7_3_GET SPIO_NOC_ROUTER_2_6_6_RE_UNSD_7_3_SET ns_noc_io_spio_soc_ip.csr 203054 UNSD_7_3 7 3 0x00 R PGE SPIO_NOC_ROUTER_2_6_6_RE_PGE_WIDTH SPIO_NOC_ROUTER_2_6_6_RE_PGE_MSB SPIO_NOC_ROUTER_2_6_6_RE_PGE_LSB SPIO_NOC_ROUTER_2_6_6_RE_PGE_RANGE SPIO_NOC_ROUTER_2_6_6_RE_PGE_RESET SPIO_NOC_ROUTER_2_6_6_RE_PGE_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_RE_PGE_GET SPIO_NOC_ROUTER_2_6_6_RE_PGE_SET ns_noc_io_spio_soc_ip.csr 203066 PGE 1'b1: Power gating error, traffic received after router commited to power down 8 8 0x0 R/W NLU SPIO_NOC_ROUTER_2_6_6_RE_NLU_WIDTH SPIO_NOC_ROUTER_2_6_6_RE_NLU_MSB SPIO_NOC_ROUTER_2_6_6_RE_NLU_LSB SPIO_NOC_ROUTER_2_6_6_RE_NLU_RANGE SPIO_NOC_ROUTER_2_6_6_RE_NLU_RESET SPIO_NOC_ROUTER_2_6_6_RE_NLU_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_RE_NLU_GET SPIO_NOC_ROUTER_2_6_6_RE_NLU_SET ns_noc_io_spio_soc_ip.csr 203077 NLU 1'b1: Traffic destined for North link which is unavailable 9 9 0x0 R/W ELU SPIO_NOC_ROUTER_2_6_6_RE_ELU_WIDTH SPIO_NOC_ROUTER_2_6_6_RE_ELU_MSB SPIO_NOC_ROUTER_2_6_6_RE_ELU_LSB SPIO_NOC_ROUTER_2_6_6_RE_ELU_RANGE SPIO_NOC_ROUTER_2_6_6_RE_ELU_RESET SPIO_NOC_ROUTER_2_6_6_RE_ELU_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_RE_ELU_GET SPIO_NOC_ROUTER_2_6_6_RE_ELU_SET ns_noc_io_spio_soc_ip.csr 203088 ELU 1'b1: Traffic destined for East link which is unavailable 10 10 0x0 R/W WLU SPIO_NOC_ROUTER_2_6_6_RE_WLU_WIDTH SPIO_NOC_ROUTER_2_6_6_RE_WLU_MSB SPIO_NOC_ROUTER_2_6_6_RE_WLU_LSB SPIO_NOC_ROUTER_2_6_6_RE_WLU_RANGE SPIO_NOC_ROUTER_2_6_6_RE_WLU_RESET SPIO_NOC_ROUTER_2_6_6_RE_WLU_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_RE_WLU_GET SPIO_NOC_ROUTER_2_6_6_RE_WLU_SET ns_noc_io_spio_soc_ip.csr 203099 WLU 1'b1: Traffic destined for West link which is unavailable 11 11 0x0 R/W SLU SPIO_NOC_ROUTER_2_6_6_RE_SLU_WIDTH SPIO_NOC_ROUTER_2_6_6_RE_SLU_MSB SPIO_NOC_ROUTER_2_6_6_RE_SLU_LSB SPIO_NOC_ROUTER_2_6_6_RE_SLU_RANGE SPIO_NOC_ROUTER_2_6_6_RE_SLU_RESET SPIO_NOC_ROUTER_2_6_6_RE_SLU_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_RE_SLU_GET SPIO_NOC_ROUTER_2_6_6_RE_SLU_SET ns_noc_io_spio_soc_ip.csr 203110 SLU 1'b1: Traffic destined for South link which is unavailable 12 12 0x0 R/W HLU SPIO_NOC_ROUTER_2_6_6_RE_HLU_WIDTH SPIO_NOC_ROUTER_2_6_6_RE_HLU_MSB SPIO_NOC_ROUTER_2_6_6_RE_HLU_LSB SPIO_NOC_ROUTER_2_6_6_RE_HLU_RANGE SPIO_NOC_ROUTER_2_6_6_RE_HLU_RESET SPIO_NOC_ROUTER_2_6_6_RE_HLU_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_RE_HLU_GET SPIO_NOC_ROUTER_2_6_6_RE_HLU_SET ns_noc_io_spio_soc_ip.csr 203121 HLU 1'b1: Traffic destined for H link which is unavailable 13 13 0x0 R/W ILU SPIO_NOC_ROUTER_2_6_6_RE_ILU_WIDTH SPIO_NOC_ROUTER_2_6_6_RE_ILU_MSB SPIO_NOC_ROUTER_2_6_6_RE_ILU_LSB SPIO_NOC_ROUTER_2_6_6_RE_ILU_RANGE SPIO_NOC_ROUTER_2_6_6_RE_ILU_RESET SPIO_NOC_ROUTER_2_6_6_RE_ILU_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_RE_ILU_GET SPIO_NOC_ROUTER_2_6_6_RE_ILU_SET ns_noc_io_spio_soc_ip.csr 203132 ILU 1'b1: Traffic destined for I link which is unavailable 14 14 0x0 R/W JLU SPIO_NOC_ROUTER_2_6_6_RE_JLU_WIDTH SPIO_NOC_ROUTER_2_6_6_RE_JLU_MSB SPIO_NOC_ROUTER_2_6_6_RE_JLU_LSB SPIO_NOC_ROUTER_2_6_6_RE_JLU_RANGE SPIO_NOC_ROUTER_2_6_6_RE_JLU_RESET SPIO_NOC_ROUTER_2_6_6_RE_JLU_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_RE_JLU_GET SPIO_NOC_ROUTER_2_6_6_RE_JLU_SET ns_noc_io_spio_soc_ip.csr 203143 JLU 1'b1: Traffic destined for J link which is unavailable 15 15 0x0 R/W KLU SPIO_NOC_ROUTER_2_6_6_RE_KLU_WIDTH SPIO_NOC_ROUTER_2_6_6_RE_KLU_MSB SPIO_NOC_ROUTER_2_6_6_RE_KLU_LSB SPIO_NOC_ROUTER_2_6_6_RE_KLU_RANGE SPIO_NOC_ROUTER_2_6_6_RE_KLU_RESET SPIO_NOC_ROUTER_2_6_6_RE_KLU_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_RE_KLU_GET SPIO_NOC_ROUTER_2_6_6_RE_KLU_SET ns_noc_io_spio_soc_ip.csr 203154 KLU 1'b1: Traffic destined for K link which is unavailable 16 16 0x0 R/W UNSD_31_14 SPIO_NOC_ROUTER_2_6_6_RE_UNSD_31_14_WIDTH SPIO_NOC_ROUTER_2_6_6_RE_UNSD_31_14_MSB SPIO_NOC_ROUTER_2_6_6_RE_UNSD_31_14_LSB SPIO_NOC_ROUTER_2_6_6_RE_UNSD_31_14_RANGE SPIO_NOC_ROUTER_2_6_6_RE_UNSD_31_14_RESET SPIO_NOC_ROUTER_2_6_6_RE_UNSD_31_14_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_RE_UNSD_31_14_GET SPIO_NOC_ROUTER_2_6_6_RE_UNSD_31_14_SET ns_noc_io_spio_soc_ip.csr 203165 UNSD_31_14 31 17 0x0000 R register spio_noc.router_2_6_6_rem router_2_6_6_rem SPIO_NOC_ROUTER_2_6_6_REM_ADDRESS SPIO_NOC_ROUTER_2_6_6_REM_BYTE_ADDRESS SPIO_NOC_ROUTER_2_6_6_REM_OFFSET SPIO_NOC_ROUTER_2_6_6_REM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 203339 R2_6 register rem 0x64088 R/W 0x0001fe00 Spio_noc_router_2_6_6_rem This register is used to select whether the interrupt events in the Router Event Interrupt Status register should send an interrupt when asserted. If the corresponding bit is set to 1, an interrupt will not be sent. This register can be read and written to. false false false false OVFIM SPIO_NOC_ROUTER_2_6_6_REM_OVFIM_WIDTH SPIO_NOC_ROUTER_2_6_6_REM_OVFIM_MSB SPIO_NOC_ROUTER_2_6_6_REM_OVFIM_LSB SPIO_NOC_ROUTER_2_6_6_REM_OVFIM_RANGE SPIO_NOC_ROUTER_2_6_6_REM_OVFIM_RESET SPIO_NOC_ROUTER_2_6_6_REM_OVFIM_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_REM_OVFIM_GET SPIO_NOC_ROUTER_2_6_6_REM_OVFIM_SET ns_noc_io_spio_soc_ip.csr 203192 OVFIM 1'b1: Masks or disables an interrupt from being generated by the input event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 0 0 0x0 R/W CSR_PARERRM SPIO_NOC_ROUTER_2_6_6_REM_CSR_PARERRM_WIDTH SPIO_NOC_ROUTER_2_6_6_REM_CSR_PARERRM_MSB SPIO_NOC_ROUTER_2_6_6_REM_CSR_PARERRM_LSB SPIO_NOC_ROUTER_2_6_6_REM_CSR_PARERRM_RANGE SPIO_NOC_ROUTER_2_6_6_REM_CSR_PARERRM_RESET SPIO_NOC_ROUTER_2_6_6_REM_CSR_PARERRM_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_REM_CSR_PARERRM_GET SPIO_NOC_ROUTER_2_6_6_REM_CSR_PARERRM_SET ns_noc_io_spio_soc_ip.csr 203203 CSR_PARERRM 1'b1: Mask CSR parity error interrupt 1 1 0x0 R/W OVFOM SPIO_NOC_ROUTER_2_6_6_REM_OVFOM_WIDTH SPIO_NOC_ROUTER_2_6_6_REM_OVFOM_MSB SPIO_NOC_ROUTER_2_6_6_REM_OVFOM_LSB SPIO_NOC_ROUTER_2_6_6_REM_OVFOM_RANGE SPIO_NOC_ROUTER_2_6_6_REM_OVFOM_RESET SPIO_NOC_ROUTER_2_6_6_REM_OVFOM_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_REM_OVFOM_GET SPIO_NOC_ROUTER_2_6_6_REM_OVFOM_SET ns_noc_io_spio_soc_ip.csr 203217 OVFOM 1'b1: Masks or disables an interrupt from being generated by the output event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 2 2 0x0 R/W UNSD_7_3 SPIO_NOC_ROUTER_2_6_6_REM_UNSD_7_3_WIDTH SPIO_NOC_ROUTER_2_6_6_REM_UNSD_7_3_MSB SPIO_NOC_ROUTER_2_6_6_REM_UNSD_7_3_LSB SPIO_NOC_ROUTER_2_6_6_REM_UNSD_7_3_RANGE SPIO_NOC_ROUTER_2_6_6_REM_UNSD_7_3_RESET SPIO_NOC_ROUTER_2_6_6_REM_UNSD_7_3_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_REM_UNSD_7_3_GET SPIO_NOC_ROUTER_2_6_6_REM_UNSD_7_3_SET ns_noc_io_spio_soc_ip.csr 203228 UNSD_7_3 7 3 0x00 R PGM SPIO_NOC_ROUTER_2_6_6_REM_PGM_WIDTH SPIO_NOC_ROUTER_2_6_6_REM_PGM_MSB SPIO_NOC_ROUTER_2_6_6_REM_PGM_LSB SPIO_NOC_ROUTER_2_6_6_REM_PGM_RANGE SPIO_NOC_ROUTER_2_6_6_REM_PGM_RESET SPIO_NOC_ROUTER_2_6_6_REM_PGM_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_REM_PGM_GET SPIO_NOC_ROUTER_2_6_6_REM_PGM_SET ns_noc_io_spio_soc_ip.csr 203239 PGM 1'b1: Mask PGE error interrupt 8 8 0x0 R/W MN SPIO_NOC_ROUTER_2_6_6_REM_MN_WIDTH SPIO_NOC_ROUTER_2_6_6_REM_MN_MSB SPIO_NOC_ROUTER_2_6_6_REM_MN_LSB SPIO_NOC_ROUTER_2_6_6_REM_MN_RANGE SPIO_NOC_ROUTER_2_6_6_REM_MN_RESET SPIO_NOC_ROUTER_2_6_6_REM_MN_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_REM_MN_GET SPIO_NOC_ROUTER_2_6_6_REM_MN_SET ns_noc_io_spio_soc_ip.csr 203250 MN 1'b1: Mask NLU error interrupt 9 9 0x1 R/W ME SPIO_NOC_ROUTER_2_6_6_REM_ME_WIDTH SPIO_NOC_ROUTER_2_6_6_REM_ME_MSB SPIO_NOC_ROUTER_2_6_6_REM_ME_LSB SPIO_NOC_ROUTER_2_6_6_REM_ME_RANGE SPIO_NOC_ROUTER_2_6_6_REM_ME_RESET SPIO_NOC_ROUTER_2_6_6_REM_ME_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_REM_ME_GET SPIO_NOC_ROUTER_2_6_6_REM_ME_SET ns_noc_io_spio_soc_ip.csr 203261 ME 1'b1: Mask ELU error interrupt 10 10 0x1 R/W MW SPIO_NOC_ROUTER_2_6_6_REM_MW_WIDTH SPIO_NOC_ROUTER_2_6_6_REM_MW_MSB SPIO_NOC_ROUTER_2_6_6_REM_MW_LSB SPIO_NOC_ROUTER_2_6_6_REM_MW_RANGE SPIO_NOC_ROUTER_2_6_6_REM_MW_RESET SPIO_NOC_ROUTER_2_6_6_REM_MW_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_REM_MW_GET SPIO_NOC_ROUTER_2_6_6_REM_MW_SET ns_noc_io_spio_soc_ip.csr 203272 MW 1'b1: Mask WLU error interrupt 11 11 0x1 R/W MS SPIO_NOC_ROUTER_2_6_6_REM_MS_WIDTH SPIO_NOC_ROUTER_2_6_6_REM_MS_MSB SPIO_NOC_ROUTER_2_6_6_REM_MS_LSB SPIO_NOC_ROUTER_2_6_6_REM_MS_RANGE SPIO_NOC_ROUTER_2_6_6_REM_MS_RESET SPIO_NOC_ROUTER_2_6_6_REM_MS_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_REM_MS_GET SPIO_NOC_ROUTER_2_6_6_REM_MS_SET ns_noc_io_spio_soc_ip.csr 203283 MS 1'b1: Mask SLU error interrupt 12 12 0x1 R/W MH SPIO_NOC_ROUTER_2_6_6_REM_MH_WIDTH SPIO_NOC_ROUTER_2_6_6_REM_MH_MSB SPIO_NOC_ROUTER_2_6_6_REM_MH_LSB SPIO_NOC_ROUTER_2_6_6_REM_MH_RANGE SPIO_NOC_ROUTER_2_6_6_REM_MH_RESET SPIO_NOC_ROUTER_2_6_6_REM_MH_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_REM_MH_GET SPIO_NOC_ROUTER_2_6_6_REM_MH_SET ns_noc_io_spio_soc_ip.csr 203294 MH 1'b1: Mask HLU error interrupt 13 13 0x1 R/W MI SPIO_NOC_ROUTER_2_6_6_REM_MI_WIDTH SPIO_NOC_ROUTER_2_6_6_REM_MI_MSB SPIO_NOC_ROUTER_2_6_6_REM_MI_LSB SPIO_NOC_ROUTER_2_6_6_REM_MI_RANGE SPIO_NOC_ROUTER_2_6_6_REM_MI_RESET SPIO_NOC_ROUTER_2_6_6_REM_MI_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_REM_MI_GET SPIO_NOC_ROUTER_2_6_6_REM_MI_SET ns_noc_io_spio_soc_ip.csr 203305 MI 1'b1: Mask ILU error interrupt 14 14 0x1 R/W MJ SPIO_NOC_ROUTER_2_6_6_REM_MJ_WIDTH SPIO_NOC_ROUTER_2_6_6_REM_MJ_MSB SPIO_NOC_ROUTER_2_6_6_REM_MJ_LSB SPIO_NOC_ROUTER_2_6_6_REM_MJ_RANGE SPIO_NOC_ROUTER_2_6_6_REM_MJ_RESET SPIO_NOC_ROUTER_2_6_6_REM_MJ_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_REM_MJ_GET SPIO_NOC_ROUTER_2_6_6_REM_MJ_SET ns_noc_io_spio_soc_ip.csr 203316 MJ 1'b1: Mask JLU error interrupt 15 15 0x1 R/W MK SPIO_NOC_ROUTER_2_6_6_REM_MK_WIDTH SPIO_NOC_ROUTER_2_6_6_REM_MK_MSB SPIO_NOC_ROUTER_2_6_6_REM_MK_LSB SPIO_NOC_ROUTER_2_6_6_REM_MK_RANGE SPIO_NOC_ROUTER_2_6_6_REM_MK_RESET SPIO_NOC_ROUTER_2_6_6_REM_MK_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_REM_MK_GET SPIO_NOC_ROUTER_2_6_6_REM_MK_SET ns_noc_io_spio_soc_ip.csr 203327 MK 1'b1: Mask KLU error interrupt 16 16 0x1 R/W UNSD_31_14 SPIO_NOC_ROUTER_2_6_6_REM_UNSD_31_14_WIDTH SPIO_NOC_ROUTER_2_6_6_REM_UNSD_31_14_MSB SPIO_NOC_ROUTER_2_6_6_REM_UNSD_31_14_LSB SPIO_NOC_ROUTER_2_6_6_REM_UNSD_31_14_RANGE SPIO_NOC_ROUTER_2_6_6_REM_UNSD_31_14_RESET SPIO_NOC_ROUTER_2_6_6_REM_UNSD_31_14_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_REM_UNSD_31_14_GET SPIO_NOC_ROUTER_2_6_6_REM_UNSD_31_14_SET ns_noc_io_spio_soc_ip.csr 203338 UNSD_31_14 31 17 0x0000 R register spio_noc.router_2_6_6_id router_2_6_6_id SPIO_NOC_ROUTER_2_6_6_ID_ADDRESS SPIO_NOC_ROUTER_2_6_6_ID_BYTE_ADDRESS SPIO_NOC_ROUTER_2_6_6_ID_OFFSET SPIO_NOC_ROUTER_2_6_6_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 203408 R2_6 register id 0x640A0 R 0x010000a2 Spio_noc_router_2_6_6_id This register holds layer and position information for the router. It is a read-only register. It can be used for debugging software access to the NoC elements by confirming that a read has successfully targeted the correct NoC element. false false false false LAYER SPIO_NOC_ROUTER_2_6_6_ID_LAYER_WIDTH SPIO_NOC_ROUTER_2_6_6_ID_LAYER_MSB SPIO_NOC_ROUTER_2_6_6_ID_LAYER_LSB SPIO_NOC_ROUTER_2_6_6_ID_LAYER_RANGE SPIO_NOC_ROUTER_2_6_6_ID_LAYER_RESET SPIO_NOC_ROUTER_2_6_6_ID_LAYER_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_ID_LAYER_GET SPIO_NOC_ROUTER_2_6_6_ID_LAYER_SET ns_noc_io_spio_soc_ip.csr 203364 LAYER 5-bit identifier of the NoC layer on which this router is located 4 0 0x02 R POS SPIO_NOC_ROUTER_2_6_6_ID_POS_WIDTH SPIO_NOC_ROUTER_2_6_6_ID_POS_MSB SPIO_NOC_ROUTER_2_6_6_ID_POS_LSB SPIO_NOC_ROUTER_2_6_6_ID_POS_RANGE SPIO_NOC_ROUTER_2_6_6_ID_POS_RESET SPIO_NOC_ROUTER_2_6_6_ID_POS_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_ID_POS_GET SPIO_NOC_ROUTER_2_6_6_ID_POS_SET ns_noc_io_spio_soc_ip.csr 203375 POS 16-bit position ID of this router in the NoC 20 5 0x0005 R ZERO SPIO_NOC_ROUTER_2_6_6_ID_ZERO_WIDTH SPIO_NOC_ROUTER_2_6_6_ID_ZERO_MSB SPIO_NOC_ROUTER_2_6_6_ID_ZERO_LSB SPIO_NOC_ROUTER_2_6_6_ID_ZERO_RANGE SPIO_NOC_ROUTER_2_6_6_ID_ZERO_RESET SPIO_NOC_ROUTER_2_6_6_ID_ZERO_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_ID_ZERO_GET SPIO_NOC_ROUTER_2_6_6_ID_ZERO_SET ns_noc_io_spio_soc_ip.csr 203386 ZERO Zeroes 23 21 0x0 R ONE SPIO_NOC_ROUTER_2_6_6_ID_ONE_WIDTH SPIO_NOC_ROUTER_2_6_6_ID_ONE_MSB SPIO_NOC_ROUTER_2_6_6_ID_ONE_LSB SPIO_NOC_ROUTER_2_6_6_ID_ONE_RANGE SPIO_NOC_ROUTER_2_6_6_ID_ONE_RESET SPIO_NOC_ROUTER_2_6_6_ID_ONE_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_ID_ONE_GET SPIO_NOC_ROUTER_2_6_6_ID_ONE_SET ns_noc_io_spio_soc_ip.csr 203397 ONE One 24 24 0x1 R UNSD_31_25 SPIO_NOC_ROUTER_2_6_6_ID_UNSD_31_25_WIDTH SPIO_NOC_ROUTER_2_6_6_ID_UNSD_31_25_MSB SPIO_NOC_ROUTER_2_6_6_ID_UNSD_31_25_LSB SPIO_NOC_ROUTER_2_6_6_ID_UNSD_31_25_RANGE SPIO_NOC_ROUTER_2_6_6_ID_UNSD_31_25_RESET SPIO_NOC_ROUTER_2_6_6_ID_UNSD_31_25_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_ID_UNSD_31_25_GET SPIO_NOC_ROUTER_2_6_6_ID_UNSD_31_25_SET ns_noc_io_spio_soc_ip.csr 203407 UNSD_31_25 31 25 0x00 R register spio_noc.router_2_6_6_rcgo router_2_6_6_rcgo SPIO_NOC_ROUTER_2_6_6_RCGO_ADDRESS SPIO_NOC_ROUTER_2_6_6_RCGO_BYTE_ADDRESS SPIO_NOC_ROUTER_2_6_6_RCGO_OFFSET SPIO_NOC_ROUTER_2_6_6_RCGO_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 203447 R2_6 register rcgo 0x640B0 R/W 0x00000000 Spio_noc_router_2_6_6_rcgo This register is used by coarse grained clock gating logic. This register can be set to override coarse clock gating for the entire router. Coarse clock gating for selective routers can be overridden by locally setting this register, if the user does not want incur and aggregate coarse clock gating cycle penalty over a "fast path/critical path" through the NoC. false false false false FPO SPIO_NOC_ROUTER_2_6_6_RCGO_FPO_WIDTH SPIO_NOC_ROUTER_2_6_6_RCGO_FPO_MSB SPIO_NOC_ROUTER_2_6_6_RCGO_FPO_LSB SPIO_NOC_ROUTER_2_6_6_RCGO_FPO_RANGE SPIO_NOC_ROUTER_2_6_6_RCGO_FPO_RESET SPIO_NOC_ROUTER_2_6_6_RCGO_FPO_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_RCGO_FPO_GET SPIO_NOC_ROUTER_2_6_6_RCGO_FPO_SET ns_noc_io_spio_soc_ip.csr 203435 FPO 1'b1: Coarse clock gating is locally disabled (for fast path) 1'b0: Coarse clock gating is locally enabled 0 0 0x0 R/W UNSD_31_1 SPIO_NOC_ROUTER_2_6_6_RCGO_UNSD_31_1_WIDTH SPIO_NOC_ROUTER_2_6_6_RCGO_UNSD_31_1_MSB SPIO_NOC_ROUTER_2_6_6_RCGO_UNSD_31_1_LSB SPIO_NOC_ROUTER_2_6_6_RCGO_UNSD_31_1_RANGE SPIO_NOC_ROUTER_2_6_6_RCGO_UNSD_31_1_RESET SPIO_NOC_ROUTER_2_6_6_RCGO_UNSD_31_1_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_RCGO_UNSD_31_1_GET SPIO_NOC_ROUTER_2_6_6_RCGO_UNSD_31_1_SET ns_noc_io_spio_soc_ip.csr 203446 UNSD_31_1 31 1 0x00000000 R register spio_noc.router_2_6_6_p0_rperr router_2_6_6_p0_rperr SPIO_NOC_ROUTER_2_6_6_P0_RPERR_ADDRESS SPIO_NOC_ROUTER_2_6_6_P0_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_2_6_6_P0_RPERR_OFFSET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 203738 R2_6 register p0_rperr 0x640B8 R/W 0x00000000 Spio_noc_router_2_6_6_p0_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 203490 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 203501 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 203512 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 203523 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_2_6_6_P0_RPERR_CR_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERR_CR_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_CR_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_CR_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERR_CR_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERR_CR_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 203534 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_2_6_6_P0_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 203545 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_0_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_0_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_0_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_0_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_0_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 203556 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_0_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_0_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_0_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_0_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 203567 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_0_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_0_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_0_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_0_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 203579 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_0_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_0_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_0_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_0_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 203590 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_1_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_1_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_1_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_1_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_1_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 203602 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_1_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_1_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_1_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_1_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 203614 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_1_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_1_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_1_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_1_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 203627 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_1_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_1_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_1_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_1_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 203639 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_2_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_2_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_2_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_2_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_2_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 203651 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_2_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_2_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_2_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_2_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 203663 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_2_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_2_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_2_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_2_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 203676 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_2_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_2_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_2_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_2_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 203688 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_3_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_3_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_3_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_3_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_3_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 203700 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_3_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_3_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_3_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_3_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 203712 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_3_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_3_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_3_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_3_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 203725 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_3_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_3_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_3_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_3_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 203737 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_2_6_6_p1_rperr router_2_6_6_p1_rperr SPIO_NOC_ROUTER_2_6_6_P1_RPERR_ADDRESS SPIO_NOC_ROUTER_2_6_6_P1_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_2_6_6_P1_RPERR_OFFSET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 204029 R2_6 register p1_rperr 0x640C0 R/W 0x00000000 Spio_noc_router_2_6_6_p1_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 203781 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 203792 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 203803 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 203814 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_2_6_6_P1_RPERR_CR_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERR_CR_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_CR_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_CR_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERR_CR_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERR_CR_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 203825 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_2_6_6_P1_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 203836 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_0_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_0_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_0_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_0_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_0_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 203847 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_0_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_0_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_0_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_0_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 203858 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_0_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_0_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_0_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_0_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 203870 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_0_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_0_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_0_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_0_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 203881 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_1_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_1_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_1_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_1_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_1_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 203893 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_1_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_1_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_1_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_1_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 203905 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_1_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_1_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_1_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_1_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 203918 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_1_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_1_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_1_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_1_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 203930 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_2_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_2_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_2_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_2_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_2_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 203942 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_2_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_2_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_2_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_2_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 203954 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_2_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_2_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_2_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_2_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 203967 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_2_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_2_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_2_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_2_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 203979 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_3_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_3_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_3_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_3_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_3_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 203991 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_3_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_3_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_3_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_3_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 204003 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_3_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_3_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_3_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_3_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 204016 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_3_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_3_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_3_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_3_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 204028 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_2_6_6_p4_rperr router_2_6_6_p4_rperr SPIO_NOC_ROUTER_2_6_6_P4_RPERR_ADDRESS SPIO_NOC_ROUTER_2_6_6_P4_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_2_6_6_P4_RPERR_OFFSET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 204320 R2_6 register p4_rperr 0x640D8 R/W 0x00000000 Spio_noc_router_2_6_6_p4_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 204072 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 204083 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 204094 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 204105 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_2_6_6_P4_RPERR_CR_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERR_CR_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_CR_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_CR_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERR_CR_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERR_CR_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 204116 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_2_6_6_P4_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 204127 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_0_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_0_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_0_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_0_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_0_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 204138 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_0_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_0_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_0_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_0_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 204149 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_0_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_0_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_0_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_0_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 204161 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_0_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_0_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_0_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_0_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 204172 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_1_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_1_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_1_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_1_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_1_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 204184 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_1_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_1_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_1_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_1_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 204196 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_1_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_1_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_1_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_1_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 204209 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_1_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_1_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_1_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_1_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 204221 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_2_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_2_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_2_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_2_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_2_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 204233 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_2_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_2_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_2_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_2_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 204245 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_2_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_2_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_2_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_2_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 204258 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_2_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_2_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_2_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_2_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 204270 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_3_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_3_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_3_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_3_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_3_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 204282 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_3_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_3_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_3_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_3_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 204294 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_3_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_3_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_3_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_3_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 204307 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_3_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_3_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_3_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_3_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 204319 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_2_6_6_p0_rperrm router_2_6_6_p0_rperrm SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_ADDRESS SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_OFFSET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 204578 R2_6 register p0_rperrm 0x640F8 R/W 0x00000000 Spio_noc_router_2_6_6_p0_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 204342 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 204353 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 204364 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 204375 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_CR_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_CR_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_CR_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_CR_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_CR_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 204386 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 204397 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_0_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_0_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_0_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_0_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 204408 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_0_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 204419 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_0_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 204431 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_0_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 204442 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_1_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_1_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_1_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_1_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 204453 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_1_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 204464 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_1_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 204476 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_1_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 204487 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_2_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_2_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_2_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_2_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 204498 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_2_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 204509 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_2_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 204521 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_2_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 204532 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_3_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_3_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_3_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_3_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 204543 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_3_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 204554 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_3_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 204566 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_3_GET SPIO_NOC_ROUTER_2_6_6_P0_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 204577 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_2_6_6_p1_rperrm router_2_6_6_p1_rperrm SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_ADDRESS SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_OFFSET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 204836 R2_6 register p1_rperrm 0x64100 R/W 0x00000000 Spio_noc_router_2_6_6_p1_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 204600 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 204611 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 204622 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 204633 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_CR_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_CR_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_CR_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_CR_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_CR_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 204644 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 204655 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_0_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_0_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_0_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_0_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 204666 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_0_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 204677 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_0_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 204689 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_0_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 204700 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_1_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_1_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_1_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_1_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 204711 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_1_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 204722 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_1_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 204734 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_1_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 204745 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_2_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_2_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_2_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_2_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 204756 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_2_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 204767 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_2_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 204779 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_2_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 204790 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_3_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_3_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_3_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_3_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 204801 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_3_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 204812 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_3_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 204824 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_3_GET SPIO_NOC_ROUTER_2_6_6_P1_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 204835 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_2_6_6_p4_rperrm router_2_6_6_p4_rperrm SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_ADDRESS SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_OFFSET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 205094 R2_6 register p4_rperrm 0x64118 R/W 0x00000000 Spio_noc_router_2_6_6_p4_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 204858 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 204869 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 204880 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 204891 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_CR_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_CR_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_CR_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_CR_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_CR_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 204902 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 204913 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_0_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_0_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_0_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_0_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 204924 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_0_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 204935 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_0_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 204947 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_0_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 204958 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_1_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_1_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_1_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_1_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 204969 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_1_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 204980 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_1_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 204992 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_1_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 205003 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_2_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_2_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_2_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_2_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 205014 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_2_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 205025 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_2_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 205037 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_2_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 205048 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_3_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_3_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_3_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_3_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 205059 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_3_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 205070 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_3_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 205082 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_3_GET SPIO_NOC_ROUTER_2_6_6_P4_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 205093 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_2_7_7_re router_2_7_7_re SPIO_NOC_ROUTER_2_7_7_RE_ADDRESS SPIO_NOC_ROUTER_2_7_7_RE_BYTE_ADDRESS SPIO_NOC_ROUTER_2_7_7_RE_OFFSET SPIO_NOC_ROUTER_2_7_7_RE_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 205268 R2_7 register re 0x68080 R/W 0x00000000 Spio_noc_router_2_7_7_re This register tracks the interrupt or error events that can occur in the router. The only interrupt event is the event counter overflow. This register is readable, and can be cleared by performing a write with the write data bits set to 0 for the bits that should be cleared. false false false false OVFI SPIO_NOC_ROUTER_2_7_7_RE_OVFI_WIDTH SPIO_NOC_ROUTER_2_7_7_RE_OVFI_MSB SPIO_NOC_ROUTER_2_7_7_RE_OVFI_LSB SPIO_NOC_ROUTER_2_7_7_RE_OVFI_RANGE SPIO_NOC_ROUTER_2_7_7_RE_OVFI_RESET SPIO_NOC_ROUTER_2_7_7_RE_OVFI_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_RE_OVFI_GET SPIO_NOC_ROUTER_2_7_7_RE_OVFI_SET ns_noc_io_spio_soc_ip.csr 205120 OVFI 1'b1: In this status bit indicates that the router input event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 0 0 0x0 R/W CSR_PARERR SPIO_NOC_ROUTER_2_7_7_RE_CSR_PARERR_WIDTH SPIO_NOC_ROUTER_2_7_7_RE_CSR_PARERR_MSB SPIO_NOC_ROUTER_2_7_7_RE_CSR_PARERR_LSB SPIO_NOC_ROUTER_2_7_7_RE_CSR_PARERR_RANGE SPIO_NOC_ROUTER_2_7_7_RE_CSR_PARERR_RESET SPIO_NOC_ROUTER_2_7_7_RE_CSR_PARERR_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_RE_CSR_PARERR_GET SPIO_NOC_ROUTER_2_7_7_RE_CSR_PARERR_SET ns_noc_io_spio_soc_ip.csr 205131 CSR_PARERR 1'b1: Parity error in config/status registers 1 1 0x0 R/W OVFO SPIO_NOC_ROUTER_2_7_7_RE_OVFO_WIDTH SPIO_NOC_ROUTER_2_7_7_RE_OVFO_MSB SPIO_NOC_ROUTER_2_7_7_RE_OVFO_LSB SPIO_NOC_ROUTER_2_7_7_RE_OVFO_RANGE SPIO_NOC_ROUTER_2_7_7_RE_OVFO_RESET SPIO_NOC_ROUTER_2_7_7_RE_OVFO_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_RE_OVFO_GET SPIO_NOC_ROUTER_2_7_7_RE_OVFO_SET ns_noc_io_spio_soc_ip.csr 205145 OVFO 1'b1: In this status bit indicates that the router output event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 2 2 0x0 R/W UNSD_7_3 SPIO_NOC_ROUTER_2_7_7_RE_UNSD_7_3_WIDTH SPIO_NOC_ROUTER_2_7_7_RE_UNSD_7_3_MSB SPIO_NOC_ROUTER_2_7_7_RE_UNSD_7_3_LSB SPIO_NOC_ROUTER_2_7_7_RE_UNSD_7_3_RANGE SPIO_NOC_ROUTER_2_7_7_RE_UNSD_7_3_RESET SPIO_NOC_ROUTER_2_7_7_RE_UNSD_7_3_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_RE_UNSD_7_3_GET SPIO_NOC_ROUTER_2_7_7_RE_UNSD_7_3_SET ns_noc_io_spio_soc_ip.csr 205156 UNSD_7_3 7 3 0x00 R PGE SPIO_NOC_ROUTER_2_7_7_RE_PGE_WIDTH SPIO_NOC_ROUTER_2_7_7_RE_PGE_MSB SPIO_NOC_ROUTER_2_7_7_RE_PGE_LSB SPIO_NOC_ROUTER_2_7_7_RE_PGE_RANGE SPIO_NOC_ROUTER_2_7_7_RE_PGE_RESET SPIO_NOC_ROUTER_2_7_7_RE_PGE_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_RE_PGE_GET SPIO_NOC_ROUTER_2_7_7_RE_PGE_SET ns_noc_io_spio_soc_ip.csr 205168 PGE 1'b1: Power gating error, traffic received after router commited to power down 8 8 0x0 R/W NLU SPIO_NOC_ROUTER_2_7_7_RE_NLU_WIDTH SPIO_NOC_ROUTER_2_7_7_RE_NLU_MSB SPIO_NOC_ROUTER_2_7_7_RE_NLU_LSB SPIO_NOC_ROUTER_2_7_7_RE_NLU_RANGE SPIO_NOC_ROUTER_2_7_7_RE_NLU_RESET SPIO_NOC_ROUTER_2_7_7_RE_NLU_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_RE_NLU_GET SPIO_NOC_ROUTER_2_7_7_RE_NLU_SET ns_noc_io_spio_soc_ip.csr 205179 NLU 1'b1: Traffic destined for North link which is unavailable 9 9 0x0 R/W ELU SPIO_NOC_ROUTER_2_7_7_RE_ELU_WIDTH SPIO_NOC_ROUTER_2_7_7_RE_ELU_MSB SPIO_NOC_ROUTER_2_7_7_RE_ELU_LSB SPIO_NOC_ROUTER_2_7_7_RE_ELU_RANGE SPIO_NOC_ROUTER_2_7_7_RE_ELU_RESET SPIO_NOC_ROUTER_2_7_7_RE_ELU_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_RE_ELU_GET SPIO_NOC_ROUTER_2_7_7_RE_ELU_SET ns_noc_io_spio_soc_ip.csr 205190 ELU 1'b1: Traffic destined for East link which is unavailable 10 10 0x0 R/W WLU SPIO_NOC_ROUTER_2_7_7_RE_WLU_WIDTH SPIO_NOC_ROUTER_2_7_7_RE_WLU_MSB SPIO_NOC_ROUTER_2_7_7_RE_WLU_LSB SPIO_NOC_ROUTER_2_7_7_RE_WLU_RANGE SPIO_NOC_ROUTER_2_7_7_RE_WLU_RESET SPIO_NOC_ROUTER_2_7_7_RE_WLU_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_RE_WLU_GET SPIO_NOC_ROUTER_2_7_7_RE_WLU_SET ns_noc_io_spio_soc_ip.csr 205201 WLU 1'b1: Traffic destined for West link which is unavailable 11 11 0x0 R/W SLU SPIO_NOC_ROUTER_2_7_7_RE_SLU_WIDTH SPIO_NOC_ROUTER_2_7_7_RE_SLU_MSB SPIO_NOC_ROUTER_2_7_7_RE_SLU_LSB SPIO_NOC_ROUTER_2_7_7_RE_SLU_RANGE SPIO_NOC_ROUTER_2_7_7_RE_SLU_RESET SPIO_NOC_ROUTER_2_7_7_RE_SLU_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_RE_SLU_GET SPIO_NOC_ROUTER_2_7_7_RE_SLU_SET ns_noc_io_spio_soc_ip.csr 205212 SLU 1'b1: Traffic destined for South link which is unavailable 12 12 0x0 R/W HLU SPIO_NOC_ROUTER_2_7_7_RE_HLU_WIDTH SPIO_NOC_ROUTER_2_7_7_RE_HLU_MSB SPIO_NOC_ROUTER_2_7_7_RE_HLU_LSB SPIO_NOC_ROUTER_2_7_7_RE_HLU_RANGE SPIO_NOC_ROUTER_2_7_7_RE_HLU_RESET SPIO_NOC_ROUTER_2_7_7_RE_HLU_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_RE_HLU_GET SPIO_NOC_ROUTER_2_7_7_RE_HLU_SET ns_noc_io_spio_soc_ip.csr 205223 HLU 1'b1: Traffic destined for H link which is unavailable 13 13 0x0 R/W ILU SPIO_NOC_ROUTER_2_7_7_RE_ILU_WIDTH SPIO_NOC_ROUTER_2_7_7_RE_ILU_MSB SPIO_NOC_ROUTER_2_7_7_RE_ILU_LSB SPIO_NOC_ROUTER_2_7_7_RE_ILU_RANGE SPIO_NOC_ROUTER_2_7_7_RE_ILU_RESET SPIO_NOC_ROUTER_2_7_7_RE_ILU_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_RE_ILU_GET SPIO_NOC_ROUTER_2_7_7_RE_ILU_SET ns_noc_io_spio_soc_ip.csr 205234 ILU 1'b1: Traffic destined for I link which is unavailable 14 14 0x0 R/W JLU SPIO_NOC_ROUTER_2_7_7_RE_JLU_WIDTH SPIO_NOC_ROUTER_2_7_7_RE_JLU_MSB SPIO_NOC_ROUTER_2_7_7_RE_JLU_LSB SPIO_NOC_ROUTER_2_7_7_RE_JLU_RANGE SPIO_NOC_ROUTER_2_7_7_RE_JLU_RESET SPIO_NOC_ROUTER_2_7_7_RE_JLU_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_RE_JLU_GET SPIO_NOC_ROUTER_2_7_7_RE_JLU_SET ns_noc_io_spio_soc_ip.csr 205245 JLU 1'b1: Traffic destined for J link which is unavailable 15 15 0x0 R/W KLU SPIO_NOC_ROUTER_2_7_7_RE_KLU_WIDTH SPIO_NOC_ROUTER_2_7_7_RE_KLU_MSB SPIO_NOC_ROUTER_2_7_7_RE_KLU_LSB SPIO_NOC_ROUTER_2_7_7_RE_KLU_RANGE SPIO_NOC_ROUTER_2_7_7_RE_KLU_RESET SPIO_NOC_ROUTER_2_7_7_RE_KLU_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_RE_KLU_GET SPIO_NOC_ROUTER_2_7_7_RE_KLU_SET ns_noc_io_spio_soc_ip.csr 205256 KLU 1'b1: Traffic destined for K link which is unavailable 16 16 0x0 R/W UNSD_31_14 SPIO_NOC_ROUTER_2_7_7_RE_UNSD_31_14_WIDTH SPIO_NOC_ROUTER_2_7_7_RE_UNSD_31_14_MSB SPIO_NOC_ROUTER_2_7_7_RE_UNSD_31_14_LSB SPIO_NOC_ROUTER_2_7_7_RE_UNSD_31_14_RANGE SPIO_NOC_ROUTER_2_7_7_RE_UNSD_31_14_RESET SPIO_NOC_ROUTER_2_7_7_RE_UNSD_31_14_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_RE_UNSD_31_14_GET SPIO_NOC_ROUTER_2_7_7_RE_UNSD_31_14_SET ns_noc_io_spio_soc_ip.csr 205267 UNSD_31_14 31 17 0x0000 R register spio_noc.router_2_7_7_rem router_2_7_7_rem SPIO_NOC_ROUTER_2_7_7_REM_ADDRESS SPIO_NOC_ROUTER_2_7_7_REM_BYTE_ADDRESS SPIO_NOC_ROUTER_2_7_7_REM_OFFSET SPIO_NOC_ROUTER_2_7_7_REM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 205441 R2_7 register rem 0x68088 R/W 0x0001fe00 Spio_noc_router_2_7_7_rem This register is used to select whether the interrupt events in the Router Event Interrupt Status register should send an interrupt when asserted. If the corresponding bit is set to 1, an interrupt will not be sent. This register can be read and written to. false false false false OVFIM SPIO_NOC_ROUTER_2_7_7_REM_OVFIM_WIDTH SPIO_NOC_ROUTER_2_7_7_REM_OVFIM_MSB SPIO_NOC_ROUTER_2_7_7_REM_OVFIM_LSB SPIO_NOC_ROUTER_2_7_7_REM_OVFIM_RANGE SPIO_NOC_ROUTER_2_7_7_REM_OVFIM_RESET SPIO_NOC_ROUTER_2_7_7_REM_OVFIM_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_REM_OVFIM_GET SPIO_NOC_ROUTER_2_7_7_REM_OVFIM_SET ns_noc_io_spio_soc_ip.csr 205294 OVFIM 1'b1: Masks or disables an interrupt from being generated by the input event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 0 0 0x0 R/W CSR_PARERRM SPIO_NOC_ROUTER_2_7_7_REM_CSR_PARERRM_WIDTH SPIO_NOC_ROUTER_2_7_7_REM_CSR_PARERRM_MSB SPIO_NOC_ROUTER_2_7_7_REM_CSR_PARERRM_LSB SPIO_NOC_ROUTER_2_7_7_REM_CSR_PARERRM_RANGE SPIO_NOC_ROUTER_2_7_7_REM_CSR_PARERRM_RESET SPIO_NOC_ROUTER_2_7_7_REM_CSR_PARERRM_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_REM_CSR_PARERRM_GET SPIO_NOC_ROUTER_2_7_7_REM_CSR_PARERRM_SET ns_noc_io_spio_soc_ip.csr 205305 CSR_PARERRM 1'b1: Mask CSR parity error interrupt 1 1 0x0 R/W OVFOM SPIO_NOC_ROUTER_2_7_7_REM_OVFOM_WIDTH SPIO_NOC_ROUTER_2_7_7_REM_OVFOM_MSB SPIO_NOC_ROUTER_2_7_7_REM_OVFOM_LSB SPIO_NOC_ROUTER_2_7_7_REM_OVFOM_RANGE SPIO_NOC_ROUTER_2_7_7_REM_OVFOM_RESET SPIO_NOC_ROUTER_2_7_7_REM_OVFOM_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_REM_OVFOM_GET SPIO_NOC_ROUTER_2_7_7_REM_OVFOM_SET ns_noc_io_spio_soc_ip.csr 205319 OVFOM 1'b1: Masks or disables an interrupt from being generated by the output event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 2 2 0x0 R/W UNSD_7_3 SPIO_NOC_ROUTER_2_7_7_REM_UNSD_7_3_WIDTH SPIO_NOC_ROUTER_2_7_7_REM_UNSD_7_3_MSB SPIO_NOC_ROUTER_2_7_7_REM_UNSD_7_3_LSB SPIO_NOC_ROUTER_2_7_7_REM_UNSD_7_3_RANGE SPIO_NOC_ROUTER_2_7_7_REM_UNSD_7_3_RESET SPIO_NOC_ROUTER_2_7_7_REM_UNSD_7_3_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_REM_UNSD_7_3_GET SPIO_NOC_ROUTER_2_7_7_REM_UNSD_7_3_SET ns_noc_io_spio_soc_ip.csr 205330 UNSD_7_3 7 3 0x00 R PGM SPIO_NOC_ROUTER_2_7_7_REM_PGM_WIDTH SPIO_NOC_ROUTER_2_7_7_REM_PGM_MSB SPIO_NOC_ROUTER_2_7_7_REM_PGM_LSB SPIO_NOC_ROUTER_2_7_7_REM_PGM_RANGE SPIO_NOC_ROUTER_2_7_7_REM_PGM_RESET SPIO_NOC_ROUTER_2_7_7_REM_PGM_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_REM_PGM_GET SPIO_NOC_ROUTER_2_7_7_REM_PGM_SET ns_noc_io_spio_soc_ip.csr 205341 PGM 1'b1: Mask PGE error interrupt 8 8 0x0 R/W MN SPIO_NOC_ROUTER_2_7_7_REM_MN_WIDTH SPIO_NOC_ROUTER_2_7_7_REM_MN_MSB SPIO_NOC_ROUTER_2_7_7_REM_MN_LSB SPIO_NOC_ROUTER_2_7_7_REM_MN_RANGE SPIO_NOC_ROUTER_2_7_7_REM_MN_RESET SPIO_NOC_ROUTER_2_7_7_REM_MN_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_REM_MN_GET SPIO_NOC_ROUTER_2_7_7_REM_MN_SET ns_noc_io_spio_soc_ip.csr 205352 MN 1'b1: Mask NLU error interrupt 9 9 0x1 R/W ME SPIO_NOC_ROUTER_2_7_7_REM_ME_WIDTH SPIO_NOC_ROUTER_2_7_7_REM_ME_MSB SPIO_NOC_ROUTER_2_7_7_REM_ME_LSB SPIO_NOC_ROUTER_2_7_7_REM_ME_RANGE SPIO_NOC_ROUTER_2_7_7_REM_ME_RESET SPIO_NOC_ROUTER_2_7_7_REM_ME_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_REM_ME_GET SPIO_NOC_ROUTER_2_7_7_REM_ME_SET ns_noc_io_spio_soc_ip.csr 205363 ME 1'b1: Mask ELU error interrupt 10 10 0x1 R/W MW SPIO_NOC_ROUTER_2_7_7_REM_MW_WIDTH SPIO_NOC_ROUTER_2_7_7_REM_MW_MSB SPIO_NOC_ROUTER_2_7_7_REM_MW_LSB SPIO_NOC_ROUTER_2_7_7_REM_MW_RANGE SPIO_NOC_ROUTER_2_7_7_REM_MW_RESET SPIO_NOC_ROUTER_2_7_7_REM_MW_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_REM_MW_GET SPIO_NOC_ROUTER_2_7_7_REM_MW_SET ns_noc_io_spio_soc_ip.csr 205374 MW 1'b1: Mask WLU error interrupt 11 11 0x1 R/W MS SPIO_NOC_ROUTER_2_7_7_REM_MS_WIDTH SPIO_NOC_ROUTER_2_7_7_REM_MS_MSB SPIO_NOC_ROUTER_2_7_7_REM_MS_LSB SPIO_NOC_ROUTER_2_7_7_REM_MS_RANGE SPIO_NOC_ROUTER_2_7_7_REM_MS_RESET SPIO_NOC_ROUTER_2_7_7_REM_MS_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_REM_MS_GET SPIO_NOC_ROUTER_2_7_7_REM_MS_SET ns_noc_io_spio_soc_ip.csr 205385 MS 1'b1: Mask SLU error interrupt 12 12 0x1 R/W MH SPIO_NOC_ROUTER_2_7_7_REM_MH_WIDTH SPIO_NOC_ROUTER_2_7_7_REM_MH_MSB SPIO_NOC_ROUTER_2_7_7_REM_MH_LSB SPIO_NOC_ROUTER_2_7_7_REM_MH_RANGE SPIO_NOC_ROUTER_2_7_7_REM_MH_RESET SPIO_NOC_ROUTER_2_7_7_REM_MH_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_REM_MH_GET SPIO_NOC_ROUTER_2_7_7_REM_MH_SET ns_noc_io_spio_soc_ip.csr 205396 MH 1'b1: Mask HLU error interrupt 13 13 0x1 R/W MI SPIO_NOC_ROUTER_2_7_7_REM_MI_WIDTH SPIO_NOC_ROUTER_2_7_7_REM_MI_MSB SPIO_NOC_ROUTER_2_7_7_REM_MI_LSB SPIO_NOC_ROUTER_2_7_7_REM_MI_RANGE SPIO_NOC_ROUTER_2_7_7_REM_MI_RESET SPIO_NOC_ROUTER_2_7_7_REM_MI_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_REM_MI_GET SPIO_NOC_ROUTER_2_7_7_REM_MI_SET ns_noc_io_spio_soc_ip.csr 205407 MI 1'b1: Mask ILU error interrupt 14 14 0x1 R/W MJ SPIO_NOC_ROUTER_2_7_7_REM_MJ_WIDTH SPIO_NOC_ROUTER_2_7_7_REM_MJ_MSB SPIO_NOC_ROUTER_2_7_7_REM_MJ_LSB SPIO_NOC_ROUTER_2_7_7_REM_MJ_RANGE SPIO_NOC_ROUTER_2_7_7_REM_MJ_RESET SPIO_NOC_ROUTER_2_7_7_REM_MJ_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_REM_MJ_GET SPIO_NOC_ROUTER_2_7_7_REM_MJ_SET ns_noc_io_spio_soc_ip.csr 205418 MJ 1'b1: Mask JLU error interrupt 15 15 0x1 R/W MK SPIO_NOC_ROUTER_2_7_7_REM_MK_WIDTH SPIO_NOC_ROUTER_2_7_7_REM_MK_MSB SPIO_NOC_ROUTER_2_7_7_REM_MK_LSB SPIO_NOC_ROUTER_2_7_7_REM_MK_RANGE SPIO_NOC_ROUTER_2_7_7_REM_MK_RESET SPIO_NOC_ROUTER_2_7_7_REM_MK_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_REM_MK_GET SPIO_NOC_ROUTER_2_7_7_REM_MK_SET ns_noc_io_spio_soc_ip.csr 205429 MK 1'b1: Mask KLU error interrupt 16 16 0x1 R/W UNSD_31_14 SPIO_NOC_ROUTER_2_7_7_REM_UNSD_31_14_WIDTH SPIO_NOC_ROUTER_2_7_7_REM_UNSD_31_14_MSB SPIO_NOC_ROUTER_2_7_7_REM_UNSD_31_14_LSB SPIO_NOC_ROUTER_2_7_7_REM_UNSD_31_14_RANGE SPIO_NOC_ROUTER_2_7_7_REM_UNSD_31_14_RESET SPIO_NOC_ROUTER_2_7_7_REM_UNSD_31_14_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_REM_UNSD_31_14_GET SPIO_NOC_ROUTER_2_7_7_REM_UNSD_31_14_SET ns_noc_io_spio_soc_ip.csr 205440 UNSD_31_14 31 17 0x0000 R register spio_noc.router_2_7_7_id router_2_7_7_id SPIO_NOC_ROUTER_2_7_7_ID_ADDRESS SPIO_NOC_ROUTER_2_7_7_ID_BYTE_ADDRESS SPIO_NOC_ROUTER_2_7_7_ID_OFFSET SPIO_NOC_ROUTER_2_7_7_ID_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 205510 R2_7 register id 0x680A0 R 0x010000c2 Spio_noc_router_2_7_7_id This register holds layer and position information for the router. It is a read-only register. It can be used for debugging software access to the NoC elements by confirming that a read has successfully targeted the correct NoC element. false false false false LAYER SPIO_NOC_ROUTER_2_7_7_ID_LAYER_WIDTH SPIO_NOC_ROUTER_2_7_7_ID_LAYER_MSB SPIO_NOC_ROUTER_2_7_7_ID_LAYER_LSB SPIO_NOC_ROUTER_2_7_7_ID_LAYER_RANGE SPIO_NOC_ROUTER_2_7_7_ID_LAYER_RESET SPIO_NOC_ROUTER_2_7_7_ID_LAYER_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_ID_LAYER_GET SPIO_NOC_ROUTER_2_7_7_ID_LAYER_SET ns_noc_io_spio_soc_ip.csr 205466 LAYER 5-bit identifier of the NoC layer on which this router is located 4 0 0x02 R POS SPIO_NOC_ROUTER_2_7_7_ID_POS_WIDTH SPIO_NOC_ROUTER_2_7_7_ID_POS_MSB SPIO_NOC_ROUTER_2_7_7_ID_POS_LSB SPIO_NOC_ROUTER_2_7_7_ID_POS_RANGE SPIO_NOC_ROUTER_2_7_7_ID_POS_RESET SPIO_NOC_ROUTER_2_7_7_ID_POS_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_ID_POS_GET SPIO_NOC_ROUTER_2_7_7_ID_POS_SET ns_noc_io_spio_soc_ip.csr 205477 POS 16-bit position ID of this router in the NoC 20 5 0x0006 R ZERO SPIO_NOC_ROUTER_2_7_7_ID_ZERO_WIDTH SPIO_NOC_ROUTER_2_7_7_ID_ZERO_MSB SPIO_NOC_ROUTER_2_7_7_ID_ZERO_LSB SPIO_NOC_ROUTER_2_7_7_ID_ZERO_RANGE SPIO_NOC_ROUTER_2_7_7_ID_ZERO_RESET SPIO_NOC_ROUTER_2_7_7_ID_ZERO_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_ID_ZERO_GET SPIO_NOC_ROUTER_2_7_7_ID_ZERO_SET ns_noc_io_spio_soc_ip.csr 205488 ZERO Zeroes 23 21 0x0 R ONE SPIO_NOC_ROUTER_2_7_7_ID_ONE_WIDTH SPIO_NOC_ROUTER_2_7_7_ID_ONE_MSB SPIO_NOC_ROUTER_2_7_7_ID_ONE_LSB SPIO_NOC_ROUTER_2_7_7_ID_ONE_RANGE SPIO_NOC_ROUTER_2_7_7_ID_ONE_RESET SPIO_NOC_ROUTER_2_7_7_ID_ONE_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_ID_ONE_GET SPIO_NOC_ROUTER_2_7_7_ID_ONE_SET ns_noc_io_spio_soc_ip.csr 205499 ONE One 24 24 0x1 R UNSD_31_25 SPIO_NOC_ROUTER_2_7_7_ID_UNSD_31_25_WIDTH SPIO_NOC_ROUTER_2_7_7_ID_UNSD_31_25_MSB SPIO_NOC_ROUTER_2_7_7_ID_UNSD_31_25_LSB SPIO_NOC_ROUTER_2_7_7_ID_UNSD_31_25_RANGE SPIO_NOC_ROUTER_2_7_7_ID_UNSD_31_25_RESET SPIO_NOC_ROUTER_2_7_7_ID_UNSD_31_25_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_ID_UNSD_31_25_GET SPIO_NOC_ROUTER_2_7_7_ID_UNSD_31_25_SET ns_noc_io_spio_soc_ip.csr 205509 UNSD_31_25 31 25 0x00 R register spio_noc.router_2_7_7_rcgo router_2_7_7_rcgo SPIO_NOC_ROUTER_2_7_7_RCGO_ADDRESS SPIO_NOC_ROUTER_2_7_7_RCGO_BYTE_ADDRESS SPIO_NOC_ROUTER_2_7_7_RCGO_OFFSET SPIO_NOC_ROUTER_2_7_7_RCGO_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 205549 R2_7 register rcgo 0x680B0 R/W 0x00000000 Spio_noc_router_2_7_7_rcgo This register is used by coarse grained clock gating logic. This register can be set to override coarse clock gating for the entire router. Coarse clock gating for selective routers can be overridden by locally setting this register, if the user does not want incur and aggregate coarse clock gating cycle penalty over a "fast path/critical path" through the NoC. false false false false FPO SPIO_NOC_ROUTER_2_7_7_RCGO_FPO_WIDTH SPIO_NOC_ROUTER_2_7_7_RCGO_FPO_MSB SPIO_NOC_ROUTER_2_7_7_RCGO_FPO_LSB SPIO_NOC_ROUTER_2_7_7_RCGO_FPO_RANGE SPIO_NOC_ROUTER_2_7_7_RCGO_FPO_RESET SPIO_NOC_ROUTER_2_7_7_RCGO_FPO_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_RCGO_FPO_GET SPIO_NOC_ROUTER_2_7_7_RCGO_FPO_SET ns_noc_io_spio_soc_ip.csr 205537 FPO 1'b1: Coarse clock gating is locally disabled (for fast path) 1'b0: Coarse clock gating is locally enabled 0 0 0x0 R/W UNSD_31_1 SPIO_NOC_ROUTER_2_7_7_RCGO_UNSD_31_1_WIDTH SPIO_NOC_ROUTER_2_7_7_RCGO_UNSD_31_1_MSB SPIO_NOC_ROUTER_2_7_7_RCGO_UNSD_31_1_LSB SPIO_NOC_ROUTER_2_7_7_RCGO_UNSD_31_1_RANGE SPIO_NOC_ROUTER_2_7_7_RCGO_UNSD_31_1_RESET SPIO_NOC_ROUTER_2_7_7_RCGO_UNSD_31_1_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_RCGO_UNSD_31_1_GET SPIO_NOC_ROUTER_2_7_7_RCGO_UNSD_31_1_SET ns_noc_io_spio_soc_ip.csr 205548 UNSD_31_1 31 1 0x00000000 R register spio_noc.router_2_7_7_p1_rperr router_2_7_7_p1_rperr SPIO_NOC_ROUTER_2_7_7_P1_RPERR_ADDRESS SPIO_NOC_ROUTER_2_7_7_P1_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_2_7_7_P1_RPERR_OFFSET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 205840 R2_7 register p1_rperr 0x680C0 R/W 0x00000000 Spio_noc_router_2_7_7_p1_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 205592 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 205603 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 205614 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 205625 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_2_7_7_P1_RPERR_CR_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERR_CR_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_CR_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_CR_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERR_CR_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERR_CR_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 205636 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_2_7_7_P1_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 205647 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_0_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_0_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_0_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_0_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_0_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 205658 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_0_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_0_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_0_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_0_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 205669 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_0_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_0_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_0_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_0_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 205681 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_0_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_0_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_0_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_0_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 205692 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_1_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_1_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_1_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_1_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_1_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 205704 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_1_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_1_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_1_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_1_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 205716 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_1_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_1_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_1_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_1_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 205729 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_1_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_1_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_1_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_1_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 205741 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_2_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_2_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_2_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_2_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_2_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 205753 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_2_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_2_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_2_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_2_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 205765 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_2_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_2_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_2_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_2_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 205778 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_2_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_2_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_2_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_2_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 205790 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_3_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_3_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_3_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_3_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_3_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 205802 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_3_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_3_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_3_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_3_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 205814 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_3_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_3_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_3_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_3_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 205827 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_3_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_3_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_3_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_3_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 205839 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_2_7_7_p2_rperr router_2_7_7_p2_rperr SPIO_NOC_ROUTER_2_7_7_P2_RPERR_ADDRESS SPIO_NOC_ROUTER_2_7_7_P2_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_2_7_7_P2_RPERR_OFFSET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 206131 R2_7 register p2_rperr 0x680C8 R/W 0x00000000 Spio_noc_router_2_7_7_p2_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 205883 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 205894 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 205905 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 205916 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_2_7_7_P2_RPERR_CR_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERR_CR_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_CR_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_CR_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERR_CR_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERR_CR_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 205927 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_2_7_7_P2_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 205938 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_0_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_0_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_0_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_0_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_0_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 205949 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_0_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_0_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_0_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_0_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 205960 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_0_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_0_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_0_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_0_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 205972 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_0_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_0_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_0_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_0_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 205983 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_1_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_1_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_1_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_1_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_1_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 205995 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_1_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_1_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_1_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_1_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 206007 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_1_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_1_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_1_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_1_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 206020 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_1_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_1_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_1_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_1_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 206032 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_2_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_2_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_2_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_2_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_2_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 206044 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_2_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_2_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_2_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_2_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 206056 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_2_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_2_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_2_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_2_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 206069 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_2_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_2_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_2_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_2_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 206081 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_3_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_3_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_3_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_3_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_3_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 206093 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_3_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_3_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_3_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_3_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 206105 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_3_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_3_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_3_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_3_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 206118 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_3_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_3_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_3_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_3_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 206130 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_2_7_7_p4_rperr router_2_7_7_p4_rperr SPIO_NOC_ROUTER_2_7_7_P4_RPERR_ADDRESS SPIO_NOC_ROUTER_2_7_7_P4_RPERR_BYTE_ADDRESS SPIO_NOC_ROUTER_2_7_7_P4_RPERR_OFFSET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 206422 R2_7 register p4_rperr 0x680D8 R/W 0x00000000 Spio_noc_router_2_7_7_p4_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_SET ns_noc_io_spio_soc_ip.csr 206174 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_SET ns_noc_io_spio_soc_ip.csr 206185 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_SET ns_noc_io_spio_soc_ip.csr 206196 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_SET ns_noc_io_spio_soc_ip.csr 206207 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR SPIO_NOC_ROUTER_2_7_7_P4_RPERR_CR_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERR_CR_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_CR_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_CR_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERR_CR_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_CR_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERR_CR_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_CR_SET ns_noc_io_spio_soc_ip.csr 206218 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_2_7_7_P4_RPERR_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERR_UNSD_15_5_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_UNSD_15_5_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_UNSD_15_5_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERR_UNSD_15_5_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERR_UNSD_15_5_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 206229 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_0_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_0_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_0_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_0_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_0_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_0_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_0_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_0_SET ns_noc_io_spio_soc_ip.csr 206240 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_0_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_0_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_0_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_0_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_0_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_0_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_0_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_0_SET ns_noc_io_spio_soc_ip.csr 206251 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_0_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_0_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_0_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_0_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_0_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_0_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_0_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_0_SET ns_noc_io_spio_soc_ip.csr 206263 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_0_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_0_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_0_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_0_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_0_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_0_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_0_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_0_SET ns_noc_io_spio_soc_ip.csr 206274 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_1_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_1_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_1_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_1_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_1_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_1_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_1_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_1_SET ns_noc_io_spio_soc_ip.csr 206286 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_1_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_1_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_1_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_1_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_1_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_1_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_1_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_1_SET ns_noc_io_spio_soc_ip.csr 206298 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_1_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_1_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_1_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_1_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_1_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_1_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_1_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_1_SET ns_noc_io_spio_soc_ip.csr 206311 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_1_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_1_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_1_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_1_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_1_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_1_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_1_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_1_SET ns_noc_io_spio_soc_ip.csr 206323 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_2_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_2_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_2_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_2_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_2_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_2_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_2_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_2_SET ns_noc_io_spio_soc_ip.csr 206335 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_2_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_2_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_2_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_2_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_2_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_2_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_2_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_2_SET ns_noc_io_spio_soc_ip.csr 206347 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_2_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_2_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_2_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_2_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_2_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_2_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_2_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_2_SET ns_noc_io_spio_soc_ip.csr 206360 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_2_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_2_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_2_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_2_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_2_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_2_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_2_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_2_SET ns_noc_io_spio_soc_ip.csr 206372 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_3_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_3_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_3_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_3_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_3_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_3_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_3_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_D_3_SET ns_noc_io_spio_soc_ip.csr 206384 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_3_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_3_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_3_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_3_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_3_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_3_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_3_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_SB_3_SET ns_noc_io_spio_soc_ip.csr 206396 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_3_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_3_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_3_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_3_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_3_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_3_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_3_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_PK_3_SET ns_noc_io_spio_soc_ip.csr 206409 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_3_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_3_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_3_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_3_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_3_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_3_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_3_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERR_RI_3_SET ns_noc_io_spio_soc_ip.csr 206421 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register spio_noc.router_2_7_7_p1_rperrm router_2_7_7_p1_rperrm SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_ADDRESS SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_OFFSET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 206680 R2_7 register p1_rperrm 0x68100 R/W 0x00000000 Spio_noc_router_2_7_7_p1_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 206444 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 206455 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 206466 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 206477 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_CR_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_CR_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_CR_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_CR_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_CR_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 206488 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 206499 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_0_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_0_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_0_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_0_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 206510 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_0_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 206521 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_0_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 206533 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_0_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 206544 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_1_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_1_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_1_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_1_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 206555 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_1_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 206566 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_1_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 206578 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_1_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 206589 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_2_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_2_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_2_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_2_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 206600 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_2_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 206611 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_2_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 206623 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_2_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 206634 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_3_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_3_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_3_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_3_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 206645 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_3_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 206656 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_3_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 206668 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_3_GET SPIO_NOC_ROUTER_2_7_7_P1_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 206679 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_2_7_7_p2_rperrm router_2_7_7_p2_rperrm SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_ADDRESS SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_OFFSET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 206938 R2_7 register p2_rperrm 0x68108 R/W 0x00000000 Spio_noc_router_2_7_7_p2_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 206702 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 206713 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 206724 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 206735 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_CR_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_CR_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_CR_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_CR_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_CR_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 206746 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 206757 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_0_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_0_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_0_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_0_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 206768 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_0_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 206779 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_0_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 206791 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_0_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 206802 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_1_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_1_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_1_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_1_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 206813 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_1_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 206824 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_1_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 206836 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_1_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 206847 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_2_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_2_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_2_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_2_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 206858 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_2_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 206869 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_2_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 206881 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_2_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 206892 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_3_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_3_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_3_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_3_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 206903 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_3_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 206914 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_3_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 206926 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_3_GET SPIO_NOC_ROUTER_2_7_7_P2_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 206937 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register spio_noc.router_2_7_7_p4_rperrm router_2_7_7_p4_rperrm SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_ADDRESS SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_BYTE_ADDRESS SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_OFFSET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_BYTE_OFFSET ns_noc_io_spio_soc_ip.csr 207196 R2_7 register p4_rperrm 0x68118 R/W 0x00000000 Spio_noc_router_2_7_7_p4_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_SET ns_noc_io_spio_soc_ip.csr 206960 D MaskParity Error in Link Data. 0 0 0x0 R/W SB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_SET ns_noc_io_spio_soc_ip.csr 206971 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_SET ns_noc_io_spio_soc_ip.csr 206982 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_SET ns_noc_io_spio_soc_ip.csr 206993 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_CR_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_CR_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_CR_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_CR_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_CR_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_CR_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_CR_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_CR_SET ns_noc_io_spio_soc_ip.csr 207004 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_UNSD_15_5_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_UNSD_15_5_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_UNSD_15_5_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_UNSD_15_5_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_UNSD_15_5_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_UNSD_15_5_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_UNSD_15_5_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_UNSD_15_5_SET ns_noc_io_spio_soc_ip.csr 207015 UNSD_15_5 15 5 0x000 R D_0 SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_0_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_0_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_0_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_0_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_0_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_0_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_0_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_0_SET ns_noc_io_spio_soc_ip.csr 207026 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_0_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_0_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_0_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_0_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_0_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_0_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_0_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_0_SET ns_noc_io_spio_soc_ip.csr 207037 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_0_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_0_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_0_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_0_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_0_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_0_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_0_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_0_SET ns_noc_io_spio_soc_ip.csr 207049 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_0_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_0_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_0_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_0_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_0_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_0_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_0_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_0_SET ns_noc_io_spio_soc_ip.csr 207060 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_1_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_1_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_1_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_1_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_1_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_1_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_1_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_1_SET ns_noc_io_spio_soc_ip.csr 207071 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_1_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_1_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_1_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_1_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_1_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_1_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_1_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_1_SET ns_noc_io_spio_soc_ip.csr 207082 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_1_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_1_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_1_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_1_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_1_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_1_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_1_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_1_SET ns_noc_io_spio_soc_ip.csr 207094 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_1_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_1_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_1_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_1_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_1_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_1_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_1_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_1_SET ns_noc_io_spio_soc_ip.csr 207105 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_2_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_2_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_2_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_2_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_2_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_2_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_2_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_2_SET ns_noc_io_spio_soc_ip.csr 207116 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_2_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_2_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_2_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_2_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_2_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_2_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_2_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_2_SET ns_noc_io_spio_soc_ip.csr 207127 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_2_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_2_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_2_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_2_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_2_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_2_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_2_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_2_SET ns_noc_io_spio_soc_ip.csr 207139 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_2_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_2_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_2_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_2_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_2_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_2_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_2_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_2_SET ns_noc_io_spio_soc_ip.csr 207150 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_3_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_3_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_3_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_3_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_3_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_3_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_3_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_D_3_SET ns_noc_io_spio_soc_ip.csr 207161 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_3_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_3_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_3_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_3_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_3_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_3_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_3_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_SB_3_SET ns_noc_io_spio_soc_ip.csr 207172 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_3_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_3_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_3_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_3_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_3_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_3_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_3_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_PK_3_SET ns_noc_io_spio_soc_ip.csr 207184 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_3_WIDTH SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_3_MSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_3_LSB SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_3_RANGE SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_3_RESET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_3_FIELD_MASK SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_3_GET SPIO_NOC_ROUTER_2_7_7_P4_RPERRM_RI_3_SET ns_noc_io_spio_soc_ip.csr 207195 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W

Addressmap Information for 'ns_noc_io_spio_soc_ip'

Input File Information

Header File Information

Enum Information